hw/omap_lcdc.c

   1 /*
   2  * OMAP LCD controller.
   3  *
   4  * Copyright (C) 2006-2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20 #include "hw.h"
  21 #include "console.h"
  22 #include "omap.h"
  23
  24 struct omap_lcd_panel_s {
  25     qemu_irq irq;
  26     DisplayState *state;
  27     QEMUConsole *console;
  28     ram_addr_t imif_base;
  29     ram_addr_t emiff_base;
  30
  31     int plm;
  32     int tft;
  33     int mono;
  34     int enable;
  35     int width;
  36     int height;
  37     int interrupts;
  38     uint32_t timing[3];
  39     uint32_t subpanel;
  40     uint32_t ctrl;
  41
  42     struct omap_dma_lcd_channel_s *dma;
  43     uint16_t palette[256];
  44     int palette_done;
  45     int frame_done;
  46     int invalidate;
  47     int sync_error;
  48 };
  49
  50 static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
  51 {
  52     if (s->frame_done && (s->interrupts & 1)) {
  53         qemu_irq_raise(s->irq);
  54         return;
  55     }
  56
  57     if (s->palette_done && (s->interrupts & 2)) {
  58         qemu_irq_raise(s->irq);
  59         return;
  60     }
  61
  62     if (s->sync_error) {
  63         qemu_irq_raise(s->irq);
  64         return;
  65     }
  66
  67     qemu_irq_lower(s->irq);
  68 }
  69
  70 #include "pixel_ops.h"
  71
  72 typedef void draw_line_func(
  73                 uint8_t *d, const uint8_t *s, int width, const uint16_t *pal);
  74
  75 #define DEPTH 8
  76 #include "omap_lcd_template.h"
  77 #define DEPTH 15
  78 #include "omap_lcd_template.h"
  79 #define DEPTH 16
  80 #include "omap_lcd_template.h"
  81 #define DEPTH 32
  82 #include "omap_lcd_template.h"
  83
  84 static draw_line_func *draw_line_table2[33] = {
  85     [0 ... 32]  = 0,
  86     [8]         = draw_line2_8,
  87     [15]        = draw_line2_15,
  88     [16]        = draw_line2_16,
  89     [32]        = draw_line2_32,
  90 }, *draw_line_table4[33] = {
  91     [0 ... 32]  = 0,
  92     [8]         = draw_line4_8,
  93     [15]        = draw_line4_15,
  94     [16]        = draw_line4_16,
  95     [32]        = draw_line4_32,
  96 }, *draw_line_table8[33] = {
  97     [0 ... 32]  = 0,
  98     [8]         = draw_line8_8,
  99     [15]        = draw_line8_15,
 100     [16]        = draw_line8_16,
 101     [32]        = draw_line8_32,
 102 }, *draw_line_table12[33] = {
 103     [0 ... 32]  = 0,
 104     [8]         = draw_line12_8,
 105     [15]        = draw_line12_15,
 106     [16]        = draw_line12_16,
 107     [32]        = draw_line12_32,
 108 }, *draw_line_table16[33] = {
 109     [0 ... 32]  = 0,
 110     [8]         = draw_line16_8,
 111     [15]        = draw_line16_15,
 112     [16]        = draw_line16_16,
 113     [32]        = draw_line16_32,
 114 };
 115
 116 static void omap_update_display(void *opaque)
 117 {
 118     struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
 119     draw_line_func *draw_line;
 120     int size, dirty[2], minline, maxline, height;
 121     int line, width, linesize, step, bpp, frame_offset;
 122     ram_addr_t frame_base, scanline, newline, x;
 123     uint8_t *s, *d;
 124
 125     if (!omap_lcd || omap_lcd->plm == 1 ||
 126                     !omap_lcd->enable || !ds_get_bits_per_pixel(omap_lcd->state))
 127         return;
 128
 129     frame_offset = 0;
 130     if (omap_lcd->plm != 2) {
 131         memcpy(omap_lcd->palette, phys_ram_base +
 132                         omap_lcd->dma->phys_framebuffer[
 133                         omap_lcd->dma->current_frame], 0x200);
 134         switch (omap_lcd->palette[0] >> 12 & 7) {
 135         case 3 ... 7:
 136             frame_offset += 0x200;
 137             break;
 138         default:
 139             frame_offset += 0x20;
 140         }
 141     }
 142
 143     /* Colour depth */
 144     switch ((omap_lcd->palette[0] >> 12) & 7) {
 145     case 1:
 146         draw_line = draw_line_table2[ds_get_bits_per_pixel(omap_lcd->state)];
 147         bpp = 2;
 148         break;
 149
 150     case 2:
 151         draw_line = draw_line_table4[ds_get_bits_per_pixel(omap_lcd->state)];
 152         bpp = 4;
 153         break;
 154
 155     case 3:
 156         draw_line = draw_line_table8[ds_get_bits_per_pixel(omap_lcd->state)];
 157         bpp = 8;
 158         break;
 159
 160     case 4 ... 7:
 161         if (!omap_lcd->tft)
 162             draw_line = draw_line_table12[ds_get_bits_per_pixel(omap_lcd->state)];
 163         else
 164             draw_line = draw_line_table16[ds_get_bits_per_pixel(omap_lcd->state)];
 165         bpp = 16;
 166         break;
 167
 168     default:
 169         /* Unsupported at the moment.  */
 170         return;
 171     }
 172
 173     /* Resolution */
 174     width = omap_lcd->width;
 175     if (width != ds_get_width(omap_lcd->state) ||
 176             omap_lcd->height != ds_get_height(omap_lcd->state)) {
 177         qemu_console_resize(omap_lcd->console,
 178                             omap_lcd->width, omap_lcd->height);
 179         omap_lcd->invalidate = 1;
 180     }
 181
 182     if (omap_lcd->dma->current_frame == 0)
 183         size = omap_lcd->dma->src_f1_bottom - omap_lcd->dma->src_f1_top;
 184     else
 185         size = omap_lcd->dma->src_f2_bottom - omap_lcd->dma->src_f2_top;
 186
 187     if (frame_offset + ((width * omap_lcd->height * bpp) >> 3) > size + 2) {
 188         omap_lcd->sync_error = 1;
 189         omap_lcd_interrupts(omap_lcd);
 190         omap_lcd->enable = 0;
 191         return;
 192     }
 193
 194     /* Content */
 195     frame_base = omap_lcd->dma->phys_framebuffer[
 196             omap_lcd->dma->current_frame] + frame_offset;
 197     omap_lcd->dma->condition |= 1 << omap_lcd->dma->current_frame;
 198     if (omap_lcd->dma->interrupts & 1)
 199         qemu_irq_raise(omap_lcd->dma->irq);
 200     if (omap_lcd->dma->dual)
 201         omap_lcd->dma->current_frame ^= 1;
 202
 203     if (!ds_get_bits_per_pixel(omap_lcd->state))
 204         return;
 205
 206     line = 0;
 207     height = omap_lcd->height;
 208     if (omap_lcd->subpanel & (1 << 31)) {
 209         if (omap_lcd->subpanel & (1 << 29))
 210             line = (omap_lcd->subpanel >> 16) & 0x3ff;
 211         else
 212             height = (omap_lcd->subpanel >> 16) & 0x3ff;
 213         /* TODO: fill the rest of the panel with DPD */
 214     }
 215     step = width * bpp >> 3;
 216     scanline = frame_base + step * line;
 217     s = (uint8_t *) (phys_ram_base + scanline);
 218     d = ds_get_data(omap_lcd->state);
 219     linesize = ds_get_linesize(omap_lcd->state);
 220
 221     dirty[0] = dirty[1] =
 222             cpu_physical_memory_get_dirty(scanline, VGA_DIRTY_FLAG);
 223     minline = height;
 224     maxline = line;
 225     for (; line < height; line ++) {
 226         newline = scanline + step;
 227         for (x = scanline + TARGET_PAGE_SIZE; x < newline;
 228                         x += TARGET_PAGE_SIZE) {
 229             dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
 230             dirty[0] |= dirty[1];
 231         }
 232         if (dirty[0] || omap_lcd->invalidate) {
 233             draw_line(d, s, width, omap_lcd->palette);
 234             if (line < minline)
 235                 minline = line;
 236             maxline = line + 1;
 237         }
 238         scanline = newline;
 239         dirty[0] = dirty[1];
 240         s += step;
 241         d += linesize;
 242     }
 243
 244     if (maxline >= minline) {
 245         dpy_update(omap_lcd->state, 0, minline, width, maxline);
 246         cpu_physical_memory_reset_dirty(frame_base + step * minline,
 247                         frame_base + step * maxline, VGA_DIRTY_FLAG);
 248     }
 249 }
 250
 251 static int ppm_save(const char *filename, uint8_t *data,
 252                 int w, int h, int linesize)
 253 {
 254     FILE *f;
 255     uint8_t *d, *d1;
 256     unsigned int v;
 257     int y, x, bpp;
 258
 259     f = fopen(filename, "wb");
 260     if (!f)
 261         return -1;
 262     fprintf(f, "P6\n%d %d\n%d\n", w, h, 255);
 263     d1 = data;
 264     bpp = linesize / w;
 265     for (y = 0; y < h; y ++) {
 266         d = d1;
 267         for (x = 0; x < w; x ++) {
 268             v = *(uint32_t *) d;
 269             switch (bpp) {
 270             case 2:
 271                 fputc((v >> 8) & 0xf8, f);
 272                 fputc((v >> 3) & 0xfc, f);
 273                 fputc((v << 3) & 0xf8, f);
 274                 break;
 275             case 3:
 276             case 4:
 277             default:
 278                 fputc((v >> 16) & 0xff, f);
 279                 fputc((v >> 8) & 0xff, f);
 280                 fputc((v) & 0xff, f);
 281                 break;
 282             }
 283             d += bpp;
 284         }
 285         d1 += linesize;
 286     }
 287     fclose(f);
 288     return 0;
 289 }
 290
 291 static void omap_screen_dump(void *opaque, const char *filename) {
 292     struct omap_lcd_panel_s *omap_lcd = opaque;
 293     omap_update_display(opaque);
 294     if (omap_lcd && ds_get_data(omap_lcd->state))
 295         ppm_save(filename, ds_get_data(omap_lcd->state),
 296                 omap_lcd->width, omap_lcd->height,
 297                 ds_get_linesize(omap_lcd->state));
 298 }
 299
 300 static void omap_invalidate_display(void *opaque) {
 301     struct omap_lcd_panel_s *omap_lcd = opaque;
 302     omap_lcd->invalidate = 1;
 303 }
 304
 305 static void omap_lcd_update(struct omap_lcd_panel_s *s) {
 306     if (!s->enable) {
 307         s->dma->current_frame = -1;
 308         s->sync_error = 0;
 309         if (s->plm != 1)
 310             s->frame_done = 1;
 311         omap_lcd_interrupts(s);
 312         return;
 313     }
 314
 315     if (s->dma->current_frame == -1) {
 316         s->frame_done = 0;
 317         s->palette_done = 0;
 318         s->dma->current_frame = 0;
 319     }
 320
 321     if (!s->dma->mpu->port[s->dma->src].addr_valid(s->dma->mpu,
 322                             s->dma->src_f1_top) ||
 323                     !s->dma->mpu->port[
 324                     s->dma->src].addr_valid(s->dma->mpu,
 325                             s->dma->src_f1_bottom) ||
 326                     (s->dma->dual &&
 327                      (!s->dma->mpu->port[
 328                       s->dma->src].addr_valid(s->dma->mpu,
 329                               s->dma->src_f2_top) ||
 330                       !s->dma->mpu->port[
 331                       s->dma->src].addr_valid(s->dma->mpu,
 332                               s->dma->src_f2_bottom)))) {
 333         s->dma->condition |= 1 << 2;
 334         if (s->dma->interrupts & (1 << 1))
 335             qemu_irq_raise(s->dma->irq);
 336         s->enable = 0;
 337         return;
 338     }
 339
 340      if (s->dma->src == imif) {
 341         /* Framebuffers are in SRAM */
 342         s->dma->phys_framebuffer[0] = s->imif_base +
 343                 s->dma->src_f1_top - OMAP_IMIF_BASE;
 344
 345         s->dma->phys_framebuffer[1] = s->imif_base +
 346                 s->dma->src_f2_top - OMAP_IMIF_BASE;
 347     } else {
 348         /* Framebuffers are in RAM */
 349         s->dma->phys_framebuffer[0] = s->emiff_base +
 350                 s->dma->src_f1_top - OMAP_EMIFF_BASE;
 351
 352         s->dma->phys_framebuffer[1] = s->emiff_base +
 353                 s->dma->src_f2_top - OMAP_EMIFF_BASE;
 354     }
 355
 356     if (s->plm != 2 && !s->palette_done) {
 357         memcpy(s->palette, phys_ram_base +
 358                 s->dma->phys_framebuffer[s->dma->current_frame], 0x200);
 359         s->palette_done = 1;
 360         omap_lcd_interrupts(s);
 361     }
 362 }
 363
 364 static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr)
 365 {
 366     struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
 367
 368     switch (addr) {
 369     case 0x00:  /* LCD_CONTROL */
 370         return (s->tft << 23) | (s->plm << 20) |
 371                 (s->tft << 7) | (s->interrupts << 3) |
 372                 (s->mono << 1) | s->enable | s->ctrl | 0xfe000c34;
 373
 374     case 0x04:  /* LCD_TIMING0 */
 375         return (s->timing[0] << 10) | (s->width - 1) | 0x0000000f;
 376
 377     case 0x08:  /* LCD_TIMING1 */
 378         return (s->timing[1] << 10) | (s->height - 1);
 379
 380     case 0x0c:  /* LCD_TIMING2 */
 381         return s->timing[2] | 0xfc000000;
 382
 383     case 0x10:  /* LCD_STATUS */
 384         return (s->palette_done << 6) | (s->sync_error << 2) | s->frame_done;
 385
 386     case 0x14:  /* LCD_SUBPANEL */
 387         return s->subpanel;
 388
 389     default:
 390         break;
 391     }
 392     OMAP_BAD_REG(addr);
 393     return 0;
 394 }
 395
 396 static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
 397                 uint32_t value)
 398 {
 399     struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
 400
 401     switch (addr) {
 402     case 0x00:  /* LCD_CONTROL */
 403         s->plm = (value >> 20) & 3;
 404         s->tft = (value >> 7) & 1;
 405         s->interrupts = (value >> 3) & 3;
 406         s->mono = (value >> 1) & 1;
 407         s->ctrl = value & 0x01cff300;
 408         if (s->enable != (value & 1)) {
 409             s->enable = value & 1;
 410             omap_lcd_update(s);
 411         }
 412         break;
 413
 414     case 0x04:  /* LCD_TIMING0 */
 415         s->timing[0] = value >> 10;
 416         s->width = (value & 0x3ff) + 1;
 417         break;
 418
 419     case 0x08:  /* LCD_TIMING1 */
 420         s->timing[1] = value >> 10;
 421         s->height = (value & 0x3ff) + 1;
 422         break;
 423
 424     case 0x0c:  /* LCD_TIMING2 */
 425         s->timing[2] = value;
 426         break;
 427
 428     case 0x10:  /* LCD_STATUS */
 429         break;
 430
 431     case 0x14:  /* LCD_SUBPANEL */
 432         s->subpanel = value & 0xa1ffffff;
 433         break;
 434
 435     default:
 436         OMAP_BAD_REG(addr);
 437     }
 438 }
 439
 440 static CPUReadMemoryFunc *omap_lcdc_readfn[] = {
 441     omap_lcdc_read,
 442     omap_lcdc_read,
 443     omap_lcdc_read,
 444 };
 445
 446 static CPUWriteMemoryFunc *omap_lcdc_writefn[] = {
 447     omap_lcdc_write,
 448     omap_lcdc_write,
 449     omap_lcdc_write,
 450 };
 451
 452 void omap_lcdc_reset(struct omap_lcd_panel_s *s)
 453 {
 454     s->dma->current_frame = -1;
 455     s->plm = 0;
 456     s->tft = 0;
 457     s->mono = 0;
 458     s->enable = 0;
 459     s->width = 0;
 460     s->height = 0;
 461     s->interrupts = 0;
 462     s->timing[0] = 0;
 463     s->timing[1] = 0;
 464     s->timing[2] = 0;
 465     s->subpanel = 0;
 466     s->palette_done = 0;
 467     s->frame_done = 0;
 468     s->sync_error = 0;
 469     s->invalidate = 1;
 470     s->subpanel = 0;
 471     s->ctrl = 0;
 472 }
 473
 474 struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
 475                 struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
 476                 ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk)
 477 {
 478     int iomemtype;
 479     struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *)
 480             qemu_mallocz(sizeof(struct omap_lcd_panel_s));
 481
 482     s->irq = irq;
 483     s->dma = dma;
 484     s->state = ds;
 485     s->imif_base = imif_base;
 486     s->emiff_base = emiff_base;
 487     omap_lcdc_reset(s);
 488
 489     iomemtype = cpu_register_io_memory(0, omap_lcdc_readfn,
 490                     omap_lcdc_writefn, s);
 491     cpu_register_physical_memory(base, 0x100, iomemtype);
 492
 493     s->console = graphic_console_init(ds, omap_update_display,
 494                                       omap_invalidate_display,
 495                                       omap_screen_dump, NULL, s);
 496
 497     return s;
 498 }