target-ppc/cpu.h

   1 /*
   2  *  PowerPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #if !defined (__CPU_PPC_H__)
  21 #define __CPU_PPC_H__
  22
  23 #include "config.h"
  24 #include <stdint.h>
  25
  26 #if defined(TARGET_PPC64) || (HOST_LONG_BITS >= 64)
  27 /* When using 64 bits temporary registers,
  28  * we can use 64 bits GPR with no extra cost
  29  */
  30 #define TARGET_PPCSPE
  31 #endif
  32
  33 #if defined (TARGET_PPC64)
  34 typedef uint64_t ppc_gpr_t;
  35 #define TARGET_LONG_BITS 64
  36 #define TARGET_GPR_BITS  64
  37 #define REGX "%016" PRIx64
  38 #define ADDRX "%016" PRIx64
  39 #elif defined(TARGET_PPCSPE)
  40 /* GPR are 64 bits: used by vector extension */
  41 typedef uint64_t ppc_gpr_t;
  42 #define TARGET_LONG_BITS 32
  43 #define TARGET_GPR_BITS  64
  44 #define REGX "%016" PRIx64
  45 #define ADDRX "%08" PRIx32
  46 #else
  47 typedef uint32_t ppc_gpr_t;
  48 #define TARGET_LONG_BITS 32
  49 #define TARGET_GPR_BITS  32
  50 #define REGX "%08" PRIx32
  51 #define ADDRX "%08" PRIx32
  52 #endif
  53
  54 #include "cpu-defs.h"
  55
  56 #include <setjmp.h>
  57
  58 #include "softfloat.h"
  59
  60 #define TARGET_HAS_ICE 1
  61
  62 #if defined (TARGET_PPC64)
  63 #define ELF_MACHINE     EM_PPC64
  64 #else
  65 #define ELF_MACHINE     EM_PPC
  66 #endif
  67
  68 /* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
  69  *                              have different cache line sizes
  70  */
  71 #define ICACHE_LINE_SIZE 32
  72 #define DCACHE_LINE_SIZE 32
  73
  74 /* XXX: put this in a common place */
  75 #define likely(x)   __builtin_expect(!!(x), 1)
  76 #define unlikely(x) __builtin_expect(!!(x), 0)
  77
  78 /*****************************************************************************/
  79 /* PVR definitions for most known PowerPC */
  80 enum {
  81     /* PowerPC 401 cores */
  82     CPU_PPC_401A1     = 0x00210000,
  83     CPU_PPC_401B2     = 0x00220000,
  84     CPU_PPC_401C2     = 0x00230000,
  85     CPU_PPC_401D2     = 0x00240000,
  86     CPU_PPC_401E2     = 0x00250000,
  87     CPU_PPC_401F2     = 0x00260000,
  88     CPU_PPC_401G2     = 0x00270000,
  89 #define CPU_PPC_401 CPU_PPC_401G2
  90     CPU_PPC_IOP480    = 0x40100000, /* 401B2 ? */
  91     CPU_PPC_COBRA     = 0x10100000, /* IBM Processor for Network Resources */
  92     /* PowerPC 403 cores */
  93     CPU_PPC_403GA     = 0x00200011,
  94     CPU_PPC_403GB     = 0x00200100,
  95     CPU_PPC_403GC     = 0x00200200,
  96     CPU_PPC_403GCX    = 0x00201400,
  97 #define CPU_PPC_403 CPU_PPC_403GCX
  98     /* PowerPC 405 cores */
  99     CPU_PPC_405CR     = 0x40110145,
 100 #define CPU_PPC_405GP CPU_PPC_405CR
 101     CPU_PPC_405EP     = 0x51210950,
 102     CPU_PPC_405GPR    = 0x50910951,
 103     CPU_PPC_405D2     = 0x20010000,
 104     CPU_PPC_405D4     = 0x41810000,
 105 #define CPU_PPC_405 CPU_PPC_405D4
 106     CPU_PPC_NPE405H   = 0x414100C0,
 107     CPU_PPC_NPE405H2  = 0x41410140,
 108     CPU_PPC_NPE405L   = 0x416100C0,
 109     /* XXX: missing 405LP, LC77700 */
 110     /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
 111 #if 0
 112     CPU_PPC_STB01000  = xxx,
 113 #endif
 114 #if 0
 115     CPU_PPC_STB01010  = xxx,
 116 #endif
 117 #if 0
 118     CPU_PPC_STB0210   = xxx,
 119 #endif
 120     CPU_PPC_STB03     = 0x40310000,
 121 #if 0
 122     CPU_PPC_STB043    = xxx,
 123 #endif
 124 #if 0
 125     CPU_PPC_STB045    = xxx,
 126 #endif
 127     CPU_PPC_STB25     = 0x51510950,
 128 #if 0
 129     CPU_PPC_STB130    = xxx,
 130 #endif
 131     /* Xilinx cores */
 132     CPU_PPC_X2VP4     = 0x20010820,
 133 #define CPU_PPC_X2VP7 CPU_PPC_X2VP4
 134     CPU_PPC_X2VP20    = 0x20010860,
 135 #define CPU_PPC_X2VP50 CPU_PPC_X2VP20
 136     /* PowerPC 440 cores */
 137     CPU_PPC_440EP     = 0x422218D3,
 138 #define CPU_PPC_440GR CPU_PPC_440EP
 139     CPU_PPC_440GP     = 0x40120481,
 140     CPU_PPC_440GX     = 0x51B21850,
 141     CPU_PPC_440GXc    = 0x51B21892,
 142     CPU_PPC_440GXf    = 0x51B21894,
 143     CPU_PPC_440SP     = 0x53221850,
 144     CPU_PPC_440SP2    = 0x53221891,
 145     CPU_PPC_440SPE    = 0x53421890,
 146     /* XXX: missing 440GRX */
 147     /* PowerPC 460 cores - TODO */
 148     /* PowerPC MPC 5xx cores */
 149     CPU_PPC_5xx       = 0x00020020,
 150     /* PowerPC MPC 8xx cores (aka PowerQUICC) */
 151     CPU_PPC_8xx       = 0x00500000,
 152     /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
 153     CPU_PPC_82xx_HIP3 = 0x00810101,
 154     CPU_PPC_82xx_HIP4 = 0x80811014,
 155     CPU_PPC_827x      = 0x80822013,
 156     /* eCores */
 157     CPU_PPC_e200      = 0x81120000,
 158     CPU_PPC_e500v110  = 0x80200010,
 159     CPU_PPC_e500v120  = 0x80200020,
 160     CPU_PPC_e500v210  = 0x80210010,
 161     CPU_PPC_e500v220  = 0x80210020,
 162 #define CPU_PPC_e500 CPU_PPC_e500v220
 163     CPU_PPC_e600      = 0x80040010,
 164     /* PowerPC 6xx cores */
 165     CPU_PPC_601       = 0x00010001,
 166     CPU_PPC_602       = 0x00050100,
 167     CPU_PPC_603       = 0x00030100,
 168     CPU_PPC_603E      = 0x00060101,
 169     CPU_PPC_603P      = 0x00070000,
 170     CPU_PPC_603E7v    = 0x00070100,
 171     CPU_PPC_603E7v2   = 0x00070201,
 172     CPU_PPC_603E7     = 0x00070200,
 173     CPU_PPC_603R      = 0x00071201,
 174     CPU_PPC_G2        = 0x00810011,
 175     CPU_PPC_G2H4      = 0x80811010,
 176     CPU_PPC_G2gp      = 0x80821010,
 177     CPU_PPC_G2ls      = 0x90810010,
 178     CPU_PPC_G2LE      = 0x80820010,
 179     CPU_PPC_G2LEgp    = 0x80822010,
 180     CPU_PPC_G2LEls    = 0xA0822010,
 181     CPU_PPC_604       = 0x00040000,
 182     CPU_PPC_604E      = 0x00090100, /* Also 2110 & 2120 */
 183     CPU_PPC_604R      = 0x000a0101,
 184     /* PowerPC 74x/75x cores (aka G3) */
 185     CPU_PPC_74x       = 0x00080000,
 186     CPU_PPC_740E      = 0x00080100,
 187     CPU_PPC_750E      = 0x00080200,
 188     CPU_PPC_755_10    = 0x00083100,
 189     CPU_PPC_755_11    = 0x00083101,
 190     CPU_PPC_755_20    = 0x00083200,
 191     CPU_PPC_755D      = 0x00083202,
 192     CPU_PPC_755E      = 0x00083203,
 193 #define CPU_PPC_755 CPU_PPC_755E
 194     CPU_PPC_74xP      = 0x10080000,
 195     CPU_PPC_750CXE21  = 0x00082201,
 196     CPU_PPC_750CXE22  = 0x00082212,
 197     CPU_PPC_750CXE23  = 0x00082203,
 198     CPU_PPC_750CXE24  = 0x00082214,
 199     CPU_PPC_750CXE24b = 0x00083214,
 200     CPU_PPC_750CXE31  = 0x00083211,
 201     CPU_PPC_750CXE31b = 0x00083311,
 202 #define CPU_PPC_750CXE CPU_PPC_750CXE31b
 203     CPU_PPC_750CXR    = 0x00083410,
 204     CPU_PPC_750FX10   = 0x70000100,
 205     CPU_PPC_750FX20   = 0x70000200,
 206     CPU_PPC_750FX21   = 0x70000201,
 207     CPU_PPC_750FX22   = 0x70000202,
 208     CPU_PPC_750FX23   = 0x70000203,
 209 #define CPU_PPC_750FX CPU_PPC_750FX23
 210     CPU_PPC_750FL     = 0x700A0203,
 211     CPU_PPC_750GX10   = 0x70020100,
 212     CPU_PPC_750GX11   = 0x70020101,
 213     CPU_PPC_750GX12   = 0x70020102,
 214 #define CPU_PPC_750GX CPU_PPC_750GX12
 215     CPU_PPC_750GL     = 0x70020102,
 216     CPU_PPC_750L30    = 0x00088300,
 217     CPU_PPC_750L32    = 0x00088302,
 218     CPU_PPC_750CL     = 0x00087200,
 219     /* PowerPC 74xx cores (aka G4) */
 220     CPU_PPC_7400      = 0x000C0100,
 221     CPU_PPC_7410C     = 0x800C1102,
 222     CPU_PPC_7410D     = 0x800C1103,
 223     CPU_PPC_7410E     = 0x800C1104,
 224     CPU_PPC_7441      = 0x80000210,
 225     CPU_PPC_7445      = 0x80010100,
 226     CPU_PPC_7447      = 0x80020100,
 227     CPU_PPC_7447A     = 0x80030101,
 228     CPU_PPC_7448      = 0x80040100,
 229     CPU_PPC_7450      = 0x80000200,
 230     CPU_PPC_7450b     = 0x80000201,
 231     CPU_PPC_7451      = 0x80000203,
 232     CPU_PPC_7451G     = 0x80000210,
 233     CPU_PPC_7455      = 0x80010201,
 234     CPU_PPC_7455F     = 0x80010303,
 235     CPU_PPC_7455G     = 0x80010304,
 236     CPU_PPC_7457      = 0x80020101,
 237     CPU_PPC_7457C     = 0x80020102,
 238     CPU_PPC_7457A     = 0x80030000,
 239     /* 64 bits PowerPC */
 240     CPU_PPC_620       = 0x00140000,
 241     CPU_PPC_630       = 0x00400000,
 242     CPU_PPC_631       = 0x00410000,
 243     CPU_PPC_POWER4    = 0x00350000,
 244     CPU_PPC_POWER4P   = 0x00380000,
 245     CPU_PPC_POWER5    = 0x003A0000,
 246     CPU_PPC_POWER5P   = 0x003B0000,
 247     CPU_PPC_970       = 0x00390000,
 248     CPU_PPC_970FX10   = 0x00391100,
 249     CPU_PPC_970FX20   = 0x003C0200,
 250     CPU_PPC_970FX21   = 0x003C0201,
 251     CPU_PPC_970FX30   = 0x003C0300,
 252     CPU_PPC_970FX31   = 0x003C0301,
 253 #define CPU_PPC_970FX CPU_PPC_970FX31
 254     CPU_PPC_970MP10   = 0x00440100,
 255     CPU_PPC_970MP11   = 0x00440101,
 256 #define CPU_PPC_970MP CPU_PPC_970MP11
 257     CPU_PPC_CELL10    = 0x00700100,
 258     CPU_PPC_CELL20    = 0x00700400,
 259     CPU_PPC_CELL30    = 0x00700500,
 260     CPU_PPC_CELL31    = 0x00700501,
 261 #define CPU_PPC_CELL32 CPU_PPC_CELL31
 262 #define CPU_PPC_CELL CPU_PPC_CELL32
 263     CPU_PPC_RS64      = 0x00330000,
 264     CPU_PPC_RS64II    = 0x00340000,
 265     CPU_PPC_RS64III   = 0x00360000,
 266     CPU_PPC_RS64IV    = 0x00370000,
 267     /* Original POWER */
 268     /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
 269      * POWER2 (RIOS2) & RSC2 (P2SC) here
 270      */
 271 #if 0
 272     CPU_POWER         = xxx,
 273 #endif
 274 #if 0
 275     CPU_POWER2        = xxx,
 276 #endif
 277 };
 278
 279 /* System version register (used on MPC 8xxx) */
 280 enum {
 281     PPC_SVR_8540      = 0x80300000,
 282     PPC_SVR_8541E     = 0x807A0010,
 283     PPC_SVR_8543v10   = 0x80320010,
 284     PPC_SVR_8543v11   = 0x80320011,
 285     PPC_SVR_8543v20   = 0x80320020,
 286     PPC_SVR_8543Ev10  = 0x803A0010,
 287     PPC_SVR_8543Ev11  = 0x803A0011,
 288     PPC_SVR_8543Ev20  = 0x803A0020,
 289     PPC_SVR_8545      = 0x80310220,
 290     PPC_SVR_8545E     = 0x80390220,
 291     PPC_SVR_8547E     = 0x80390120,
 292     PPC_SCR_8548v10   = 0x80310010,
 293     PPC_SCR_8548v11   = 0x80310011,
 294     PPC_SCR_8548v20   = 0x80310020,
 295     PPC_SVR_8548Ev10  = 0x80390010,
 296     PPC_SVR_8548Ev11  = 0x80390011,
 297     PPC_SVR_8548Ev20  = 0x80390020,
 298     PPC_SVR_8555E     = 0x80790010,
 299     PPC_SVR_8560v10   = 0x80700010,
 300     PPC_SVR_8560v20   = 0x80700020,
 301 };
 302
 303 /*****************************************************************************/
 304 /* Instruction types */
 305 enum {
 306     PPC_NONE        = 0x00000000,
 307     /* integer operations instructions             */
 308     /* flow control instructions                   */
 309     /* virtual memory instructions                 */
 310     /* ld/st with reservation instructions         */
 311     /* cache control instructions                  */
 312     /* spr/msr access instructions                 */
 313     PPC_INSNS_BASE  = 0x0000000000000001ULL,
 314 #define PPC_INTEGER PPC_INSNS_BASE
 315 #define PPC_FLOW    PPC_INSNS_BASE
 316 #define PPC_MEM     PPC_INSNS_BASE
 317 #define PPC_RES     PPC_INSNS_BASE
 318 #define PPC_CACHE   PPC_INSNS_BASE
 319 #define PPC_MISC    PPC_INSNS_BASE
 320     /* floating point operations instructions      */
 321     PPC_FLOAT       = 0x0000000000000002ULL,
 322     /* more floating point operations instructions */
 323     PPC_FLOAT_EXT   = 0x0000000000000004ULL,
 324     /* external control instructions               */
 325     PPC_EXTERN      = 0x0000000000000008ULL,
 326     /* segment register access instructions        */
 327     PPC_SEGMENT     = 0x0000000000000010ULL,
 328     /* Optional cache control instructions         */
 329     PPC_CACHE_OPT   = 0x0000000000000020ULL,
 330     /* Optional floating point op instructions     */
 331     PPC_FLOAT_OPT   = 0x0000000000000040ULL,
 332     /* Optional memory control instructions        */
 333     PPC_MEM_TLBIA   = 0x0000000000000080ULL,
 334     PPC_MEM_TLBIE   = 0x0000000000000100ULL,
 335     PPC_MEM_TLBSYNC = 0x0000000000000200ULL,
 336     /* eieio & sync                                */
 337     PPC_MEM_SYNC    = 0x0000000000000400ULL,
 338     /* PowerPC 6xx TLB management instructions     */
 339     PPC_6xx_TLB     = 0x0000000000000800ULL,
 340     /* Altivec support                             */
 341     PPC_ALTIVEC     = 0x0000000000001000ULL,
 342     /* Time base support                           */
 343     PPC_TB          = 0x0000000000002000ULL,
 344     /* Embedded PowerPC dedicated instructions     */
 345     PPC_EMB_COMMON  = 0x0000000000004000ULL,
 346     /* PowerPC 40x exception model                 */
 347     PPC_40x_EXCP    = 0x0000000000008000ULL,
 348     /* PowerPC 40x specific instructions           */
 349     PPC_40x_SPEC    = 0x0000000000010000ULL,
 350     /* PowerPC 405 Mac instructions                */
 351     PPC_405_MAC     = 0x0000000000020000ULL,
 352     /* PowerPC 440 specific instructions           */
 353     PPC_440_SPEC    = 0x0000000000040000ULL,
 354     /* Specific extensions */
 355     /* Power-to-PowerPC bridge (601)               */
 356     PPC_POWER_BR    = 0x0000000000080000ULL,
 357     /* PowerPC 602 specific */
 358     PPC_602_SPEC    = 0x0000000000100000ULL,
 359     /* Deprecated instructions                     */
 360     /* Original POWER instruction set              */
 361     PPC_POWER       = 0x0000000000200000ULL,
 362     /* POWER2 instruction set extension            */
 363     PPC_POWER2      = 0x0000000000400000ULL,
 364     /* Power RTC support */
 365     PPC_POWER_RTC   = 0x0000000000800000ULL,
 366     /* 64 bits PowerPC instructions                */
 367     /* 64 bits PowerPC instruction set             */
 368     PPC_64B         = 0x0000000001000000ULL,
 369     /* 64 bits hypervisor extensions               */
 370     PPC_64H         = 0x0000000002000000ULL,
 371     /* 64 bits PowerPC "bridge" features           */
 372     PPC_64_BRIDGE   = 0x0000000004000000ULL,
 373     /* BookE (embedded) PowerPC specification      */
 374     PPC_BOOKE       = 0x0000000008000000ULL,
 375     /* eieio */
 376     PPC_MEM_EIEIO   = 0x0000000010000000ULL,
 377     /* e500 vector instructions */
 378     PPC_E500_VECTOR = 0x0000000020000000ULL,
 379     /* PowerPC 4xx dedicated instructions     */
 380     PPC_4xx_COMMON  = 0x0000000040000000ULL,
 381     /* PowerPC 2.03 specification extensions */
 382     PPC_203         = 0x0000000080000000ULL,
 383     /* PowerPC 2.03 SPE extension */
 384     PPC_SPE         = 0x0000000100000000ULL,
 385     /* PowerPC 2.03 SPE floating-point extension */
 386     PPC_SPEFPU      = 0x0000000200000000ULL,
 387 };
 388
 389 /* CPU run-time flags (MMU and exception model) */
 390 enum {
 391     /* MMU model */
 392     PPC_FLAGS_MMU_MASK     = 0x0000000F,
 393     /* Standard 32 bits PowerPC MMU */
 394     PPC_FLAGS_MMU_32B      = 0x00000000,
 395     /* Standard 64 bits PowerPC MMU */
 396     PPC_FLAGS_MMU_64B      = 0x00000001,
 397     /* PowerPC 601 MMU */
 398     PPC_FLAGS_MMU_601      = 0x00000002,
 399     /* PowerPC 6xx MMU with software TLB */
 400     PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
 401     /* PowerPC 4xx MMU with software TLB */
 402     PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
 403     /* PowerPC 403 MMU */
 404     PPC_FLAGS_MMU_403      = 0x00000005,
 405     /* Freescale e500 MMU model */
 406     PPC_FLAGS_MMU_e500     = 0x00000006,
 407     /* BookE MMU model */
 408     PPC_FLAGS_MMU_BOOKE    = 0x00000007,
 409     /* Exception model */
 410     PPC_FLAGS_EXCP_MASK    = 0x000000F0,
 411     /* Standard PowerPC exception model */
 412     PPC_FLAGS_EXCP_STD     = 0x00000000,
 413     /* PowerPC 40x exception model */
 414     PPC_FLAGS_EXCP_40x     = 0x00000010,
 415     /* PowerPC 601 exception model */
 416     PPC_FLAGS_EXCP_601     = 0x00000020,
 417     /* PowerPC 602 exception model */
 418     PPC_FLAGS_EXCP_602     = 0x00000030,
 419     /* PowerPC 603 exception model */
 420     PPC_FLAGS_EXCP_603     = 0x00000040,
 421     /* PowerPC 604 exception model */
 422     PPC_FLAGS_EXCP_604     = 0x00000050,
 423     /* PowerPC 7x0 exception model */
 424     PPC_FLAGS_EXCP_7x0     = 0x00000060,
 425     /* PowerPC 7x5 exception model */
 426     PPC_FLAGS_EXCP_7x5     = 0x00000070,
 427     /* PowerPC 74xx exception model */
 428     PPC_FLAGS_EXCP_74xx    = 0x00000080,
 429     /* PowerPC 970 exception model */
 430     PPC_FLAGS_EXCP_970     = 0x00000090,
 431     /* BookE exception model */
 432     PPC_FLAGS_EXCP_BOOKE   = 0x000000A0,
 433 };
 434
 435 #define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
 436 #define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
 437
 438 /*****************************************************************************/
 439 /* Supported instruction set definitions */
 440 /* This generates an empty opcode table... */
 441 #define PPC_INSNS_TODO (PPC_NONE)
 442 #define PPC_FLAGS_TODO (0x00000000)
 443
 444 /* PowerPC 40x instruction set */
 445 #define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON)
 446 /* PowerPC 401 */
 447 #define PPC_INSNS_401 (PPC_INSNS_TODO)
 448 #define PPC_FLAGS_401 (PPC_FLAGS_TODO)
 449 /* PowerPC 403 */
 450 #define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO |         \
 451                        PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP |        \
 452                        PPC_40x_SPEC)
 453 #define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
 454 /* PowerPC 405 */
 455 #define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO |         \
 456                        PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB |               \
 457                        PPC_4xx_COMMON | PPC_40x_SPEC |  PPC_40x_EXCP |        \
 458                        PPC_405_MAC)
 459 #define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
 460 /* PowerPC 440 */
 461 #define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE |            \
 462                        PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
 463 #define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)
 464 /* Generic BookE PowerPC */
 465 #define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO |          \
 466                          PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT)
 467 #define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)
 468 /* e500 core */
 469 #define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO |           \
 470                         PPC_CACHE_OPT | PPC_E500_VECTOR)
 471 #define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
 472 /* Non-embedded PowerPC */
 473 #define PPC_INSNS_COMMON  (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC |        \
 474                             PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
 475 /* PowerPC 601 */
 476 #define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
 477 #define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
 478 /* PowerPC 602 */
 479 #define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |       \
 480                        PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)
 481 #define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
 482 /* PowerPC 603 */
 483 #define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |       \
 484                        PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
 485 #define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
 486 /* PowerPC G2 */
 487 #define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |        \
 488                       PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
 489 #define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
 490 /* PowerPC 604 */
 491 #define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
 492                        PPC_MEM_TLBSYNC | PPC_TB)
 493 #define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)
 494 /* PowerPC 740/750 (aka G3) */
 495 #define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
 496                        PPC_MEM_TLBSYNC | PPC_TB)
 497 #define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)
 498 /* PowerPC 745/755 */
 499 #define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
 500                        PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
 501 #define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)
 502 /* PowerPC 74xx (aka G4) */
 503 #define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC |      \
 504                         PPC_MEM_TLBSYNC | PPC_TB)
 505 #define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)
 506
 507 /* Default PowerPC will be 604/970 */
 508 #define PPC_INSNS_PPC32 PPC_INSNS_604
 509 #define PPC_FLAGS_PPC32 PPC_FLAGS_604
 510 #if 0
 511 #define PPC_INSNS_PPC64 PPC_INSNS_970
 512 #define PPC_FLAGS_PPC64 PPC_FLAGS_970
 513 #endif
 514 #define PPC_INSNS_DEFAULT PPC_INSNS_604
 515 #define PPC_FLAGS_DEFAULT PPC_FLAGS_604
 516 typedef struct ppc_def_t ppc_def_t;
 517
 518 /*****************************************************************************/
 519 /* Types used to describe some PowerPC registers */
 520 typedef struct CPUPPCState CPUPPCState;
 521 typedef struct opc_handler_t opc_handler_t;
 522 typedef struct ppc_tb_t ppc_tb_t;
 523 typedef struct ppc_spr_t ppc_spr_t;
 524 typedef struct ppc_dcr_t ppc_dcr_t;
 525 typedef struct ppc_avr_t ppc_avr_t;
 526 typedef struct ppc_tlb_t ppc_tlb_t;
 527
 528 /* SPR access micro-ops generations callbacks */
 529 struct ppc_spr_t {
 530     void (*uea_read)(void *opaque, int spr_num);
 531     void (*uea_write)(void *opaque, int spr_num);
 532 #if !defined(CONFIG_USER_ONLY)
 533     void (*oea_read)(void *opaque, int spr_num);
 534     void (*oea_write)(void *opaque, int spr_num);
 535 #endif
 536     const unsigned char *name;
 537 };
 538
 539 /* Altivec registers (128 bits) */
 540 struct ppc_avr_t {
 541     uint32_t u[4];
 542 };
 543
 544 /* Software TLB cache */
 545 struct ppc_tlb_t {
 546     target_ulong pte0;
 547     target_ulong pte1;
 548     target_ulong EPN;
 549     target_ulong PID;
 550     int size;
 551 };
 552
 553 /*****************************************************************************/
 554 /* Machine state register bits definition                                    */
 555 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 556 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 557 #define MSR_HV   60 /* hypervisor state                               hflags */
 558 #define MSR_UCLE 26 /* User-mode cache lock enable on e500                   */
 559 #define MSR_VR   25 /* altivec available                              hflags */
 560 #define MSR_SPE  25 /* SPE enable on e500                             hflags */
 561 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
 562 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 563 #define MSR_KEY  19 /* key bit on 603e                                       */
 564 #define MSR_POW  18 /* Power management                                      */
 565 #define MSR_WE   18 /* Wait state enable on embedded PowerPC                 */
 566 #define MSR_TGPR 17 /* TGPR usage on 602/603                                 */
 567 #define MSR_TLB  17 /* TLB update on ?                                       */
 568 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC         */
 569 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
 570 #define MSR_EE   15 /* External interrupt enable                             */
 571 #define MSR_PR   14 /* Problem state                                  hflags */
 572 #define MSR_FP   13 /* Floating point available                       hflags */
 573 #define MSR_ME   12 /* Machine check interrupt enable                        */
 574 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
 575 #define MSR_SE   10 /* Single-step trace enable                       hflags */
 576 #define MSR_DWE  10 /* Debug wait enable on 405                              */
 577 #define MSR_UBLE 10 /* User BTB lock enable on e500                          */
 578 #define MSR_BE   9  /* Branch trace enable                            hflags */
 579 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC           */
 580 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 581 #define MSR_AL   7  /* AL bit on POWER                                       */
 582 #define MSR_IP   6  /* Interrupt prefix                                      */
 583 #define MSR_IR   5  /* Instruction relocate                                  */
 584 #define MSR_IS   5  /* Instruction address space on embedded PowerPC         */
 585 #define MSR_DR   4  /* Data relocate                                         */
 586 #define MSR_DS   4  /* Data address space on embedded PowerPC                */
 587 #define MSR_PE   3  /* Protection enable on 403                              */
 588 #define MSR_EP   3  /* Exception prefix on 601                               */
 589 #define MSR_PX   2  /* Protection exclusive on 403                           */
 590 #define MSR_PMM  2  /* Performance monitor mark on POWER                     */
 591 #define MSR_RI   1  /* Recoverable interrupt                                 */
 592 #define MSR_LE   0  /* Little-endian mode                             hflags */
 593 #define msr_sf   env->msr[MSR_SF]
 594 #define msr_isf  env->msr[MSR_ISF]
 595 #define msr_hv   env->msr[MSR_HV]
 596 #define msr_ucle env->msr[MSR_UCLE]
 597 #define msr_vr   env->msr[MSR_VR]
 598 #define msr_spe  env->msr[MSR_SPE]
 599 #define msr_ap   env->msr[MSR_AP]
 600 #define msr_sa   env->msr[MSR_SA]
 601 #define msr_key  env->msr[MSR_KEY]
 602 #define msr_pow  env->msr[MSR_POW]
 603 #define msr_we   env->msr[MSR_WE]
 604 #define msr_tgpr env->msr[MSR_TGPR]
 605 #define msr_tlb  env->msr[MSR_TLB]
 606 #define msr_ce   env->msr[MSR_CE]
 607 #define msr_ile  env->msr[MSR_ILE]
 608 #define msr_ee   env->msr[MSR_EE]
 609 #define msr_pr   env->msr[MSR_PR]
 610 #define msr_fp   env->msr[MSR_FP]
 611 #define msr_me   env->msr[MSR_ME]
 612 #define msr_fe0  env->msr[MSR_FE0]
 613 #define msr_se   env->msr[MSR_SE]
 614 #define msr_dwe  env->msr[MSR_DWE]
 615 #define msr_uble env->msr[MSR_UBLE]
 616 #define msr_be   env->msr[MSR_BE]
 617 #define msr_de   env->msr[MSR_DE]
 618 #define msr_fe1  env->msr[MSR_FE1]
 619 #define msr_al   env->msr[MSR_AL]
 620 #define msr_ip   env->msr[MSR_IP]
 621 #define msr_ir   env->msr[MSR_IR]
 622 #define msr_is   env->msr[MSR_IS]
 623 #define msr_dr   env->msr[MSR_DR]
 624 #define msr_ds   env->msr[MSR_DS]
 625 #define msr_pe   env->msr[MSR_PE]
 626 #define msr_ep   env->msr[MSR_EP]
 627 #define msr_px   env->msr[MSR_PX]
 628 #define msr_pmm  env->msr[MSR_PMM]
 629 #define msr_ri   env->msr[MSR_RI]
 630 #define msr_le   env->msr[MSR_LE]
 631
 632 /*****************************************************************************/
 633 /* The whole PowerPC CPU context */
 634 struct CPUPPCState {
 635     /* First are the most commonly used resources
 636      * during translated code execution
 637      */
 638 #if TARGET_GPR_BITS > HOST_LONG_BITS
 639     /* temporary fixed-point registers
 640      * used to emulate 64 bits target on 32 bits hosts
 641      */
 642     target_ulong t0, t1, t2;
 643 #endif
 644     ppc_avr_t t0_avr, t1_avr, t2_avr;
 645
 646     /* general purpose registers */
 647     ppc_gpr_t gpr[32];
 648     /* LR */
 649     target_ulong lr;
 650     /* CTR */
 651     target_ulong ctr;
 652     /* condition register */
 653     uint8_t crf[8];
 654     /* XER */
 655     /* XXX: We use only 5 fields, but we want to keep the structure aligned */
 656     uint8_t xer[8];
 657     /* Reservation address */
 658     target_ulong reserve;
 659
 660     /* Those ones are used in supervisor mode only */
 661     /* machine state register */
 662     uint8_t msr[64];
 663     /* temporary general purpose registers */
 664     ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
 665
 666     /* Floating point execution context */
 667     /* temporary float registers */
 668     float64 ft0;
 669     float64 ft1;
 670     float64 ft2;
 671     float_status fp_status;
 672     /* floating point registers */
 673     float64 fpr[32];
 674     /* floating point status and control register */
 675     uint8_t fpscr[8];
 676
 677     CPU_COMMON
 678
 679     int halted; /* TRUE if the CPU is in suspend state */
 680
 681     int access_type; /* when a memory exception occurs, the access
 682                         type is stored here */
 683
 684     /* MMU context */
 685     /* Address space register */
 686     target_ulong asr;
 687     /* segment registers */
 688     target_ulong sdr1;
 689     target_ulong sr[16];
 690     /* BATs */
 691     int nb_BATs;
 692     target_ulong DBAT[2][8];
 693     target_ulong IBAT[2][8];
 694
 695     /* Other registers */
 696     /* Special purpose registers */
 697     target_ulong spr[1024];
 698     /* Altivec registers */
 699     ppc_avr_t avr[32];
 700     uint32_t vscr;
 701     /* SPE registers */
 702     ppc_gpr_t spe_acc;
 703     float_status spe_status;
 704     uint32_t spe_fscr;
 705
 706     /* Internal devices resources */
 707     /* Time base and decrementer */
 708     ppc_tb_t *tb_env;
 709     /* Device control registers */
 710     int (*dcr_read)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong *val);
 711     int (*dcr_write)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong val);
 712     ppc_dcr_t *dcr_env;
 713
 714     /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
 715     int nb_tlb;      /* Total number of TLB                                  */
 716     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
 717     int nb_ways;     /* Number of ways in the TLB set                        */
 718     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
 719     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
 720     ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */
 721     /* Callbacks for specific checks on some implementations */
 722     int (*tlb_check_more)(CPUPPCState *env, struct ppc_tlb_t *tlb, int *prot,
 723                           target_ulong vaddr, int rw, int acc_type,
 724                           int is_user);
 725     /* 403 dedicated access protection registers */
 726     target_ulong pb[4];
 727
 728     /* Those resources are used during exception processing */
 729     /* CPU model definition */
 730     uint64_t msr_mask;
 731     uint32_t flags;
 732
 733     int exception_index;
 734     int error_code;
 735     int interrupt_request;
 736
 737     /* Those resources are used only during code translation */
 738     /* Next instruction pointer */
 739     target_ulong nip;
 740     /* SPR translation callbacks */
 741     ppc_spr_t spr_cb[1024];
 742     /* opcode handlers */
 743     opc_handler_t *opcodes[0x40];
 744
 745     /* Those resources are used only in Qemu core */
 746     jmp_buf jmp_env;
 747     int user_mode_only; /* user mode only simulation */
 748     uint32_t hflags;
 749
 750     /* Power management */
 751     int power_mode;
 752
 753     /* temporary hack to handle OSI calls (only used if non NULL) */
 754     int (*osi_call)(struct CPUPPCState *env);
 755 };
 756
 757 /* Context used internally during MMU translations */
 758 typedef struct mmu_ctx_t mmu_ctx_t;
 759 struct mmu_ctx_t {
 760     target_phys_addr_t raddr;      /* Real address              */
 761     int prot;                      /* Protection bits           */
 762     target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
 763     target_ulong ptem;             /* Virtual segment ID | API  */
 764     int key;                       /* Access key                */
 765 };
 766
 767 /*****************************************************************************/
 768 CPUPPCState *cpu_ppc_init(void);
 769 int cpu_ppc_exec(CPUPPCState *s);
 770 void cpu_ppc_close(CPUPPCState *s);
 771 /* you can call this signal handler from your SIGBUS and SIGSEGV
 772    signal handlers to inform the virtual CPU of exceptions. non zero
 773    is returned if the signal was handled by the virtual CPU.  */
 774 int cpu_ppc_signal_handler(int host_signum, void *pinfo,
 775                            void *puc);
 776
 777 void do_interrupt (CPUPPCState *env);
 778 void cpu_loop_exit(void);
 779
 780 void dump_stack (CPUPPCState *env);
 781
 782 #if !defined(CONFIG_USER_ONLY)
 783 target_ulong do_load_ibatu (CPUPPCState *env, int nr);
 784 target_ulong do_load_ibatl (CPUPPCState *env, int nr);
 785 void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
 786 void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
 787 target_ulong do_load_dbatu (CPUPPCState *env, int nr);
 788 target_ulong do_load_dbatl (CPUPPCState *env, int nr);
 789 void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
 790 void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
 791 target_ulong do_load_sdr1 (CPUPPCState *env);
 792 void do_store_sdr1 (CPUPPCState *env, target_ulong value);
 793 #if defined(TARGET_PPC64)
 794 target_ulong ppc_load_asr (CPUPPCState *env);
 795 void ppc_store_asr (CPUPPCState *env, target_ulong value);
 796 #endif
 797 target_ulong do_load_sr (CPUPPCState *env, int srnum);
 798 void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
 799 #endif
 800 uint32_t ppc_load_xer (CPUPPCState *env);
 801 void ppc_store_xer (CPUPPCState *env, uint32_t value);
 802 target_ulong do_load_msr (CPUPPCState *env);
 803 void do_store_msr (CPUPPCState *env, target_ulong value);
 804 void ppc_store_msr32 (CPUPPCState *env, uint32_t value);
 805
 806 void do_compute_hflags (CPUPPCState *env);
 807
 808 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
 809 int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
 810 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 811 int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
 812
 813 /* Time-base and decrementer management */
 814 #ifndef NO_CPU_IO_DEFS
 815 uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
 816 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
 817 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
 818 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
 819 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
 820 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
 821 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
 822 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
 823 #if !defined(CONFIG_USER_ONLY)
 824 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
 825 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
 826 target_ulong load_40x_pit (CPUPPCState *env);
 827 void store_40x_pit (CPUPPCState *env, target_ulong val);
 828 void store_booke_tcr (CPUPPCState *env, target_ulong val);
 829 void store_booke_tsr (CPUPPCState *env, target_ulong val);
 830 #endif
 831 #endif
 832
 833 #define TARGET_PAGE_BITS 12
 834 #include "cpu-all.h"
 835
 836 /*****************************************************************************/
 837 /* Registers definitions */
 838 #define ugpr(n) (env->gpr[n])
 839
 840 #define XER_SO 31
 841 #define XER_OV 30
 842 #define XER_CA 29
 843 #define XER_CMP 8
 844 #define XER_BC 0
 845 #define xer_so  env->xer[4]
 846 #define xer_ov  env->xer[6]
 847 #define xer_ca  env->xer[2]
 848 #define xer_cmp env->xer[1]
 849 #define xer_bc env->xer[0]
 850
 851 /* SPR definitions */
 852 #define SPR_MQ           (0x000)
 853 #define SPR_XER          (0x001)
 854 #define SPR_601_VRTCU    (0x004)
 855 #define SPR_601_VRTCL    (0x005)
 856 #define SPR_601_UDECR    (0x006)
 857 #define SPR_LR           (0x008)
 858 #define SPR_CTR          (0x009)
 859 #define SPR_DSISR        (0x012)
 860 #define SPR_DAR          (0x013)
 861 #define SPR_601_RTCU     (0x014)
 862 #define SPR_601_RTCL     (0x015)
 863 #define SPR_DECR         (0x016)
 864 #define SPR_SDR1         (0x019)
 865 #define SPR_SRR0         (0x01A)
 866 #define SPR_SRR1         (0x01B)
 867 #define SPR_BOOKE_PID    (0x030)
 868 #define SPR_BOOKE_DECAR  (0x036)
 869 #define SPR_CSRR0        (0x03A)
 870 #define SPR_CSRR1        (0x03B)
 871 #define SPR_BOOKE_DEAR   (0x03D)
 872 #define SPR_BOOKE_ESR    (0x03E)
 873 #define SPR_BOOKE_EVPR   (0x03F)
 874 #define SPR_8xx_EIE      (0x050)
 875 #define SPR_8xx_EID      (0x051)
 876 #define SPR_8xx_NRE      (0x052)
 877 #define SPR_58x_CMPA     (0x090)
 878 #define SPR_58x_CMPB     (0x091)
 879 #define SPR_58x_CMPC     (0x092)
 880 #define SPR_58x_CMPD     (0x093)
 881 #define SPR_58x_ICR      (0x094)
 882 #define SPR_58x_DER      (0x094)
 883 #define SPR_58x_COUNTA   (0x096)
 884 #define SPR_58x_COUNTB   (0x097)
 885 #define SPR_58x_CMPE     (0x098)
 886 #define SPR_58x_CMPF     (0x099)
 887 #define SPR_58x_CMPG     (0x09A)
 888 #define SPR_58x_CMPH     (0x09B)
 889 #define SPR_58x_LCTRL1   (0x09C)
 890 #define SPR_58x_LCTRL2   (0x09D)
 891 #define SPR_58x_ICTRL    (0x09E)
 892 #define SPR_58x_BAR      (0x09F)
 893 #define SPR_VRSAVE       (0x100)
 894 #define SPR_USPRG0       (0x100)
 895 #define SPR_USPRG4       (0x104)
 896 #define SPR_USPRG5       (0x105)
 897 #define SPR_USPRG6       (0x106)
 898 #define SPR_USPRG7       (0x107)
 899 #define SPR_VTBL         (0x10C)
 900 #define SPR_VTBU         (0x10D)
 901 #define SPR_SPRG0        (0x110)
 902 #define SPR_SPRG1        (0x111)
 903 #define SPR_SPRG2        (0x112)
 904 #define SPR_SPRG3        (0x113)
 905 #define SPR_SPRG4        (0x114)
 906 #define SPR_SCOMC        (0x114)
 907 #define SPR_SPRG5        (0x115)
 908 #define SPR_SCOMD        (0x115)
 909 #define SPR_SPRG6        (0x116)
 910 #define SPR_SPRG7        (0x117)
 911 #define SPR_ASR          (0x118)
 912 #define SPR_EAR          (0x11A)
 913 #define SPR_TBL          (0x11C)
 914 #define SPR_TBU          (0x11D)
 915 #define SPR_SVR          (0x11E)
 916 #define SPR_BOOKE_PIR    (0x11E)
 917 #define SPR_PVR          (0x11F)
 918 #define SPR_HSPRG0       (0x130)
 919 #define SPR_BOOKE_DBSR   (0x130)
 920 #define SPR_HSPRG1       (0x131)
 921 #define SPR_BOOKE_DBCR0  (0x134)
 922 #define SPR_IBCR         (0x135)
 923 #define SPR_BOOKE_DBCR1  (0x135)
 924 #define SPR_DBCR         (0x136)
 925 #define SPR_HDEC         (0x136)
 926 #define SPR_BOOKE_DBCR2  (0x136)
 927 #define SPR_HIOR         (0x137)
 928 #define SPR_MBAR         (0x137)
 929 #define SPR_RMOR         (0x138)
 930 #define SPR_BOOKE_IAC1   (0x138)
 931 #define SPR_HRMOR        (0x139)
 932 #define SPR_BOOKE_IAC2   (0x139)
 933 #define SPR_HSSR0        (0x13A)
 934 #define SPR_BOOKE_IAC3   (0x13A)
 935 #define SPR_HSSR1        (0x13B)
 936 #define SPR_BOOKE_IAC4   (0x13B)
 937 #define SPR_LPCR         (0x13C)
 938 #define SPR_BOOKE_DAC1   (0x13C)
 939 #define SPR_LPIDR        (0x13D)
 940 #define SPR_DABR2        (0x13D)
 941 #define SPR_BOOKE_DAC2   (0x13D)
 942 #define SPR_BOOKE_DVC1   (0x13E)
 943 #define SPR_BOOKE_DVC2   (0x13F)
 944 #define SPR_BOOKE_TSR    (0x150)
 945 #define SPR_BOOKE_TCR    (0x154)
 946 #define SPR_BOOKE_IVOR0  (0x190)
 947 #define SPR_BOOKE_IVOR1  (0x191)
 948 #define SPR_BOOKE_IVOR2  (0x192)
 949 #define SPR_BOOKE_IVOR3  (0x193)
 950 #define SPR_BOOKE_IVOR4  (0x194)
 951 #define SPR_BOOKE_IVOR5  (0x195)
 952 #define SPR_BOOKE_IVOR6  (0x196)
 953 #define SPR_BOOKE_IVOR7  (0x197)
 954 #define SPR_BOOKE_IVOR8  (0x198)
 955 #define SPR_BOOKE_IVOR9  (0x199)
 956 #define SPR_BOOKE_IVOR10 (0x19A)
 957 #define SPR_BOOKE_IVOR11 (0x19B)
 958 #define SPR_BOOKE_IVOR12 (0x19C)
 959 #define SPR_BOOKE_IVOR13 (0x19D)
 960 #define SPR_BOOKE_IVOR14 (0x19E)
 961 #define SPR_BOOKE_IVOR15 (0x19F)
 962 #define SPR_E500_SPEFSCR (0x200)
 963 #define SPR_E500_BBEAR   (0x201)
 964 #define SPR_E500_BBTAR   (0x202)
 965 #define SPR_BOOKE_ATBL   (0x20E)
 966 #define SPR_BOOKE_ATBU   (0x20F)
 967 #define SPR_IBAT0U       (0x210)
 968 #define SPR_E500_IVOR32  (0x210)
 969 #define SPR_IBAT0L       (0x211)
 970 #define SPR_E500_IVOR33  (0x211)
 971 #define SPR_IBAT1U       (0x212)
 972 #define SPR_E500_IVOR34  (0x212)
 973 #define SPR_IBAT1L       (0x213)
 974 #define SPR_E500_IVOR35  (0x213)
 975 #define SPR_IBAT2U       (0x214)
 976 #define SPR_IBAT2L       (0x215)
 977 #define SPR_E500_L1CFG0  (0x215)
 978 #define SPR_IBAT3U       (0x216)
 979 #define SPR_E500_L1CFG1  (0x216)
 980 #define SPR_IBAT3L       (0x217)
 981 #define SPR_DBAT0U       (0x218)
 982 #define SPR_DBAT0L       (0x219)
 983 #define SPR_DBAT1U       (0x21A)
 984 #define SPR_DBAT1L       (0x21B)
 985 #define SPR_DBAT2U       (0x21C)
 986 #define SPR_DBAT2L       (0x21D)
 987 #define SPR_DBAT3U       (0x21E)
 988 #define SPR_DBAT3L       (0x21F)
 989 #define SPR_IBAT4U       (0x230)
 990 #define SPR_IBAT4L       (0x231)
 991 #define SPR_IBAT5U       (0x232)
 992 #define SPR_IBAT5L       (0x233)
 993 #define SPR_IBAT6U       (0x234)
 994 #define SPR_IBAT6L       (0x235)
 995 #define SPR_IBAT7U       (0x236)
 996 #define SPR_IBAT7L       (0x237)
 997 #define SPR_DBAT4U       (0x238)
 998 #define SPR_DBAT4L       (0x239)
 999 #define SPR_DBAT5U       (0x23A)
1000 #define SPR_E500_MCSRR0  (0x23A)
1001 #define SPR_DBAT5L       (0x23B)
1002 #define SPR_E500_MCSRR1  (0x23B)
1003 #define SPR_DBAT6U       (0x23C)
1004 #define SPR_E500_MCSR    (0x23C)
1005 #define SPR_DBAT6L       (0x23D)
1006 #define SPR_E500_MCAR    (0x23D)
1007 #define SPR_DBAT7U       (0x23E)
1008 #define SPR_DBAT7L       (0x23F)
1009 #define SPR_E500_MAS0    (0x270)
1010 #define SPR_E500_MAS1    (0x271)
1011 #define SPR_E500_MAS2    (0x272)
1012 #define SPR_E500_MAS3    (0x273)
1013 #define SPR_E500_MAS4    (0x274)
1014 #define SPR_E500_MAS6    (0x276)
1015 #define SPR_E500_PID1    (0x279)
1016 #define SPR_E500_PID2    (0x27A)
1017 #define SPR_E500_TLB0CFG (0x2B0)
1018 #define SPR_E500_TLB1CFG (0x2B1)
1019 #define SPR_440_INV0     (0x370)
1020 #define SPR_440_INV1     (0x371)
1021 #define SPR_440_INV2     (0x372)
1022 #define SPR_440_INV3     (0x373)
1023 #define SPR_440_IVT0     (0x374)
1024 #define SPR_440_IVT1     (0x375)
1025 #define SPR_440_IVT2     (0x376)
1026 #define SPR_440_IVT3     (0x377)
1027 #define SPR_440_DNV0     (0x390)
1028 #define SPR_440_DNV1     (0x391)
1029 #define SPR_440_DNV2     (0x392)
1030 #define SPR_440_DNV3     (0x393)
1031 #define SPR_440_DVT0     (0x394)
1032 #define SPR_440_DVT1     (0x395)
1033 #define SPR_440_DVT2     (0x396)
1034 #define SPR_440_DVT3     (0x397)
1035 #define SPR_440_DVLIM    (0x398)
1036 #define SPR_440_IVLIM    (0x399)
1037 #define SPR_440_RSTCFG   (0x39B)
1038 #define SPR_440_DCBTRL   (0x39C)
1039 #define SPR_440_DCBTRH   (0x39D)
1040 #define SPR_440_ICBTRL   (0x39E)
1041 #define SPR_440_ICBTRH   (0x39F)
1042 #define SPR_UMMCR0       (0x3A8)
1043 #define SPR_UPMC1        (0x3A9)
1044 #define SPR_UPMC2        (0x3AA)
1045 #define SPR_USIA         (0x3AB)
1046 #define SPR_UMMCR1       (0x3AC)
1047 #define SPR_UPMC3        (0x3AD)
1048 #define SPR_UPMC4        (0x3AE)
1049 #define SPR_USDA         (0x3AF)
1050 #define SPR_40x_ZPR      (0x3B0)
1051 #define SPR_E500_MAS7    (0x3B0)
1052 #define SPR_40x_PID      (0x3B1)
1053 #define SPR_440_MMUCR    (0x3B2)
1054 #define SPR_4xx_CCR0     (0x3B3)
1055 #define SPR_405_IAC3     (0x3B4)
1056 #define SPR_405_IAC4     (0x3B5)
1057 #define SPR_405_DVC1     (0x3B6)
1058 #define SPR_405_DVC2     (0x3B7)
1059 #define SPR_MMCR0        (0x3B8)
1060 #define SPR_PMC1         (0x3B9)
1061 #define SPR_40x_SGR      (0x3B9)
1062 #define SPR_PMC2         (0x3BA)
1063 #define SPR_40x_DCWR     (0x3BA)
1064 #define SPR_SIA          (0x3BB)
1065 #define SPR_405_SLER     (0x3BB)
1066 #define SPR_MMCR1        (0x3BC)
1067 #define SPR_405_SU0R     (0x3BC)
1068 #define SPR_PMC3         (0x3BD)
1069 #define SPR_405_DBCR1    (0x3BD)
1070 #define SPR_PMC4         (0x3BE)
1071 #define SPR_SDA          (0x3BF)
1072 #define SPR_403_VTBL     (0x3CC)
1073 #define SPR_403_VTBU     (0x3CD)
1074 #define SPR_DMISS        (0x3D0)
1075 #define SPR_DCMP         (0x3D1)
1076 #define SPR_HASH1        (0x3D2)
1077 #define SPR_HASH2        (0x3D3)
1078 #define SPR_4xx_ICDBDR   (0x3D3)
1079 #define SPR_IMISS        (0x3D4)
1080 #define SPR_40x_ESR      (0x3D4)
1081 #define SPR_ICMP         (0x3D5)
1082 #define SPR_40x_DEAR     (0x3D5)
1083 #define SPR_RPA          (0x3D6)
1084 #define SPR_40x_EVPR     (0x3D6)
1085 #define SPR_403_CDBCR    (0x3D7)
1086 #define SPR_TCR          (0x3D8)
1087 #define SPR_40x_TSR      (0x3D8)
1088 #define SPR_IBR          (0x3DA)
1089 #define SPR_40x_TCR      (0x3DA)
1090 #define SPR_ESASR        (0x3DB)
1091 #define SPR_40x_PIT      (0x3DB)
1092 #define SPR_403_TBL      (0x3DC)
1093 #define SPR_403_TBU      (0x3DD)
1094 #define SPR_SEBR         (0x3DE)
1095 #define SPR_40x_SRR2     (0x3DE)
1096 #define SPR_SER          (0x3DF)
1097 #define SPR_40x_SRR3     (0x3DF)
1098 #define SPR_HID0         (0x3F0)
1099 #define SPR_40x_DBSR     (0x3F0)
1100 #define SPR_HID1         (0x3F1)
1101 #define SPR_IABR         (0x3F2)
1102 #define SPR_40x_DBCR0    (0x3F2)
1103 #define SPR_601_HID2     (0x3F2)
1104 #define SPR_E500_L1CSR0  (0x3F2)
1105 #define SPR_HID2         (0x3F3)
1106 #define SPR_E500_L1CSR1  (0x3F3)
1107 #define SPR_440_DBDR     (0x3F3)
1108 #define SPR_40x_IAC1     (0x3F4)
1109 #define SPR_E500_MMUCSR0 (0x3F4)
1110 #define SPR_DABR         (0x3F5)
1111 #define DABR_MASK (~(target_ulong)0x7)
1112 #define SPR_E500_BUCSR   (0x3F5)
1113 #define SPR_40x_IAC2     (0x3F5)
1114 #define SPR_601_HID5     (0x3F5)
1115 #define SPR_40x_DAC1     (0x3F6)
1116 #define SPR_40x_DAC2     (0x3F7)
1117 #define SPR_E500_MMUCFG  (0x3F7)
1118 #define SPR_L2PM         (0x3F8)
1119 #define SPR_750_HID2     (0x3F8)
1120 #define SPR_L2CR         (0x3F9)
1121 #define SPR_IABR2        (0x3FA)
1122 #define SPR_40x_DCCR     (0x3FA)
1123 #define SPR_ICTC         (0x3FB)
1124 #define SPR_40x_ICCR     (0x3FB)
1125 #define SPR_THRM1        (0x3FC)
1126 #define SPR_403_PBL1     (0x3FC)
1127 #define SPR_SP           (0x3FD)
1128 #define SPR_THRM2        (0x3FD)
1129 #define SPR_403_PBU1     (0x3FD)
1130 #define SPR_LT           (0x3FE)
1131 #define SPR_THRM3        (0x3FE)
1132 #define SPR_FPECR        (0x3FE)
1133 #define SPR_403_PBL2     (0x3FE)
1134 #define SPR_PIR          (0x3FF)
1135 #define SPR_403_PBU2     (0x3FF)
1136 #define SPR_601_HID15    (0x3FF)
1137 #define SPR_E500_SVR     (0x3FF)
1138
1139 /*****************************************************************************/
1140 /* Memory access type :
1141  * may be needed for precise access rights control and precise exceptions.
1142  */
1143 enum {
1144     /* 1 bit to define user level / supervisor access */
1145     ACCESS_USER  = 0x00,
1146     ACCESS_SUPER = 0x01,
1147     /* Type of instruction that generated the access */
1148     ACCESS_CODE  = 0x10, /* Code fetch access                */
1149     ACCESS_INT   = 0x20, /* Integer load/store access        */
1150     ACCESS_FLOAT = 0x30, /* floating point load/store access */
1151     ACCESS_RES   = 0x40, /* load/store with reservation      */
1152     ACCESS_EXT   = 0x50, /* external access                  */
1153     ACCESS_CACHE = 0x60, /* Cache manipulation               */
1154 };
1155
1156 /*****************************************************************************/
1157 /* Exceptions */
1158 #define EXCP_NONE          -1
1159 /* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */
1160 #define EXCP_RESET         0x0100 /* System reset                            */
1161 #define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception                 */
1162 #define EXCP_DSI           0x0300 /* Data storage exception                  */
1163 #define EXCP_DSEG          0x0380 /* Data segment exception                  */
1164 #define EXCP_ISI           0x0400 /* Instruction storage exception           */
1165 #define EXCP_ISEG          0x0480 /* Instruction segment exception           */
1166 #define EXCP_EXTERNAL      0x0500 /* External interruption                   */
1167 #define EXCP_ALIGN         0x0600 /* Alignment exception                     */
1168 #define EXCP_PROGRAM       0x0700 /* Program exception                       */
1169 #define EXCP_NO_FP         0x0800 /* Floating point unavailable exception    */
1170 #define EXCP_DECR          0x0900 /* Decrementer exception                   */
1171 #define EXCP_HDECR         0x0980 /* Hypervisor decrementer exception        */
1172 #define EXCP_SYSCALL       0x0C00 /* System call                             */
1173 #define EXCP_TRACE         0x0D00 /* Trace exception                         */
1174 #define EXCP_PERF          0x0F00 /* Performance monitor exception           */
1175 /* Exceptions defined in PowerPC 32 bits programming environment manual      */
1176 #define EXCP_FP_ASSIST     0x0E00 /* Floating-point assist                   */
1177 /* Implementation specific exceptions                                        */
1178 /* 40x exceptions                                                            */
1179 #define EXCP_40x_PIT       0x1000 /* Programmable interval timer interrupt   */
1180 #define EXCP_40x_FIT       0x1010 /* Fixed interval timer interrupt          */
1181 #define EXCP_40x_WATCHDOG  0x1020 /* Watchdog timer exception                */
1182 #define EXCP_40x_DTLBMISS  0x1100 /* Data TLB miss exception                 */
1183 #define EXCP_40x_ITLBMISS  0x1200 /* Instruction TLB miss exception          */
1184 #define EXCP_40x_DEBUG     0x2000 /* Debug exception                         */
1185 /* 405 specific exceptions                                                   */
1186 #define EXCP_405_APU       0x0F20 /* APU unavailable exception               */
1187 /* TLB assist exceptions (602/603)                                           */
1188 #define EXCP_I_TLBMISS     0x1000 /* Instruction TLB miss                    */
1189 #define EXCP_DL_TLBMISS    0x1100 /* Data load TLB miss                      */
1190 #define EXCP_DS_TLBMISS    0x1200 /* Data store TLB miss                     */
1191 /* Breakpoint exceptions (602/603/604/620/740/745/750/755...)                */
1192 #define EXCP_IABR          0x1300 /* Instruction address breakpoint          */
1193 #define EXCP_SMI           0x1400 /* System management interrupt             */
1194 /* Altivec related exceptions                                                */
1195 #define EXCP_VPU           0x0F20 /* VPU unavailable exception               */
1196 /* 601 specific exceptions                                                   */
1197 #define EXCP_601_IO        0x0600 /* IO error exception                      */
1198 #define EXCP_601_RUNM      0x2000 /* Run mode exception                      */
1199 /* 602 specific exceptions                                                   */
1200 #define EXCP_602_WATCHDOG  0x1500 /* Watchdog exception                      */
1201 #define EXCP_602_EMUL      0x1600 /* Emulation trap exception                */
1202 /* G2 specific exceptions                                                    */
1203 #define EXCP_G2_CRIT       0x0A00 /* Critical interrupt                      */
1204 /* MPC740/745/750 & IBM 750 specific exceptions                              */
1205 #define EXCP_THRM          0x1700 /* Thermal management interrupt            */
1206 /* 74xx specific exceptions                                                  */
1207 #define EXCP_74xx_VPUA     0x1600 /* VPU assist exception                    */
1208 /* 970FX specific exceptions                                                 */
1209 #define EXCP_970_SOFTP     0x1500 /* Soft patch exception                    */
1210 #define EXCP_970_MAINT     0x1600 /* Maintenance exception                   */
1211 #define EXCP_970_THRM      0x1800 /* Thermal exception                       */
1212 #define EXCP_970_VPUA      0x1700 /* VPU assist exception                    */
1213 /* SPE related exceptions                                                    */
1214 #define EXCP_NO_SPE        0x0F20 /* SPE unavailable exception               */
1215 /* End of exception vectors area                                             */
1216 #define EXCP_PPC_MAX       0x4000
1217 /* Qemu exceptions: special cases we want to stop translation                */
1218 #define EXCP_MTMSR         0x11000 /* mtmsr instruction:                     */
1219                                    /* may change privilege level             */
1220 #define EXCP_BRANCH        0x11001 /* branch instruction                     */
1221 #define EXCP_SYSCALL_USER  0x12000 /* System call in user mode only          */
1222 #define EXCP_INTERRUPT_CRITICAL 0x13000 /* critical IRQ                      */
1223
1224 /* Error codes */
1225 enum {
1226     /* Exception subtypes for EXCP_ALIGN                            */
1227     EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception           */
1228     EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store */
1229     EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access    */
1230     EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary */
1231     EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary  */
1232     EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access           */
1233     /* Exception subtypes for EXCP_PROGRAM                          */
1234     /* FP exceptions */
1235     EXCP_FP            = 0x10,
1236     EXCP_FP_OX         = 0x01,  /* FP overflow                      */
1237     EXCP_FP_UX         = 0x02,  /* FP underflow                     */
1238     EXCP_FP_ZX         = 0x03,  /* FP divide by zero                */
1239     EXCP_FP_XX         = 0x04,  /* FP inexact                       */
1240     EXCP_FP_VXNAN      = 0x05,  /* FP invalid SNaN op               */
1241     EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite substraction */
1242     EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide       */
1243     EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide           */
1244     EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero       */
1245     EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare               */
1246     EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation             */
1247     EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root           */
1248     EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion    */
1249     /* Invalid instruction */
1250     EXCP_INVAL         = 0x20,
1251     EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction              */
1252     EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction         */
1253     EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access               */
1254     EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr */
1255     /* Privileged instruction */
1256     EXCP_PRIV          = 0x30,
1257     EXCP_PRIV_OPC      = 0x01,
1258     EXCP_PRIV_REG      = 0x02,
1259     /* Trap */
1260     EXCP_TRAP          = 0x40,
1261 };
1262
1263 /*****************************************************************************/
1264
1265 #endif /* !defined (__CPU_PPC_H__) */