Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions
[qemu/mini2440.git] / gdbstub.c
blobb8198ee29fdf30ad9e7e2ec0a3742ef3923b1e4d
1 /*
2 * gdb server stub
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
20 #include "config.h"
21 #include "qemu-common.h"
22 #ifdef CONFIG_USER_ONLY
23 #include <stdlib.h>
24 #include <stdio.h>
25 #include <stdarg.h>
26 #include <string.h>
27 #include <errno.h>
28 #include <unistd.h>
29 #include <fcntl.h>
31 #include "qemu.h"
32 #else
33 #include "qemu-char.h"
34 #include "sysemu.h"
35 #include "gdbstub.h"
36 #endif
38 #define MAX_PACKET_LENGTH 4096
40 #include "qemu_socket.h"
43 enum {
44 GDB_SIGNAL_0 = 0,
45 GDB_SIGNAL_INT = 2,
46 GDB_SIGNAL_TRAP = 5,
47 GDB_SIGNAL_UNKNOWN = 143
50 #ifdef CONFIG_USER_ONLY
52 /* Map target signal numbers to GDB protocol signal numbers and vice
53 * versa. For user emulation's currently supported systems, we can
54 * assume most signals are defined.
57 static int gdb_signal_table[] = {
59 TARGET_SIGHUP,
60 TARGET_SIGINT,
61 TARGET_SIGQUIT,
62 TARGET_SIGILL,
63 TARGET_SIGTRAP,
64 TARGET_SIGABRT,
65 -1, /* SIGEMT */
66 TARGET_SIGFPE,
67 TARGET_SIGKILL,
68 TARGET_SIGBUS,
69 TARGET_SIGSEGV,
70 TARGET_SIGSYS,
71 TARGET_SIGPIPE,
72 TARGET_SIGALRM,
73 TARGET_SIGTERM,
74 TARGET_SIGURG,
75 TARGET_SIGSTOP,
76 TARGET_SIGTSTP,
77 TARGET_SIGCONT,
78 TARGET_SIGCHLD,
79 TARGET_SIGTTIN,
80 TARGET_SIGTTOU,
81 TARGET_SIGIO,
82 TARGET_SIGXCPU,
83 TARGET_SIGXFSZ,
84 TARGET_SIGVTALRM,
85 TARGET_SIGPROF,
86 TARGET_SIGWINCH,
87 -1, /* SIGLOST */
88 TARGET_SIGUSR1,
89 TARGET_SIGUSR2,
90 TARGET_SIGPWR,
91 -1, /* SIGPOLL */
92 -1,
93 -1,
94 -1,
95 -1,
96 -1,
97 -1,
98 -1,
99 -1,
103 __SIGRTMIN + 1,
104 __SIGRTMIN + 2,
105 __SIGRTMIN + 3,
106 __SIGRTMIN + 4,
107 __SIGRTMIN + 5,
108 __SIGRTMIN + 6,
109 __SIGRTMIN + 7,
110 __SIGRTMIN + 8,
111 __SIGRTMIN + 9,
112 __SIGRTMIN + 10,
113 __SIGRTMIN + 11,
114 __SIGRTMIN + 12,
115 __SIGRTMIN + 13,
116 __SIGRTMIN + 14,
117 __SIGRTMIN + 15,
118 __SIGRTMIN + 16,
119 __SIGRTMIN + 17,
120 __SIGRTMIN + 18,
121 __SIGRTMIN + 19,
122 __SIGRTMIN + 20,
123 __SIGRTMIN + 21,
124 __SIGRTMIN + 22,
125 __SIGRTMIN + 23,
126 __SIGRTMIN + 24,
127 __SIGRTMIN + 25,
128 __SIGRTMIN + 26,
129 __SIGRTMIN + 27,
130 __SIGRTMIN + 28,
131 __SIGRTMIN + 29,
132 __SIGRTMIN + 30,
133 __SIGRTMIN + 31,
134 -1, /* SIGCANCEL */
135 __SIGRTMIN,
136 __SIGRTMIN + 32,
137 __SIGRTMIN + 33,
138 __SIGRTMIN + 34,
139 __SIGRTMIN + 35,
140 __SIGRTMIN + 36,
141 __SIGRTMIN + 37,
142 __SIGRTMIN + 38,
143 __SIGRTMIN + 39,
144 __SIGRTMIN + 40,
145 __SIGRTMIN + 41,
146 __SIGRTMIN + 42,
147 __SIGRTMIN + 43,
148 __SIGRTMIN + 44,
149 __SIGRTMIN + 45,
150 __SIGRTMIN + 46,
151 __SIGRTMIN + 47,
152 __SIGRTMIN + 48,
153 __SIGRTMIN + 49,
154 __SIGRTMIN + 50,
155 __SIGRTMIN + 51,
156 __SIGRTMIN + 52,
157 __SIGRTMIN + 53,
158 __SIGRTMIN + 54,
159 __SIGRTMIN + 55,
160 __SIGRTMIN + 56,
161 __SIGRTMIN + 57,
162 __SIGRTMIN + 58,
163 __SIGRTMIN + 59,
164 __SIGRTMIN + 60,
165 __SIGRTMIN + 61,
166 __SIGRTMIN + 62,
167 __SIGRTMIN + 63,
168 __SIGRTMIN + 64,
169 __SIGRTMIN + 65,
170 __SIGRTMIN + 66,
171 __SIGRTMIN + 67,
172 __SIGRTMIN + 68,
173 __SIGRTMIN + 69,
174 __SIGRTMIN + 70,
175 __SIGRTMIN + 71,
176 __SIGRTMIN + 72,
177 __SIGRTMIN + 73,
178 __SIGRTMIN + 74,
179 __SIGRTMIN + 75,
180 __SIGRTMIN + 76,
181 __SIGRTMIN + 77,
182 __SIGRTMIN + 78,
183 __SIGRTMIN + 79,
184 __SIGRTMIN + 80,
185 __SIGRTMIN + 81,
186 __SIGRTMIN + 82,
187 __SIGRTMIN + 83,
188 __SIGRTMIN + 84,
189 __SIGRTMIN + 85,
190 __SIGRTMIN + 86,
191 __SIGRTMIN + 87,
192 __SIGRTMIN + 88,
193 __SIGRTMIN + 89,
194 __SIGRTMIN + 90,
195 __SIGRTMIN + 91,
196 __SIGRTMIN + 92,
197 __SIGRTMIN + 93,
198 __SIGRTMIN + 94,
199 __SIGRTMIN + 95,
200 -1, /* SIGINFO */
201 -1, /* UNKNOWN */
202 -1, /* DEFAULT */
210 #else
211 /* In system mode we only need SIGINT and SIGTRAP; other signals
212 are not yet supported. */
214 enum {
215 TARGET_SIGINT = 2,
216 TARGET_SIGTRAP = 5
219 static int gdb_signal_table[] = {
222 TARGET_SIGINT,
225 TARGET_SIGTRAP
227 #endif
229 #ifdef CONFIG_USER_ONLY
230 static int target_signal_to_gdb (int sig)
232 int i;
233 for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++)
234 if (gdb_signal_table[i] == sig)
235 return i;
236 return GDB_SIGNAL_UNKNOWN;
238 #endif
240 static int gdb_signal_to_target (int sig)
242 if (sig < ARRAY_SIZE (gdb_signal_table))
243 return gdb_signal_table[sig];
244 else
245 return -1;
248 //#define DEBUG_GDB
250 typedef struct GDBRegisterState {
251 int base_reg;
252 int num_regs;
253 gdb_reg_cb get_reg;
254 gdb_reg_cb set_reg;
255 const char *xml;
256 struct GDBRegisterState *next;
257 } GDBRegisterState;
259 enum RSState {
260 RS_IDLE,
261 RS_GETLINE,
262 RS_CHKSUM1,
263 RS_CHKSUM2,
264 RS_SYSCALL,
266 typedef struct GDBState {
267 CPUState *c_cpu; /* current CPU for step/continue ops */
268 CPUState *g_cpu; /* current CPU for other ops */
269 CPUState *query_cpu; /* for q{f|s}ThreadInfo */
270 enum RSState state; /* parsing state */
271 char line_buf[MAX_PACKET_LENGTH];
272 int line_buf_index;
273 int line_csum;
274 uint8_t last_packet[MAX_PACKET_LENGTH + 4];
275 int last_packet_len;
276 int signal;
277 #ifdef CONFIG_USER_ONLY
278 int fd;
279 int running_state;
280 #else
281 CharDriverState *chr;
282 #endif
283 } GDBState;
285 /* By default use no IRQs and no timers while single stepping so as to
286 * make single stepping like an ICE HW step.
288 static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
290 static GDBState *gdbserver_state;
292 /* This is an ugly hack to cope with both new and old gdb.
293 If gdb sends qXfer:features:read then assume we're talking to a newish
294 gdb that understands target descriptions. */
295 static int gdb_has_xml;
297 #ifdef CONFIG_USER_ONLY
298 /* XXX: This is not thread safe. Do we care? */
299 static int gdbserver_fd = -1;
301 static int get_char(GDBState *s)
303 uint8_t ch;
304 int ret;
306 for(;;) {
307 ret = recv(s->fd, &ch, 1, 0);
308 if (ret < 0) {
309 if (errno == ECONNRESET)
310 s->fd = -1;
311 if (errno != EINTR && errno != EAGAIN)
312 return -1;
313 } else if (ret == 0) {
314 close(s->fd);
315 s->fd = -1;
316 return -1;
317 } else {
318 break;
321 return ch;
323 #endif
325 static gdb_syscall_complete_cb gdb_current_syscall_cb;
327 enum {
328 GDB_SYS_UNKNOWN,
329 GDB_SYS_ENABLED,
330 GDB_SYS_DISABLED,
331 } gdb_syscall_mode;
333 /* If gdb is connected when the first semihosting syscall occurs then use
334 remote gdb syscalls. Otherwise use native file IO. */
335 int use_gdb_syscalls(void)
337 if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
338 gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
339 : GDB_SYS_DISABLED);
341 return gdb_syscall_mode == GDB_SYS_ENABLED;
344 /* Resume execution. */
345 static inline void gdb_continue(GDBState *s)
347 #ifdef CONFIG_USER_ONLY
348 s->running_state = 1;
349 #else
350 vm_start();
351 #endif
354 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
356 #ifdef CONFIG_USER_ONLY
357 int ret;
359 while (len > 0) {
360 ret = send(s->fd, buf, len, 0);
361 if (ret < 0) {
362 if (errno != EINTR && errno != EAGAIN)
363 return;
364 } else {
365 buf += ret;
366 len -= ret;
369 #else
370 qemu_chr_write(s->chr, buf, len);
371 #endif
374 static inline int fromhex(int v)
376 if (v >= '0' && v <= '9')
377 return v - '0';
378 else if (v >= 'A' && v <= 'F')
379 return v - 'A' + 10;
380 else if (v >= 'a' && v <= 'f')
381 return v - 'a' + 10;
382 else
383 return 0;
386 static inline int tohex(int v)
388 if (v < 10)
389 return v + '0';
390 else
391 return v - 10 + 'a';
394 static void memtohex(char *buf, const uint8_t *mem, int len)
396 int i, c;
397 char *q;
398 q = buf;
399 for(i = 0; i < len; i++) {
400 c = mem[i];
401 *q++ = tohex(c >> 4);
402 *q++ = tohex(c & 0xf);
404 *q = '\0';
407 static void hextomem(uint8_t *mem, const char *buf, int len)
409 int i;
411 for(i = 0; i < len; i++) {
412 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
413 buf += 2;
417 /* return -1 if error, 0 if OK */
418 static int put_packet_binary(GDBState *s, const char *buf, int len)
420 int csum, i;
421 uint8_t *p;
423 for(;;) {
424 p = s->last_packet;
425 *(p++) = '$';
426 memcpy(p, buf, len);
427 p += len;
428 csum = 0;
429 for(i = 0; i < len; i++) {
430 csum += buf[i];
432 *(p++) = '#';
433 *(p++) = tohex((csum >> 4) & 0xf);
434 *(p++) = tohex((csum) & 0xf);
436 s->last_packet_len = p - s->last_packet;
437 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
439 #ifdef CONFIG_USER_ONLY
440 i = get_char(s);
441 if (i < 0)
442 return -1;
443 if (i == '+')
444 break;
445 #else
446 break;
447 #endif
449 return 0;
452 /* return -1 if error, 0 if OK */
453 static int put_packet(GDBState *s, const char *buf)
455 #ifdef DEBUG_GDB
456 printf("reply='%s'\n", buf);
457 #endif
459 return put_packet_binary(s, buf, strlen(buf));
462 /* The GDB remote protocol transfers values in target byte order. This means
463 we can use the raw memory access routines to access the value buffer.
464 Conveniently, these also handle the case where the buffer is mis-aligned.
466 #define GET_REG8(val) do { \
467 stb_p(mem_buf, val); \
468 return 1; \
469 } while(0)
470 #define GET_REG16(val) do { \
471 stw_p(mem_buf, val); \
472 return 2; \
473 } while(0)
474 #define GET_REG32(val) do { \
475 stl_p(mem_buf, val); \
476 return 4; \
477 } while(0)
478 #define GET_REG64(val) do { \
479 stq_p(mem_buf, val); \
480 return 8; \
481 } while(0)
483 #if TARGET_LONG_BITS == 64
484 #define GET_REGL(val) GET_REG64(val)
485 #define ldtul_p(addr) ldq_p(addr)
486 #else
487 #define GET_REGL(val) GET_REG32(val)
488 #define ldtul_p(addr) ldl_p(addr)
489 #endif
491 #if defined(TARGET_I386)
493 #ifdef TARGET_X86_64
494 static const int gpr_map[16] = {
495 R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
496 8, 9, 10, 11, 12, 13, 14, 15
498 #else
499 static const int gpr_map[8] = {0, 1, 2, 3, 4, 5, 6, 7};
500 #endif
502 #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
504 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
506 if (n < CPU_NB_REGS) {
507 GET_REGL(env->regs[gpr_map[n]]);
508 } else if (n >= CPU_NB_REGS + 8 && n < CPU_NB_REGS + 16) {
509 /* FIXME: byteswap float values. */
510 #ifdef USE_X86LDOUBLE
511 memcpy(mem_buf, &env->fpregs[n - (CPU_NB_REGS + 8)], 10);
512 #else
513 memset(mem_buf, 0, 10);
514 #endif
515 return 10;
516 } else if (n >= CPU_NB_REGS + 24) {
517 n -= CPU_NB_REGS + 24;
518 if (n < CPU_NB_REGS) {
519 stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
520 stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
521 return 16;
522 } else if (n == CPU_NB_REGS) {
523 GET_REG32(env->mxcsr);
525 } else {
526 n -= CPU_NB_REGS;
527 switch (n) {
528 case 0: GET_REGL(env->eip);
529 case 1: GET_REG32(env->eflags);
530 case 2: GET_REG32(env->segs[R_CS].selector);
531 case 3: GET_REG32(env->segs[R_SS].selector);
532 case 4: GET_REG32(env->segs[R_DS].selector);
533 case 5: GET_REG32(env->segs[R_ES].selector);
534 case 6: GET_REG32(env->segs[R_FS].selector);
535 case 7: GET_REG32(env->segs[R_GS].selector);
536 /* 8...15 x87 regs. */
537 case 16: GET_REG32(env->fpuc);
538 case 17: GET_REG32((env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11);
539 case 18: GET_REG32(0); /* ftag */
540 case 19: GET_REG32(0); /* fiseg */
541 case 20: GET_REG32(0); /* fioff */
542 case 21: GET_REG32(0); /* foseg */
543 case 22: GET_REG32(0); /* fooff */
544 case 23: GET_REG32(0); /* fop */
545 /* 24+ xmm regs. */
548 return 0;
551 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int i)
553 uint32_t tmp;
555 if (i < CPU_NB_REGS) {
556 env->regs[gpr_map[i]] = ldtul_p(mem_buf);
557 return sizeof(target_ulong);
558 } else if (i >= CPU_NB_REGS + 8 && i < CPU_NB_REGS + 16) {
559 i -= CPU_NB_REGS + 8;
560 #ifdef USE_X86LDOUBLE
561 memcpy(&env->fpregs[i], mem_buf, 10);
562 #endif
563 return 10;
564 } else if (i >= CPU_NB_REGS + 24) {
565 i -= CPU_NB_REGS + 24;
566 if (i < CPU_NB_REGS) {
567 env->xmm_regs[i].XMM_Q(0) = ldq_p(mem_buf);
568 env->xmm_regs[i].XMM_Q(1) = ldq_p(mem_buf + 8);
569 return 16;
570 } else if (i == CPU_NB_REGS) {
571 env->mxcsr = ldl_p(mem_buf);
572 return 4;
574 } else {
575 i -= CPU_NB_REGS;
576 switch (i) {
577 case 0: env->eip = ldtul_p(mem_buf); return sizeof(target_ulong);
578 case 1: env->eflags = ldl_p(mem_buf); return 4;
579 #if defined(CONFIG_USER_ONLY)
580 #define LOAD_SEG(index, sreg)\
581 tmp = ldl_p(mem_buf);\
582 if (tmp != env->segs[sreg].selector)\
583 cpu_x86_load_seg(env, sreg, tmp);
584 #else
585 /* FIXME: Honor segment registers. Needs to avoid raising an exception
586 when the selector is invalid. */
587 #define LOAD_SEG(index, sreg) do {} while(0)
588 #endif
589 case 2: LOAD_SEG(10, R_CS); return 4;
590 case 3: LOAD_SEG(11, R_SS); return 4;
591 case 4: LOAD_SEG(12, R_DS); return 4;
592 case 5: LOAD_SEG(13, R_ES); return 4;
593 case 6: LOAD_SEG(14, R_FS); return 4;
594 case 7: LOAD_SEG(15, R_GS); return 4;
595 /* 8...15 x87 regs. */
596 case 16: env->fpuc = ldl_p(mem_buf); return 4;
597 case 17:
598 tmp = ldl_p(mem_buf);
599 env->fpstt = (tmp >> 11) & 7;
600 env->fpus = tmp & ~0x3800;
601 return 4;
602 case 18: /* ftag */ return 4;
603 case 19: /* fiseg */ return 4;
604 case 20: /* fioff */ return 4;
605 case 21: /* foseg */ return 4;
606 case 22: /* fooff */ return 4;
607 case 23: /* fop */ return 4;
608 /* 24+ xmm regs. */
611 /* Unrecognised register. */
612 return 0;
615 #elif defined (TARGET_PPC)
617 #define NUM_CORE_REGS 71
619 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
621 if (n < 32) {
622 /* gprs */
623 GET_REGL(env->gpr[n]);
624 } else if (n < 64) {
625 /* fprs */
626 stfq_p(mem_buf, env->fpr[n-32]);
627 return 8;
628 } else {
629 switch (n) {
630 case 64: GET_REGL(env->nip);
631 case 65: GET_REGL(env->msr);
632 case 66:
634 uint32_t cr = 0;
635 int i;
636 for (i = 0; i < 8; i++)
637 cr |= env->crf[i] << (32 - ((i + 1) * 4));
638 GET_REG32(cr);
640 case 67: GET_REGL(env->lr);
641 case 68: GET_REGL(env->ctr);
642 case 69: GET_REGL(env->xer);
643 case 70: GET_REG32(0); /* fpscr */
646 return 0;
649 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
651 if (n < 32) {
652 /* gprs */
653 env->gpr[n] = ldtul_p(mem_buf);
654 return sizeof(target_ulong);
655 } else if (n < 64) {
656 /* fprs */
657 env->fpr[n-32] = ldfq_p(mem_buf);
658 return 8;
659 } else {
660 switch (n) {
661 case 64:
662 env->nip = ldtul_p(mem_buf);
663 return sizeof(target_ulong);
664 case 65:
665 ppc_store_msr(env, ldtul_p(mem_buf));
666 return sizeof(target_ulong);
667 case 66:
669 uint32_t cr = ldl_p(mem_buf);
670 int i;
671 for (i = 0; i < 8; i++)
672 env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
673 return 4;
675 case 67:
676 env->lr = ldtul_p(mem_buf);
677 return sizeof(target_ulong);
678 case 68:
679 env->ctr = ldtul_p(mem_buf);
680 return sizeof(target_ulong);
681 case 69:
682 env->xer = ldtul_p(mem_buf);
683 return sizeof(target_ulong);
684 case 70:
685 /* fpscr */
686 return 4;
689 return 0;
692 #elif defined (TARGET_SPARC)
694 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
695 #define NUM_CORE_REGS 86
696 #else
697 #define NUM_CORE_REGS 73
698 #endif
700 #ifdef TARGET_ABI32
701 #define GET_REGA(val) GET_REG32(val)
702 #else
703 #define GET_REGA(val) GET_REGL(val)
704 #endif
706 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
708 if (n < 8) {
709 /* g0..g7 */
710 GET_REGA(env->gregs[n]);
712 if (n < 32) {
713 /* register window */
714 GET_REGA(env->regwptr[n - 8]);
716 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
717 if (n < 64) {
718 /* fprs */
719 GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
721 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
722 switch (n) {
723 case 64: GET_REGA(env->y);
724 case 65: GET_REGA(GET_PSR(env));
725 case 66: GET_REGA(env->wim);
726 case 67: GET_REGA(env->tbr);
727 case 68: GET_REGA(env->pc);
728 case 69: GET_REGA(env->npc);
729 case 70: GET_REGA(env->fsr);
730 case 71: GET_REGA(0); /* csr */
731 case 72: GET_REGA(0);
733 #else
734 if (n < 64) {
735 /* f0-f31 */
736 GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
738 if (n < 80) {
739 /* f32-f62 (double width, even numbers only) */
740 uint64_t val;
742 val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;
743 val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);
744 GET_REG64(val);
746 switch (n) {
747 case 80: GET_REGL(env->pc);
748 case 81: GET_REGL(env->npc);
749 case 82: GET_REGL(((uint64_t)GET_CCR(env) << 32) |
750 ((env->asi & 0xff) << 24) |
751 ((env->pstate & 0xfff) << 8) |
752 GET_CWP64(env));
753 case 83: GET_REGL(env->fsr);
754 case 84: GET_REGL(env->fprs);
755 case 85: GET_REGL(env->y);
757 #endif
758 return 0;
761 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
763 #if defined(TARGET_ABI32)
764 abi_ulong tmp;
766 tmp = ldl_p(mem_buf);
767 #else
768 target_ulong tmp;
770 tmp = ldtul_p(mem_buf);
771 #endif
773 if (n < 8) {
774 /* g0..g7 */
775 env->gregs[n] = tmp;
776 } else if (n < 32) {
777 /* register window */
778 env->regwptr[n - 8] = tmp;
780 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
781 else if (n < 64) {
782 /* fprs */
783 *((uint32_t *)&env->fpr[n - 32]) = tmp;
784 } else {
785 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
786 switch (n) {
787 case 64: env->y = tmp; break;
788 case 65: PUT_PSR(env, tmp); break;
789 case 66: env->wim = tmp; break;
790 case 67: env->tbr = tmp; break;
791 case 68: env->pc = tmp; break;
792 case 69: env->npc = tmp; break;
793 case 70: env->fsr = tmp; break;
794 default: return 0;
797 return 4;
798 #else
799 else if (n < 64) {
800 /* f0-f31 */
801 env->fpr[n] = ldfl_p(mem_buf);
802 return 4;
803 } else if (n < 80) {
804 /* f32-f62 (double width, even numbers only) */
805 *((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32;
806 *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp;
807 } else {
808 switch (n) {
809 case 80: env->pc = tmp; break;
810 case 81: env->npc = tmp; break;
811 case 82:
812 PUT_CCR(env, tmp >> 32);
813 env->asi = (tmp >> 24) & 0xff;
814 env->pstate = (tmp >> 8) & 0xfff;
815 PUT_CWP64(env, tmp & 0xff);
816 break;
817 case 83: env->fsr = tmp; break;
818 case 84: env->fprs = tmp; break;
819 case 85: env->y = tmp; break;
820 default: return 0;
823 return 8;
824 #endif
826 #elif defined (TARGET_ARM)
828 /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
829 whatever the target description contains. Due to a historical mishap
830 the FPA registers appear in between core integer regs and the CPSR.
831 We hack round this by giving the FPA regs zero size when talking to a
832 newer gdb. */
833 #define NUM_CORE_REGS 26
834 #define GDB_CORE_XML "arm-core.xml"
836 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
838 if (n < 16) {
839 /* Core integer register. */
840 GET_REG32(env->regs[n]);
842 if (n < 24) {
843 /* FPA registers. */
844 if (gdb_has_xml)
845 return 0;
846 memset(mem_buf, 0, 12);
847 return 12;
849 switch (n) {
850 case 24:
851 /* FPA status register. */
852 if (gdb_has_xml)
853 return 0;
854 GET_REG32(0);
855 case 25:
856 /* CPSR */
857 GET_REG32(cpsr_read(env));
859 /* Unknown register. */
860 return 0;
863 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
865 uint32_t tmp;
867 tmp = ldl_p(mem_buf);
869 /* Mask out low bit of PC to workaround gdb bugs. This will probably
870 cause problems if we ever implement the Jazelle DBX extensions. */
871 if (n == 15)
872 tmp &= ~1;
874 if (n < 16) {
875 /* Core integer register. */
876 env->regs[n] = tmp;
877 return 4;
879 if (n < 24) { /* 16-23 */
880 /* FPA registers (ignored). */
881 if (gdb_has_xml)
882 return 0;
883 return 12;
885 switch (n) {
886 case 24:
887 /* FPA status register (ignored). */
888 if (gdb_has_xml)
889 return 0;
890 return 4;
891 case 25:
892 /* CPSR */
893 cpsr_write (env, tmp, 0xffffffff);
894 return 4;
896 /* Unknown register. */
897 return 0;
900 #elif defined (TARGET_M68K)
902 #define NUM_CORE_REGS 18
904 #define GDB_CORE_XML "cf-core.xml"
906 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
908 if (n < 8) {
909 /* D0-D7 */
910 GET_REG32(env->dregs[n]);
911 } else if (n < 16) {
912 /* A0-A7 */
913 GET_REG32(env->aregs[n - 8]);
914 } else {
915 switch (n) {
916 case 16: GET_REG32(env->sr);
917 case 17: GET_REG32(env->pc);
920 /* FP registers not included here because they vary between
921 ColdFire and m68k. Use XML bits for these. */
922 return 0;
925 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
927 uint32_t tmp;
929 tmp = ldl_p(mem_buf);
931 if (n < 8) {
932 /* D0-D7 */
933 env->dregs[n] = tmp;
934 } else if (n < 8) {
935 /* A0-A7 */
936 env->aregs[n - 8] = tmp;
937 } else {
938 switch (n) {
939 case 16: env->sr = tmp; break;
940 case 17: env->pc = tmp; break;
941 default: return 0;
944 return 4;
946 #elif defined (TARGET_MIPS)
948 #define NUM_CORE_REGS 73
950 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
952 if (n < 32) {
953 GET_REGL(env->active_tc.gpr[n]);
955 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
956 if (n >= 38 && n < 70) {
957 if (env->CP0_Status & (1 << CP0St_FR))
958 GET_REGL(env->active_fpu.fpr[n - 38].d);
959 else
960 GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
962 switch (n) {
963 case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
964 case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
967 switch (n) {
968 case 32: GET_REGL((int32_t)env->CP0_Status);
969 case 33: GET_REGL(env->active_tc.LO[0]);
970 case 34: GET_REGL(env->active_tc.HI[0]);
971 case 35: GET_REGL(env->CP0_BadVAddr);
972 case 36: GET_REGL((int32_t)env->CP0_Cause);
973 case 37: GET_REGL(env->active_tc.PC);
974 case 72: GET_REGL(0); /* fp */
975 case 89: GET_REGL((int32_t)env->CP0_PRid);
977 if (n >= 73 && n <= 88) {
978 /* 16 embedded regs. */
979 GET_REGL(0);
982 return 0;
985 /* convert MIPS rounding mode in FCR31 to IEEE library */
986 static unsigned int ieee_rm[] =
988 float_round_nearest_even,
989 float_round_to_zero,
990 float_round_up,
991 float_round_down
993 #define RESTORE_ROUNDING_MODE \
994 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
996 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
998 target_ulong tmp;
1000 tmp = ldtul_p(mem_buf);
1002 if (n < 32) {
1003 env->active_tc.gpr[n] = tmp;
1004 return sizeof(target_ulong);
1006 if (env->CP0_Config1 & (1 << CP0C1_FP)
1007 && n >= 38 && n < 73) {
1008 if (n < 70) {
1009 if (env->CP0_Status & (1 << CP0St_FR))
1010 env->active_fpu.fpr[n - 38].d = tmp;
1011 else
1012 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1014 switch (n) {
1015 case 70:
1016 env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1017 /* set rounding mode */
1018 RESTORE_ROUNDING_MODE;
1019 #ifndef CONFIG_SOFTFLOAT
1020 /* no floating point exception for native float */
1021 SET_FP_ENABLE(env->active_fpu.fcr31, 0);
1022 #endif
1023 break;
1024 case 71: env->active_fpu.fcr0 = tmp; break;
1026 return sizeof(target_ulong);
1028 switch (n) {
1029 case 32: env->CP0_Status = tmp; break;
1030 case 33: env->active_tc.LO[0] = tmp; break;
1031 case 34: env->active_tc.HI[0] = tmp; break;
1032 case 35: env->CP0_BadVAddr = tmp; break;
1033 case 36: env->CP0_Cause = tmp; break;
1034 case 37: env->active_tc.PC = tmp; break;
1035 case 72: /* fp, ignored */ break;
1036 default:
1037 if (n > 89)
1038 return 0;
1039 /* Other registers are readonly. Ignore writes. */
1040 break;
1043 return sizeof(target_ulong);
1045 #elif defined (TARGET_SH4)
1047 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
1048 /* FIXME: We should use XML for this. */
1050 #define NUM_CORE_REGS 59
1052 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1054 if (n < 8) {
1055 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1056 GET_REGL(env->gregs[n + 16]);
1057 } else {
1058 GET_REGL(env->gregs[n]);
1060 } else if (n < 16) {
1061 GET_REGL(env->gregs[n - 8]);
1062 } else if (n >= 25 && n < 41) {
1063 GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
1064 } else if (n >= 43 && n < 51) {
1065 GET_REGL(env->gregs[n - 43]);
1066 } else if (n >= 51 && n < 59) {
1067 GET_REGL(env->gregs[n - (51 - 16)]);
1069 switch (n) {
1070 case 16: GET_REGL(env->pc);
1071 case 17: GET_REGL(env->pr);
1072 case 18: GET_REGL(env->gbr);
1073 case 19: GET_REGL(env->vbr);
1074 case 20: GET_REGL(env->mach);
1075 case 21: GET_REGL(env->macl);
1076 case 22: GET_REGL(env->sr);
1077 case 23: GET_REGL(env->fpul);
1078 case 24: GET_REGL(env->fpscr);
1079 case 41: GET_REGL(env->ssr);
1080 case 42: GET_REGL(env->spc);
1083 return 0;
1086 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1088 uint32_t tmp;
1090 tmp = ldl_p(mem_buf);
1092 if (n < 8) {
1093 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1094 env->gregs[n + 16] = tmp;
1095 } else {
1096 env->gregs[n] = tmp;
1098 return 4;
1099 } else if (n < 16) {
1100 env->gregs[n - 8] = tmp;
1101 return 4;
1102 } else if (n >= 25 && n < 41) {
1103 env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
1104 } else if (n >= 43 && n < 51) {
1105 env->gregs[n - 43] = tmp;
1106 return 4;
1107 } else if (n >= 51 && n < 59) {
1108 env->gregs[n - (51 - 16)] = tmp;
1109 return 4;
1111 switch (n) {
1112 case 16: env->pc = tmp;
1113 case 17: env->pr = tmp;
1114 case 18: env->gbr = tmp;
1115 case 19: env->vbr = tmp;
1116 case 20: env->mach = tmp;
1117 case 21: env->macl = tmp;
1118 case 22: env->sr = tmp;
1119 case 23: env->fpul = tmp;
1120 case 24: env->fpscr = tmp;
1121 case 41: env->ssr = tmp;
1122 case 42: env->spc = tmp;
1123 default: return 0;
1126 return 4;
1128 #elif defined (TARGET_CRIS)
1130 #define NUM_CORE_REGS 49
1132 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1134 uint8_t srs;
1136 srs = env->pregs[PR_SRS];
1137 if (n < 16) {
1138 GET_REG32(env->regs[n]);
1141 if (n >= 21 && n < 32) {
1142 GET_REG32(env->pregs[n - 16]);
1144 if (n >= 33 && n < 49) {
1145 GET_REG32(env->sregs[srs][n - 33]);
1147 switch (n) {
1148 case 16: GET_REG8(env->pregs[0]);
1149 case 17: GET_REG8(env->pregs[1]);
1150 case 18: GET_REG32(env->pregs[2]);
1151 case 19: GET_REG8(srs);
1152 case 20: GET_REG16(env->pregs[4]);
1153 case 32: GET_REG32(env->pc);
1156 return 0;
1159 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1161 uint32_t tmp;
1163 if (n > 49)
1164 return 0;
1166 tmp = ldl_p(mem_buf);
1168 if (n < 16) {
1169 env->regs[n] = tmp;
1172 if (n >= 21 && n < 32) {
1173 env->pregs[n - 16] = tmp;
1176 /* FIXME: Should support function regs be writable? */
1177 switch (n) {
1178 case 16: return 1;
1179 case 17: return 1;
1180 case 18: env->pregs[PR_PID] = tmp; break;
1181 case 19: return 1;
1182 case 20: return 2;
1183 case 32: env->pc = tmp; break;
1186 return 4;
1188 #elif defined (TARGET_ALPHA)
1190 #define NUM_CORE_REGS 65
1192 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1194 if (n < 31) {
1195 GET_REGL(env->ir[n]);
1197 else if (n == 31) {
1198 GET_REGL(0);
1200 else if (n<63) {
1201 uint64_t val;
1203 val=*((uint64_t *)&env->fir[n-32]);
1204 GET_REGL(val);
1206 else if (n==63) {
1207 GET_REGL(env->fpcr);
1209 else if (n==64) {
1210 GET_REGL(env->pc);
1212 else {
1213 GET_REGL(0);
1216 return 0;
1219 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1221 target_ulong tmp;
1222 tmp = ldtul_p(mem_buf);
1224 if (n < 31) {
1225 env->ir[n] = tmp;
1228 if (n > 31 && n < 63) {
1229 env->fir[n - 32] = ldfl_p(mem_buf);
1232 if (n == 64 ) {
1233 env->pc=tmp;
1236 return 8;
1238 #else
1240 #define NUM_CORE_REGS 0
1242 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1244 return 0;
1247 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1249 return 0;
1252 #endif
1254 static int num_g_regs = NUM_CORE_REGS;
1256 #ifdef GDB_CORE_XML
1257 /* Encode data using the encoding for 'x' packets. */
1258 static int memtox(char *buf, const char *mem, int len)
1260 char *p = buf;
1261 char c;
1263 while (len--) {
1264 c = *(mem++);
1265 switch (c) {
1266 case '#': case '$': case '*': case '}':
1267 *(p++) = '}';
1268 *(p++) = c ^ 0x20;
1269 break;
1270 default:
1271 *(p++) = c;
1272 break;
1275 return p - buf;
1278 static const char *get_feature_xml(const char *p, const char **newp)
1280 extern const char *const xml_builtin[][2];
1281 size_t len;
1282 int i;
1283 const char *name;
1284 static char target_xml[1024];
1286 len = 0;
1287 while (p[len] && p[len] != ':')
1288 len++;
1289 *newp = p + len;
1291 name = NULL;
1292 if (strncmp(p, "target.xml", len) == 0) {
1293 /* Generate the XML description for this CPU. */
1294 if (!target_xml[0]) {
1295 GDBRegisterState *r;
1297 snprintf(target_xml, sizeof(target_xml),
1298 "<?xml version=\"1.0\"?>"
1299 "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1300 "<target>"
1301 "<xi:include href=\"%s\"/>",
1302 GDB_CORE_XML);
1304 for (r = first_cpu->gdb_regs; r; r = r->next) {
1305 strcat(target_xml, "<xi:include href=\"");
1306 strcat(target_xml, r->xml);
1307 strcat(target_xml, "\"/>");
1309 strcat(target_xml, "</target>");
1311 return target_xml;
1313 for (i = 0; ; i++) {
1314 name = xml_builtin[i][0];
1315 if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
1316 break;
1318 return name ? xml_builtin[i][1] : NULL;
1320 #endif
1322 static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
1324 GDBRegisterState *r;
1326 if (reg < NUM_CORE_REGS)
1327 return cpu_gdb_read_register(env, mem_buf, reg);
1329 for (r = env->gdb_regs; r; r = r->next) {
1330 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1331 return r->get_reg(env, mem_buf, reg - r->base_reg);
1334 return 0;
1337 static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
1339 GDBRegisterState *r;
1341 if (reg < NUM_CORE_REGS)
1342 return cpu_gdb_write_register(env, mem_buf, reg);
1344 for (r = env->gdb_regs; r; r = r->next) {
1345 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1346 return r->set_reg(env, mem_buf, reg - r->base_reg);
1349 return 0;
1352 /* Register a supplemental set of CPU registers. If g_pos is nonzero it
1353 specifies the first register number and these registers are included in
1354 a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
1355 gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1358 void gdb_register_coprocessor(CPUState * env,
1359 gdb_reg_cb get_reg, gdb_reg_cb set_reg,
1360 int num_regs, const char *xml, int g_pos)
1362 GDBRegisterState *s;
1363 GDBRegisterState **p;
1364 static int last_reg = NUM_CORE_REGS;
1366 s = (GDBRegisterState *)qemu_mallocz(sizeof(GDBRegisterState));
1367 s->base_reg = last_reg;
1368 s->num_regs = num_regs;
1369 s->get_reg = get_reg;
1370 s->set_reg = set_reg;
1371 s->xml = xml;
1372 p = &env->gdb_regs;
1373 while (*p) {
1374 /* Check for duplicates. */
1375 if (strcmp((*p)->xml, xml) == 0)
1376 return;
1377 p = &(*p)->next;
1379 /* Add to end of list. */
1380 last_reg += num_regs;
1381 *p = s;
1382 if (g_pos) {
1383 if (g_pos != s->base_reg) {
1384 fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
1385 "Expected %d got %d\n", xml, g_pos, s->base_reg);
1386 } else {
1387 num_g_regs = last_reg;
1392 /* GDB breakpoint/watchpoint types */
1393 #define GDB_BREAKPOINT_SW 0
1394 #define GDB_BREAKPOINT_HW 1
1395 #define GDB_WATCHPOINT_WRITE 2
1396 #define GDB_WATCHPOINT_READ 3
1397 #define GDB_WATCHPOINT_ACCESS 4
1399 #ifndef CONFIG_USER_ONLY
1400 static const int xlat_gdb_type[] = {
1401 [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE,
1402 [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ,
1403 [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
1405 #endif
1407 static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
1409 CPUState *env;
1410 int err = 0;
1412 switch (type) {
1413 case GDB_BREAKPOINT_SW:
1414 case GDB_BREAKPOINT_HW:
1415 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1416 err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
1417 if (err)
1418 break;
1420 return err;
1421 #ifndef CONFIG_USER_ONLY
1422 case GDB_WATCHPOINT_WRITE:
1423 case GDB_WATCHPOINT_READ:
1424 case GDB_WATCHPOINT_ACCESS:
1425 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1426 err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
1427 NULL);
1428 if (err)
1429 break;
1431 return err;
1432 #endif
1433 default:
1434 return -ENOSYS;
1438 static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
1440 CPUState *env;
1441 int err = 0;
1443 switch (type) {
1444 case GDB_BREAKPOINT_SW:
1445 case GDB_BREAKPOINT_HW:
1446 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1447 err = cpu_breakpoint_remove(env, addr, BP_GDB);
1448 if (err)
1449 break;
1451 return err;
1452 #ifndef CONFIG_USER_ONLY
1453 case GDB_WATCHPOINT_WRITE:
1454 case GDB_WATCHPOINT_READ:
1455 case GDB_WATCHPOINT_ACCESS:
1456 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1457 err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]);
1458 if (err)
1459 break;
1461 return err;
1462 #endif
1463 default:
1464 return -ENOSYS;
1468 static void gdb_breakpoint_remove_all(void)
1470 CPUState *env;
1472 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1473 cpu_breakpoint_remove_all(env, BP_GDB);
1474 #ifndef CONFIG_USER_ONLY
1475 cpu_watchpoint_remove_all(env, BP_GDB);
1476 #endif
1480 static int gdb_handle_packet(GDBState *s, const char *line_buf)
1482 CPUState *env;
1483 const char *p;
1484 int ch, reg_size, type, res, thread;
1485 char buf[MAX_PACKET_LENGTH];
1486 uint8_t mem_buf[MAX_PACKET_LENGTH];
1487 uint8_t *registers;
1488 target_ulong addr, len;
1490 #ifdef DEBUG_GDB
1491 printf("command='%s'\n", line_buf);
1492 #endif
1493 p = line_buf;
1494 ch = *p++;
1495 switch(ch) {
1496 case '?':
1497 /* TODO: Make this return the correct value for user-mode. */
1498 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP,
1499 s->c_cpu->cpu_index+1);
1500 put_packet(s, buf);
1501 /* Remove all the breakpoints when this query is issued,
1502 * because gdb is doing and initial connect and the state
1503 * should be cleaned up.
1505 gdb_breakpoint_remove_all();
1506 break;
1507 case 'c':
1508 if (*p != '\0') {
1509 addr = strtoull(p, (char **)&p, 16);
1510 #if defined(TARGET_I386)
1511 s->c_cpu->eip = addr;
1512 #elif defined (TARGET_PPC)
1513 s->c_cpu->nip = addr;
1514 #elif defined (TARGET_SPARC)
1515 s->c_cpu->pc = addr;
1516 s->c_cpu->npc = addr + 4;
1517 #elif defined (TARGET_ARM)
1518 s->c_cpu->regs[15] = addr;
1519 #elif defined (TARGET_SH4)
1520 s->c_cpu->pc = addr;
1521 #elif defined (TARGET_MIPS)
1522 s->c_cpu->active_tc.PC = addr;
1523 #elif defined (TARGET_CRIS)
1524 s->c_cpu->pc = addr;
1525 #elif defined (TARGET_ALPHA)
1526 s->c_cpu->pc = addr;
1527 #endif
1529 s->signal = 0;
1530 gdb_continue(s);
1531 return RS_IDLE;
1532 case 'C':
1533 s->signal = gdb_signal_to_target (strtoul(p, (char **)&p, 16));
1534 if (s->signal == -1)
1535 s->signal = 0;
1536 gdb_continue(s);
1537 return RS_IDLE;
1538 case 'k':
1539 /* Kill the target */
1540 fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
1541 exit(0);
1542 case 'D':
1543 /* Detach packet */
1544 gdb_breakpoint_remove_all();
1545 gdb_continue(s);
1546 put_packet(s, "OK");
1547 break;
1548 case 's':
1549 if (*p != '\0') {
1550 addr = strtoull(p, (char **)&p, 16);
1551 #if defined(TARGET_I386)
1552 s->c_cpu->eip = addr;
1553 #elif defined (TARGET_PPC)
1554 s->c_cpu->nip = addr;
1555 #elif defined (TARGET_SPARC)
1556 s->c_cpu->pc = addr;
1557 s->c_cpu->npc = addr + 4;
1558 #elif defined (TARGET_ARM)
1559 s->c_cpu->regs[15] = addr;
1560 #elif defined (TARGET_SH4)
1561 s->c_cpu->pc = addr;
1562 #elif defined (TARGET_MIPS)
1563 s->c_cpu->active_tc.PC = addr;
1564 #elif defined (TARGET_CRIS)
1565 s->c_cpu->pc = addr;
1566 #elif defined (TARGET_ALPHA)
1567 s->c_cpu->pc = addr;
1568 #endif
1570 cpu_single_step(s->c_cpu, sstep_flags);
1571 gdb_continue(s);
1572 return RS_IDLE;
1573 case 'F':
1575 target_ulong ret;
1576 target_ulong err;
1578 ret = strtoull(p, (char **)&p, 16);
1579 if (*p == ',') {
1580 p++;
1581 err = strtoull(p, (char **)&p, 16);
1582 } else {
1583 err = 0;
1585 if (*p == ',')
1586 p++;
1587 type = *p;
1588 if (gdb_current_syscall_cb)
1589 gdb_current_syscall_cb(s->c_cpu, ret, err);
1590 if (type == 'C') {
1591 put_packet(s, "T02");
1592 } else {
1593 gdb_continue(s);
1596 break;
1597 case 'g':
1598 len = 0;
1599 for (addr = 0; addr < num_g_regs; addr++) {
1600 reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
1601 len += reg_size;
1603 memtohex(buf, mem_buf, len);
1604 put_packet(s, buf);
1605 break;
1606 case 'G':
1607 registers = mem_buf;
1608 len = strlen(p) / 2;
1609 hextomem((uint8_t *)registers, p, len);
1610 for (addr = 0; addr < num_g_regs && len > 0; addr++) {
1611 reg_size = gdb_write_register(s->g_cpu, registers, addr);
1612 len -= reg_size;
1613 registers += reg_size;
1615 put_packet(s, "OK");
1616 break;
1617 case 'm':
1618 addr = strtoull(p, (char **)&p, 16);
1619 if (*p == ',')
1620 p++;
1621 len = strtoull(p, NULL, 16);
1622 if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
1623 put_packet (s, "E14");
1624 } else {
1625 memtohex(buf, mem_buf, len);
1626 put_packet(s, buf);
1628 break;
1629 case 'M':
1630 addr = strtoull(p, (char **)&p, 16);
1631 if (*p == ',')
1632 p++;
1633 len = strtoull(p, (char **)&p, 16);
1634 if (*p == ':')
1635 p++;
1636 hextomem(mem_buf, p, len);
1637 if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0)
1638 put_packet(s, "E14");
1639 else
1640 put_packet(s, "OK");
1641 break;
1642 case 'p':
1643 /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
1644 This works, but can be very slow. Anything new enough to
1645 understand XML also knows how to use this properly. */
1646 if (!gdb_has_xml)
1647 goto unknown_command;
1648 addr = strtoull(p, (char **)&p, 16);
1649 reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
1650 if (reg_size) {
1651 memtohex(buf, mem_buf, reg_size);
1652 put_packet(s, buf);
1653 } else {
1654 put_packet(s, "E14");
1656 break;
1657 case 'P':
1658 if (!gdb_has_xml)
1659 goto unknown_command;
1660 addr = strtoull(p, (char **)&p, 16);
1661 if (*p == '=')
1662 p++;
1663 reg_size = strlen(p) / 2;
1664 hextomem(mem_buf, p, reg_size);
1665 gdb_write_register(s->g_cpu, mem_buf, addr);
1666 put_packet(s, "OK");
1667 break;
1668 case 'Z':
1669 case 'z':
1670 type = strtoul(p, (char **)&p, 16);
1671 if (*p == ',')
1672 p++;
1673 addr = strtoull(p, (char **)&p, 16);
1674 if (*p == ',')
1675 p++;
1676 len = strtoull(p, (char **)&p, 16);
1677 if (ch == 'Z')
1678 res = gdb_breakpoint_insert(addr, len, type);
1679 else
1680 res = gdb_breakpoint_remove(addr, len, type);
1681 if (res >= 0)
1682 put_packet(s, "OK");
1683 else if (res == -ENOSYS)
1684 put_packet(s, "");
1685 else
1686 put_packet(s, "E22");
1687 break;
1688 case 'H':
1689 type = *p++;
1690 thread = strtoull(p, (char **)&p, 16);
1691 if (thread == -1 || thread == 0) {
1692 put_packet(s, "OK");
1693 break;
1695 for (env = first_cpu; env != NULL; env = env->next_cpu)
1696 if (env->cpu_index + 1 == thread)
1697 break;
1698 if (env == NULL) {
1699 put_packet(s, "E22");
1700 break;
1702 switch (type) {
1703 case 'c':
1704 s->c_cpu = env;
1705 put_packet(s, "OK");
1706 break;
1707 case 'g':
1708 s->g_cpu = env;
1709 put_packet(s, "OK");
1710 break;
1711 default:
1712 put_packet(s, "E22");
1713 break;
1715 break;
1716 case 'T':
1717 thread = strtoull(p, (char **)&p, 16);
1718 #ifndef CONFIG_USER_ONLY
1719 if (thread > 0 && thread < smp_cpus + 1)
1720 #else
1721 if (thread == 1)
1722 #endif
1723 put_packet(s, "OK");
1724 else
1725 put_packet(s, "E22");
1726 break;
1727 case 'q':
1728 case 'Q':
1729 /* parse any 'q' packets here */
1730 if (!strcmp(p,"qemu.sstepbits")) {
1731 /* Query Breakpoint bit definitions */
1732 snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1733 SSTEP_ENABLE,
1734 SSTEP_NOIRQ,
1735 SSTEP_NOTIMER);
1736 put_packet(s, buf);
1737 break;
1738 } else if (strncmp(p,"qemu.sstep",10) == 0) {
1739 /* Display or change the sstep_flags */
1740 p += 10;
1741 if (*p != '=') {
1742 /* Display current setting */
1743 snprintf(buf, sizeof(buf), "0x%x", sstep_flags);
1744 put_packet(s, buf);
1745 break;
1747 p++;
1748 type = strtoul(p, (char **)&p, 16);
1749 sstep_flags = type;
1750 put_packet(s, "OK");
1751 break;
1752 } else if (strcmp(p,"C") == 0) {
1753 /* "Current thread" remains vague in the spec, so always return
1754 * the first CPU (gdb returns the first thread). */
1755 put_packet(s, "QC1");
1756 break;
1757 } else if (strcmp(p,"fThreadInfo") == 0) {
1758 s->query_cpu = first_cpu;
1759 goto report_cpuinfo;
1760 } else if (strcmp(p,"sThreadInfo") == 0) {
1761 report_cpuinfo:
1762 if (s->query_cpu) {
1763 snprintf(buf, sizeof(buf), "m%x", s->query_cpu->cpu_index+1);
1764 put_packet(s, buf);
1765 s->query_cpu = s->query_cpu->next_cpu;
1766 } else
1767 put_packet(s, "l");
1768 break;
1769 } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) {
1770 thread = strtoull(p+16, (char **)&p, 16);
1771 for (env = first_cpu; env != NULL; env = env->next_cpu)
1772 if (env->cpu_index + 1 == thread) {
1773 len = snprintf((char *)mem_buf, sizeof(mem_buf),
1774 "CPU#%d [%s]", env->cpu_index,
1775 env->halted ? "halted " : "running");
1776 memtohex(buf, mem_buf, len);
1777 put_packet(s, buf);
1778 break;
1780 break;
1782 #ifdef CONFIG_LINUX_USER
1783 else if (strncmp(p, "Offsets", 7) == 0) {
1784 TaskState *ts = s->c_cpu->opaque;
1786 snprintf(buf, sizeof(buf),
1787 "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
1788 ";Bss=" TARGET_ABI_FMT_lx,
1789 ts->info->code_offset,
1790 ts->info->data_offset,
1791 ts->info->data_offset);
1792 put_packet(s, buf);
1793 break;
1795 #endif
1796 if (strncmp(p, "Supported", 9) == 0) {
1797 snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH);
1798 #ifdef GDB_CORE_XML
1799 strcat(buf, ";qXfer:features:read+");
1800 #endif
1801 put_packet(s, buf);
1802 break;
1804 #ifdef GDB_CORE_XML
1805 if (strncmp(p, "Xfer:features:read:", 19) == 0) {
1806 const char *xml;
1807 target_ulong total_len;
1809 gdb_has_xml = 1;
1810 p += 19;
1811 xml = get_feature_xml(p, &p);
1812 if (!xml) {
1813 snprintf(buf, sizeof(buf), "E00");
1814 put_packet(s, buf);
1815 break;
1818 if (*p == ':')
1819 p++;
1820 addr = strtoul(p, (char **)&p, 16);
1821 if (*p == ',')
1822 p++;
1823 len = strtoul(p, (char **)&p, 16);
1825 total_len = strlen(xml);
1826 if (addr > total_len) {
1827 snprintf(buf, sizeof(buf), "E00");
1828 put_packet(s, buf);
1829 break;
1831 if (len > (MAX_PACKET_LENGTH - 5) / 2)
1832 len = (MAX_PACKET_LENGTH - 5) / 2;
1833 if (len < total_len - addr) {
1834 buf[0] = 'm';
1835 len = memtox(buf + 1, xml + addr, len);
1836 } else {
1837 buf[0] = 'l';
1838 len = memtox(buf + 1, xml + addr, total_len - addr);
1840 put_packet_binary(s, buf, len + 1);
1841 break;
1843 #endif
1844 /* Unrecognised 'q' command. */
1845 goto unknown_command;
1847 default:
1848 unknown_command:
1849 /* put empty packet */
1850 buf[0] = '\0';
1851 put_packet(s, buf);
1852 break;
1854 return RS_IDLE;
1857 void gdb_set_stop_cpu(CPUState *env)
1859 gdbserver_state->c_cpu = env;
1860 gdbserver_state->g_cpu = env;
1863 #ifndef CONFIG_USER_ONLY
1864 static void gdb_vm_stopped(void *opaque, int reason)
1866 GDBState *s = gdbserver_state;
1867 CPUState *env = s->c_cpu;
1868 char buf[256];
1869 const char *type;
1870 int ret;
1872 if (s->state == RS_SYSCALL)
1873 return;
1875 /* disable single step if it was enable */
1876 cpu_single_step(env, 0);
1878 if (reason == EXCP_DEBUG) {
1879 if (env->watchpoint_hit) {
1880 switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
1881 case BP_MEM_READ:
1882 type = "r";
1883 break;
1884 case BP_MEM_ACCESS:
1885 type = "a";
1886 break;
1887 default:
1888 type = "";
1889 break;
1891 snprintf(buf, sizeof(buf),
1892 "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
1893 GDB_SIGNAL_TRAP, env->cpu_index+1, type,
1894 env->watchpoint_hit->vaddr);
1895 put_packet(s, buf);
1896 env->watchpoint_hit = NULL;
1897 return;
1899 tb_flush(env);
1900 ret = GDB_SIGNAL_TRAP;
1901 } else if (reason == EXCP_INTERRUPT) {
1902 ret = GDB_SIGNAL_INT;
1903 } else {
1904 ret = 0;
1906 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, env->cpu_index+1);
1907 put_packet(s, buf);
1909 #endif
1911 /* Send a gdb syscall request.
1912 This accepts limited printf-style format specifiers, specifically:
1913 %x - target_ulong argument printed in hex.
1914 %lx - 64-bit argument printed in hex.
1915 %s - string pointer (target_ulong) and length (int) pair. */
1916 void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
1918 va_list va;
1919 char buf[256];
1920 char *p;
1921 target_ulong addr;
1922 uint64_t i64;
1923 GDBState *s;
1925 s = gdbserver_state;
1926 if (!s)
1927 return;
1928 gdb_current_syscall_cb = cb;
1929 s->state = RS_SYSCALL;
1930 #ifndef CONFIG_USER_ONLY
1931 vm_stop(EXCP_DEBUG);
1932 #endif
1933 s->state = RS_IDLE;
1934 va_start(va, fmt);
1935 p = buf;
1936 *(p++) = 'F';
1937 while (*fmt) {
1938 if (*fmt == '%') {
1939 fmt++;
1940 switch (*fmt++) {
1941 case 'x':
1942 addr = va_arg(va, target_ulong);
1943 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx, addr);
1944 break;
1945 case 'l':
1946 if (*(fmt++) != 'x')
1947 goto bad_format;
1948 i64 = va_arg(va, uint64_t);
1949 p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64);
1950 break;
1951 case 's':
1952 addr = va_arg(va, target_ulong);
1953 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx "/%x",
1954 addr, va_arg(va, int));
1955 break;
1956 default:
1957 bad_format:
1958 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
1959 fmt - 1);
1960 break;
1962 } else {
1963 *(p++) = *(fmt++);
1966 *p = 0;
1967 va_end(va);
1968 put_packet(s, buf);
1969 #ifdef CONFIG_USER_ONLY
1970 gdb_handlesig(s->c_cpu, 0);
1971 #else
1972 cpu_interrupt(s->c_cpu, CPU_INTERRUPT_EXIT);
1973 #endif
1976 static void gdb_read_byte(GDBState *s, int ch)
1978 int i, csum;
1979 uint8_t reply;
1981 #ifndef CONFIG_USER_ONLY
1982 if (s->last_packet_len) {
1983 /* Waiting for a response to the last packet. If we see the start
1984 of a new command then abandon the previous response. */
1985 if (ch == '-') {
1986 #ifdef DEBUG_GDB
1987 printf("Got NACK, retransmitting\n");
1988 #endif
1989 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
1991 #ifdef DEBUG_GDB
1992 else if (ch == '+')
1993 printf("Got ACK\n");
1994 else
1995 printf("Got '%c' when expecting ACK/NACK\n", ch);
1996 #endif
1997 if (ch == '+' || ch == '$')
1998 s->last_packet_len = 0;
1999 if (ch != '$')
2000 return;
2002 if (vm_running) {
2003 /* when the CPU is running, we cannot do anything except stop
2004 it when receiving a char */
2005 vm_stop(EXCP_INTERRUPT);
2006 } else
2007 #endif
2009 switch(s->state) {
2010 case RS_IDLE:
2011 if (ch == '$') {
2012 s->line_buf_index = 0;
2013 s->state = RS_GETLINE;
2015 break;
2016 case RS_GETLINE:
2017 if (ch == '#') {
2018 s->state = RS_CHKSUM1;
2019 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
2020 s->state = RS_IDLE;
2021 } else {
2022 s->line_buf[s->line_buf_index++] = ch;
2024 break;
2025 case RS_CHKSUM1:
2026 s->line_buf[s->line_buf_index] = '\0';
2027 s->line_csum = fromhex(ch) << 4;
2028 s->state = RS_CHKSUM2;
2029 break;
2030 case RS_CHKSUM2:
2031 s->line_csum |= fromhex(ch);
2032 csum = 0;
2033 for(i = 0; i < s->line_buf_index; i++) {
2034 csum += s->line_buf[i];
2036 if (s->line_csum != (csum & 0xff)) {
2037 reply = '-';
2038 put_buffer(s, &reply, 1);
2039 s->state = RS_IDLE;
2040 } else {
2041 reply = '+';
2042 put_buffer(s, &reply, 1);
2043 s->state = gdb_handle_packet(s, s->line_buf);
2045 break;
2046 default:
2047 abort();
2052 #ifdef CONFIG_USER_ONLY
2054 gdb_queuesig (void)
2056 GDBState *s;
2058 s = gdbserver_state;
2060 if (gdbserver_fd < 0 || s->fd < 0)
2061 return 0;
2062 else
2063 return 1;
2067 gdb_handlesig (CPUState *env, int sig)
2069 GDBState *s;
2070 char buf[256];
2071 int n;
2073 s = gdbserver_state;
2074 if (gdbserver_fd < 0 || s->fd < 0)
2075 return sig;
2077 /* disable single step if it was enabled */
2078 cpu_single_step(env, 0);
2079 tb_flush(env);
2081 if (sig != 0)
2083 snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb (sig));
2084 put_packet(s, buf);
2086 /* put_packet() might have detected that the peer terminated the
2087 connection. */
2088 if (s->fd < 0)
2089 return sig;
2091 sig = 0;
2092 s->state = RS_IDLE;
2093 s->running_state = 0;
2094 while (s->running_state == 0) {
2095 n = read (s->fd, buf, 256);
2096 if (n > 0)
2098 int i;
2100 for (i = 0; i < n; i++)
2101 gdb_read_byte (s, buf[i]);
2103 else if (n == 0 || errno != EAGAIN)
2105 /* XXX: Connection closed. Should probably wait for annother
2106 connection before continuing. */
2107 return sig;
2110 sig = s->signal;
2111 s->signal = 0;
2112 return sig;
2115 /* Tell the remote gdb that the process has exited. */
2116 void gdb_exit(CPUState *env, int code)
2118 GDBState *s;
2119 char buf[4];
2121 s = gdbserver_state;
2122 if (gdbserver_fd < 0 || s->fd < 0)
2123 return;
2125 snprintf(buf, sizeof(buf), "W%02x", code);
2126 put_packet(s, buf);
2129 /* Tell the remote gdb that the process has exited due to SIG. */
2130 void gdb_signalled(CPUState *env, int sig)
2132 GDBState *s;
2133 char buf[4];
2135 s = gdbserver_state;
2136 if (gdbserver_fd < 0 || s->fd < 0)
2137 return;
2139 snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb (sig));
2140 put_packet(s, buf);
2143 static void gdb_accept(void)
2145 GDBState *s;
2146 struct sockaddr_in sockaddr;
2147 socklen_t len;
2148 int val, fd;
2150 for(;;) {
2151 len = sizeof(sockaddr);
2152 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
2153 if (fd < 0 && errno != EINTR) {
2154 perror("accept");
2155 return;
2156 } else if (fd >= 0) {
2157 break;
2161 /* set short latency */
2162 val = 1;
2163 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
2165 s = qemu_mallocz(sizeof(GDBState));
2166 if (!s) {
2167 errno = ENOMEM;
2168 perror("accept");
2169 return;
2172 memset (s, 0, sizeof (GDBState));
2173 s->c_cpu = first_cpu;
2174 s->g_cpu = first_cpu;
2175 s->fd = fd;
2176 gdb_has_xml = 0;
2178 gdbserver_state = s;
2180 fcntl(fd, F_SETFL, O_NONBLOCK);
2183 static int gdbserver_open(int port)
2185 struct sockaddr_in sockaddr;
2186 int fd, val, ret;
2188 fd = socket(PF_INET, SOCK_STREAM, 0);
2189 if (fd < 0) {
2190 perror("socket");
2191 return -1;
2194 /* allow fast reuse */
2195 val = 1;
2196 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
2198 sockaddr.sin_family = AF_INET;
2199 sockaddr.sin_port = htons(port);
2200 sockaddr.sin_addr.s_addr = 0;
2201 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
2202 if (ret < 0) {
2203 perror("bind");
2204 return -1;
2206 ret = listen(fd, 0);
2207 if (ret < 0) {
2208 perror("listen");
2209 return -1;
2211 return fd;
2214 int gdbserver_start(int port)
2216 gdbserver_fd = gdbserver_open(port);
2217 if (gdbserver_fd < 0)
2218 return -1;
2219 /* accept connections */
2220 gdb_accept();
2221 return 0;
2224 /* Disable gdb stub for child processes. */
2225 void gdbserver_fork(CPUState *env)
2227 GDBState *s = gdbserver_state;
2228 if (gdbserver_fd < 0 || s->fd < 0)
2229 return;
2230 close(s->fd);
2231 s->fd = -1;
2232 cpu_breakpoint_remove_all(env, BP_GDB);
2233 cpu_watchpoint_remove_all(env, BP_GDB);
2235 #else
2236 static int gdb_chr_can_receive(void *opaque)
2238 /* We can handle an arbitrarily large amount of data.
2239 Pick the maximum packet size, which is as good as anything. */
2240 return MAX_PACKET_LENGTH;
2243 static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
2245 int i;
2247 for (i = 0; i < size; i++) {
2248 gdb_read_byte(gdbserver_state, buf[i]);
2252 static void gdb_chr_event(void *opaque, int event)
2254 switch (event) {
2255 case CHR_EVENT_RESET:
2256 vm_stop(EXCP_INTERRUPT);
2257 gdb_has_xml = 0;
2258 break;
2259 default:
2260 break;
2264 int gdbserver_start(const char *port)
2266 GDBState *s;
2267 char gdbstub_port_name[128];
2268 int port_num;
2269 char *p;
2270 CharDriverState *chr;
2272 if (!port || !*port)
2273 return -1;
2275 port_num = strtol(port, &p, 10);
2276 if (*p == 0) {
2277 /* A numeric value is interpreted as a port number. */
2278 snprintf(gdbstub_port_name, sizeof(gdbstub_port_name),
2279 "tcp::%d,nowait,nodelay,server", port_num);
2280 port = gdbstub_port_name;
2283 chr = qemu_chr_open("gdb", port);
2284 if (!chr)
2285 return -1;
2287 s = qemu_mallocz(sizeof(GDBState));
2288 if (!s) {
2289 return -1;
2291 s->c_cpu = first_cpu;
2292 s->g_cpu = first_cpu;
2293 s->chr = chr;
2294 gdbserver_state = s;
2295 qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
2296 gdb_chr_event, NULL);
2297 qemu_add_vm_stop_handler(gdb_vm_stopped, NULL);
2298 return 0;
2300 #endif