Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions
[qemu/mini2440.git] / exec-all.h
blob4b828c591b6b0c0c127ab4f4021f86bebdc9ebfa
1 /*
2 * internal execution defines for qemu
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
21 #ifndef _EXEC_ALL_H_
22 #define _EXEC_ALL_H_
23 /* allow to see translation results - the slowdown should be negligible, so we leave it */
24 #define DEBUG_DISAS
26 /* is_jmp field values */
27 #define DISAS_NEXT 0 /* next instruction can be analyzed */
28 #define DISAS_JUMP 1 /* only pc was modified dynamically */
29 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
30 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
32 typedef struct TranslationBlock TranslationBlock;
34 /* XXX: make safe guess about sizes */
35 #define MAX_OP_PER_INSTR 64
36 /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
37 #define MAX_OPC_PARAM 10
38 #define OPC_BUF_SIZE 512
39 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
41 /* Maximum size a TCG op can expand to. This is complicated because a
42 single op may require several host instructions and regirster reloads.
43 For now take a wild guess at 128 bytes, which should allow at least
44 a couple of fixup instructions per argument. */
45 #define TCG_MAX_OP_SIZE 128
47 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
49 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
50 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
51 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
52 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
53 extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
54 extern target_ulong gen_opc_jump_pc[2];
55 extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
57 typedef void (GenOpFunc)(void);
58 typedef void (GenOpFunc1)(long);
59 typedef void (GenOpFunc2)(long, long);
60 typedef void (GenOpFunc3)(long, long, long);
62 #include "qemu-log.h"
64 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
65 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
66 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
67 unsigned long searched_pc, int pc_pos, void *puc);
69 unsigned long code_gen_max_block_size(void);
70 void cpu_gen_init(void);
71 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
72 int *gen_code_size_ptr);
73 int cpu_restore_state(struct TranslationBlock *tb,
74 CPUState *env, unsigned long searched_pc,
75 void *puc);
76 int cpu_restore_state_copy(struct TranslationBlock *tb,
77 CPUState *env, unsigned long searched_pc,
78 void *puc);
79 void cpu_resume_from_signal(CPUState *env1, void *puc);
80 void cpu_io_recompile(CPUState *env, void *retaddr);
81 TranslationBlock *tb_gen_code(CPUState *env,
82 target_ulong pc, target_ulong cs_base, int flags,
83 int cflags);
84 void cpu_exec_init(CPUState *env);
85 void cpu_loop_exit(void);
86 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
87 void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
88 int is_cpu_write_access);
89 void tb_invalidate_page_range(target_ulong start, target_ulong end);
90 void tlb_flush_page(CPUState *env, target_ulong addr);
91 void tlb_flush(CPUState *env, int flush_global);
92 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
93 target_phys_addr_t paddr, int prot,
94 int mmu_idx, int is_softmmu);
95 static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
96 target_phys_addr_t paddr, int prot,
97 int mmu_idx, int is_softmmu)
99 if (prot & PAGE_READ)
100 prot |= PAGE_EXEC;
101 return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
104 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
106 #define CODE_GEN_PHYS_HASH_BITS 15
107 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
109 #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024)
111 /* estimated block size for TB allocation */
112 /* XXX: use a per code average code fragment size and modulate it
113 according to the host CPU */
114 #if defined(CONFIG_SOFTMMU)
115 #define CODE_GEN_AVG_BLOCK_SIZE 128
116 #else
117 #define CODE_GEN_AVG_BLOCK_SIZE 64
118 #endif
120 #if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
121 #define USE_DIRECT_JUMP
122 #endif
123 #if defined(__i386__) && !defined(_WIN32)
124 #define USE_DIRECT_JUMP
125 #endif
127 struct TranslationBlock {
128 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
129 target_ulong cs_base; /* CS base for this block */
130 uint64_t flags; /* flags defining in which context the code was generated */
131 uint16_t size; /* size of target code for this block (1 <=
132 size <= TARGET_PAGE_SIZE) */
133 uint16_t cflags; /* compile flags */
134 #define CF_COUNT_MASK 0x7fff
135 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */
137 uint8_t *tc_ptr; /* pointer to the translated code */
138 /* next matching tb for physical address. */
139 struct TranslationBlock *phys_hash_next;
140 /* first and second physical page containing code. The lower bit
141 of the pointer tells the index in page_next[] */
142 struct TranslationBlock *page_next[2];
143 target_ulong page_addr[2];
145 /* the following data are used to directly call another TB from
146 the code of this one. */
147 uint16_t tb_next_offset[2]; /* offset of original jump target */
148 #ifdef USE_DIRECT_JUMP
149 uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
150 #else
151 unsigned long tb_next[2]; /* address of jump generated code */
152 #endif
153 /* list of TBs jumping to this one. This is a circular list using
154 the two least significant bits of the pointers to tell what is
155 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
156 jmp_first */
157 struct TranslationBlock *jmp_next[2];
158 struct TranslationBlock *jmp_first;
159 uint32_t icount;
162 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
164 target_ulong tmp;
165 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
166 return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
169 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
171 target_ulong tmp;
172 tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
173 return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
174 | (tmp & TB_JMP_ADDR_MASK));
177 static inline unsigned int tb_phys_hash_func(unsigned long pc)
179 return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
182 TranslationBlock *tb_alloc(target_ulong pc);
183 void tb_free(TranslationBlock *tb);
184 void tb_flush(CPUState *env);
185 void tb_link_phys(TranslationBlock *tb,
186 target_ulong phys_pc, target_ulong phys_page2);
187 void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
189 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
190 extern uint8_t *code_gen_ptr;
191 extern int code_gen_max_blocks;
193 #if defined(USE_DIRECT_JUMP)
195 #if defined(__powerpc__)
196 extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
197 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
198 #elif defined(__i386__) || defined(__x86_64__)
199 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
201 /* patch the branch destination */
202 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
203 /* no need to flush icache explicitly */
205 #elif defined(__arm__)
206 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
208 #if QEMU_GNUC_PREREQ(4, 1)
209 void __clear_cache(char *beg, char *end);
210 #else
211 register unsigned long _beg __asm ("a1");
212 register unsigned long _end __asm ("a2");
213 register unsigned long _flg __asm ("a3");
214 #endif
216 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
217 *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff;
219 #if QEMU_GNUC_PREREQ(4, 1)
220 __clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
221 #else
222 /* flush icache */
223 _beg = jmp_addr;
224 _end = jmp_addr + 4;
225 _flg = 0;
226 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
227 #endif
229 #endif
231 static inline void tb_set_jmp_target(TranslationBlock *tb,
232 int n, unsigned long addr)
234 unsigned long offset;
236 offset = tb->tb_jmp_offset[n];
237 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
238 offset = tb->tb_jmp_offset[n + 2];
239 if (offset != 0xffff)
240 tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
243 #else
245 /* set the jump target */
246 static inline void tb_set_jmp_target(TranslationBlock *tb,
247 int n, unsigned long addr)
249 tb->tb_next[n] = addr;
252 #endif
254 static inline void tb_add_jump(TranslationBlock *tb, int n,
255 TranslationBlock *tb_next)
257 /* NOTE: this test is only needed for thread safety */
258 if (!tb->jmp_next[n]) {
259 /* patch the native jump address */
260 tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
262 /* add in TB jmp circular list */
263 tb->jmp_next[n] = tb_next->jmp_first;
264 tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
268 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
270 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
271 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
272 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
274 #include "qemu-lock.h"
276 extern spinlock_t tb_lock;
278 extern int tb_invalidated_flag;
280 #if !defined(CONFIG_USER_ONLY)
282 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
283 void *retaddr);
285 #include "softmmu_defs.h"
287 #define ACCESS_TYPE (NB_MMU_MODES + 1)
288 #define MEMSUFFIX _code
289 #define env cpu_single_env
291 #define DATA_SIZE 1
292 #include "softmmu_header.h"
294 #define DATA_SIZE 2
295 #include "softmmu_header.h"
297 #define DATA_SIZE 4
298 #include "softmmu_header.h"
300 #define DATA_SIZE 8
301 #include "softmmu_header.h"
303 #undef ACCESS_TYPE
304 #undef MEMSUFFIX
305 #undef env
307 #endif
309 #if defined(CONFIG_USER_ONLY)
310 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
312 return addr;
314 #else
315 /* NOTE: this function can trigger an exception */
316 /* NOTE2: the returned address is not exactly the physical address: it
317 is the offset relative to phys_ram_base */
318 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
320 int mmu_idx, page_index, pd;
322 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
323 mmu_idx = cpu_mmu_index(env1);
324 if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
325 (addr & TARGET_PAGE_MASK))) {
326 ldub_code(addr);
328 pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
329 if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
330 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
331 do_unassigned_access(addr, 0, 1, 0, 4);
332 #else
333 cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
334 #endif
336 return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
339 /* Deterministic execution requires that IO only be performed on the last
340 instruction of a TB so that interrupts take effect immediately. */
341 static inline int can_do_io(CPUState *env)
343 if (!use_icount)
344 return 1;
346 /* If not executing code then assume we are ok. */
347 if (!env->current_tb)
348 return 1;
350 return env->can_do_io != 0;
352 #endif
354 #ifdef USE_KQEMU
355 #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
357 #define MSR_QPI_COMMBASE 0xfabe0010
359 int kqemu_init(CPUState *env);
360 int kqemu_cpu_exec(CPUState *env);
361 void kqemu_flush_page(CPUState *env, target_ulong addr);
362 void kqemu_flush(CPUState *env, int global);
363 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
364 void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
365 void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
366 ram_addr_t phys_offset);
367 void kqemu_cpu_interrupt(CPUState *env);
368 void kqemu_record_dump(void);
370 extern uint32_t kqemu_comm_base;
372 static inline int kqemu_is_ok(CPUState *env)
374 return(env->kqemu_enabled &&
375 (env->cr[0] & CR0_PE_MASK) &&
376 !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
377 (env->eflags & IF_MASK) &&
378 !(env->eflags & VM_MASK) &&
379 (env->kqemu_enabled == 2 ||
380 ((env->hflags & HF_CPL_MASK) == 3 &&
381 (env->eflags & IOPL_MASK) != IOPL_MASK)));
384 #endif
386 typedef void (CPUDebugExcpHandler)(CPUState *env);
388 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
389 #endif