exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 #ifndef _EXEC_ALL_H_
  22 #define _EXEC_ALL_H_
  23 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  24 #define DEBUG_DISAS
  25
  26 /* is_jmp field values */
  27 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  28 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  29 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  30 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  31
  32 typedef struct TranslationBlock TranslationBlock;
  33
  34 /* XXX: make safe guess about sizes */
  35 #define MAX_OP_PER_INSTR 64
  36 /* A Call op needs up to 6 + 2N parameters (N = number of arguments).  */
  37 #define MAX_OPC_PARAM 10
  38 #define OPC_BUF_SIZE 512
  39 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  40
  41 /* Maximum size a TCG op can expand to.  This is complicated because a
  42    single op may require several host instructions and regirster reloads.
  43    For now take a wild guess at 128 bytes, which should allow at least
  44    a couple of fixup instructions per argument.  */
  45 #define TCG_MAX_OP_SIZE 128
  46
  47 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  48
  49 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  50 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
  51 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  52 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  53 extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
  54 extern target_ulong gen_opc_jump_pc[2];
  55 extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
  56
  57 typedef void (GenOpFunc)(void);
  58 typedef void (GenOpFunc1)(long);
  59 typedef void (GenOpFunc2)(long, long);
  60 typedef void (GenOpFunc3)(long, long, long);
  61
  62 #include "qemu-log.h"
  63
  64 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  65 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  66 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
  67                  unsigned long searched_pc, int pc_pos, void *puc);
  68
  69 unsigned long code_gen_max_block_size(void);
  70 void cpu_gen_init(void);
  71 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  72                  int *gen_code_size_ptr);
  73 int cpu_restore_state(struct TranslationBlock *tb,
  74                       CPUState *env, unsigned long searched_pc,
  75                       void *puc);
  76 int cpu_restore_state_copy(struct TranslationBlock *tb,
  77                            CPUState *env, unsigned long searched_pc,
  78                            void *puc);
  79 void cpu_resume_from_signal(CPUState *env1, void *puc);
  80 void cpu_io_recompile(CPUState *env, void *retaddr);
  81 TranslationBlock *tb_gen_code(CPUState *env,
  82                               target_ulong pc, target_ulong cs_base, int flags,
  83                               int cflags);
  84 void cpu_exec_init(CPUState *env);
  85 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
  86 void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
  87                                    int is_cpu_write_access);
  88 void tb_invalidate_page_range(target_ulong start, target_ulong end);
  89 void tlb_flush_page(CPUState *env, target_ulong addr);
  90 void tlb_flush(CPUState *env, int flush_global);
  91 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
  92                       target_phys_addr_t paddr, int prot,
  93                       int mmu_idx, int is_softmmu);
  94 static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
  95                                target_phys_addr_t paddr, int prot,
  96                                int mmu_idx, int is_softmmu)
  97 {
  98     if (prot & PAGE_READ)
  99         prot |= PAGE_EXEC;
 100     return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
 101 }
 102
 103 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 104
 105 #define CODE_GEN_PHYS_HASH_BITS     15
 106 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 107
 108 #define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)
 109
 110 /* estimated block size for TB allocation */
 111 /* XXX: use a per code average code fragment size and modulate it
 112    according to the host CPU */
 113 #if defined(CONFIG_SOFTMMU)
 114 #define CODE_GEN_AVG_BLOCK_SIZE 128
 115 #else
 116 #define CODE_GEN_AVG_BLOCK_SIZE 64
 117 #endif
 118
 119 #if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
 120 #define USE_DIRECT_JUMP
 121 #endif
 122 #if defined(__i386__) && !defined(_WIN32)
 123 #define USE_DIRECT_JUMP
 124 #endif
 125
 126 struct TranslationBlock {
 127     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 128     target_ulong cs_base; /* CS base for this block */
 129     uint64_t flags; /* flags defining in which context the code was generated */
 130     uint16_t size;      /* size of target code for this block (1 <=
 131                            size <= TARGET_PAGE_SIZE) */
 132     uint16_t cflags;    /* compile flags */
 133 #define CF_COUNT_MASK  0x7fff
 134 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 135
 136     uint8_t *tc_ptr;    /* pointer to the translated code */
 137     /* next matching tb for physical address. */
 138     struct TranslationBlock *phys_hash_next;
 139     /* first and second physical page containing code. The lower bit
 140        of the pointer tells the index in page_next[] */
 141     struct TranslationBlock *page_next[2];
 142     target_ulong page_addr[2];
 143
 144     /* the following data are used to directly call another TB from
 145        the code of this one. */
 146     uint16_t tb_next_offset[2]; /* offset of original jump target */
 147 #ifdef USE_DIRECT_JUMP
 148     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 149 #else
 150     unsigned long tb_next[2]; /* address of jump generated code */
 151 #endif
 152     /* list of TBs jumping to this one. This is a circular list using
 153        the two least significant bits of the pointers to tell what is
 154        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 155        jmp_first */
 156     struct TranslationBlock *jmp_next[2];
 157     struct TranslationBlock *jmp_first;
 158     uint32_t icount;
 159 };
 160
 161 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 162 {
 163     target_ulong tmp;
 164     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 165     return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
 166 }
 167
 168 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 169 {
 170     target_ulong tmp;
 171     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 172     return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
 173             | (tmp & TB_JMP_ADDR_MASK));
 174 }
 175
 176 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 177 {
 178     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 179 }
 180
 181 TranslationBlock *tb_alloc(target_ulong pc);
 182 void tb_free(TranslationBlock *tb);
 183 void tb_flush(CPUState *env);
 184 void tb_link_phys(TranslationBlock *tb,
 185                   target_ulong phys_pc, target_ulong phys_page2);
 186 void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
 187
 188 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 189 extern uint8_t *code_gen_ptr;
 190 extern int code_gen_max_blocks;
 191
 192 #if defined(USE_DIRECT_JUMP)
 193
 194 #if defined(__powerpc__)
 195 extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
 196 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 197 #elif defined(__i386__) || defined(__x86_64__)
 198 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 199 {
 200     /* patch the branch destination */
 201     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 202     /* no need to flush icache explicitly */
 203 }
 204 #elif defined(__arm__)
 205 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 206 {
 207     register unsigned long _beg __asm ("a1");
 208     register unsigned long _end __asm ("a2");
 209     register unsigned long _flg __asm ("a3");
 210
 211     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 212     *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff;
 213
 214     /* flush icache */
 215     _beg = jmp_addr;
 216     _end = jmp_addr + 4;
 217     _flg = 0;
 218     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 219 }
 220 #endif
 221
 222 static inline void tb_set_jmp_target(TranslationBlock *tb,
 223                                      int n, unsigned long addr)
 224 {
 225     unsigned long offset;
 226
 227     offset = tb->tb_jmp_offset[n];
 228     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 229     offset = tb->tb_jmp_offset[n + 2];
 230     if (offset != 0xffff)
 231         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 232 }
 233
 234 #else
 235
 236 /* set the jump target */
 237 static inline void tb_set_jmp_target(TranslationBlock *tb,
 238                                      int n, unsigned long addr)
 239 {
 240     tb->tb_next[n] = addr;
 241 }
 242
 243 #endif
 244
 245 static inline void tb_add_jump(TranslationBlock *tb, int n,
 246                                TranslationBlock *tb_next)
 247 {
 248     /* NOTE: this test is only needed for thread safety */
 249     if (!tb->jmp_next[n]) {
 250         /* patch the native jump address */
 251         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 252
 253         /* add in TB jmp circular list */
 254         tb->jmp_next[n] = tb_next->jmp_first;
 255         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 256     }
 257 }
 258
 259 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 260
 261 #if defined(_WIN32)
 262 #define ASM_DATA_SECTION ".section \".data\"\n"
 263 #define ASM_PREVIOUS_SECTION ".section .text\n"
 264 #elif defined(__APPLE__)
 265 #define ASM_DATA_SECTION ".data\n"
 266 #define ASM_PREVIOUS_SECTION ".text\n"
 267 #else
 268 #define ASM_DATA_SECTION ".section \".data\"\n"
 269 #define ASM_PREVIOUS_SECTION ".previous\n"
 270 #endif
 271
 272 #define ASM_OP_LABEL_NAME(n, opname) \
 273     ASM_NAME(__op_label) #n "." ASM_NAME(opname)
 274
 275 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 276 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 277 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 278
 279 #include "qemu-lock.h"
 280
 281 extern spinlock_t tb_lock;
 282
 283 extern int tb_invalidated_flag;
 284
 285 #if !defined(CONFIG_USER_ONLY)
 286
 287 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
 288               void *retaddr);
 289
 290 #include "softmmu_defs.h"
 291
 292 #define ACCESS_TYPE (NB_MMU_MODES + 1)
 293 #define MEMSUFFIX _code
 294 #define env cpu_single_env
 295
 296 #define DATA_SIZE 1
 297 #include "softmmu_header.h"
 298
 299 #define DATA_SIZE 2
 300 #include "softmmu_header.h"
 301
 302 #define DATA_SIZE 4
 303 #include "softmmu_header.h"
 304
 305 #define DATA_SIZE 8
 306 #include "softmmu_header.h"
 307
 308 #undef ACCESS_TYPE
 309 #undef MEMSUFFIX
 310 #undef env
 311
 312 #endif
 313
 314 #if defined(CONFIG_USER_ONLY)
 315 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 316 {
 317     return addr;
 318 }
 319 #else
 320 /* NOTE: this function can trigger an exception */
 321 /* NOTE2: the returned address is not exactly the physical address: it
 322    is the offset relative to phys_ram_base */
 323 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 324 {
 325     int mmu_idx, page_index, pd;
 326
 327     page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 328     mmu_idx = cpu_mmu_index(env1);
 329     if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
 330                  (addr & TARGET_PAGE_MASK))) {
 331         ldub_code(addr);
 332     }
 333     pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
 334     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 335 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
 336         do_unassigned_access(addr, 0, 1, 0, 4);
 337 #else
 338         cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 339 #endif
 340     }
 341     return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
 342 }
 343
 344 /* Deterministic execution requires that IO only be performed on the last
 345    instruction of a TB so that interrupts take effect immediately.  */
 346 static inline int can_do_io(CPUState *env)
 347 {
 348     if (!use_icount)
 349         return 1;
 350
 351     /* If not executing code then assume we are ok.  */
 352     if (!env->current_tb)
 353         return 1;
 354
 355     return env->can_do_io != 0;
 356 }
 357 #endif
 358
 359 #ifdef USE_KQEMU
 360 #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
 361
 362 #define MSR_QPI_COMMBASE 0xfabe0010
 363
 364 int kqemu_init(CPUState *env);
 365 int kqemu_cpu_exec(CPUState *env);
 366 void kqemu_flush_page(CPUState *env, target_ulong addr);
 367 void kqemu_flush(CPUState *env, int global);
 368 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
 369 void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
 370 void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
 371                         ram_addr_t phys_offset);
 372 void kqemu_cpu_interrupt(CPUState *env);
 373 void kqemu_record_dump(void);
 374
 375 extern uint32_t kqemu_comm_base;
 376
 377 static inline int kqemu_is_ok(CPUState *env)
 378 {
 379     return(env->kqemu_enabled &&
 380            (env->cr[0] & CR0_PE_MASK) &&
 381            !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
 382            (env->eflags & IF_MASK) &&
 383            !(env->eflags & VM_MASK) &&
 384            (env->kqemu_enabled == 2 ||
 385             ((env->hflags & HF_CPL_MASK) == 3 &&
 386              (env->eflags & IOPL_MASK) != IOPL_MASK)));
 387 }
 388
 389 #endif
 390 #endif