Fix off-by-one memory region sizes.
[qemu/mini2440.git] / hw / pl050.c
blob521c9e61152887a1caf6b44d5c62e8e619034e67
1 /*
2 * Arm PrimeCell PL050 Keyboard / Mouse Interface
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
8 */
10 #include "vl.h"
12 typedef struct {
13 void *dev;
14 uint32_t base;
15 uint32_t cr;
16 uint32_t clk;
17 uint32_t last;
18 int pending;
19 qemu_irq irq;
20 int is_mouse;
21 } pl050_state;
23 #define PL050_TXEMPTY (1 << 6)
24 #define PL050_TXBUSY (1 << 5)
25 #define PL050_RXFULL (1 << 4)
26 #define PL050_RXBUSY (1 << 3)
27 #define PL050_RXPARITY (1 << 2)
28 #define PL050_KMIC (1 << 1)
29 #define PL050_KMID (1 << 0)
31 static const unsigned char pl050_id[] =
32 { 0x50, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
34 static void pl050_update(void *opaque, int level)
36 pl050_state *s = (pl050_state *)opaque;
37 int raise;
39 s->pending = level;
40 raise = (s->pending && (s->cr & 0x10) != 0)
41 || (s->cr & 0x08) != 0;
42 qemu_set_irq(s->irq, raise);
45 static uint32_t pl050_read(void *opaque, target_phys_addr_t offset)
47 pl050_state *s = (pl050_state *)opaque;
48 offset -= s->base;
49 if (offset >= 0xfe0 && offset < 0x1000)
50 return pl050_id[(offset - 0xfe0) >> 2];
52 switch (offset >> 2) {
53 case 0: /* KMICR */
54 return s->cr;
55 case 1: /* KMISTAT */
57 uint8_t val;
58 uint32_t stat;
60 val = s->last;
61 val = val ^ (val >> 4);
62 val = val ^ (val >> 2);
63 val = (val ^ (val >> 1)) & 1;
65 stat = PL050_TXEMPTY;
66 if (val)
67 stat |= PL050_RXPARITY;
68 if (s->pending)
69 stat |= PL050_RXFULL;
71 return stat;
73 case 2: /* KMIDATA */
74 if (s->pending)
75 s->last = ps2_read_data(s->dev);
76 return s->last;
77 case 3: /* KMICLKDIV */
78 return s->clk;
79 case 4: /* KMIIR */
80 return s->pending | 2;
81 default:
82 cpu_abort (cpu_single_env, "pl050_read: Bad offset %x\n", offset);
83 return 0;
87 static void pl050_write(void *opaque, target_phys_addr_t offset,
88 uint32_t value)
90 pl050_state *s = (pl050_state *)opaque;
91 offset -= s->base;
92 switch (offset >> 2) {
93 case 0: /* KMICR */
94 s->cr = value;
95 pl050_update(s, s->pending);
96 /* ??? Need to implement the enable/disable bit. */
97 break;
98 case 2: /* KMIDATA */
99 /* ??? This should toggle the TX interrupt line. */
100 /* ??? This means kbd/mouse can block each other. */
101 if (s->is_mouse) {
102 ps2_write_mouse(s->dev, value);
103 } else {
104 ps2_write_keyboard(s->dev, value);
106 break;
107 case 3: /* KMICLKDIV */
108 s->clk = value;
109 return;
110 default:
111 cpu_abort (cpu_single_env, "pl050_write: Bad offset %x\n", offset);
114 static CPUReadMemoryFunc *pl050_readfn[] = {
115 pl050_read,
116 pl050_read,
117 pl050_read
120 static CPUWriteMemoryFunc *pl050_writefn[] = {
121 pl050_write,
122 pl050_write,
123 pl050_write
126 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse)
128 int iomemtype;
129 pl050_state *s;
131 s = (pl050_state *)qemu_mallocz(sizeof(pl050_state));
132 iomemtype = cpu_register_io_memory(0, pl050_readfn,
133 pl050_writefn, s);
134 cpu_register_physical_memory(base, 0x00001000, iomemtype);
135 s->base = base;
136 s->irq = irq;
137 s->is_mouse = is_mouse;
138 if (is_mouse)
139 s->dev = ps2_mouse_init(pl050_update, s);
140 else
141 s->dev = ps2_kbd_init(pl050_update, s);
142 /* ??? Save/restore. */