target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_ARM_H
  21 #define CPU_ARM_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define ELF_MACHINE     EM_ARM
  26
  27 #include "cpu-defs.h"
  28
  29 #include "softfloat.h"
  30
  31 #define TARGET_HAS_ICE 1
  32
  33 #define EXCP_UDEF            1   /* undefined instruction */
  34 #define EXCP_SWI             2   /* software interrupt */
  35 #define EXCP_PREFETCH_ABORT  3
  36 #define EXCP_DATA_ABORT      4
  37 #define EXCP_IRQ             5
  38 #define EXCP_FIQ             6
  39 #define EXCP_BKPT            7
  40
  41 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  42                             int srcreg, int operand, uint32_t value);
  43 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  44                                int dstreg, int operand);
  45
  46 /* We currently assume float and double are IEEE single and double
  47    precision respectively.
  48    Doing runtime conversions is tricky because VFP registers may contain
  49    integer values (eg. as the result of a FTOSI instruction).
  50    s<2n> maps to the least significant half of d<n>
  51    s<2n+1> maps to the most significant half of d<n>
  52  */
  53
  54 typedef struct CPUARMState {
  55     /* Regs for current mode.  */
  56     uint32_t regs[16];
  57     /* Frequently accessed CPSR bits are stored separately for efficiently.
  58        This contains all the other bits.  Use cpsr_{read,write} to access
  59        the whole CPSR.  */
  60     uint32_t uncached_cpsr;
  61     uint32_t spsr;
  62
  63     /* Banked registers.  */
  64     uint32_t banked_spsr[6];
  65     uint32_t banked_r13[6];
  66     uint32_t banked_r14[6];
  67
  68     /* These hold r8-r12.  */
  69     uint32_t usr_regs[5];
  70     uint32_t fiq_regs[5];
  71
  72     /* cpsr flag cache for faster execution */
  73     uint32_t CF; /* 0 or 1 */
  74     uint32_t VF; /* V is the bit 31. All other bits are undefined */
  75     uint32_t NZF; /* N is bit 31. Z is computed from NZF */
  76     uint32_t QF; /* 0 or 1 */
  77
  78     int thumb; /* 0 = arm mode, 1 = thumb mode */
  79
  80     /* System control coprocessor (cp15) */
  81     struct {
  82         uint32_t c0_cpuid;
  83         uint32_t c0_cachetype;
  84         uint32_t c1_sys; /* System control register.  */
  85         uint32_t c1_coproc; /* Coprocessor access register.  */
  86         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
  87         uint32_t c2_base; /* MMU translation table base.  */
  88         uint32_t c2_data; /* MPU data cachable bits.  */
  89         uint32_t c2_insn; /* MPU instruction cachable bits.  */
  90         uint32_t c3; /* MMU domain access control register
  91                         MPU write buffer control.  */
  92         uint32_t c5_insn; /* Fault status registers.  */
  93         uint32_t c5_data;
  94         uint32_t c6_region[8]; /* MPU base/size registers.  */
  95         uint32_t c6_insn; /* Fault address registers.  */
  96         uint32_t c6_data;
  97         uint32_t c9_insn; /* Cache lockdown registers.  */
  98         uint32_t c9_data;
  99         uint32_t c13_fcse; /* FCSE PID.  */
 100         uint32_t c13_context; /* Context ID.  */
 101         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 102     } cp15;
 103
 104     /* Coprocessor IO used by peripherals */
 105     struct {
 106         ARMReadCPFunc *cp_read;
 107         ARMWriteCPFunc *cp_write;
 108         void *opaque;
 109     } cp[15];
 110
 111     /* Internal CPU feature flags.  */
 112     uint32_t features;
 113
 114     /* exception/interrupt handling */
 115     jmp_buf jmp_env;
 116     int exception_index;
 117     int interrupt_request;
 118     int user_mode_only;
 119     int halted;
 120
 121     /* VFP coprocessor state.  */
 122     struct {
 123         float64 regs[16];
 124
 125         uint32_t xregs[16];
 126         /* We store these fpcsr fields separately for convenience.  */
 127         int vec_len;
 128         int vec_stride;
 129
 130         /* Temporary variables if we don't have spare fp regs.  */
 131         float32 tmp0s, tmp1s;
 132         float64 tmp0d, tmp1d;
 133
 134         float_status fp_status;
 135     } vfp;
 136
 137     /* iwMMXt coprocessor state.  */
 138     struct {
 139         uint64_t regs[16];
 140         uint64_t val;
 141
 142         uint32_t cregs[16];
 143     } iwmmxt;
 144
 145 #if defined(CONFIG_USER_ONLY)
 146     /* For usermode syscall translation.  */
 147     int eabi;
 148 #endif
 149
 150     CPU_COMMON
 151
 152     /* These fields after the common ones so they are preserved on reset.  */
 153     int ram_size;
 154     const char *kernel_filename;
 155     const char *kernel_cmdline;
 156     const char *initrd_filename;
 157     int board_id;
 158     target_phys_addr_t loader_start;
 159 } CPUARMState;
 160
 161 CPUARMState *cpu_arm_init(void);
 162 int cpu_arm_exec(CPUARMState *s);
 163 void cpu_arm_close(CPUARMState *s);
 164 void do_interrupt(CPUARMState *);
 165 void switch_mode(CPUARMState *, int);
 166
 167 /* you can call this signal handler from your SIGBUS and SIGSEGV
 168    signal handlers to inform the virtual CPU of exceptions. non zero
 169    is returned if the signal was handled by the virtual CPU.  */
 170 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 171                            void *puc);
 172
 173 #define CPSR_M (0x1f)
 174 #define CPSR_T (1 << 5)
 175 #define CPSR_F (1 << 6)
 176 #define CPSR_I (1 << 7)
 177 #define CPSR_A (1 << 8)
 178 #define CPSR_E (1 << 9)
 179 #define CPSR_IT_2_7 (0xfc00)
 180 /* Bits 20-23 reserved.  */
 181 #define CPSR_J (1 << 24)
 182 #define CPSR_IT_0_1 (3 << 25)
 183 #define CPSR_Q (1 << 27)
 184 #define CPSR_NZCV (0xf << 28)
 185
 186 #define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV)
 187 /* Return the current CPSR value.  */
 188 static inline uint32_t cpsr_read(CPUARMState *env)
 189 {
 190     int ZF;
 191     ZF = (env->NZF == 0);
 192     return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
 193         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 194         | (env->thumb << 5);
 195 }
 196
 197 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 198 static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 199 {
 200     /* NOTE: N = 1 and Z = 1 cannot be stored currently */
 201     if (mask & CPSR_NZCV) {
 202         env->NZF = (val & 0xc0000000) ^ 0x40000000;
 203         env->CF = (val >> 29) & 1;
 204         env->VF = (val << 3) & 0x80000000;
 205     }
 206     if (mask & CPSR_Q)
 207         env->QF = ((val & CPSR_Q) != 0);
 208     if (mask & CPSR_T)
 209         env->thumb = ((val & CPSR_T) != 0);
 210
 211     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
 212         switch_mode(env, val & CPSR_M);
 213     }
 214     mask &= ~CACHED_CPSR_BITS;
 215     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
 216 }
 217
 218 enum arm_cpu_mode {
 219   ARM_CPU_MODE_USR = 0x10,
 220   ARM_CPU_MODE_FIQ = 0x11,
 221   ARM_CPU_MODE_IRQ = 0x12,
 222   ARM_CPU_MODE_SVC = 0x13,
 223   ARM_CPU_MODE_ABT = 0x17,
 224   ARM_CPU_MODE_UND = 0x1b,
 225   ARM_CPU_MODE_SYS = 0x1f
 226 };
 227
 228 /* VFP system registers.  */
 229 #define ARM_VFP_FPSID   0
 230 #define ARM_VFP_FPSCR   1
 231 #define ARM_VFP_FPEXC   8
 232 #define ARM_VFP_FPINST  9
 233 #define ARM_VFP_FPINST2 10
 234
 235 /* iwMMXt coprocessor control registers.  */
 236 #define ARM_IWMMXT_wCID         0
 237 #define ARM_IWMMXT_wCon         1
 238 #define ARM_IWMMXT_wCSSF        2
 239 #define ARM_IWMMXT_wCASF        3
 240 #define ARM_IWMMXT_wCGR0        8
 241 #define ARM_IWMMXT_wCGR1        9
 242 #define ARM_IWMMXT_wCGR2        10
 243 #define ARM_IWMMXT_wCGR3        11
 244
 245 enum arm_features {
 246     ARM_FEATURE_VFP,
 247     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 248     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 249     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 250     ARM_FEATURE_MPU     /* Only has Memory Protection Unit, not full MMU.  */
 251 };
 252
 253 static inline int arm_feature(CPUARMState *env, int feature)
 254 {
 255     return (env->features & (1u << feature)) != 0;
 256 }
 257
 258 void arm_cpu_list(void);
 259 void cpu_arm_set_model(CPUARMState *env, const char *name);
 260
 261 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 262                        ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
 263                        void *opaque);
 264
 265 #define ARM_CPUID_ARM1026   0x4106a262
 266 #define ARM_CPUID_ARM926    0x41069265
 267 #define ARM_CPUID_ARM946    0x41059461
 268 #define ARM_CPUID_PXA250    0x69052100
 269 #define ARM_CPUID_PXA255    0x69052d00
 270 #define ARM_CPUID_PXA260    0x69052903
 271 #define ARM_CPUID_PXA261    0x69052d05
 272 #define ARM_CPUID_PXA262    0x69052d06
 273 #define ARM_CPUID_PXA270    0x69054110
 274 #define ARM_CPUID_PXA270_A0 0x69054110
 275 #define ARM_CPUID_PXA270_A1 0x69054111
 276 #define ARM_CPUID_PXA270_B0 0x69054112
 277 #define ARM_CPUID_PXA270_B1 0x69054113
 278 #define ARM_CPUID_PXA270_C0 0x69054114
 279 #define ARM_CPUID_PXA270_C5 0x69054117
 280
 281 #if defined(CONFIG_USER_ONLY)
 282 #define TARGET_PAGE_BITS 12
 283 #else
 284 /* The ARM MMU allows 1k pages.  */
 285 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 286    architecture revisions.  Maybe an a configure option to disable them.  */
 287 #define TARGET_PAGE_BITS 10
 288 #endif
 289
 290 #define CPUState CPUARMState
 291 #define cpu_init cpu_arm_init
 292 #define cpu_exec cpu_arm_exec
 293 #define cpu_gen_code cpu_arm_gen_code
 294 #define cpu_signal_handler cpu_arm_signal_handler
 295
 296 #include "cpu-all.h"
 297
 298 #endif