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Fix incorrect return type.
[qemu/mini2440.git] / hw / pci.c
blobfd4ccd94758ea1a10755991c4d9c08497a3a7193
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
25
26 //#define DEBUG_PCI
27
28 #define PCI_VENDOR_ID 0x00 /* 16 bits */
29 #define PCI_DEVICE_ID 0x02 /* 16 bits */
30 #define PCI_COMMAND 0x04 /* 16 bits */
31 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
32 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
33 #define PCI_CLASS_DEVICE 0x0a /* Device class */
34 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
35 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
36 #define PCI_MIN_GNT 0x3e /* 8 bits */
37 #define PCI_MAX_LAT 0x3f /* 8 bits */
38
39 /* just used for simpler irq handling. */
40 #define PCI_DEVICES_MAX 64
41 #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
42
43 struct PCIBus {
44 int bus_num;
45 int devfn_min;
46 void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level);
47 uint32_t config_reg; /* XXX: suppress */
48 /* low level pic */
49 SetIRQFunc *low_set_irq;
50 void *irq_opaque;
51 PCIDevice *devices[256];
52 };
53
54 target_phys_addr_t pci_mem_base;
55 static int pci_irq_index;
56 static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
57 static PCIBus *first_bus;
58
59 static PCIBus *pci_register_bus(void)
60 {
61 PCIBus *bus;
62 bus = qemu_mallocz(sizeof(PCIBus));
63 first_bus = bus;
64 return bus;
65 }
66
67 void generic_pci_save(QEMUFile* f, void *opaque)
68 {
69 PCIDevice* s=(PCIDevice*)opaque;
70
71 qemu_put_buffer(f, s->config, 256);
72 }
73
74 int generic_pci_load(QEMUFile* f, void *opaque, int version_id)
75 {
76 PCIDevice* s=(PCIDevice*)opaque;
77
78 if (version_id != 1)
79 return -EINVAL;
80
81 qemu_get_buffer(f, s->config, 256);
82 return 0;
83 }
84
85 /* -1 for devfn means auto assign */
86 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
87 int instance_size, int devfn,
88 PCIConfigReadFunc *config_read,
89 PCIConfigWriteFunc *config_write)
90 {
91 PCIDevice *pci_dev;
92
93 if (pci_irq_index >= PCI_DEVICES_MAX)
94 return NULL;
95
96 if (devfn < 0) {
97 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
98 if (!bus->devices[devfn])
99 goto found;
100 }
101 return NULL;
102 found: ;
103 }
104 pci_dev = qemu_mallocz(instance_size);
105 if (!pci_dev)
106 return NULL;
107 pci_dev->bus = bus;
108 pci_dev->devfn = devfn;
109 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
110
111 if (!config_read)
112 config_read = pci_default_read_config;
113 if (!config_write)
114 config_write = pci_default_write_config;
115 pci_dev->config_read = config_read;
116 pci_dev->config_write = config_write;
117 pci_dev->irq_index = pci_irq_index++;
118 bus->devices[devfn] = pci_dev;
119 return pci_dev;
120 }
121
122 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
123 uint32_t size, int type,
124 PCIMapIORegionFunc *map_func)
125 {
126 PCIIORegion *r;
127
128 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
129 return;
130 r = &pci_dev->io_regions[region_num];
131 r->addr = -1;
132 r->size = size;
133 r->type = type;
134 r->map_func = map_func;
135 }
136
137 static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val)
138 {
139 PCIBus *s = opaque;
140 s->config_reg = val;
141 }
142
143 static uint32_t pci_addr_readl(void* opaque, uint32_t addr)
144 {
145 PCIBus *s = opaque;
146 return s->config_reg;
147 }
148
149 static void pci_update_mappings(PCIDevice *d)
150 {
151 PCIIORegion *r;
152 int cmd, i;
153 uint32_t last_addr, new_addr, config_ofs;
154
155 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
156 for(i = 0; i < PCI_NUM_REGIONS; i++) {
157 r = &d->io_regions[i];
158 if (i == PCI_ROM_SLOT) {
159 config_ofs = 0x30;
160 } else {
161 config_ofs = 0x10 + i * 4;
162 }
163 if (r->size != 0) {
164 if (r->type & PCI_ADDRESS_SPACE_IO) {
165 if (cmd & PCI_COMMAND_IO) {
166 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
167 config_ofs));
168 new_addr = new_addr & ~(r->size - 1);
169 last_addr = new_addr + r->size - 1;
170 /* NOTE: we have only 64K ioports on PC */
171 if (last_addr <= new_addr || new_addr == 0 ||
172 last_addr >= 0x10000) {
173 new_addr = -1;
174 }
175 } else {
176 new_addr = -1;
177 }
178 } else {
179 if (cmd & PCI_COMMAND_MEMORY) {
180 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
181 config_ofs));
182 /* the ROM slot has a specific enable bit */
183 if (i == PCI_ROM_SLOT && !(new_addr & 1))
184 goto no_mem_map;
185 new_addr = new_addr & ~(r->size - 1);
186 last_addr = new_addr + r->size - 1;
187 /* NOTE: we do not support wrapping */
188 /* XXX: as we cannot support really dynamic
189 mappings, we handle specific values as invalid
190 mappings. */
191 if (last_addr <= new_addr || new_addr == 0 ||
192 last_addr == -1) {
193 new_addr = -1;
194 }
195 } else {
196 no_mem_map:
197 new_addr = -1;
198 }
199 }
200 /* now do the real mapping */
201 if (new_addr != r->addr) {
202 if (r->addr != -1) {
203 if (r->type & PCI_ADDRESS_SPACE_IO) {
204 int class;
205 /* NOTE: specific hack for IDE in PC case:
206 only one byte must be mapped. */
207 class = d->config[0x0a] | (d->config[0x0b] << 8);
208 if (class == 0x0101 && r->size == 4) {
209 isa_unassign_ioport(r->addr + 2, 1);
210 } else {
211 isa_unassign_ioport(r->addr, r->size);
212 }
213 } else {
214 cpu_register_physical_memory(r->addr + pci_mem_base,
215 r->size,
216 IO_MEM_UNASSIGNED);
217 }
218 }
219 r->addr = new_addr;
220 if (r->addr != -1) {
221 r->map_func(d, i, r->addr, r->size, r->type);
222 }
223 }
224 }
225 }
226 }
227
228 uint32_t pci_default_read_config(PCIDevice *d,
229 uint32_t address, int len)
230 {
231 uint32_t val;
232 switch(len) {
233 case 1:
234 val = d->config[address];
235 break;
236 case 2:
237 val = le16_to_cpu(*(uint16_t *)(d->config + address));
238 break;
239 default:
240 case 4:
241 val = le32_to_cpu(*(uint32_t *)(d->config + address));
242 break;
243 }
244 return val;
245 }
246
247 void pci_default_write_config(PCIDevice *d,
248 uint32_t address, uint32_t val, int len)
249 {
250 int can_write, i;
251 uint32_t end, addr;
252
253 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
254 (address >= 0x30 && address < 0x34))) {
255 PCIIORegion *r;
256 int reg;
257
258 if ( address >= 0x30 ) {
259 reg = PCI_ROM_SLOT;
260 }else{
261 reg = (address - 0x10) >> 2;
262 }
263 r = &d->io_regions[reg];
264 if (r->size == 0)
265 goto default_config;
266 /* compute the stored value */
267 if (reg == PCI_ROM_SLOT) {
268 /* keep ROM enable bit */
269 val &= (~(r->size - 1)) | 1;
270 } else {
271 val &= ~(r->size - 1);
272 val |= r->type;
273 }
274 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
275 pci_update_mappings(d);
276 return;
277 }
278 default_config:
279 /* not efficient, but simple */
280 addr = address;
281 for(i = 0; i < len; i++) {
282 /* default read/write accesses */
283 switch(d->config[0x0e]) {
284 case 0x00:
285 case 0x80:
286 switch(addr) {
287 case 0x00:
288 case 0x01:
289 case 0x02:
290 case 0x03:
291 case 0x08:
292 case 0x09:
293 case 0x0a:
294 case 0x0b:
295 case 0x0e:
296 case 0x10 ... 0x27: /* base */
297 case 0x30 ... 0x33: /* rom */
298 case 0x3d:
299 can_write = 0;
300 break;
301 default:
302 can_write = 1;
303 break;
304 }
305 break;
306 default:
307 case 0x01:
308 switch(addr) {
309 case 0x00:
310 case 0x01:
311 case 0x02:
312 case 0x03:
313 case 0x08:
314 case 0x09:
315 case 0x0a:
316 case 0x0b:
317 case 0x0e:
318 case 0x38 ... 0x3b: /* rom */
319 case 0x3d:
320 can_write = 0;
321 break;
322 default:
323 can_write = 1;
324 break;
325 }
326 break;
327 }
328 if (can_write) {
329 d->config[addr] = val;
330 }
331 addr++;
332 val >>= 8;
333 }
334
335 end = address + len;
336 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
337 /* if the command register is modified, we must modify the mappings */
338 pci_update_mappings(d);
339 }
340 }
341
342 static void pci_data_write(void *opaque, uint32_t addr,
343 uint32_t val, int len)
344 {
345 PCIBus *s = opaque;
346 PCIDevice *pci_dev;
347 int config_addr, bus_num;
348
349 #if defined(DEBUG_PCI) && 0
350 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
351 s->config_reg, val, len);
352 #endif
353 if (!(s->config_reg & (1 << 31))) {
354 return;
355 }
356 bus_num = (s->config_reg >> 16) & 0xff;
357 if (bus_num != 0)
358 return;
359 pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
360 if (!pci_dev)
361 return;
362 config_addr = (s->config_reg & 0xfc) | (addr & 3);
363 #if defined(DEBUG_PCI)
364 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
365 pci_dev->name, config_addr, val, len);
366 #endif
367 pci_dev->config_write(pci_dev, config_addr, val, len);
368 }
369
370 static uint32_t pci_data_read(void *opaque, uint32_t addr,
371 int len)
372 {
373 PCIBus *s = opaque;
374 PCIDevice *pci_dev;
375 int config_addr, bus_num;
376 uint32_t val;
377
378 if (!(s->config_reg & (1 << 31)))
379 goto fail;
380 bus_num = (s->config_reg >> 16) & 0xff;
381 if (bus_num != 0)
382 goto fail;
383 pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
384 if (!pci_dev) {
385 fail:
386 switch(len) {
387 case 1:
388 val = 0xff;
389 break;
390 case 2:
391 val = 0xffff;
392 break;
393 default:
394 case 4:
395 val = 0xffffffff;
396 break;
397 }
398 goto the_end;
399 }
400 config_addr = (s->config_reg & 0xfc) | (addr & 3);
401 val = pci_dev->config_read(pci_dev, config_addr, len);
402 #if defined(DEBUG_PCI)
403 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
404 pci_dev->name, config_addr, val, len);
405 #endif
406 the_end:
407 #if defined(DEBUG_PCI) && 0
408 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
409 s->config_reg, val, len);
410 #endif
411 return val;
412 }
413
414 static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)
415 {
416 pci_data_write(opaque, addr, val, 1);
417 }
418
419 static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)
420 {
421 pci_data_write(opaque, addr, val, 2);
422 }
423
424 static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)
425 {
426 pci_data_write(opaque, addr, val, 4);
427 }
428
429 static uint32_t pci_data_readb(void* opaque, uint32_t addr)
430 {
431 return pci_data_read(opaque, addr, 1);
432 }
433
434 static uint32_t pci_data_readw(void* opaque, uint32_t addr)
435 {
436 return pci_data_read(opaque, addr, 2);
437 }
438
439 static uint32_t pci_data_readl(void* opaque, uint32_t addr)
440 {
441 return pci_data_read(opaque, addr, 4);
442 }
443
444 /* i440FX PCI bridge */
445
446 static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level);
447
448 PCIBus *i440fx_init(void)
449 {
450 PCIBus *s;
451 PCIDevice *d;
452
453 s = pci_register_bus();
454 s->set_irq = piix3_set_irq;
455
456 register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
457 register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
458
459 register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
460 register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
461 register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
462 register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
463 register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
464 register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
465
466 d = pci_register_device(s, "i440FX", sizeof(PCIDevice), 0,
467 NULL, NULL);
468
469 d->config[0x00] = 0x86; // vendor_id
470 d->config[0x01] = 0x80;
471 d->config[0x02] = 0x37; // device_id
472 d->config[0x03] = 0x12;
473 d->config[0x08] = 0x02; // revision
474 d->config[0x0a] = 0x00; // class_sub = host2pci
475 d->config[0x0b] = 0x06; // class_base = PCI_bridge
476 d->config[0x0e] = 0x00; // header_type
477 return s;
478 }
479
480 /* PIIX3 PCI to ISA bridge */
481
482 typedef struct PIIX3State {
483 PCIDevice dev;
484 } PIIX3State;
485
486 PIIX3State *piix3_state;
487
488 /* return the global irq number corresponding to a given device irq
489 pin. We could also use the bus number to have a more precise
490 mapping. */
491 static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
492 {
493 int slot_addend;
494 slot_addend = (pci_dev->devfn >> 3) - 1;
495 return (irq_num + slot_addend) & 3;
496 }
497
498 static inline int get_pci_irq_level(int irq_num)
499 {
500 int pic_level;
501 #if (PCI_IRQ_WORDS == 2)
502 pic_level = ((pci_irq_levels[irq_num][0] |
503 pci_irq_levels[irq_num][1]) != 0);
504 #else
505 {
506 int i;
507 pic_level = 0;
508 for(i = 0; i < PCI_IRQ_WORDS; i++) {
509 if (pci_irq_levels[irq_num][i]) {
510 pic_level = 1;
511 break;
512 }
513 }
514 }
515 #endif
516 return pic_level;
517 }
518
519 static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level)
520 {
521 int irq_index, shift, pic_irq, pic_level;
522 uint32_t *p;
523
524 irq_num = pci_slot_get_pirq(pci_dev, irq_num);
525 irq_index = pci_dev->irq_index;
526 p = &pci_irq_levels[irq_num][irq_index >> 5];
527 shift = (irq_index & 0x1f);
528 *p = (*p & ~(1 << shift)) | (level << shift);
529
530 /* now we change the pic irq level according to the piix irq mappings */
531 /* XXX: optimize */
532 pic_irq = piix3_state->dev.config[0x60 + irq_num];
533 if (pic_irq < 16) {
534 /* the pic level is the logical OR of all the PCI irqs mapped
535 to it */
536 pic_level = 0;
537 if (pic_irq == piix3_state->dev.config[0x60])
538 pic_level |= get_pci_irq_level(0);
539 if (pic_irq == piix3_state->dev.config[0x61])
540 pic_level |= get_pci_irq_level(1);
541 if (pic_irq == piix3_state->dev.config[0x62])
542 pic_level |= get_pci_irq_level(2);
543 if (pic_irq == piix3_state->dev.config[0x63])
544 pic_level |= get_pci_irq_level(3);
545 pic_set_irq(pic_irq, pic_level);
546 }
547 }
548
549 static void piix3_reset(PIIX3State *d)
550 {
551 uint8_t *pci_conf = d->dev.config;
552
553 pci_conf[0x04] = 0x07; // master, memory and I/O
554 pci_conf[0x05] = 0x00;
555 pci_conf[0x06] = 0x00;
556 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
557 pci_conf[0x4c] = 0x4d;
558 pci_conf[0x4e] = 0x03;
559 pci_conf[0x4f] = 0x00;
560 pci_conf[0x60] = 0x80;
561 pci_conf[0x69] = 0x02;
562 pci_conf[0x70] = 0x80;
563 pci_conf[0x76] = 0x0c;
564 pci_conf[0x77] = 0x0c;
565 pci_conf[0x78] = 0x02;
566 pci_conf[0x79] = 0x00;
567 pci_conf[0x80] = 0x00;
568 pci_conf[0x82] = 0x00;
569 pci_conf[0xa0] = 0x08;
570 pci_conf[0xa0] = 0x08;
571 pci_conf[0xa2] = 0x00;
572 pci_conf[0xa3] = 0x00;
573 pci_conf[0xa4] = 0x00;
574 pci_conf[0xa5] = 0x00;
575 pci_conf[0xa6] = 0x00;
576 pci_conf[0xa7] = 0x00;
577 pci_conf[0xa8] = 0x0f;
578 pci_conf[0xaa] = 0x00;
579 pci_conf[0xab] = 0x00;
580 pci_conf[0xac] = 0x00;
581 pci_conf[0xae] = 0x00;
582 }
583
584 void piix3_init(PCIBus *bus)
585 {
586 PIIX3State *d;
587 uint8_t *pci_conf;
588
589 d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State),
590 -1, NULL, NULL);
591 register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d);
592
593 piix3_state = d;
594 pci_conf = d->dev.config;
595
596 pci_conf[0x00] = 0x86; // Intel
597 pci_conf[0x01] = 0x80;
598 pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
599 pci_conf[0x03] = 0x70;
600 pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
601 pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
602 pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
603
604 piix3_reset(d);
605 }
606
607 /* PREP pci init */
608
609 static inline void set_config(PCIBus *s, target_phys_addr_t addr)
610 {
611 int devfn, i;
612
613 for(i = 0; i < 11; i++) {
614 if ((addr & (1 << (11 + i))) != 0)
615 break;
616 }
617 devfn = ((addr >> 8) & 7) | (i << 3);
618 s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8);
619 }
620
621 static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
622 {
623 PCIBus *s = opaque;
624 set_config(s, addr);
625 pci_data_write(s, addr, val, 1);
626 }
627
628 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
629 {
630 PCIBus *s = opaque;
631 set_config(s, addr);
632 #ifdef TARGET_WORDS_BIGENDIAN
633 val = bswap16(val);
634 #endif
635 pci_data_write(s, addr, val, 2);
636 }
637
638 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
639 {
640 PCIBus *s = opaque;
641 set_config(s, addr);
642 #ifdef TARGET_WORDS_BIGENDIAN
643 val = bswap32(val);
644 #endif
645 pci_data_write(s, addr, val, 4);
646 }
647
648 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
649 {
650 PCIBus *s = opaque;
651 uint32_t val;
652 set_config(s, addr);
653 val = pci_data_read(s, addr, 1);
654 return val;
655 }
656
657 static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
658 {
659 PCIBus *s = opaque;
660 uint32_t val;
661 set_config(s, addr);
662 val = pci_data_read(s, addr, 2);
663 #ifdef TARGET_WORDS_BIGENDIAN
664 val = bswap16(val);
665 #endif
666 return val;
667 }
668
669 static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
670 {
671 PCIBus *s = opaque;
672 uint32_t val;
673 set_config(s, addr);
674 val = pci_data_read(s, addr, 4);
675 #ifdef TARGET_WORDS_BIGENDIAN
676 val = bswap32(val);
677 #endif
678 return val;
679 }
680
681 static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
682 &PPC_PCIIO_writeb,
683 &PPC_PCIIO_writew,
684 &PPC_PCIIO_writel,
685 };
686
687 static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
688 &PPC_PCIIO_readb,
689 &PPC_PCIIO_readw,
690 &PPC_PCIIO_readl,
691 };
692
693 static void prep_set_irq(PCIDevice *d, int irq_num, int level)
694 {
695 /* XXX: we do not simulate the hardware - we rely on the BIOS to
696 set correctly for irq line field */
697 pic_set_irq(d->config[PCI_INTERRUPT_LINE], level);
698 }
699
700 PCIBus *pci_prep_init(void)
701 {
702 PCIBus *s;
703 PCIDevice *d;
704 int PPC_io_memory;
705
706 s = pci_register_bus();
707 s->set_irq = prep_set_irq;
708
709 register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
710 register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
711
712 register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
713 register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
714 register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
715 register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
716 register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
717 register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
718
719 PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
720 PPC_PCIIO_write, s);
721 cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
722
723 /* PCI host bridge */
724 d = pci_register_device(s, "PREP Host Bridge - Motorola Raven",
725 sizeof(PCIDevice), 0, NULL, NULL);
726 d->config[0x00] = 0x57; // vendor_id : Motorola
727 d->config[0x01] = 0x10;
728 d->config[0x02] = 0x01; // device_id : Raven
729 d->config[0x03] = 0x48;
730 d->config[0x08] = 0x00; // revision
731 d->config[0x0A] = 0x00; // class_sub = pci host
732 d->config[0x0B] = 0x06; // class_base = PCI_bridge
733 d->config[0x0C] = 0x08; // cache_line_size
734 d->config[0x0D] = 0x10; // latency_timer
735 d->config[0x0E] = 0x00; // header_type
736 d->config[0x34] = 0x00; // capabilities_pointer
737
738 return s;
739 }
740
741
742 /* Grackle PCI host */
743 static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
744 uint32_t val)
745 {
746 PCIBus *s = opaque;
747 #ifdef TARGET_WORDS_BIGENDIAN
748 val = bswap32(val);
749 #endif
750 s->config_reg = val;
751 }
752
753 static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
754 {
755 PCIBus *s = opaque;
756 uint32_t val;
757
758 val = s->config_reg;
759 #ifdef TARGET_WORDS_BIGENDIAN
760 val = bswap32(val);
761 #endif
762 return val;
763 }
764
765 static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
766 &pci_grackle_config_writel,
767 &pci_grackle_config_writel,
768 &pci_grackle_config_writel,
769 };
770
771 static CPUReadMemoryFunc *pci_grackle_config_read[] = {
772 &pci_grackle_config_readl,
773 &pci_grackle_config_readl,
774 &pci_grackle_config_readl,
775 };
776
777 static void pci_grackle_writeb (void *opaque, target_phys_addr_t addr,
778 uint32_t val)
779 {
780 PCIBus *s = opaque;
781 pci_data_write(s, addr, val, 1);
782 }
783
784 static void pci_grackle_writew (void *opaque, target_phys_addr_t addr,
785 uint32_t val)
786 {
787 PCIBus *s = opaque;
788 #ifdef TARGET_WORDS_BIGENDIAN
789 val = bswap16(val);
790 #endif
791 pci_data_write(s, addr, val, 2);
792 }
793
794 static void pci_grackle_writel (void *opaque, target_phys_addr_t addr,
795 uint32_t val)
796 {
797 PCIBus *s = opaque;
798 #ifdef TARGET_WORDS_BIGENDIAN
799 val = bswap32(val);
800 #endif
801 pci_data_write(s, addr, val, 4);
802 }
803
804 static uint32_t pci_grackle_readb (void *opaque, target_phys_addr_t addr)
805 {
806 PCIBus *s = opaque;
807 uint32_t val;
808 val = pci_data_read(s, addr, 1);
809 return val;
810 }
811
812 static uint32_t pci_grackle_readw (void *opaque, target_phys_addr_t addr)
813 {
814 PCIBus *s = opaque;
815 uint32_t val;
816 val = pci_data_read(s, addr, 2);
817 #ifdef TARGET_WORDS_BIGENDIAN
818 val = bswap16(val);
819 #endif
820 return val;
821 }
822
823 static uint32_t pci_grackle_readl (void *opaque, target_phys_addr_t addr)
824 {
825 PCIBus *s = opaque;
826 uint32_t val;
827
828 val = pci_data_read(s, addr, 4);
829 #ifdef TARGET_WORDS_BIGENDIAN
830 val = bswap32(val);
831 #endif
832 return val;
833 }
834
835 static CPUWriteMemoryFunc *pci_grackle_write[] = {
836 &pci_grackle_writeb,
837 &pci_grackle_writew,
838 &pci_grackle_writel,
839 };
840
841 static CPUReadMemoryFunc *pci_grackle_read[] = {
842 &pci_grackle_readb,
843 &pci_grackle_readw,
844 &pci_grackle_readl,
845 };
846
847 void pci_set_pic(PCIBus *bus, SetIRQFunc *set_irq, void *irq_opaque)
848 {
849 bus->low_set_irq = set_irq;
850 bus->irq_opaque = irq_opaque;
851 }
852
853 /* XXX: we do not simulate the hardware - we rely on the BIOS to
854 set correctly for irq line field */
855 static void pci_set_irq_simple(PCIDevice *d, int irq_num, int level)
856 {
857 PCIBus *s = d->bus;
858 s->low_set_irq(s->irq_opaque, d->config[PCI_INTERRUPT_LINE], level);
859 }
860
861 PCIBus *pci_grackle_init(uint32_t base)
862 {
863 PCIBus *s;
864 PCIDevice *d;
865 int pci_mem_config, pci_mem_data;
866
867 s = pci_register_bus();
868 s->set_irq = pci_set_irq_simple;
869
870 pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
871 pci_grackle_config_write, s);
872 pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,
873 pci_grackle_write, s);
874 cpu_register_physical_memory(base, 0x1000, pci_mem_config);
875 cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);
876 d = pci_register_device(s, "Grackle host bridge", sizeof(PCIDevice),
877 0, NULL, NULL);
878 d->config[0x00] = 0x57; // vendor_id
879 d->config[0x01] = 0x10;
880 d->config[0x02] = 0x02; // device_id
881 d->config[0x03] = 0x00;
882 d->config[0x08] = 0x00; // revision
883 d->config[0x09] = 0x01;
884 d->config[0x0a] = 0x00; // class_sub = host
885 d->config[0x0b] = 0x06; // class_base = PCI_bridge
886 d->config[0x0e] = 0x00; // header_type
887
888 d->config[0x18] = 0x00; // primary_bus
889 d->config[0x19] = 0x01; // secondary_bus
890 d->config[0x1a] = 0x00; // subordinate_bus
891 d->config[0x1c] = 0x00;
892 d->config[0x1d] = 0x00;
893
894 d->config[0x20] = 0x00; // memory_base
895 d->config[0x21] = 0x00;
896 d->config[0x22] = 0x01; // memory_limit
897 d->config[0x23] = 0x00;
898
899 d->config[0x24] = 0x00; // prefetchable_memory_base
900 d->config[0x25] = 0x00;
901 d->config[0x26] = 0x00; // prefetchable_memory_limit
902 d->config[0x27] = 0x00;
903
904 #if 0
905 /* PCI2PCI bridge same values as PearPC - check this */
906 d->config[0x00] = 0x11; // vendor_id
907 d->config[0x01] = 0x10;
908 d->config[0x02] = 0x26; // device_id
909 d->config[0x03] = 0x00;
910 d->config[0x08] = 0x02; // revision
911 d->config[0x0a] = 0x04; // class_sub = pci2pci
912 d->config[0x0b] = 0x06; // class_base = PCI_bridge
913 d->config[0x0e] = 0x01; // header_type
914
915 d->config[0x18] = 0x0; // primary_bus
916 d->config[0x19] = 0x1; // secondary_bus
917 d->config[0x1a] = 0x1; // subordinate_bus
918 d->config[0x1c] = 0x10; // io_base
919 d->config[0x1d] = 0x20; // io_limit
920
921 d->config[0x20] = 0x80; // memory_base
922 d->config[0x21] = 0x80;
923 d->config[0x22] = 0x90; // memory_limit
924 d->config[0x23] = 0x80;
925
926 d->config[0x24] = 0x00; // prefetchable_memory_base
927 d->config[0x25] = 0x84;
928 d->config[0x26] = 0x00; // prefetchable_memory_limit
929 d->config[0x27] = 0x85;
930 #endif
931 return s;
932 }
933
934 /* Uninorth PCI host (for all Mac99 and newer machines */
935 static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
936 uint32_t val)
937 {
938 PCIBus *s = opaque;
939 int i;
940
941 #ifdef TARGET_WORDS_BIGENDIAN
942 val = bswap32(val);
943 #endif
944
945 for (i = 11; i < 32; i++) {
946 if ((val & (1 << i)) != 0)
947 break;
948 }
949 #if 0
950 s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
951 #else
952 s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11);
953 #endif
954 }
955
956 static uint32_t pci_unin_main_config_readl (void *opaque,
957 target_phys_addr_t addr)
958 {
959 PCIBus *s = opaque;
960 uint32_t val;
961 int devfn;
962
963 devfn = (s->config_reg >> 8) & 0xFF;
964 val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC);
965 #ifdef TARGET_WORDS_BIGENDIAN
966 val = bswap32(val);
967 #endif
968
969 return val;
970 }
971
972 static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
973 &pci_unin_main_config_writel,
974 &pci_unin_main_config_writel,
975 &pci_unin_main_config_writel,
976 };
977
978 static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
979 &pci_unin_main_config_readl,
980 &pci_unin_main_config_readl,
981 &pci_unin_main_config_readl,
982 };
983
984 static void pci_unin_main_writeb (void *opaque, target_phys_addr_t addr,
985 uint32_t val)
986 {
987 PCIBus *s = opaque;
988 pci_data_write(s, addr & 7, val, 1);
989 }
990
991 static void pci_unin_main_writew (void *opaque, target_phys_addr_t addr,
992 uint32_t val)
993 {
994 PCIBus *s = opaque;
995 #ifdef TARGET_WORDS_BIGENDIAN
996 val = bswap16(val);
997 #endif
998 pci_data_write(s, addr & 7, val, 2);
999 }
1000
1001 static void pci_unin_main_writel (void *opaque, target_phys_addr_t addr,
1002 uint32_t val)
1003 {
1004 PCIBus *s = opaque;
1005 #ifdef TARGET_WORDS_BIGENDIAN
1006 val = bswap32(val);
1007 #endif
1008 pci_data_write(s, addr & 7, val, 4);
1009 }
1010
1011 static uint32_t pci_unin_main_readb (void *opaque, target_phys_addr_t addr)
1012 {
1013 PCIBus *s = opaque;
1014 uint32_t val;
1015
1016 val = pci_data_read(s, addr & 7, 1);
1017
1018 return val;
1019 }
1020
1021 static uint32_t pci_unin_main_readw (void *opaque, target_phys_addr_t addr)
1022 {
1023 PCIBus *s = opaque;
1024 uint32_t val;
1025
1026 val = pci_data_read(s, addr & 7, 2);
1027 #ifdef TARGET_WORDS_BIGENDIAN
1028 val = bswap16(val);
1029 #endif
1030
1031 return val;
1032 }
1033
1034 static uint32_t pci_unin_main_readl (void *opaque, target_phys_addr_t addr)
1035 {
1036 PCIBus *s = opaque;
1037 uint32_t val;
1038
1039 val = pci_data_read(s, addr, 4);
1040 #ifdef TARGET_WORDS_BIGENDIAN
1041 val = bswap32(val);
1042 #endif
1043
1044 return val;
1045 }
1046
1047 static CPUWriteMemoryFunc *pci_unin_main_write[] = {
1048 &pci_unin_main_writeb,
1049 &pci_unin_main_writew,
1050 &pci_unin_main_writel,
1051 };
1052
1053 static CPUReadMemoryFunc *pci_unin_main_read[] = {
1054 &pci_unin_main_readb,
1055 &pci_unin_main_readw,
1056 &pci_unin_main_readl,
1057 };
1058
1059 #if 0
1060
1061 static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
1062 uint32_t val)
1063 {
1064 PCIBus *s = opaque;
1065
1066 #ifdef TARGET_WORDS_BIGENDIAN
1067 val = bswap32(val);
1068 #endif
1069 s->config_reg = 0x80000000 | (val & ~0x00000001);
1070 }
1071
1072 static uint32_t pci_unin_config_readl (void *opaque,
1073 target_phys_addr_t addr)
1074 {
1075 PCIBus *s = opaque;
1076 uint32_t val;
1077
1078 val = (s->config_reg | 0x00000001) & ~0x80000000;
1079 #ifdef TARGET_WORDS_BIGENDIAN
1080 val = bswap32(val);
1081 #endif
1082
1083 return val;
1084 }
1085
1086 static CPUWriteMemoryFunc *pci_unin_config_write[] = {
1087 &pci_unin_config_writel,
1088 &pci_unin_config_writel,
1089 &pci_unin_config_writel,
1090 };
1091
1092 static CPUReadMemoryFunc *pci_unin_config_read[] = {
1093 &pci_unin_config_readl,
1094 &pci_unin_config_readl,
1095 &pci_unin_config_readl,
1096 };
1097
1098 static void pci_unin_writeb (void *opaque, target_phys_addr_t addr,
1099 uint32_t val)
1100 {
1101 PCIBus *s = opaque;
1102 pci_data_write(s, addr & 3, val, 1);
1103 }
1104
1105 static void pci_unin_writew (void *opaque, target_phys_addr_t addr,
1106 uint32_t val)
1107 {
1108 PCIBus *s = opaque;
1109 #ifdef TARGET_WORDS_BIGENDIAN
1110 val = bswap16(val);
1111 #endif
1112 pci_data_write(s, addr & 3, val, 2);
1113 }
1114
1115 static void pci_unin_writel (void *opaque, target_phys_addr_t addr,
1116 uint32_t val)
1117 {
1118 PCIBus *s = opaque;
1119 #ifdef TARGET_WORDS_BIGENDIAN
1120 val = bswap32(val);
1121 #endif
1122 pci_data_write(s, addr & 3, val, 4);
1123 }
1124
1125 static uint32_t pci_unin_readb (void *opaque, target_phys_addr_t addr)
1126 {
1127 PCIBus *s = opaque;
1128 uint32_t val;
1129
1130 val = pci_data_read(s, addr & 3, 1);
1131
1132 return val;
1133 }
1134
1135 static uint32_t pci_unin_readw (void *opaque, target_phys_addr_t addr)
1136 {
1137 PCIBus *s = opaque;
1138 uint32_t val;
1139
1140 val = pci_data_read(s, addr & 3, 2);
1141 #ifdef TARGET_WORDS_BIGENDIAN
1142 val = bswap16(val);
1143 #endif
1144
1145 return val;
1146 }
1147
1148 static uint32_t pci_unin_readl (void *opaque, target_phys_addr_t addr)
1149 {
1150 PCIBus *s = opaque;
1151 uint32_t val;
1152
1153 val = pci_data_read(s, addr & 3, 4);
1154 #ifdef TARGET_WORDS_BIGENDIAN
1155 val = bswap32(val);
1156 #endif
1157
1158 return val;
1159 }
1160
1161 static CPUWriteMemoryFunc *pci_unin_write[] = {
1162 &pci_unin_writeb,
1163 &pci_unin_writew,
1164 &pci_unin_writel,
1165 };
1166
1167 static CPUReadMemoryFunc *pci_unin_read[] = {
1168 &pci_unin_readb,
1169 &pci_unin_readw,
1170 &pci_unin_readl,
1171 };
1172 #endif
1173
1174 PCIBus *pci_pmac_init(void)
1175 {
1176 PCIBus *s;
1177 PCIDevice *d;
1178 int pci_mem_config, pci_mem_data;
1179
1180 /* Use values found on a real PowerMac */
1181 /* Uninorth main bus */
1182 s = pci_register_bus();
1183 s->set_irq = pci_set_irq_simple;
1184
1185 pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
1186 pci_unin_main_config_write, s);
1187 pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
1188 pci_unin_main_write, s);
1189 cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
1190 cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
1191 s->devfn_min = 11 << 3;
1192 d = pci_register_device(s, "Uni-north main", sizeof(PCIDevice),
1193 11 << 3, NULL, NULL);
1194 d->config[0x00] = 0x6b; // vendor_id : Apple
1195 d->config[0x01] = 0x10;
1196 d->config[0x02] = 0x1F; // device_id
1197 d->config[0x03] = 0x00;
1198 d->config[0x08] = 0x00; // revision
1199 d->config[0x0A] = 0x00; // class_sub = pci host
1200 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1201 d->config[0x0C] = 0x08; // cache_line_size
1202 d->config[0x0D] = 0x10; // latency_timer
1203 d->config[0x0E] = 0x00; // header_type
1204 d->config[0x34] = 0x00; // capabilities_pointer
1205
1206 #if 0 // XXX: not activated as PPC BIOS doesn't handle mutiple buses properly
1207 /* pci-to-pci bridge */
1208 d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
1209 NULL, NULL);
1210 d->config[0x00] = 0x11; // vendor_id : TI
1211 d->config[0x01] = 0x10;
1212 d->config[0x02] = 0x26; // device_id
1213 d->config[0x03] = 0x00;
1214 d->config[0x08] = 0x05; // revision
1215 d->config[0x0A] = 0x04; // class_sub = pci2pci
1216 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1217 d->config[0x0C] = 0x08; // cache_line_size
1218 d->config[0x0D] = 0x20; // latency_timer
1219 d->config[0x0E] = 0x01; // header_type
1220
1221 d->config[0x18] = 0x01; // primary_bus
1222 d->config[0x19] = 0x02; // secondary_bus
1223 d->config[0x1A] = 0x02; // subordinate_bus
1224 d->config[0x1B] = 0x20; // secondary_latency_timer
1225 d->config[0x1C] = 0x11; // io_base
1226 d->config[0x1D] = 0x01; // io_limit
1227 d->config[0x20] = 0x00; // memory_base
1228 d->config[0x21] = 0x80;
1229 d->config[0x22] = 0x00; // memory_limit
1230 d->config[0x23] = 0x80;
1231 d->config[0x24] = 0x01; // prefetchable_memory_base
1232 d->config[0x25] = 0x80;
1233 d->config[0x26] = 0xF1; // prefectchable_memory_limit
1234 d->config[0x27] = 0x7F;
1235 // d->config[0x34] = 0xdc // capabilities_pointer
1236 #endif
1237 #if 0 // XXX: not needed for now
1238 /* Uninorth AGP bus */
1239 s = &pci_bridge[1];
1240 pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
1241 pci_unin_config_write, s);
1242 pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
1243 pci_unin_write, s);
1244 cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
1245 cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
1246
1247 d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
1248 NULL, NULL);
1249 d->config[0x00] = 0x6b; // vendor_id : Apple
1250 d->config[0x01] = 0x10;
1251 d->config[0x02] = 0x20; // device_id
1252 d->config[0x03] = 0x00;
1253 d->config[0x08] = 0x00; // revision
1254 d->config[0x0A] = 0x00; // class_sub = pci host
1255 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1256 d->config[0x0C] = 0x08; // cache_line_size
1257 d->config[0x0D] = 0x10; // latency_timer
1258 d->config[0x0E] = 0x00; // header_type
1259 // d->config[0x34] = 0x80; // capabilities_pointer
1260 #endif
1261
1262 #if 0 // XXX: not needed for now
1263 /* Uninorth internal bus */
1264 s = &pci_bridge[2];
1265 pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
1266 pci_unin_config_write, s);
1267 pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
1268 pci_unin_write, s);
1269 cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
1270 cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
1271
1272 d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
1273 3, 11 << 3, NULL, NULL);
1274 d->config[0x00] = 0x6b; // vendor_id : Apple
1275 d->config[0x01] = 0x10;
1276 d->config[0x02] = 0x1E; // device_id
1277 d->config[0x03] = 0x00;
1278 d->config[0x08] = 0x00; // revision
1279 d->config[0x0A] = 0x00; // class_sub = pci host
1280 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1281 d->config[0x0C] = 0x08; // cache_line_size
1282 d->config[0x0D] = 0x10; // latency_timer
1283 d->config[0x0E] = 0x00; // header_type
1284 d->config[0x34] = 0x00; // capabilities_pointer
1285 #endif
1286 return s;
1287 }
1288
1289 /* Ultrasparc APB PCI host */
1290 static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
1291 uint32_t val)
1292 {
1293 PCIBus *s = opaque;
1294 int i;
1295
1296 for (i = 11; i < 32; i++) {
1297 if ((val & (1 << i)) != 0)
1298 break;
1299 }
1300 s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
1301 }
1302
1303 static uint32_t pci_apb_config_readl (void *opaque,
1304 target_phys_addr_t addr)
1305 {
1306 PCIBus *s = opaque;
1307 uint32_t val;
1308 int devfn;
1309
1310 devfn = (s->config_reg >> 8) & 0xFF;
1311 val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC);
1312 return val;
1313 }
1314
1315 static CPUWriteMemoryFunc *pci_apb_config_write[] = {
1316 &pci_apb_config_writel,
1317 &pci_apb_config_writel,
1318 &pci_apb_config_writel,
1319 };
1320
1321 static CPUReadMemoryFunc *pci_apb_config_read[] = {
1322 &pci_apb_config_readl,
1323 &pci_apb_config_readl,
1324 &pci_apb_config_readl,
1325 };
1326
1327 static void apb_config_writel (void *opaque, target_phys_addr_t addr,
1328 uint32_t val)
1329 {
1330 //PCIBus *s = opaque;
1331
1332 switch (addr & 0x3f) {
1333 case 0x00: // Control/Status
1334 case 0x10: // AFSR
1335 case 0x18: // AFAR
1336 case 0x20: // Diagnostic
1337 case 0x28: // Target address space
1338 // XXX
1339 default:
1340 break;
1341 }
1342 }
1343
1344 static uint32_t apb_config_readl (void *opaque,
1345 target_phys_addr_t addr)
1346 {
1347 //PCIBus *s = opaque;
1348 uint32_t val;
1349
1350 switch (addr & 0x3f) {
1351 case 0x00: // Control/Status
1352 case 0x10: // AFSR
1353 case 0x18: // AFAR
1354 case 0x20: // Diagnostic
1355 case 0x28: // Target address space
1356 // XXX
1357 default:
1358 val = 0;
1359 break;
1360 }
1361 return val;
1362 }
1363
1364 static CPUWriteMemoryFunc *apb_config_write[] = {
1365 &apb_config_writel,
1366 &apb_config_writel,
1367 &apb_config_writel,
1368 };
1369
1370 static CPUReadMemoryFunc *apb_config_read[] = {
1371 &apb_config_readl,
1372 &apb_config_readl,
1373 &apb_config_readl,
1374 };
1375
1376 static void pci_apb_writeb (void *opaque, target_phys_addr_t addr,
1377 uint32_t val)
1378 {
1379 PCIBus *s = opaque;
1380
1381 pci_data_write(s, addr & 7, val, 1);
1382 }
1383
1384 static void pci_apb_writew (void *opaque, target_phys_addr_t addr,
1385 uint32_t val)
1386 {
1387 PCIBus *s = opaque;
1388
1389 pci_data_write(s, addr & 7, val, 2);
1390 }
1391
1392 static void pci_apb_writel (void *opaque, target_phys_addr_t addr,
1393 uint32_t val)
1394 {
1395 PCIBus *s = opaque;
1396
1397 pci_data_write(s, addr & 7, val, 4);
1398 }
1399
1400 static uint32_t pci_apb_readb (void *opaque, target_phys_addr_t addr)
1401 {
1402 PCIBus *s = opaque;
1403 uint32_t val;
1404
1405 val = pci_data_read(s, addr & 7, 1);
1406 return val;
1407 }
1408
1409 static uint32_t pci_apb_readw (void *opaque, target_phys_addr_t addr)
1410 {
1411 PCIBus *s = opaque;
1412 uint32_t val;
1413
1414 val = pci_data_read(s, addr & 7, 2);
1415 return val;
1416 }
1417
1418 static uint32_t pci_apb_readl (void *opaque, target_phys_addr_t addr)
1419 {
1420 PCIBus *s = opaque;
1421 uint32_t val;
1422
1423 val = pci_data_read(s, addr, 4);
1424 return val;
1425 }
1426
1427 static CPUWriteMemoryFunc *pci_apb_write[] = {
1428 &pci_apb_writeb,
1429 &pci_apb_writew,
1430 &pci_apb_writel,
1431 };
1432
1433 static CPUReadMemoryFunc *pci_apb_read[] = {
1434 &pci_apb_readb,
1435 &pci_apb_readw,
1436 &pci_apb_readl,
1437 };
1438
1439 static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
1440 uint32_t val)
1441 {
1442 cpu_outb(NULL, addr & 0xffff, val);
1443 }
1444
1445 static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
1446 uint32_t val)
1447 {
1448 cpu_outw(NULL, addr & 0xffff, val);
1449 }
1450
1451 static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
1452 uint32_t val)
1453 {
1454 cpu_outl(NULL, addr & 0xffff, val);
1455 }
1456
1457 static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
1458 {
1459 uint32_t val;
1460
1461 val = cpu_inb(NULL, addr & 0xffff);
1462 return val;
1463 }
1464
1465 static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
1466 {
1467 uint32_t val;
1468
1469 val = cpu_inw(NULL, addr & 0xffff);
1470 return val;
1471 }
1472
1473 static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
1474 {
1475 uint32_t val;
1476
1477 val = cpu_inl(NULL, addr & 0xffff);
1478 return val;
1479 }
1480
1481 static CPUWriteMemoryFunc *pci_apb_iowrite[] = {
1482 &pci_apb_iowriteb,
1483 &pci_apb_iowritew,
1484 &pci_apb_iowritel,
1485 };
1486
1487 static CPUReadMemoryFunc *pci_apb_ioread[] = {
1488 &pci_apb_ioreadb,
1489 &pci_apb_ioreadw,
1490 &pci_apb_ioreadl,
1491 };
1492
1493 PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base)
1494 {
1495 PCIBus *s;
1496 PCIDevice *d;
1497 int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
1498
1499 /* Ultrasparc APB main bus */
1500 s = pci_register_bus();
1501 s->set_irq = pci_set_irq_simple;
1502
1503 pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read,
1504 pci_apb_config_write, s);
1505 apb_config = cpu_register_io_memory(0, apb_config_read,
1506 apb_config_write, s);
1507 pci_mem_data = cpu_register_io_memory(0, pci_apb_read,
1508 pci_apb_write, s);
1509 pci_ioport = cpu_register_io_memory(0, pci_apb_ioread,
1510 pci_apb_iowrite, s);
1511
1512 cpu_register_physical_memory(special_base + 0x2000ULL, 0x40, apb_config);
1513 cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10, pci_mem_config);
1514 cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, pci_ioport);
1515 cpu_register_physical_memory(mem_base, 0x10000000, pci_mem_data); // XXX size should be 4G-prom
1516
1517 d = pci_register_device(s, "Advanced PCI Bus", sizeof(PCIDevice),
1518 -1, NULL, NULL);
1519 d->config[0x00] = 0x8e; // vendor_id : Sun
1520 d->config[0x01] = 0x10;
1521 d->config[0x02] = 0x00; // device_id
1522 d->config[0x03] = 0xa0;
1523 d->config[0x04] = 0x06; // command = bus master, pci mem
1524 d->config[0x05] = 0x00;
1525 d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
1526 d->config[0x07] = 0x03; // status = medium devsel
1527 d->config[0x08] = 0x00; // revision
1528 d->config[0x09] = 0x00; // programming i/f
1529 d->config[0x0A] = 0x00; // class_sub = pci host
1530 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1531 d->config[0x0D] = 0x10; // latency_timer
1532 d->config[0x0E] = 0x00; // header_type
1533 return s;
1534 }
1535
1536 /***********************************************************/
1537 /* generic PCI irq support */
1538
1539 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1540 void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
1541 {
1542 PCIBus *bus = pci_dev->bus;
1543 bus->set_irq(pci_dev, irq_num, level);
1544 }
1545
1546 /***********************************************************/
1547 /* monitor info on PCI */
1548
1549 static void pci_info_device(PCIDevice *d)
1550 {
1551 int i, class;
1552 PCIIORegion *r;
1553
1554 term_printf(" Bus %2d, device %3d, function %d:\n",
1555 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
1556 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1557 term_printf(" ");
1558 switch(class) {
1559 case 0x0101:
1560 term_printf("IDE controller");
1561 break;
1562 case 0x0200:
1563 term_printf("Ethernet controller");
1564 break;
1565 case 0x0300:
1566 term_printf("VGA controller");
1567 break;
1568 default:
1569 term_printf("Class %04x", class);
1570 break;
1571 }
1572 term_printf(": PCI device %04x:%04x\n",
1573 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1574 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
1575
1576 if (d->config[PCI_INTERRUPT_PIN] != 0) {
1577 term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
1578 }
1579 for(i = 0;i < PCI_NUM_REGIONS; i++) {
1580 r = &d->io_regions[i];
1581 if (r->size != 0) {
1582 term_printf(" BAR%d: ", i);
1583 if (r->type & PCI_ADDRESS_SPACE_IO) {
1584 term_printf("I/O at 0x%04x [0x%04x].\n",
1585 r->addr, r->addr + r->size - 1);
1586 } else {
1587 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
1588 r->addr, r->addr + r->size - 1);
1589 }
1590 }
1591 }
1592 }
1593
1594 void pci_info(void)
1595 {
1596 PCIBus *bus = first_bus;
1597 PCIDevice *d;
1598 int devfn;
1599
1600 if (bus) {
1601 for(devfn = 0; devfn < 256; devfn++) {
1602 d = bus->devices[devfn];
1603 if (d)
1604 pci_info_device(d);
1605 }
1606 }
1607 }
1608
1609 /***********************************************************/
1610 /* XXX: the following should be moved to the PC BIOS */
1611
1612 static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
1613 {
1614 return cpu_inb(NULL, addr);
1615 }
1616
1617 static void isa_outb(uint32_t val, uint32_t addr)
1618 {
1619 cpu_outb(NULL, addr, val);
1620 }
1621
1622 static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
1623 {
1624 return cpu_inw(NULL, addr);
1625 }
1626
1627 static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr)
1628 {
1629 cpu_outw(NULL, addr, val);
1630 }
1631
1632 static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
1633 {
1634 return cpu_inl(NULL, addr);
1635 }
1636
1637 static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr)
1638 {
1639 cpu_outl(NULL, addr, val);
1640 }
1641
1642 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
1643 {
1644 PCIBus *s = d->bus;
1645 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1646 (d->devfn << 8) | addr;
1647 pci_data_write(s, 0, val, 4);
1648 }
1649
1650 static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
1651 {
1652 PCIBus *s = d->bus;
1653 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1654 (d->devfn << 8) | (addr & ~3);
1655 pci_data_write(s, addr & 3, val, 2);
1656 }
1657
1658 static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
1659 {
1660 PCIBus *s = d->bus;
1661 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1662 (d->devfn << 8) | (addr & ~3);
1663 pci_data_write(s, addr & 3, val, 1);
1664 }
1665
1666 static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
1667 {
1668 PCIBus *s = d->bus;
1669 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1670 (d->devfn << 8) | addr;
1671 return pci_data_read(s, 0, 4);
1672 }
1673
1674 static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
1675 {
1676 PCIBus *s = d->bus;
1677 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1678 (d->devfn << 8) | (addr & ~3);
1679 return pci_data_read(s, addr & 3, 2);
1680 }
1681
1682 static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
1683 {
1684 PCIBus *s = d->bus;
1685 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1686 (d->devfn << 8) | (addr & ~3);
1687 return pci_data_read(s, addr & 3, 1);
1688 }
1689
1690 static uint32_t pci_bios_io_addr;
1691 static uint32_t pci_bios_mem_addr;
1692 /* host irqs corresponding to PCI irqs A-D */
1693 static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
1694
1695 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
1696 {
1697 PCIIORegion *r;
1698 uint16_t cmd;
1699 uint32_t ofs;
1700
1701 if ( region_num == PCI_ROM_SLOT ) {
1702 ofs = 0x30;
1703 }else{
1704 ofs = 0x10 + region_num * 4;
1705 }
1706
1707 pci_config_writel(d, ofs, addr);
1708 r = &d->io_regions[region_num];
1709
1710 /* enable memory mappings */
1711 cmd = pci_config_readw(d, PCI_COMMAND);
1712 if ( region_num == PCI_ROM_SLOT )
1713 cmd |= 2;
1714 else if (r->type & PCI_ADDRESS_SPACE_IO)
1715 cmd |= 1;
1716 else
1717 cmd |= 2;
1718 pci_config_writew(d, PCI_COMMAND, cmd);
1719 }
1720
1721 static void pci_bios_init_device(PCIDevice *d)
1722 {
1723 int class;
1724 PCIIORegion *r;
1725 uint32_t *paddr;
1726 int i, pin, pic_irq, vendor_id, device_id;
1727
1728 class = pci_config_readw(d, PCI_CLASS_DEVICE);
1729 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1730 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1731 switch(class) {
1732 case 0x0101:
1733 if (vendor_id == 0x8086 && device_id == 0x7010) {
1734 /* PIIX3 IDE */
1735 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
1736 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
1737 goto default_map;
1738 } else {
1739 /* IDE: we map it as in ISA mode */
1740 pci_set_io_region_addr(d, 0, 0x1f0);
1741 pci_set_io_region_addr(d, 1, 0x3f4);
1742 pci_set_io_region_addr(d, 2, 0x170);
1743 pci_set_io_region_addr(d, 3, 0x374);
1744 }
1745 break;
1746 case 0x0300:
1747 if (vendor_id != 0x1234)
1748 goto default_map;
1749 /* VGA: map frame buffer to default Bochs VBE address */
1750 pci_set_io_region_addr(d, 0, 0xE0000000);
1751 break;
1752 case 0x0800:
1753 /* PIC */
1754 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1755 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1756 if (vendor_id == 0x1014) {
1757 /* IBM */
1758 if (device_id == 0x0046 || device_id == 0xFFFF) {
1759 /* MPIC & MPIC2 */
1760 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
1761 }
1762 }
1763 break;
1764 case 0xff00:
1765 if (vendor_id == 0x0106b &&
1766 (device_id == 0x0017 || device_id == 0x0022)) {
1767 /* macio bridge */
1768 pci_set_io_region_addr(d, 0, 0x80800000);
1769 }
1770 break;
1771 default:
1772 default_map:
1773 /* default memory mappings */
1774 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1775 r = &d->io_regions[i];
1776 if (r->size) {
1777 if (r->type & PCI_ADDRESS_SPACE_IO)
1778 paddr = &pci_bios_io_addr;
1779 else
1780 paddr = &pci_bios_mem_addr;
1781 *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
1782 pci_set_io_region_addr(d, i, *paddr);
1783 *paddr += r->size;
1784 }
1785 }
1786 break;
1787 }
1788
1789 /* map the interrupt */
1790 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
1791 if (pin != 0) {
1792 pin = pci_slot_get_pirq(d, pin - 1);
1793 pic_irq = pci_irqs[pin];
1794 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
1795 }
1796 }
1797
1798 /*
1799 * This function initializes the PCI devices as a normal PCI BIOS
1800 * would do. It is provided just in case the BIOS has no support for
1801 * PCI.
1802 */
1803 void pci_bios_init(void)
1804 {
1805 PCIBus *bus;
1806 PCIDevice *d;
1807 int devfn, i, irq;
1808 uint8_t elcr[2];
1809
1810 pci_bios_io_addr = 0xc000;
1811 pci_bios_mem_addr = 0xf0000000;
1812
1813 /* activate IRQ mappings */
1814 elcr[0] = 0x00;
1815 elcr[1] = 0x00;
1816 for(i = 0; i < 4; i++) {
1817 irq = pci_irqs[i];
1818 /* set to trigger level */
1819 elcr[irq >> 3] |= (1 << (irq & 7));
1820 /* activate irq remapping in PIIX */
1821 pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
1822 }
1823 isa_outb(elcr[0], 0x4d0);
1824 isa_outb(elcr[1], 0x4d1);
1825
1826 bus = first_bus;
1827 if (bus) {
1828 for(devfn = 0; devfn < 256; devfn++) {
1829 d = bus->devices[devfn];
1830 if (d)
1831 pci_bios_init_device(d);
1832 }
1833 }
1834 }
1835
1836 /* Initialize a PCI NIC. */
1837 void pci_nic_init(PCIBus *bus, NICInfo *nd)
1838 {
1839 if (strcmp(nd->model, "ne2k_pci") == 0) {
1840 pci_ne2000_init(bus, nd);
1841 } else if (strcmp(nd->model, "rtl8139") == 0) {
1842 pci_rtl8139_init(bus, nd);
1843 } else {
1844 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
1845 exit (1);
1846 }
1847 }
1848
Samsung s3c2440 and arm920t support for the mini2440 dev board