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Fix incorrect return type.
[qemu/mini2440.git] / hw / cirrus_vga.c
blob934cde99055d56eb5636c6ffb8eac0a584ada112
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "vl.h"
30 #include "vga_int.h"
31
32 /*
33 * TODO:
34 * - destination write mask support not complete (bits 5..7)
35 * - optimize linear mappings
36 * - optimize bitblt functions
37 */
38
39 //#define DEBUG_CIRRUS
40 //#define DEBUG_BITBLT
41
42 /***************************************
43 *
44 * definitions
45 *
46 ***************************************/
47
48 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
49
50 // ID
51 #define CIRRUS_ID_CLGD5422 (0x23<<2)
52 #define CIRRUS_ID_CLGD5426 (0x24<<2)
53 #define CIRRUS_ID_CLGD5424 (0x25<<2)
54 #define CIRRUS_ID_CLGD5428 (0x26<<2)
55 #define CIRRUS_ID_CLGD5430 (0x28<<2)
56 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
57 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
58 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
59
60 // sequencer 0x07
61 #define CIRRUS_SR7_BPP_VGA 0x00
62 #define CIRRUS_SR7_BPP_SVGA 0x01
63 #define CIRRUS_SR7_BPP_MASK 0x0e
64 #define CIRRUS_SR7_BPP_8 0x00
65 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
66 #define CIRRUS_SR7_BPP_24 0x04
67 #define CIRRUS_SR7_BPP_16 0x06
68 #define CIRRUS_SR7_BPP_32 0x08
69 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
70
71 // sequencer 0x0f
72 #define CIRRUS_MEMSIZE_512k 0x08
73 #define CIRRUS_MEMSIZE_1M 0x10
74 #define CIRRUS_MEMSIZE_2M 0x18
75 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
76
77 // sequencer 0x12
78 #define CIRRUS_CURSOR_SHOW 0x01
79 #define CIRRUS_CURSOR_HIDDENPEL 0x02
80 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
81
82 // sequencer 0x17
83 #define CIRRUS_BUSTYPE_VLBFAST 0x10
84 #define CIRRUS_BUSTYPE_PCI 0x20
85 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
86 #define CIRRUS_BUSTYPE_ISA 0x38
87 #define CIRRUS_MMIO_ENABLE 0x04
88 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
89 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
90
91 // control 0x0b
92 #define CIRRUS_BANKING_DUAL 0x01
93 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
94
95 // control 0x30
96 #define CIRRUS_BLTMODE_BACKWARDS 0x01
97 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
98 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
99 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
100 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
101 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
102 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
103 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
104 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
105 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
106 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
107
108 // control 0x31
109 #define CIRRUS_BLT_BUSY 0x01
110 #define CIRRUS_BLT_START 0x02
111 #define CIRRUS_BLT_RESET 0x04
112 #define CIRRUS_BLT_FIFOUSED 0x10
113 #define CIRRUS_BLT_AUTOSTART 0x80
114
115 // control 0x32
116 #define CIRRUS_ROP_0 0x00
117 #define CIRRUS_ROP_SRC_AND_DST 0x05
118 #define CIRRUS_ROP_NOP 0x06
119 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
120 #define CIRRUS_ROP_NOTDST 0x0b
121 #define CIRRUS_ROP_SRC 0x0d
122 #define CIRRUS_ROP_1 0x0e
123 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
124 #define CIRRUS_ROP_SRC_XOR_DST 0x59
125 #define CIRRUS_ROP_SRC_OR_DST 0x6d
126 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
127 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
128 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
129 #define CIRRUS_ROP_NOTSRC 0xd0
130 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
131 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
132
133 #define CIRRUS_ROP_NOP_INDEX 2
134 #define CIRRUS_ROP_SRC_INDEX 5
135
136 // control 0x33
137 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
138 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
139 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
140
141 // memory-mapped IO
142 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
143 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
144 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
145 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
146 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
147 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
148 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
149 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
150 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
151 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
152 #define CIRRUS_MMIO_BLTROP 0x1a // byte
153 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
154 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
155 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
156 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
157 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
158 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
159 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
160 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
161 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
162 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
163 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
164 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
165 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
166 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
167 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
168 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
169 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
170 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
171
172 // PCI 0x00: vendor, 0x02: device
173 #define PCI_VENDOR_CIRRUS 0x1013
174 #define PCI_DEVICE_CLGD5462 0x00d0
175 #define PCI_DEVICE_CLGD5465 0x00d6
176
177 // PCI 0x04: command(word), 0x06(word): status
178 #define PCI_COMMAND_IOACCESS 0x0001
179 #define PCI_COMMAND_MEMACCESS 0x0002
180 #define PCI_COMMAND_BUSMASTER 0x0004
181 #define PCI_COMMAND_SPECIALCYCLE 0x0008
182 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
183 #define PCI_COMMAND_PALETTESNOOPING 0x0020
184 #define PCI_COMMAND_PARITYDETECTION 0x0040
185 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
186 #define PCI_COMMAND_SERR 0x0100
187 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
188 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
189 #define PCI_CLASS_BASE_DISPLAY 0x03
190 // PCI 0x08, 0x00ff0000
191 #define PCI_CLASS_SUB_VGA 0x00
192 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
193 #define PCI_CLASS_HEADERTYPE_00h 0x00
194 // 0x10-0x3f (headertype 00h)
195 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
196 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
197 #define PCI_MAP_MEM 0x0
198 #define PCI_MAP_IO 0x1
199 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
200 #define PCI_MAP_IO_ADDR_MASK (~0x3)
201 #define PCI_MAP_MEMFLAGS_32BIT 0x0
202 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
203 #define PCI_MAP_MEMFLAGS_64BIT 0x4
204 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
205 // PCI 0x28: cardbus CIS pointer
206 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
207 // PCI 0x30: expansion ROM base address
208 #define PCI_ROMBIOS_ENABLED 0x1
209 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
210 // PCI 0x38: reserved
211 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
212
213 #define CIRRUS_PNPMMIO_SIZE 0x1000
214
215
216 /* I/O and memory hook */
217 #define CIRRUS_HOOK_NOT_HANDLED 0
218 #define CIRRUS_HOOK_HANDLED 1
219
220 struct CirrusVGAState;
221 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
222 uint8_t * dst, const uint8_t * src,
223 int dstpitch, int srcpitch,
224 int bltwidth, int bltheight);
225 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
226 uint8_t *dst, int dst_pitch, int width, int height);
227
228 typedef struct CirrusVGAState {
229 VGA_STATE_COMMON
230
231 int cirrus_linear_io_addr;
232 int cirrus_linear_bitblt_io_addr;
233 int cirrus_mmio_io_addr;
234 uint32_t cirrus_addr_mask;
235 uint32_t linear_mmio_mask;
236 uint8_t cirrus_shadow_gr0;
237 uint8_t cirrus_shadow_gr1;
238 uint8_t cirrus_hidden_dac_lockindex;
239 uint8_t cirrus_hidden_dac_data;
240 uint32_t cirrus_bank_base[2];
241 uint32_t cirrus_bank_limit[2];
242 uint8_t cirrus_hidden_palette[48];
243 uint32_t hw_cursor_x;
244 uint32_t hw_cursor_y;
245 int cirrus_blt_pixelwidth;
246 int cirrus_blt_width;
247 int cirrus_blt_height;
248 int cirrus_blt_dstpitch;
249 int cirrus_blt_srcpitch;
250 uint32_t cirrus_blt_fgcol;
251 uint32_t cirrus_blt_bgcol;
252 uint32_t cirrus_blt_dstaddr;
253 uint32_t cirrus_blt_srcaddr;
254 uint8_t cirrus_blt_mode;
255 uint8_t cirrus_blt_modeext;
256 cirrus_bitblt_rop_t cirrus_rop;
257 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
258 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
259 uint8_t *cirrus_srcptr;
260 uint8_t *cirrus_srcptr_end;
261 uint32_t cirrus_srccounter;
262 /* hwcursor display state */
263 int last_hw_cursor_size;
264 int last_hw_cursor_x;
265 int last_hw_cursor_y;
266 int last_hw_cursor_y_start;
267 int last_hw_cursor_y_end;
268 int real_vram_size; /* XXX: suppress that */
269 CPUWriteMemoryFunc **cirrus_linear_write;
270 } CirrusVGAState;
271
272 typedef struct PCICirrusVGAState {
273 PCIDevice dev;
274 CirrusVGAState cirrus_vga;
275 } PCICirrusVGAState;
276
277 static uint8_t rop_to_index[256];
278
279 /***************************************
280 *
281 * prototypes.
282 *
283 ***************************************/
284
285
286 static void cirrus_bitblt_reset(CirrusVGAState *s);
287 static void cirrus_update_memory_access(CirrusVGAState *s);
288
289 /***************************************
290 *
291 * raster operations
292 *
293 ***************************************/
294
295 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
296 uint8_t *dst,const uint8_t *src,
297 int dstpitch,int srcpitch,
298 int bltwidth,int bltheight)
299 {
300 }
301
302 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
303 uint8_t *dst,
304 int dstpitch, int bltwidth,int bltheight)
305 {
306 }
307
308 #define ROP_NAME 0
309 #define ROP_OP(d, s) d = 0
310 #include "cirrus_vga_rop.h"
311
312 #define ROP_NAME src_and_dst
313 #define ROP_OP(d, s) d = (s) & (d)
314 #include "cirrus_vga_rop.h"
315
316 #define ROP_NAME src_and_notdst
317 #define ROP_OP(d, s) d = (s) & (~(d))
318 #include "cirrus_vga_rop.h"
319
320 #define ROP_NAME notdst
321 #define ROP_OP(d, s) d = ~(d)
322 #include "cirrus_vga_rop.h"
323
324 #define ROP_NAME src
325 #define ROP_OP(d, s) d = s
326 #include "cirrus_vga_rop.h"
327
328 #define ROP_NAME 1
329 #define ROP_OP(d, s) d = ~0
330 #include "cirrus_vga_rop.h"
331
332 #define ROP_NAME notsrc_and_dst
333 #define ROP_OP(d, s) d = (~(s)) & (d)
334 #include "cirrus_vga_rop.h"
335
336 #define ROP_NAME src_xor_dst
337 #define ROP_OP(d, s) d = (s) ^ (d)
338 #include "cirrus_vga_rop.h"
339
340 #define ROP_NAME src_or_dst
341 #define ROP_OP(d, s) d = (s) | (d)
342 #include "cirrus_vga_rop.h"
343
344 #define ROP_NAME notsrc_or_notdst
345 #define ROP_OP(d, s) d = (~(s)) | (~(d))
346 #include "cirrus_vga_rop.h"
347
348 #define ROP_NAME src_notxor_dst
349 #define ROP_OP(d, s) d = ~((s) ^ (d))
350 #include "cirrus_vga_rop.h"
351
352 #define ROP_NAME src_or_notdst
353 #define ROP_OP(d, s) d = (s) | (~(d))
354 #include "cirrus_vga_rop.h"
355
356 #define ROP_NAME notsrc
357 #define ROP_OP(d, s) d = (~(s))
358 #include "cirrus_vga_rop.h"
359
360 #define ROP_NAME notsrc_or_dst
361 #define ROP_OP(d, s) d = (~(s)) | (d)
362 #include "cirrus_vga_rop.h"
363
364 #define ROP_NAME notsrc_and_notdst
365 #define ROP_OP(d, s) d = (~(s)) & (~(d))
366 #include "cirrus_vga_rop.h"
367
368 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
369 cirrus_bitblt_rop_fwd_0,
370 cirrus_bitblt_rop_fwd_src_and_dst,
371 cirrus_bitblt_rop_nop,
372 cirrus_bitblt_rop_fwd_src_and_notdst,
373 cirrus_bitblt_rop_fwd_notdst,
374 cirrus_bitblt_rop_fwd_src,
375 cirrus_bitblt_rop_fwd_1,
376 cirrus_bitblt_rop_fwd_notsrc_and_dst,
377 cirrus_bitblt_rop_fwd_src_xor_dst,
378 cirrus_bitblt_rop_fwd_src_or_dst,
379 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
380 cirrus_bitblt_rop_fwd_src_notxor_dst,
381 cirrus_bitblt_rop_fwd_src_or_notdst,
382 cirrus_bitblt_rop_fwd_notsrc,
383 cirrus_bitblt_rop_fwd_notsrc_or_dst,
384 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
385 };
386
387 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
388 cirrus_bitblt_rop_bkwd_0,
389 cirrus_bitblt_rop_bkwd_src_and_dst,
390 cirrus_bitblt_rop_nop,
391 cirrus_bitblt_rop_bkwd_src_and_notdst,
392 cirrus_bitblt_rop_bkwd_notdst,
393 cirrus_bitblt_rop_bkwd_src,
394 cirrus_bitblt_rop_bkwd_1,
395 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
396 cirrus_bitblt_rop_bkwd_src_xor_dst,
397 cirrus_bitblt_rop_bkwd_src_or_dst,
398 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
399 cirrus_bitblt_rop_bkwd_src_notxor_dst,
400 cirrus_bitblt_rop_bkwd_src_or_notdst,
401 cirrus_bitblt_rop_bkwd_notsrc,
402 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
403 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
404 };
405
406 #define ROP2(name) {\
407 name ## _8,\
408 name ## _16,\
409 name ## _24,\
410 name ## _32,\
411 }
412
413 #define ROP_NOP2(func) {\
414 func,\
415 func,\
416 func,\
417 func,\
418 }
419
420 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
421 ROP2(cirrus_patternfill_0),
422 ROP2(cirrus_patternfill_src_and_dst),
423 ROP_NOP2(cirrus_bitblt_rop_nop),
424 ROP2(cirrus_patternfill_src_and_notdst),
425 ROP2(cirrus_patternfill_notdst),
426 ROP2(cirrus_patternfill_src),
427 ROP2(cirrus_patternfill_1),
428 ROP2(cirrus_patternfill_notsrc_and_dst),
429 ROP2(cirrus_patternfill_src_xor_dst),
430 ROP2(cirrus_patternfill_src_or_dst),
431 ROP2(cirrus_patternfill_notsrc_or_notdst),
432 ROP2(cirrus_patternfill_src_notxor_dst),
433 ROP2(cirrus_patternfill_src_or_notdst),
434 ROP2(cirrus_patternfill_notsrc),
435 ROP2(cirrus_patternfill_notsrc_or_dst),
436 ROP2(cirrus_patternfill_notsrc_and_notdst),
437 };
438
439 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
440 ROP2(cirrus_colorexpand_transp_0),
441 ROP2(cirrus_colorexpand_transp_src_and_dst),
442 ROP_NOP2(cirrus_bitblt_rop_nop),
443 ROP2(cirrus_colorexpand_transp_src_and_notdst),
444 ROP2(cirrus_colorexpand_transp_notdst),
445 ROP2(cirrus_colorexpand_transp_src),
446 ROP2(cirrus_colorexpand_transp_1),
447 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
448 ROP2(cirrus_colorexpand_transp_src_xor_dst),
449 ROP2(cirrus_colorexpand_transp_src_or_dst),
450 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
451 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
452 ROP2(cirrus_colorexpand_transp_src_or_notdst),
453 ROP2(cirrus_colorexpand_transp_notsrc),
454 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
455 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
456 };
457
458 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
459 ROP2(cirrus_colorexpand_0),
460 ROP2(cirrus_colorexpand_src_and_dst),
461 ROP_NOP2(cirrus_bitblt_rop_nop),
462 ROP2(cirrus_colorexpand_src_and_notdst),
463 ROP2(cirrus_colorexpand_notdst),
464 ROP2(cirrus_colorexpand_src),
465 ROP2(cirrus_colorexpand_1),
466 ROP2(cirrus_colorexpand_notsrc_and_dst),
467 ROP2(cirrus_colorexpand_src_xor_dst),
468 ROP2(cirrus_colorexpand_src_or_dst),
469 ROP2(cirrus_colorexpand_notsrc_or_notdst),
470 ROP2(cirrus_colorexpand_src_notxor_dst),
471 ROP2(cirrus_colorexpand_src_or_notdst),
472 ROP2(cirrus_colorexpand_notsrc),
473 ROP2(cirrus_colorexpand_notsrc_or_dst),
474 ROP2(cirrus_colorexpand_notsrc_and_notdst),
475 };
476
477 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
478 ROP2(cirrus_colorexpand_pattern_transp_0),
479 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
480 ROP_NOP2(cirrus_bitblt_rop_nop),
481 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
482 ROP2(cirrus_colorexpand_pattern_transp_notdst),
483 ROP2(cirrus_colorexpand_pattern_transp_src),
484 ROP2(cirrus_colorexpand_pattern_transp_1),
485 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
486 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
487 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
488 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
489 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
490 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
491 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
492 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
493 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
494 };
495
496 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
497 ROP2(cirrus_colorexpand_pattern_0),
498 ROP2(cirrus_colorexpand_pattern_src_and_dst),
499 ROP_NOP2(cirrus_bitblt_rop_nop),
500 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
501 ROP2(cirrus_colorexpand_pattern_notdst),
502 ROP2(cirrus_colorexpand_pattern_src),
503 ROP2(cirrus_colorexpand_pattern_1),
504 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
505 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
506 ROP2(cirrus_colorexpand_pattern_src_or_dst),
507 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
508 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
509 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
510 ROP2(cirrus_colorexpand_pattern_notsrc),
511 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
512 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
513 };
514
515 static const cirrus_fill_t cirrus_fill[16][4] = {
516 ROP2(cirrus_fill_0),
517 ROP2(cirrus_fill_src_and_dst),
518 ROP_NOP2(cirrus_bitblt_fill_nop),
519 ROP2(cirrus_fill_src_and_notdst),
520 ROP2(cirrus_fill_notdst),
521 ROP2(cirrus_fill_src),
522 ROP2(cirrus_fill_1),
523 ROP2(cirrus_fill_notsrc_and_dst),
524 ROP2(cirrus_fill_src_xor_dst),
525 ROP2(cirrus_fill_src_or_dst),
526 ROP2(cirrus_fill_notsrc_or_notdst),
527 ROP2(cirrus_fill_src_notxor_dst),
528 ROP2(cirrus_fill_src_or_notdst),
529 ROP2(cirrus_fill_notsrc),
530 ROP2(cirrus_fill_notsrc_or_dst),
531 ROP2(cirrus_fill_notsrc_and_notdst),
532 };
533
534 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
535 {
536 unsigned int color;
537 switch (s->cirrus_blt_pixelwidth) {
538 case 1:
539 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
540 break;
541 case 2:
542 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
543 s->cirrus_blt_fgcol = le16_to_cpu(color);
544 break;
545 case 3:
546 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
547 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
548 break;
549 default:
550 case 4:
551 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
552 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
553 s->cirrus_blt_fgcol = le32_to_cpu(color);
554 break;
555 }
556 }
557
558 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
559 {
560 unsigned int color;
561 switch (s->cirrus_blt_pixelwidth) {
562 case 1:
563 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
564 break;
565 case 2:
566 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
567 s->cirrus_blt_bgcol = le16_to_cpu(color);
568 break;
569 case 3:
570 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
571 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
572 break;
573 default:
574 case 4:
575 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
576 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
577 s->cirrus_blt_bgcol = le32_to_cpu(color);
578 break;
579 }
580 }
581
582 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
583 int off_pitch, int bytesperline,
584 int lines)
585 {
586 int y;
587 int off_cur;
588 int off_cur_end;
589
590 for (y = 0; y < lines; y++) {
591 off_cur = off_begin;
592 off_cur_end = off_cur + bytesperline;
593 off_cur &= TARGET_PAGE_MASK;
594 while (off_cur < off_cur_end) {
595 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
596 off_cur += TARGET_PAGE_SIZE;
597 }
598 off_begin += off_pitch;
599 }
600 }
601
602 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
603 const uint8_t * src)
604 {
605 uint8_t *dst;
606
607 dst = s->vram_ptr + s->cirrus_blt_dstaddr;
608 (*s->cirrus_rop) (s, dst, src,
609 s->cirrus_blt_dstpitch, 0,
610 s->cirrus_blt_width, s->cirrus_blt_height);
611 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
612 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
613 s->cirrus_blt_height);
614 return 1;
615 }
616
617 /* fill */
618
619 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
620 {
621 cirrus_fill_t rop_func;
622
623 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
624 rop_func(s, s->vram_ptr + s->cirrus_blt_dstaddr,
625 s->cirrus_blt_dstpitch,
626 s->cirrus_blt_width, s->cirrus_blt_height);
627 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
628 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
629 s->cirrus_blt_height);
630 cirrus_bitblt_reset(s);
631 return 1;
632 }
633
634 /***************************************
635 *
636 * bitblt (video-to-video)
637 *
638 ***************************************/
639
640 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
641 {
642 return cirrus_bitblt_common_patterncopy(s,
643 s->vram_ptr +
644 (s->cirrus_blt_srcaddr & ~7));
645 }
646
647 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
648 {
649 (*s->cirrus_rop) (s, s->vram_ptr + s->cirrus_blt_dstaddr,
650 s->vram_ptr + s->cirrus_blt_srcaddr,
651 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
652 s->cirrus_blt_width, s->cirrus_blt_height);
653 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
654 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
655 s->cirrus_blt_height);
656 return 1;
657 }
658
659 /***************************************
660 *
661 * bitblt (cpu-to-video)
662 *
663 ***************************************/
664
665 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
666 {
667 int copy_count;
668 uint8_t *end_ptr;
669
670 if (s->cirrus_srccounter > 0) {
671 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
672 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
673 the_end:
674 s->cirrus_srccounter = 0;
675 cirrus_bitblt_reset(s);
676 } else {
677 /* at least one scan line */
678 do {
679 (*s->cirrus_rop)(s, s->vram_ptr + s->cirrus_blt_dstaddr,
680 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
681 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
682 s->cirrus_blt_width, 1);
683 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
684 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
685 if (s->cirrus_srccounter <= 0)
686 goto the_end;
687 /* more bytes than needed can be transfered because of
688 word alignment, so we keep them for the next line */
689 /* XXX: keep alignment to speed up transfer */
690 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
691 copy_count = s->cirrus_srcptr_end - end_ptr;
692 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
693 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
694 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
695 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
696 }
697 }
698 }
699
700 /***************************************
701 *
702 * bitblt wrapper
703 *
704 ***************************************/
705
706 static void cirrus_bitblt_reset(CirrusVGAState * s)
707 {
708 s->gr[0x31] &=
709 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
710 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
711 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
712 s->cirrus_srccounter = 0;
713 cirrus_update_memory_access(s);
714 }
715
716 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
717 {
718 int w;
719
720 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
721 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
722 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
723
724 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
725 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
726 s->cirrus_blt_srcpitch = 8;
727 } else {
728 /* XXX: check for 24 bpp */
729 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
730 }
731 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
732 } else {
733 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
734 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
735 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
736 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
737 else
738 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
739 } else {
740 /* always align input size to 32 bits */
741 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
742 }
743 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
744 }
745 s->cirrus_srcptr = s->cirrus_bltbuf;
746 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
747 cirrus_update_memory_access(s);
748 return 1;
749 }
750
751 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
752 {
753 /* XXX */
754 #ifdef DEBUG_BITBLT
755 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
756 #endif
757 return 0;
758 }
759
760 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
761 {
762 int ret;
763
764 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
765 ret = cirrus_bitblt_videotovideo_patterncopy(s);
766 } else {
767 ret = cirrus_bitblt_videotovideo_copy(s);
768 }
769 if (ret)
770 cirrus_bitblt_reset(s);
771 return ret;
772 }
773
774 static void cirrus_bitblt_start(CirrusVGAState * s)
775 {
776 uint8_t blt_rop;
777
778 s->gr[0x31] |= CIRRUS_BLT_BUSY;
779
780 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
781 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
782 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
783 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
784 s->cirrus_blt_dstaddr =
785 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
786 s->cirrus_blt_srcaddr =
787 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
788 s->cirrus_blt_mode = s->gr[0x30];
789 s->cirrus_blt_modeext = s->gr[0x33];
790 blt_rop = s->gr[0x32];
791
792 #ifdef DEBUG_BITBLT
793 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
794 blt_rop,
795 s->cirrus_blt_mode,
796 s->cirrus_blt_modeext,
797 s->cirrus_blt_width,
798 s->cirrus_blt_height,
799 s->cirrus_blt_dstpitch,
800 s->cirrus_blt_srcpitch,
801 s->cirrus_blt_dstaddr,
802 s->cirrus_blt_srcaddr,
803 s->gr[0x2f]);
804 #endif
805
806 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
807 case CIRRUS_BLTMODE_PIXELWIDTH8:
808 s->cirrus_blt_pixelwidth = 1;
809 break;
810 case CIRRUS_BLTMODE_PIXELWIDTH16:
811 s->cirrus_blt_pixelwidth = 2;
812 break;
813 case CIRRUS_BLTMODE_PIXELWIDTH24:
814 s->cirrus_blt_pixelwidth = 3;
815 break;
816 case CIRRUS_BLTMODE_PIXELWIDTH32:
817 s->cirrus_blt_pixelwidth = 4;
818 break;
819 default:
820 #ifdef DEBUG_BITBLT
821 printf("cirrus: bitblt - pixel width is unknown\n");
822 #endif
823 goto bitblt_ignore;
824 }
825 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
826
827 if ((s->
828 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
829 CIRRUS_BLTMODE_MEMSYSDEST))
830 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
831 #ifdef DEBUG_BITBLT
832 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
833 #endif
834 goto bitblt_ignore;
835 }
836
837 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
838 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
839 CIRRUS_BLTMODE_TRANSPARENTCOMP |
840 CIRRUS_BLTMODE_PATTERNCOPY |
841 CIRRUS_BLTMODE_COLOREXPAND)) ==
842 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
843 cirrus_bitblt_fgcol(s);
844 cirrus_bitblt_solidfill(s, blt_rop);
845 } else {
846 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
847 CIRRUS_BLTMODE_PATTERNCOPY)) ==
848 CIRRUS_BLTMODE_COLOREXPAND) {
849
850 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
851 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
852 cirrus_bitblt_bgcol(s);
853 else
854 cirrus_bitblt_fgcol(s);
855 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
856 } else {
857 cirrus_bitblt_fgcol(s);
858 cirrus_bitblt_bgcol(s);
859 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
860 }
861 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
862 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
863 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
864 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
865 cirrus_bitblt_bgcol(s);
866 else
867 cirrus_bitblt_fgcol(s);
868 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
869 } else {
870 cirrus_bitblt_fgcol(s);
871 cirrus_bitblt_bgcol(s);
872 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
873 }
874 } else {
875 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
876 }
877 } else {
878 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
879 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
880 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
881 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
882 } else {
883 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
884 }
885 }
886
887 // setup bitblt engine.
888 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
889 if (!cirrus_bitblt_cputovideo(s))
890 goto bitblt_ignore;
891 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
892 if (!cirrus_bitblt_videotocpu(s))
893 goto bitblt_ignore;
894 } else {
895 if (!cirrus_bitblt_videotovideo(s))
896 goto bitblt_ignore;
897 }
898 }
899 return;
900 bitblt_ignore:;
901 cirrus_bitblt_reset(s);
902 }
903
904 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
905 {
906 unsigned old_value;
907
908 old_value = s->gr[0x31];
909 s->gr[0x31] = reg_value;
910
911 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
912 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
913 cirrus_bitblt_reset(s);
914 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
915 ((reg_value & CIRRUS_BLT_START) != 0)) {
916 cirrus_bitblt_start(s);
917 }
918 }
919
920
921 /***************************************
922 *
923 * basic parameters
924 *
925 ***************************************/
926
927 static void cirrus_get_offsets(VGAState *s1,
928 uint32_t *pline_offset,
929 uint32_t *pstart_addr)
930 {
931 CirrusVGAState * s = (CirrusVGAState *)s1;
932 uint32_t start_addr;
933 uint32_t line_offset;
934
935 line_offset = s->cr[0x13]
936 | ((s->cr[0x1b] & 0x10) << 4);
937 line_offset <<= 3;
938 *pline_offset = line_offset;
939
940 start_addr = (s->cr[0x0c] << 8)
941 | s->cr[0x0d]
942 | ((s->cr[0x1b] & 0x01) << 16)
943 | ((s->cr[0x1b] & 0x0c) << 15)
944 | ((s->cr[0x1d] & 0x80) << 12);
945 *pstart_addr = start_addr;
946 }
947
948 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
949 {
950 uint32_t ret = 16;
951
952 switch (s->cirrus_hidden_dac_data & 0xf) {
953 case 0:
954 ret = 15;
955 break; /* Sierra HiColor */
956 case 1:
957 ret = 16;
958 break; /* XGA HiColor */
959 default:
960 #ifdef DEBUG_CIRRUS
961 printf("cirrus: invalid DAC value %x in 16bpp\n",
962 (s->cirrus_hidden_dac_data & 0xf));
963 #endif
964 ret = 15; /* XXX */
965 break;
966 }
967 return ret;
968 }
969
970 static int cirrus_get_bpp(VGAState *s1)
971 {
972 CirrusVGAState * s = (CirrusVGAState *)s1;
973 uint32_t ret = 8;
974
975 if ((s->sr[0x07] & 0x01) != 0) {
976 /* Cirrus SVGA */
977 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
978 case CIRRUS_SR7_BPP_8:
979 ret = 8;
980 break;
981 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
982 ret = cirrus_get_bpp16_depth(s);
983 break;
984 case CIRRUS_SR7_BPP_24:
985 ret = 24;
986 break;
987 case CIRRUS_SR7_BPP_16:
988 ret = cirrus_get_bpp16_depth(s);
989 break;
990 case CIRRUS_SR7_BPP_32:
991 ret = 32;
992 break;
993 default:
994 #ifdef DEBUG_CIRRUS
995 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
996 #endif
997 ret = 8;
998 break;
999 }
1000 } else {
1001 /* VGA */
1002 ret = 0;
1003 }
1004
1005 return ret;
1006 }
1007
1008 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1009 {
1010 int width, height;
1011
1012 width = (s->cr[0x01] + 1) * 8;
1013 height = s->cr[0x12] |
1014 ((s->cr[0x07] & 0x02) << 7) |
1015 ((s->cr[0x07] & 0x40) << 3);
1016 height = (height + 1);
1017 /* interlace support */
1018 if (s->cr[0x1a] & 0x01)
1019 height = height * 2;
1020 *pwidth = width;
1021 *pheight = height;
1022 }
1023
1024 /***************************************
1025 *
1026 * bank memory
1027 *
1028 ***************************************/
1029
1030 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1031 {
1032 unsigned offset;
1033 unsigned limit;
1034
1035 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1036 offset = s->gr[0x09 + bank_index];
1037 else /* single bank */
1038 offset = s->gr[0x09];
1039
1040 if ((s->gr[0x0b] & 0x20) != 0)
1041 offset <<= 14;
1042 else
1043 offset <<= 12;
1044
1045 if (s->real_vram_size <= offset)
1046 limit = 0;
1047 else
1048 limit = s->real_vram_size - offset;
1049
1050 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1051 if (limit > 0x8000) {
1052 offset += 0x8000;
1053 limit -= 0x8000;
1054 } else {
1055 limit = 0;
1056 }
1057 }
1058
1059 if (limit > 0) {
1060 s->cirrus_bank_base[bank_index] = offset;
1061 s->cirrus_bank_limit[bank_index] = limit;
1062 } else {
1063 s->cirrus_bank_base[bank_index] = 0;
1064 s->cirrus_bank_limit[bank_index] = 0;
1065 }
1066 }
1067
1068 /***************************************
1069 *
1070 * I/O access between 0x3c4-0x3c5
1071 *
1072 ***************************************/
1073
1074 static int
1075 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1076 {
1077 switch (reg_index) {
1078 case 0x00: // Standard VGA
1079 case 0x01: // Standard VGA
1080 case 0x02: // Standard VGA
1081 case 0x03: // Standard VGA
1082 case 0x04: // Standard VGA
1083 return CIRRUS_HOOK_NOT_HANDLED;
1084 case 0x06: // Unlock Cirrus extensions
1085 *reg_value = s->sr[reg_index];
1086 break;
1087 case 0x10:
1088 case 0x30:
1089 case 0x50:
1090 case 0x70: // Graphics Cursor X
1091 case 0x90:
1092 case 0xb0:
1093 case 0xd0:
1094 case 0xf0: // Graphics Cursor X
1095 *reg_value = s->sr[0x10];
1096 break;
1097 case 0x11:
1098 case 0x31:
1099 case 0x51:
1100 case 0x71: // Graphics Cursor Y
1101 case 0x91:
1102 case 0xb1:
1103 case 0xd1:
1104 case 0xf1: // Graphics Cursor Y
1105 *reg_value = s->sr[0x11];
1106 break;
1107 case 0x05: // ???
1108 case 0x07: // Extended Sequencer Mode
1109 case 0x08: // EEPROM Control
1110 case 0x09: // Scratch Register 0
1111 case 0x0a: // Scratch Register 1
1112 case 0x0b: // VCLK 0
1113 case 0x0c: // VCLK 1
1114 case 0x0d: // VCLK 2
1115 case 0x0e: // VCLK 3
1116 case 0x0f: // DRAM Control
1117 case 0x12: // Graphics Cursor Attribute
1118 case 0x13: // Graphics Cursor Pattern Address
1119 case 0x14: // Scratch Register 2
1120 case 0x15: // Scratch Register 3
1121 case 0x16: // Performance Tuning Register
1122 case 0x17: // Configuration Readback and Extended Control
1123 case 0x18: // Signature Generator Control
1124 case 0x19: // Signal Generator Result
1125 case 0x1a: // Signal Generator Result
1126 case 0x1b: // VCLK 0 Denominator & Post
1127 case 0x1c: // VCLK 1 Denominator & Post
1128 case 0x1d: // VCLK 2 Denominator & Post
1129 case 0x1e: // VCLK 3 Denominator & Post
1130 case 0x1f: // BIOS Write Enable and MCLK select
1131 #ifdef DEBUG_CIRRUS
1132 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1133 #endif
1134 *reg_value = s->sr[reg_index];
1135 break;
1136 default:
1137 #ifdef DEBUG_CIRRUS
1138 printf("cirrus: inport sr_index %02x\n", reg_index);
1139 #endif
1140 *reg_value = 0xff;
1141 break;
1142 }
1143
1144 return CIRRUS_HOOK_HANDLED;
1145 }
1146
1147 static int
1148 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1149 {
1150 switch (reg_index) {
1151 case 0x00: // Standard VGA
1152 case 0x01: // Standard VGA
1153 case 0x02: // Standard VGA
1154 case 0x03: // Standard VGA
1155 case 0x04: // Standard VGA
1156 return CIRRUS_HOOK_NOT_HANDLED;
1157 case 0x06: // Unlock Cirrus extensions
1158 reg_value &= 0x17;
1159 if (reg_value == 0x12) {
1160 s->sr[reg_index] = 0x12;
1161 } else {
1162 s->sr[reg_index] = 0x0f;
1163 }
1164 break;
1165 case 0x10:
1166 case 0x30:
1167 case 0x50:
1168 case 0x70: // Graphics Cursor X
1169 case 0x90:
1170 case 0xb0:
1171 case 0xd0:
1172 case 0xf0: // Graphics Cursor X
1173 s->sr[0x10] = reg_value;
1174 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1175 break;
1176 case 0x11:
1177 case 0x31:
1178 case 0x51:
1179 case 0x71: // Graphics Cursor Y
1180 case 0x91:
1181 case 0xb1:
1182 case 0xd1:
1183 case 0xf1: // Graphics Cursor Y
1184 s->sr[0x11] = reg_value;
1185 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1186 break;
1187 case 0x07: // Extended Sequencer Mode
1188 case 0x08: // EEPROM Control
1189 case 0x09: // Scratch Register 0
1190 case 0x0a: // Scratch Register 1
1191 case 0x0b: // VCLK 0
1192 case 0x0c: // VCLK 1
1193 case 0x0d: // VCLK 2
1194 case 0x0e: // VCLK 3
1195 case 0x0f: // DRAM Control
1196 case 0x12: // Graphics Cursor Attribute
1197 case 0x13: // Graphics Cursor Pattern Address
1198 case 0x14: // Scratch Register 2
1199 case 0x15: // Scratch Register 3
1200 case 0x16: // Performance Tuning Register
1201 case 0x18: // Signature Generator Control
1202 case 0x19: // Signature Generator Result
1203 case 0x1a: // Signature Generator Result
1204 case 0x1b: // VCLK 0 Denominator & Post
1205 case 0x1c: // VCLK 1 Denominator & Post
1206 case 0x1d: // VCLK 2 Denominator & Post
1207 case 0x1e: // VCLK 3 Denominator & Post
1208 case 0x1f: // BIOS Write Enable and MCLK select
1209 s->sr[reg_index] = reg_value;
1210 #ifdef DEBUG_CIRRUS
1211 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1212 reg_index, reg_value);
1213 #endif
1214 break;
1215 case 0x17: // Configuration Readback and Extended Control
1216 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1217 cirrus_update_memory_access(s);
1218 break;
1219 default:
1220 #ifdef DEBUG_CIRRUS
1221 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1222 reg_value);
1223 #endif
1224 break;
1225 }
1226
1227 return CIRRUS_HOOK_HANDLED;
1228 }
1229
1230 /***************************************
1231 *
1232 * I/O access at 0x3c6
1233 *
1234 ***************************************/
1235
1236 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1237 {
1238 *reg_value = 0xff;
1239 if (++s->cirrus_hidden_dac_lockindex == 5) {
1240 *reg_value = s->cirrus_hidden_dac_data;
1241 s->cirrus_hidden_dac_lockindex = 0;
1242 }
1243 }
1244
1245 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1246 {
1247 if (s->cirrus_hidden_dac_lockindex == 4) {
1248 s->cirrus_hidden_dac_data = reg_value;
1249 #if defined(DEBUG_CIRRUS)
1250 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1251 #endif
1252 }
1253 s->cirrus_hidden_dac_lockindex = 0;
1254 }
1255
1256 /***************************************
1257 *
1258 * I/O access at 0x3c9
1259 *
1260 ***************************************/
1261
1262 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1263 {
1264 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1265 return CIRRUS_HOOK_NOT_HANDLED;
1266 *reg_value =
1267 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1268 s->dac_sub_index];
1269 if (++s->dac_sub_index == 3) {
1270 s->dac_sub_index = 0;
1271 s->dac_read_index++;
1272 }
1273 return CIRRUS_HOOK_HANDLED;
1274 }
1275
1276 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1277 {
1278 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1279 return CIRRUS_HOOK_NOT_HANDLED;
1280 s->dac_cache[s->dac_sub_index] = reg_value;
1281 if (++s->dac_sub_index == 3) {
1282 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1283 s->dac_cache, 3);
1284 /* XXX update cursor */
1285 s->dac_sub_index = 0;
1286 s->dac_write_index++;
1287 }
1288 return CIRRUS_HOOK_HANDLED;
1289 }
1290
1291 /***************************************
1292 *
1293 * I/O access between 0x3ce-0x3cf
1294 *
1295 ***************************************/
1296
1297 static int
1298 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1299 {
1300 switch (reg_index) {
1301 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1302 *reg_value = s->cirrus_shadow_gr0;
1303 return CIRRUS_HOOK_HANDLED;
1304 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1305 *reg_value = s->cirrus_shadow_gr1;
1306 return CIRRUS_HOOK_HANDLED;
1307 case 0x02: // Standard VGA
1308 case 0x03: // Standard VGA
1309 case 0x04: // Standard VGA
1310 case 0x06: // Standard VGA
1311 case 0x07: // Standard VGA
1312 case 0x08: // Standard VGA
1313 return CIRRUS_HOOK_NOT_HANDLED;
1314 case 0x05: // Standard VGA, Cirrus extended mode
1315 default:
1316 break;
1317 }
1318
1319 if (reg_index < 0x3a) {
1320 *reg_value = s->gr[reg_index];
1321 } else {
1322 #ifdef DEBUG_CIRRUS
1323 printf("cirrus: inport gr_index %02x\n", reg_index);
1324 #endif
1325 *reg_value = 0xff;
1326 }
1327
1328 return CIRRUS_HOOK_HANDLED;
1329 }
1330
1331 static int
1332 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1333 {
1334 #if defined(DEBUG_BITBLT) && 0
1335 printf("gr%02x: %02x\n", reg_index, reg_value);
1336 #endif
1337 switch (reg_index) {
1338 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1339 s->cirrus_shadow_gr0 = reg_value;
1340 return CIRRUS_HOOK_NOT_HANDLED;
1341 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1342 s->cirrus_shadow_gr1 = reg_value;
1343 return CIRRUS_HOOK_NOT_HANDLED;
1344 case 0x02: // Standard VGA
1345 case 0x03: // Standard VGA
1346 case 0x04: // Standard VGA
1347 case 0x06: // Standard VGA
1348 case 0x07: // Standard VGA
1349 case 0x08: // Standard VGA
1350 return CIRRUS_HOOK_NOT_HANDLED;
1351 case 0x05: // Standard VGA, Cirrus extended mode
1352 s->gr[reg_index] = reg_value & 0x7f;
1353 cirrus_update_memory_access(s);
1354 break;
1355 case 0x09: // bank offset #0
1356 case 0x0A: // bank offset #1
1357 s->gr[reg_index] = reg_value;
1358 cirrus_update_bank_ptr(s, 0);
1359 cirrus_update_bank_ptr(s, 1);
1360 break;
1361 case 0x0B:
1362 s->gr[reg_index] = reg_value;
1363 cirrus_update_bank_ptr(s, 0);
1364 cirrus_update_bank_ptr(s, 1);
1365 cirrus_update_memory_access(s);
1366 break;
1367 case 0x10: // BGCOLOR 0x0000ff00
1368 case 0x11: // FGCOLOR 0x0000ff00
1369 case 0x12: // BGCOLOR 0x00ff0000
1370 case 0x13: // FGCOLOR 0x00ff0000
1371 case 0x14: // BGCOLOR 0xff000000
1372 case 0x15: // FGCOLOR 0xff000000
1373 case 0x20: // BLT WIDTH 0x0000ff
1374 case 0x22: // BLT HEIGHT 0x0000ff
1375 case 0x24: // BLT DEST PITCH 0x0000ff
1376 case 0x26: // BLT SRC PITCH 0x0000ff
1377 case 0x28: // BLT DEST ADDR 0x0000ff
1378 case 0x29: // BLT DEST ADDR 0x00ff00
1379 case 0x2c: // BLT SRC ADDR 0x0000ff
1380 case 0x2d: // BLT SRC ADDR 0x00ff00
1381 case 0x2f: // BLT WRITEMASK
1382 case 0x30: // BLT MODE
1383 case 0x32: // RASTER OP
1384 case 0x33: // BLT MODEEXT
1385 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1386 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1387 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1388 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1389 s->gr[reg_index] = reg_value;
1390 break;
1391 case 0x21: // BLT WIDTH 0x001f00
1392 case 0x23: // BLT HEIGHT 0x001f00
1393 case 0x25: // BLT DEST PITCH 0x001f00
1394 case 0x27: // BLT SRC PITCH 0x001f00
1395 s->gr[reg_index] = reg_value & 0x1f;
1396 break;
1397 case 0x2a: // BLT DEST ADDR 0x3f0000
1398 s->gr[reg_index] = reg_value & 0x3f;
1399 /* if auto start mode, starts bit blt now */
1400 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1401 cirrus_bitblt_start(s);
1402 }
1403 break;
1404 case 0x2e: // BLT SRC ADDR 0x3f0000
1405 s->gr[reg_index] = reg_value & 0x3f;
1406 break;
1407 case 0x31: // BLT STATUS/START
1408 cirrus_write_bitblt(s, reg_value);
1409 break;
1410 default:
1411 #ifdef DEBUG_CIRRUS
1412 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1413 reg_value);
1414 #endif
1415 break;
1416 }
1417
1418 return CIRRUS_HOOK_HANDLED;
1419 }
1420
1421 /***************************************
1422 *
1423 * I/O access between 0x3d4-0x3d5
1424 *
1425 ***************************************/
1426
1427 static int
1428 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1429 {
1430 switch (reg_index) {
1431 case 0x00: // Standard VGA
1432 case 0x01: // Standard VGA
1433 case 0x02: // Standard VGA
1434 case 0x03: // Standard VGA
1435 case 0x04: // Standard VGA
1436 case 0x05: // Standard VGA
1437 case 0x06: // Standard VGA
1438 case 0x07: // Standard VGA
1439 case 0x08: // Standard VGA
1440 case 0x09: // Standard VGA
1441 case 0x0a: // Standard VGA
1442 case 0x0b: // Standard VGA
1443 case 0x0c: // Standard VGA
1444 case 0x0d: // Standard VGA
1445 case 0x0e: // Standard VGA
1446 case 0x0f: // Standard VGA
1447 case 0x10: // Standard VGA
1448 case 0x11: // Standard VGA
1449 case 0x12: // Standard VGA
1450 case 0x13: // Standard VGA
1451 case 0x14: // Standard VGA
1452 case 0x15: // Standard VGA
1453 case 0x16: // Standard VGA
1454 case 0x17: // Standard VGA
1455 case 0x18: // Standard VGA
1456 return CIRRUS_HOOK_NOT_HANDLED;
1457 case 0x19: // Interlace End
1458 case 0x1a: // Miscellaneous Control
1459 case 0x1b: // Extended Display Control
1460 case 0x1c: // Sync Adjust and Genlock
1461 case 0x1d: // Overlay Extended Control
1462 case 0x22: // Graphics Data Latches Readback (R)
1463 case 0x24: // Attribute Controller Toggle Readback (R)
1464 case 0x25: // Part Status
1465 case 0x27: // Part ID (R)
1466 *reg_value = s->cr[reg_index];
1467 break;
1468 case 0x26: // Attribute Controller Index Readback (R)
1469 *reg_value = s->ar_index & 0x3f;
1470 break;
1471 default:
1472 #ifdef DEBUG_CIRRUS
1473 printf("cirrus: inport cr_index %02x\n", reg_index);
1474 *reg_value = 0xff;
1475 #endif
1476 break;
1477 }
1478
1479 return CIRRUS_HOOK_HANDLED;
1480 }
1481
1482 static int
1483 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1484 {
1485 switch (reg_index) {
1486 case 0x00: // Standard VGA
1487 case 0x01: // Standard VGA
1488 case 0x02: // Standard VGA
1489 case 0x03: // Standard VGA
1490 case 0x04: // Standard VGA
1491 case 0x05: // Standard VGA
1492 case 0x06: // Standard VGA
1493 case 0x07: // Standard VGA
1494 case 0x08: // Standard VGA
1495 case 0x09: // Standard VGA
1496 case 0x0a: // Standard VGA
1497 case 0x0b: // Standard VGA
1498 case 0x0c: // Standard VGA
1499 case 0x0d: // Standard VGA
1500 case 0x0e: // Standard VGA
1501 case 0x0f: // Standard VGA
1502 case 0x10: // Standard VGA
1503 case 0x11: // Standard VGA
1504 case 0x12: // Standard VGA
1505 case 0x13: // Standard VGA
1506 case 0x14: // Standard VGA
1507 case 0x15: // Standard VGA
1508 case 0x16: // Standard VGA
1509 case 0x17: // Standard VGA
1510 case 0x18: // Standard VGA
1511 return CIRRUS_HOOK_NOT_HANDLED;
1512 case 0x19: // Interlace End
1513 case 0x1a: // Miscellaneous Control
1514 case 0x1b: // Extended Display Control
1515 case 0x1c: // Sync Adjust and Genlock
1516 case 0x1d: // Overlay Extended Control
1517 s->cr[reg_index] = reg_value;
1518 #ifdef DEBUG_CIRRUS
1519 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1520 reg_index, reg_value);
1521 #endif
1522 break;
1523 case 0x22: // Graphics Data Latches Readback (R)
1524 case 0x24: // Attribute Controller Toggle Readback (R)
1525 case 0x26: // Attribute Controller Index Readback (R)
1526 case 0x27: // Part ID (R)
1527 break;
1528 case 0x25: // Part Status
1529 default:
1530 #ifdef DEBUG_CIRRUS
1531 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1532 reg_value);
1533 #endif
1534 break;
1535 }
1536
1537 return CIRRUS_HOOK_HANDLED;
1538 }
1539
1540 /***************************************
1541 *
1542 * memory-mapped I/O (bitblt)
1543 *
1544 ***************************************/
1545
1546 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1547 {
1548 int value = 0xff;
1549
1550 switch (address) {
1551 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1552 cirrus_hook_read_gr(s, 0x00, &value);
1553 break;
1554 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1555 cirrus_hook_read_gr(s, 0x10, &value);
1556 break;
1557 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1558 cirrus_hook_read_gr(s, 0x12, &value);
1559 break;
1560 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1561 cirrus_hook_read_gr(s, 0x14, &value);
1562 break;
1563 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1564 cirrus_hook_read_gr(s, 0x01, &value);
1565 break;
1566 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1567 cirrus_hook_read_gr(s, 0x11, &value);
1568 break;
1569 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1570 cirrus_hook_read_gr(s, 0x13, &value);
1571 break;
1572 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1573 cirrus_hook_read_gr(s, 0x15, &value);
1574 break;
1575 case (CIRRUS_MMIO_BLTWIDTH + 0):
1576 cirrus_hook_read_gr(s, 0x20, &value);
1577 break;
1578 case (CIRRUS_MMIO_BLTWIDTH + 1):
1579 cirrus_hook_read_gr(s, 0x21, &value);
1580 break;
1581 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1582 cirrus_hook_read_gr(s, 0x22, &value);
1583 break;
1584 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1585 cirrus_hook_read_gr(s, 0x23, &value);
1586 break;
1587 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1588 cirrus_hook_read_gr(s, 0x24, &value);
1589 break;
1590 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1591 cirrus_hook_read_gr(s, 0x25, &value);
1592 break;
1593 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1594 cirrus_hook_read_gr(s, 0x26, &value);
1595 break;
1596 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1597 cirrus_hook_read_gr(s, 0x27, &value);
1598 break;
1599 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1600 cirrus_hook_read_gr(s, 0x28, &value);
1601 break;
1602 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1603 cirrus_hook_read_gr(s, 0x29, &value);
1604 break;
1605 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1606 cirrus_hook_read_gr(s, 0x2a, &value);
1607 break;
1608 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1609 cirrus_hook_read_gr(s, 0x2c, &value);
1610 break;
1611 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1612 cirrus_hook_read_gr(s, 0x2d, &value);
1613 break;
1614 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1615 cirrus_hook_read_gr(s, 0x2e, &value);
1616 break;
1617 case CIRRUS_MMIO_BLTWRITEMASK:
1618 cirrus_hook_read_gr(s, 0x2f, &value);
1619 break;
1620 case CIRRUS_MMIO_BLTMODE:
1621 cirrus_hook_read_gr(s, 0x30, &value);
1622 break;
1623 case CIRRUS_MMIO_BLTROP:
1624 cirrus_hook_read_gr(s, 0x32, &value);
1625 break;
1626 case CIRRUS_MMIO_BLTMODEEXT:
1627 cirrus_hook_read_gr(s, 0x33, &value);
1628 break;
1629 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1630 cirrus_hook_read_gr(s, 0x34, &value);
1631 break;
1632 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1633 cirrus_hook_read_gr(s, 0x35, &value);
1634 break;
1635 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1636 cirrus_hook_read_gr(s, 0x38, &value);
1637 break;
1638 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1639 cirrus_hook_read_gr(s, 0x39, &value);
1640 break;
1641 case CIRRUS_MMIO_BLTSTATUS:
1642 cirrus_hook_read_gr(s, 0x31, &value);
1643 break;
1644 default:
1645 #ifdef DEBUG_CIRRUS
1646 printf("cirrus: mmio read - address 0x%04x\n", address);
1647 #endif
1648 break;
1649 }
1650
1651 return (uint8_t) value;
1652 }
1653
1654 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1655 uint8_t value)
1656 {
1657 switch (address) {
1658 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1659 cirrus_hook_write_gr(s, 0x00, value);
1660 break;
1661 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1662 cirrus_hook_write_gr(s, 0x10, value);
1663 break;
1664 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1665 cirrus_hook_write_gr(s, 0x12, value);
1666 break;
1667 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1668 cirrus_hook_write_gr(s, 0x14, value);
1669 break;
1670 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1671 cirrus_hook_write_gr(s, 0x01, value);
1672 break;
1673 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1674 cirrus_hook_write_gr(s, 0x11, value);
1675 break;
1676 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1677 cirrus_hook_write_gr(s, 0x13, value);
1678 break;
1679 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1680 cirrus_hook_write_gr(s, 0x15, value);
1681 break;
1682 case (CIRRUS_MMIO_BLTWIDTH + 0):
1683 cirrus_hook_write_gr(s, 0x20, value);
1684 break;
1685 case (CIRRUS_MMIO_BLTWIDTH + 1):
1686 cirrus_hook_write_gr(s, 0x21, value);
1687 break;
1688 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1689 cirrus_hook_write_gr(s, 0x22, value);
1690 break;
1691 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1692 cirrus_hook_write_gr(s, 0x23, value);
1693 break;
1694 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1695 cirrus_hook_write_gr(s, 0x24, value);
1696 break;
1697 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1698 cirrus_hook_write_gr(s, 0x25, value);
1699 break;
1700 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1701 cirrus_hook_write_gr(s, 0x26, value);
1702 break;
1703 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1704 cirrus_hook_write_gr(s, 0x27, value);
1705 break;
1706 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1707 cirrus_hook_write_gr(s, 0x28, value);
1708 break;
1709 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1710 cirrus_hook_write_gr(s, 0x29, value);
1711 break;
1712 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1713 cirrus_hook_write_gr(s, 0x2a, value);
1714 break;
1715 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1716 /* ignored */
1717 break;
1718 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1719 cirrus_hook_write_gr(s, 0x2c, value);
1720 break;
1721 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1722 cirrus_hook_write_gr(s, 0x2d, value);
1723 break;
1724 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1725 cirrus_hook_write_gr(s, 0x2e, value);
1726 break;
1727 case CIRRUS_MMIO_BLTWRITEMASK:
1728 cirrus_hook_write_gr(s, 0x2f, value);
1729 break;
1730 case CIRRUS_MMIO_BLTMODE:
1731 cirrus_hook_write_gr(s, 0x30, value);
1732 break;
1733 case CIRRUS_MMIO_BLTROP:
1734 cirrus_hook_write_gr(s, 0x32, value);
1735 break;
1736 case CIRRUS_MMIO_BLTMODEEXT:
1737 cirrus_hook_write_gr(s, 0x33, value);
1738 break;
1739 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1740 cirrus_hook_write_gr(s, 0x34, value);
1741 break;
1742 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1743 cirrus_hook_write_gr(s, 0x35, value);
1744 break;
1745 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1746 cirrus_hook_write_gr(s, 0x38, value);
1747 break;
1748 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1749 cirrus_hook_write_gr(s, 0x39, value);
1750 break;
1751 case CIRRUS_MMIO_BLTSTATUS:
1752 cirrus_hook_write_gr(s, 0x31, value);
1753 break;
1754 default:
1755 #ifdef DEBUG_CIRRUS
1756 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1757 address, value);
1758 #endif
1759 break;
1760 }
1761 }
1762
1763 /***************************************
1764 *
1765 * write mode 4/5
1766 *
1767 * assume TARGET_PAGE_SIZE >= 16
1768 *
1769 ***************************************/
1770
1771 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1772 unsigned mode,
1773 unsigned offset,
1774 uint32_t mem_value)
1775 {
1776 int x;
1777 unsigned val = mem_value;
1778 uint8_t *dst;
1779
1780 dst = s->vram_ptr + offset;
1781 for (x = 0; x < 8; x++) {
1782 if (val & 0x80) {
1783 *dst = s->cirrus_shadow_gr1;
1784 } else if (mode == 5) {
1785 *dst = s->cirrus_shadow_gr0;
1786 }
1787 val <<= 1;
1788 dst++;
1789 }
1790 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1791 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1792 }
1793
1794 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1795 unsigned mode,
1796 unsigned offset,
1797 uint32_t mem_value)
1798 {
1799 int x;
1800 unsigned val = mem_value;
1801 uint8_t *dst;
1802
1803 dst = s->vram_ptr + offset;
1804 for (x = 0; x < 8; x++) {
1805 if (val & 0x80) {
1806 *dst = s->cirrus_shadow_gr1;
1807 *(dst + 1) = s->gr[0x11];
1808 } else if (mode == 5) {
1809 *dst = s->cirrus_shadow_gr0;
1810 *(dst + 1) = s->gr[0x10];
1811 }
1812 val <<= 1;
1813 dst += 2;
1814 }
1815 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1816 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1817 }
1818
1819 /***************************************
1820 *
1821 * memory access between 0xa0000-0xbffff
1822 *
1823 ***************************************/
1824
1825 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1826 {
1827 CirrusVGAState *s = opaque;
1828 unsigned bank_index;
1829 unsigned bank_offset;
1830 uint32_t val;
1831
1832 if ((s->sr[0x07] & 0x01) == 0) {
1833 return vga_mem_readb(s, addr);
1834 }
1835
1836 addr &= 0x1ffff;
1837
1838 if (addr < 0x10000) {
1839 /* XXX handle bitblt */
1840 /* video memory */
1841 bank_index = addr >> 15;
1842 bank_offset = addr & 0x7fff;
1843 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1844 bank_offset += s->cirrus_bank_base[bank_index];
1845 if ((s->gr[0x0B] & 0x14) == 0x14) {
1846 bank_offset <<= 4;
1847 } else if (s->gr[0x0B] & 0x02) {
1848 bank_offset <<= 3;
1849 }
1850 bank_offset &= s->cirrus_addr_mask;
1851 val = *(s->vram_ptr + bank_offset);
1852 } else
1853 val = 0xff;
1854 } else if (addr >= 0x18000 && addr < 0x18100) {
1855 /* memory-mapped I/O */
1856 val = 0xff;
1857 if ((s->sr[0x17] & 0x44) == 0x04) {
1858 val = cirrus_mmio_blt_read(s, addr & 0xff);
1859 }
1860 } else {
1861 val = 0xff;
1862 #ifdef DEBUG_CIRRUS
1863 printf("cirrus: mem_readb %06x\n", addr);
1864 #endif
1865 }
1866 return val;
1867 }
1868
1869 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
1870 {
1871 uint32_t v;
1872 #ifdef TARGET_WORDS_BIGENDIAN
1873 v = cirrus_vga_mem_readb(opaque, addr) << 8;
1874 v |= cirrus_vga_mem_readb(opaque, addr + 1);
1875 #else
1876 v = cirrus_vga_mem_readb(opaque, addr);
1877 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
1878 #endif
1879 return v;
1880 }
1881
1882 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
1883 {
1884 uint32_t v;
1885 #ifdef TARGET_WORDS_BIGENDIAN
1886 v = cirrus_vga_mem_readb(opaque, addr) << 24;
1887 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
1888 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
1889 v |= cirrus_vga_mem_readb(opaque, addr + 3);
1890 #else
1891 v = cirrus_vga_mem_readb(opaque, addr);
1892 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
1893 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
1894 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
1895 #endif
1896 return v;
1897 }
1898
1899 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
1900 uint32_t mem_value)
1901 {
1902 CirrusVGAState *s = opaque;
1903 unsigned bank_index;
1904 unsigned bank_offset;
1905 unsigned mode;
1906
1907 if ((s->sr[0x07] & 0x01) == 0) {
1908 vga_mem_writeb(s, addr, mem_value);
1909 return;
1910 }
1911
1912 addr &= 0x1ffff;
1913
1914 if (addr < 0x10000) {
1915 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
1916 /* bitblt */
1917 *s->cirrus_srcptr++ = (uint8_t) mem_value;
1918 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
1919 cirrus_bitblt_cputovideo_next(s);
1920 }
1921 } else {
1922 /* video memory */
1923 bank_index = addr >> 15;
1924 bank_offset = addr & 0x7fff;
1925 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1926 bank_offset += s->cirrus_bank_base[bank_index];
1927 if ((s->gr[0x0B] & 0x14) == 0x14) {
1928 bank_offset <<= 4;
1929 } else if (s->gr[0x0B] & 0x02) {
1930 bank_offset <<= 3;
1931 }
1932 bank_offset &= s->cirrus_addr_mask;
1933 mode = s->gr[0x05] & 0x7;
1934 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
1935 *(s->vram_ptr + bank_offset) = mem_value;
1936 cpu_physical_memory_set_dirty(s->vram_offset +
1937 bank_offset);
1938 } else {
1939 if ((s->gr[0x0B] & 0x14) != 0x14) {
1940 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
1941 bank_offset,
1942 mem_value);
1943 } else {
1944 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
1945 bank_offset,
1946 mem_value);
1947 }
1948 }
1949 }
1950 }
1951 } else if (addr >= 0x18000 && addr < 0x18100) {
1952 /* memory-mapped I/O */
1953 if ((s->sr[0x17] & 0x44) == 0x04) {
1954 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
1955 }
1956 } else {
1957 #ifdef DEBUG_CIRRUS
1958 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
1959 #endif
1960 }
1961 }
1962
1963 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1964 {
1965 #ifdef TARGET_WORDS_BIGENDIAN
1966 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
1967 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
1968 #else
1969 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
1970 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
1971 #endif
1972 }
1973
1974 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1975 {
1976 #ifdef TARGET_WORDS_BIGENDIAN
1977 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
1978 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
1979 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
1980 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
1981 #else
1982 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
1983 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
1984 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
1985 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
1986 #endif
1987 }
1988
1989 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
1990 cirrus_vga_mem_readb,
1991 cirrus_vga_mem_readw,
1992 cirrus_vga_mem_readl,
1993 };
1994
1995 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
1996 cirrus_vga_mem_writeb,
1997 cirrus_vga_mem_writew,
1998 cirrus_vga_mem_writel,
1999 };
2000
2001 /***************************************
2002 *
2003 * hardware cursor
2004 *
2005 ***************************************/
2006
2007 static inline void invalidate_cursor1(CirrusVGAState *s)
2008 {
2009 if (s->last_hw_cursor_size) {
2010 vga_invalidate_scanlines((VGAState *)s,
2011 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2012 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2013 }
2014 }
2015
2016 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2017 {
2018 const uint8_t *src;
2019 uint32_t content;
2020 int y, y_min, y_max;
2021
2022 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2023 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2024 src += (s->sr[0x13] & 0x3c) * 256;
2025 y_min = 64;
2026 y_max = -1;
2027 for(y = 0; y < 64; y++) {
2028 content = ((uint32_t *)src)[0] |
2029 ((uint32_t *)src)[1] |
2030 ((uint32_t *)src)[2] |
2031 ((uint32_t *)src)[3];
2032 if (content) {
2033 if (y < y_min)
2034 y_min = y;
2035 if (y > y_max)
2036 y_max = y;
2037 }
2038 src += 16;
2039 }
2040 } else {
2041 src += (s->sr[0x13] & 0x3f) * 256;
2042 y_min = 32;
2043 y_max = -1;
2044 for(y = 0; y < 32; y++) {
2045 content = ((uint32_t *)src)[0] |
2046 ((uint32_t *)(src + 128))[0];
2047 if (content) {
2048 if (y < y_min)
2049 y_min = y;
2050 if (y > y_max)
2051 y_max = y;
2052 }
2053 src += 4;
2054 }
2055 }
2056 if (y_min > y_max) {
2057 s->last_hw_cursor_y_start = 0;
2058 s->last_hw_cursor_y_end = 0;
2059 } else {
2060 s->last_hw_cursor_y_start = y_min;
2061 s->last_hw_cursor_y_end = y_max + 1;
2062 }
2063 }
2064
2065 /* NOTE: we do not currently handle the cursor bitmap change, so we
2066 update the cursor only if it moves. */
2067 static void cirrus_cursor_invalidate(VGAState *s1)
2068 {
2069 CirrusVGAState *s = (CirrusVGAState *)s1;
2070 int size;
2071
2072 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2073 size = 0;
2074 } else {
2075 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2076 size = 64;
2077 else
2078 size = 32;
2079 }
2080 /* invalidate last cursor and new cursor if any change */
2081 if (s->last_hw_cursor_size != size ||
2082 s->last_hw_cursor_x != s->hw_cursor_x ||
2083 s->last_hw_cursor_y != s->hw_cursor_y) {
2084
2085 invalidate_cursor1(s);
2086
2087 s->last_hw_cursor_size = size;
2088 s->last_hw_cursor_x = s->hw_cursor_x;
2089 s->last_hw_cursor_y = s->hw_cursor_y;
2090 /* compute the real cursor min and max y */
2091 cirrus_cursor_compute_yrange(s);
2092 invalidate_cursor1(s);
2093 }
2094 }
2095
2096 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2097 {
2098 CirrusVGAState *s = (CirrusVGAState *)s1;
2099 int w, h, bpp, x1, x2, poffset;
2100 unsigned int color0, color1;
2101 const uint8_t *palette, *src;
2102 uint32_t content;
2103
2104 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2105 return;
2106 /* fast test to see if the cursor intersects with the scan line */
2107 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2108 h = 64;
2109 } else {
2110 h = 32;
2111 }
2112 if (scr_y < s->hw_cursor_y ||
2113 scr_y >= (s->hw_cursor_y + h))
2114 return;
2115
2116 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2117 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2118 src += (s->sr[0x13] & 0x3c) * 256;
2119 src += (scr_y - s->hw_cursor_y) * 16;
2120 poffset = 8;
2121 content = ((uint32_t *)src)[0] |
2122 ((uint32_t *)src)[1] |
2123 ((uint32_t *)src)[2] |
2124 ((uint32_t *)src)[3];
2125 } else {
2126 src += (s->sr[0x13] & 0x3f) * 256;
2127 src += (scr_y - s->hw_cursor_y) * 4;
2128 poffset = 128;
2129 content = ((uint32_t *)src)[0] |
2130 ((uint32_t *)(src + 128))[0];
2131 }
2132 /* if nothing to draw, no need to continue */
2133 if (!content)
2134 return;
2135 w = h;
2136
2137 x1 = s->hw_cursor_x;
2138 if (x1 >= s->last_scr_width)
2139 return;
2140 x2 = s->hw_cursor_x + w;
2141 if (x2 > s->last_scr_width)
2142 x2 = s->last_scr_width;
2143 w = x2 - x1;
2144 palette = s->cirrus_hidden_palette;
2145 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2146 c6_to_8(palette[0x0 * 3 + 1]),
2147 c6_to_8(palette[0x0 * 3 + 2]));
2148 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2149 c6_to_8(palette[0xf * 3 + 1]),
2150 c6_to_8(palette[0xf * 3 + 2]));
2151 bpp = ((s->ds->depth + 7) >> 3);
2152 d1 += x1 * bpp;
2153 switch(s->ds->depth) {
2154 default:
2155 break;
2156 case 8:
2157 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2158 break;
2159 case 15:
2160 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2161 break;
2162 case 16:
2163 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2164 break;
2165 case 32:
2166 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2167 break;
2168 }
2169 }
2170
2171 /***************************************
2172 *
2173 * LFB memory access
2174 *
2175 ***************************************/
2176
2177 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2178 {
2179 CirrusVGAState *s = (CirrusVGAState *) opaque;
2180 uint32_t ret;
2181
2182 addr &= s->cirrus_addr_mask;
2183
2184 if (((s->sr[0x17] & 0x44) == 0x44) &&
2185 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2186 /* memory-mapped I/O */
2187 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2188 } else if (0) {
2189 /* XXX handle bitblt */
2190 ret = 0xff;
2191 } else {
2192 /* video memory */
2193 if ((s->gr[0x0B] & 0x14) == 0x14) {
2194 addr <<= 4;
2195 } else if (s->gr[0x0B] & 0x02) {
2196 addr <<= 3;
2197 }
2198 addr &= s->cirrus_addr_mask;
2199 ret = *(s->vram_ptr + addr);
2200 }
2201
2202 return ret;
2203 }
2204
2205 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2206 {
2207 uint32_t v;
2208 #ifdef TARGET_WORDS_BIGENDIAN
2209 v = cirrus_linear_readb(opaque, addr) << 8;
2210 v |= cirrus_linear_readb(opaque, addr + 1);
2211 #else
2212 v = cirrus_linear_readb(opaque, addr);
2213 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2214 #endif
2215 return v;
2216 }
2217
2218 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2219 {
2220 uint32_t v;
2221 #ifdef TARGET_WORDS_BIGENDIAN
2222 v = cirrus_linear_readb(opaque, addr) << 24;
2223 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2224 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2225 v |= cirrus_linear_readb(opaque, addr + 3);
2226 #else
2227 v = cirrus_linear_readb(opaque, addr);
2228 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2229 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2230 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2231 #endif
2232 return v;
2233 }
2234
2235 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2236 uint32_t val)
2237 {
2238 CirrusVGAState *s = (CirrusVGAState *) opaque;
2239 unsigned mode;
2240
2241 addr &= s->cirrus_addr_mask;
2242
2243 if (((s->sr[0x17] & 0x44) == 0x44) &&
2244 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2245 /* memory-mapped I/O */
2246 cirrus_mmio_blt_write(s, addr & 0xff, val);
2247 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2248 /* bitblt */
2249 *s->cirrus_srcptr++ = (uint8_t) val;
2250 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2251 cirrus_bitblt_cputovideo_next(s);
2252 }
2253 } else {
2254 /* video memory */
2255 if ((s->gr[0x0B] & 0x14) == 0x14) {
2256 addr <<= 4;
2257 } else if (s->gr[0x0B] & 0x02) {
2258 addr <<= 3;
2259 }
2260 addr &= s->cirrus_addr_mask;
2261
2262 mode = s->gr[0x05] & 0x7;
2263 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2264 *(s->vram_ptr + addr) = (uint8_t) val;
2265 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2266 } else {
2267 if ((s->gr[0x0B] & 0x14) != 0x14) {
2268 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2269 } else {
2270 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2271 }
2272 }
2273 }
2274 }
2275
2276 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2277 uint32_t val)
2278 {
2279 #ifdef TARGET_WORDS_BIGENDIAN
2280 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2281 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2282 #else
2283 cirrus_linear_writeb(opaque, addr, val & 0xff);
2284 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2285 #endif
2286 }
2287
2288 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2289 uint32_t val)
2290 {
2291 #ifdef TARGET_WORDS_BIGENDIAN
2292 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2293 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2294 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2295 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2296 #else
2297 cirrus_linear_writeb(opaque, addr, val & 0xff);
2298 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2299 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2300 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2301 #endif
2302 }
2303
2304
2305 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2306 cirrus_linear_readb,
2307 cirrus_linear_readw,
2308 cirrus_linear_readl,
2309 };
2310
2311 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2312 cirrus_linear_writeb,
2313 cirrus_linear_writew,
2314 cirrus_linear_writel,
2315 };
2316
2317 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2318 uint32_t val)
2319 {
2320 CirrusVGAState *s = (CirrusVGAState *) opaque;
2321
2322 addr &= s->cirrus_addr_mask;
2323 *(s->vram_ptr + addr) = val;
2324 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2325 }
2326
2327 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2328 uint32_t val)
2329 {
2330 CirrusVGAState *s = (CirrusVGAState *) opaque;
2331
2332 addr &= s->cirrus_addr_mask;
2333 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2334 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2335 }
2336
2337 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2338 uint32_t val)
2339 {
2340 CirrusVGAState *s = (CirrusVGAState *) opaque;
2341
2342 addr &= s->cirrus_addr_mask;
2343 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2344 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2345 }
2346
2347 /***************************************
2348 *
2349 * system to screen memory access
2350 *
2351 ***************************************/
2352
2353
2354 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2355 {
2356 uint32_t ret;
2357
2358 /* XXX handle bitblt */
2359 ret = 0xff;
2360 return ret;
2361 }
2362
2363 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2364 {
2365 uint32_t v;
2366 #ifdef TARGET_WORDS_BIGENDIAN
2367 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2368 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2369 #else
2370 v = cirrus_linear_bitblt_readb(opaque, addr);
2371 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2372 #endif
2373 return v;
2374 }
2375
2376 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2377 {
2378 uint32_t v;
2379 #ifdef TARGET_WORDS_BIGENDIAN
2380 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2381 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2382 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2383 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2384 #else
2385 v = cirrus_linear_bitblt_readb(opaque, addr);
2386 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2387 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2388 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2389 #endif
2390 return v;
2391 }
2392
2393 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2394 uint32_t val)
2395 {
2396 CirrusVGAState *s = (CirrusVGAState *) opaque;
2397
2398 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2399 /* bitblt */
2400 *s->cirrus_srcptr++ = (uint8_t) val;
2401 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2402 cirrus_bitblt_cputovideo_next(s);
2403 }
2404 }
2405 }
2406
2407 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2408 uint32_t val)
2409 {
2410 #ifdef TARGET_WORDS_BIGENDIAN
2411 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2412 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2413 #else
2414 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2415 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2416 #endif
2417 }
2418
2419 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2420 uint32_t val)
2421 {
2422 #ifdef TARGET_WORDS_BIGENDIAN
2423 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2424 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2425 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2426 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2427 #else
2428 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2429 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2430 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2431 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2432 #endif
2433 }
2434
2435
2436 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2437 cirrus_linear_bitblt_readb,
2438 cirrus_linear_bitblt_readw,
2439 cirrus_linear_bitblt_readl,
2440 };
2441
2442 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2443 cirrus_linear_bitblt_writeb,
2444 cirrus_linear_bitblt_writew,
2445 cirrus_linear_bitblt_writel,
2446 };
2447
2448 /* Compute the memory access functions */
2449 static void cirrus_update_memory_access(CirrusVGAState *s)
2450 {
2451 unsigned mode;
2452
2453 if ((s->sr[0x17] & 0x44) == 0x44) {
2454 goto generic_io;
2455 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2456 goto generic_io;
2457 } else {
2458 if ((s->gr[0x0B] & 0x14) == 0x14) {
2459 goto generic_io;
2460 } else if (s->gr[0x0B] & 0x02) {
2461 goto generic_io;
2462 }
2463
2464 mode = s->gr[0x05] & 0x7;
2465 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2466 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2467 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2468 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2469 } else {
2470 generic_io:
2471 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2472 s->cirrus_linear_write[1] = cirrus_linear_writew;
2473 s->cirrus_linear_write[2] = cirrus_linear_writel;
2474 }
2475 }
2476 }
2477
2478
2479 /* I/O ports */
2480
2481 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2482 {
2483 CirrusVGAState *s = opaque;
2484 int val, index;
2485
2486 /* check port range access depending on color/monochrome mode */
2487 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2488 || (addr >= 0x3d0 && addr <= 0x3df
2489 && !(s->msr & MSR_COLOR_EMULATION))) {
2490 val = 0xff;
2491 } else {
2492 switch (addr) {
2493 case 0x3c0:
2494 if (s->ar_flip_flop == 0) {
2495 val = s->ar_index;
2496 } else {
2497 val = 0;
2498 }
2499 break;
2500 case 0x3c1:
2501 index = s->ar_index & 0x1f;
2502 if (index < 21)
2503 val = s->ar[index];
2504 else
2505 val = 0;
2506 break;
2507 case 0x3c2:
2508 val = s->st00;
2509 break;
2510 case 0x3c4:
2511 val = s->sr_index;
2512 break;
2513 case 0x3c5:
2514 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2515 break;
2516 val = s->sr[s->sr_index];
2517 #ifdef DEBUG_VGA_REG
2518 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2519 #endif
2520 break;
2521 case 0x3c6:
2522 cirrus_read_hidden_dac(s, &val);
2523 break;
2524 case 0x3c7:
2525 val = s->dac_state;
2526 break;
2527 case 0x3c8:
2528 val = s->dac_write_index;
2529 s->cirrus_hidden_dac_lockindex = 0;
2530 break;
2531 case 0x3c9:
2532 if (cirrus_hook_read_palette(s, &val))
2533 break;
2534 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2535 if (++s->dac_sub_index == 3) {
2536 s->dac_sub_index = 0;
2537 s->dac_read_index++;
2538 }
2539 break;
2540 case 0x3ca:
2541 val = s->fcr;
2542 break;
2543 case 0x3cc:
2544 val = s->msr;
2545 break;
2546 case 0x3ce:
2547 val = s->gr_index;
2548 break;
2549 case 0x3cf:
2550 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2551 break;
2552 val = s->gr[s->gr_index];
2553 #ifdef DEBUG_VGA_REG
2554 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2555 #endif
2556 break;
2557 case 0x3b4:
2558 case 0x3d4:
2559 val = s->cr_index;
2560 break;
2561 case 0x3b5:
2562 case 0x3d5:
2563 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2564 break;
2565 val = s->cr[s->cr_index];
2566 #ifdef DEBUG_VGA_REG
2567 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2568 #endif
2569 break;
2570 case 0x3ba:
2571 case 0x3da:
2572 /* just toggle to fool polling */
2573 s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;
2574 val = s->st01;
2575 s->ar_flip_flop = 0;
2576 break;
2577 default:
2578 val = 0x00;
2579 break;
2580 }
2581 }
2582 #if defined(DEBUG_VGA)
2583 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2584 #endif
2585 return val;
2586 }
2587
2588 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2589 {
2590 CirrusVGAState *s = opaque;
2591 int index;
2592
2593 /* check port range access depending on color/monochrome mode */
2594 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2595 || (addr >= 0x3d0 && addr <= 0x3df
2596 && !(s->msr & MSR_COLOR_EMULATION)))
2597 return;
2598
2599 #ifdef DEBUG_VGA
2600 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2601 #endif
2602
2603 switch (addr) {
2604 case 0x3c0:
2605 if (s->ar_flip_flop == 0) {
2606 val &= 0x3f;
2607 s->ar_index = val;
2608 } else {
2609 index = s->ar_index & 0x1f;
2610 switch (index) {
2611 case 0x00 ... 0x0f:
2612 s->ar[index] = val & 0x3f;
2613 break;
2614 case 0x10:
2615 s->ar[index] = val & ~0x10;
2616 break;
2617 case 0x11:
2618 s->ar[index] = val;
2619 break;
2620 case 0x12:
2621 s->ar[index] = val & ~0xc0;
2622 break;
2623 case 0x13:
2624 s->ar[index] = val & ~0xf0;
2625 break;
2626 case 0x14:
2627 s->ar[index] = val & ~0xf0;
2628 break;
2629 default:
2630 break;
2631 }
2632 }
2633 s->ar_flip_flop ^= 1;
2634 break;
2635 case 0x3c2:
2636 s->msr = val & ~0x10;
2637 break;
2638 case 0x3c4:
2639 s->sr_index = val;
2640 break;
2641 case 0x3c5:
2642 if (cirrus_hook_write_sr(s, s->sr_index, val))
2643 break;
2644 #ifdef DEBUG_VGA_REG
2645 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2646 #endif
2647 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2648 break;
2649 case 0x3c6:
2650 cirrus_write_hidden_dac(s, val);
2651 break;
2652 case 0x3c7:
2653 s->dac_read_index = val;
2654 s->dac_sub_index = 0;
2655 s->dac_state = 3;
2656 break;
2657 case 0x3c8:
2658 s->dac_write_index = val;
2659 s->dac_sub_index = 0;
2660 s->dac_state = 0;
2661 break;
2662 case 0x3c9:
2663 if (cirrus_hook_write_palette(s, val))
2664 break;
2665 s->dac_cache[s->dac_sub_index] = val;
2666 if (++s->dac_sub_index == 3) {
2667 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2668 s->dac_sub_index = 0;
2669 s->dac_write_index++;
2670 }
2671 break;
2672 case 0x3ce:
2673 s->gr_index = val;
2674 break;
2675 case 0x3cf:
2676 if (cirrus_hook_write_gr(s, s->gr_index, val))
2677 break;
2678 #ifdef DEBUG_VGA_REG
2679 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2680 #endif
2681 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2682 break;
2683 case 0x3b4:
2684 case 0x3d4:
2685 s->cr_index = val;
2686 break;
2687 case 0x3b5:
2688 case 0x3d5:
2689 if (cirrus_hook_write_cr(s, s->cr_index, val))
2690 break;
2691 #ifdef DEBUG_VGA_REG
2692 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2693 #endif
2694 /* handle CR0-7 protection */
2695 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2696 /* can always write bit 4 of CR7 */
2697 if (s->cr_index == 7)
2698 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2699 return;
2700 }
2701 switch (s->cr_index) {
2702 case 0x01: /* horizontal display end */
2703 case 0x07:
2704 case 0x09:
2705 case 0x0c:
2706 case 0x0d:
2707 case 0x12: /* veritcal display end */
2708 s->cr[s->cr_index] = val;
2709 break;
2710
2711 default:
2712 s->cr[s->cr_index] = val;
2713 break;
2714 }
2715 break;
2716 case 0x3ba:
2717 case 0x3da:
2718 s->fcr = val & 0x10;
2719 break;
2720 }
2721 }
2722
2723 /***************************************
2724 *
2725 * memory-mapped I/O access
2726 *
2727 ***************************************/
2728
2729 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2730 {
2731 CirrusVGAState *s = (CirrusVGAState *) opaque;
2732
2733 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2734
2735 if (addr >= 0x100) {
2736 return cirrus_mmio_blt_read(s, addr - 0x100);
2737 } else {
2738 return vga_ioport_read(s, addr + 0x3c0);
2739 }
2740 }
2741
2742 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2743 {
2744 uint32_t v;
2745 #ifdef TARGET_WORDS_BIGENDIAN
2746 v = cirrus_mmio_readb(opaque, addr) << 8;
2747 v |= cirrus_mmio_readb(opaque, addr + 1);
2748 #else
2749 v = cirrus_mmio_readb(opaque, addr);
2750 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2751 #endif
2752 return v;
2753 }
2754
2755 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2756 {
2757 uint32_t v;
2758 #ifdef TARGET_WORDS_BIGENDIAN
2759 v = cirrus_mmio_readb(opaque, addr) << 24;
2760 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
2761 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
2762 v |= cirrus_mmio_readb(opaque, addr + 3);
2763 #else
2764 v = cirrus_mmio_readb(opaque, addr);
2765 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2766 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2767 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2768 #endif
2769 return v;
2770 }
2771
2772 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
2773 uint32_t val)
2774 {
2775 CirrusVGAState *s = (CirrusVGAState *) opaque;
2776
2777 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2778
2779 if (addr >= 0x100) {
2780 cirrus_mmio_blt_write(s, addr - 0x100, val);
2781 } else {
2782 vga_ioport_write(s, addr + 0x3c0, val);
2783 }
2784 }
2785
2786 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
2787 uint32_t val)
2788 {
2789 #ifdef TARGET_WORDS_BIGENDIAN
2790 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
2791 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
2792 #else
2793 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2794 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2795 #endif
2796 }
2797
2798 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
2799 uint32_t val)
2800 {
2801 #ifdef TARGET_WORDS_BIGENDIAN
2802 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
2803 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2804 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2805 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
2806 #else
2807 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2808 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2809 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2810 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2811 #endif
2812 }
2813
2814
2815 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
2816 cirrus_mmio_readb,
2817 cirrus_mmio_readw,
2818 cirrus_mmio_readl,
2819 };
2820
2821 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
2822 cirrus_mmio_writeb,
2823 cirrus_mmio_writew,
2824 cirrus_mmio_writel,
2825 };
2826
2827 /* load/save state */
2828
2829 static void cirrus_vga_save(QEMUFile *f, void *opaque)
2830 {
2831 CirrusVGAState *s = opaque;
2832
2833 qemu_put_be32s(f, &s->latch);
2834 qemu_put_8s(f, &s->sr_index);
2835 qemu_put_buffer(f, s->sr, 256);
2836 qemu_put_8s(f, &s->gr_index);
2837 qemu_put_8s(f, &s->cirrus_shadow_gr0);
2838 qemu_put_8s(f, &s->cirrus_shadow_gr1);
2839 qemu_put_buffer(f, s->gr + 2, 254);
2840 qemu_put_8s(f, &s->ar_index);
2841 qemu_put_buffer(f, s->ar, 21);
2842 qemu_put_be32s(f, &s->ar_flip_flop);
2843 qemu_put_8s(f, &s->cr_index);
2844 qemu_put_buffer(f, s->cr, 256);
2845 qemu_put_8s(f, &s->msr);
2846 qemu_put_8s(f, &s->fcr);
2847 qemu_put_8s(f, &s->st00);
2848 qemu_put_8s(f, &s->st01);
2849
2850 qemu_put_8s(f, &s->dac_state);
2851 qemu_put_8s(f, &s->dac_sub_index);
2852 qemu_put_8s(f, &s->dac_read_index);
2853 qemu_put_8s(f, &s->dac_write_index);
2854 qemu_put_buffer(f, s->dac_cache, 3);
2855 qemu_put_buffer(f, s->palette, 768);
2856
2857 qemu_put_be32s(f, &s->bank_offset);
2858
2859 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
2860 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
2861
2862 qemu_put_be32s(f, &s->hw_cursor_x);
2863 qemu_put_be32s(f, &s->hw_cursor_y);
2864 /* XXX: we do not save the bitblt state - we assume we do not save
2865 the state when the blitter is active */
2866 }
2867
2868 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
2869 {
2870 CirrusVGAState *s = opaque;
2871
2872 if (version_id != 1)
2873 return -EINVAL;
2874
2875 qemu_get_be32s(f, &s->latch);
2876 qemu_get_8s(f, &s->sr_index);
2877 qemu_get_buffer(f, s->sr, 256);
2878 qemu_get_8s(f, &s->gr_index);
2879 qemu_get_8s(f, &s->cirrus_shadow_gr0);
2880 qemu_get_8s(f, &s->cirrus_shadow_gr1);
2881 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2882 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2883 qemu_get_buffer(f, s->gr + 2, 254);
2884 qemu_get_8s(f, &s->ar_index);
2885 qemu_get_buffer(f, s->ar, 21);
2886 qemu_get_be32s(f, &s->ar_flip_flop);
2887 qemu_get_8s(f, &s->cr_index);
2888 qemu_get_buffer(f, s->cr, 256);
2889 qemu_get_8s(f, &s->msr);
2890 qemu_get_8s(f, &s->fcr);
2891 qemu_get_8s(f, &s->st00);
2892 qemu_get_8s(f, &s->st01);
2893
2894 qemu_get_8s(f, &s->dac_state);
2895 qemu_get_8s(f, &s->dac_sub_index);
2896 qemu_get_8s(f, &s->dac_read_index);
2897 qemu_get_8s(f, &s->dac_write_index);
2898 qemu_get_buffer(f, s->dac_cache, 3);
2899 qemu_get_buffer(f, s->palette, 768);
2900
2901 qemu_get_be32s(f, &s->bank_offset);
2902
2903 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
2904 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
2905
2906 qemu_get_be32s(f, &s->hw_cursor_x);
2907 qemu_get_be32s(f, &s->hw_cursor_y);
2908
2909 /* force refresh */
2910 s->graphic_mode = -1;
2911 cirrus_update_bank_ptr(s, 0);
2912 cirrus_update_bank_ptr(s, 1);
2913 return 0;
2914 }
2915
2916 /***************************************
2917 *
2918 * initialize
2919 *
2920 ***************************************/
2921
2922 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
2923 {
2924 int vga_io_memory, i;
2925 static int inited;
2926
2927 if (!inited) {
2928 inited = 1;
2929 for(i = 0;i < 256; i++)
2930 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2931 rop_to_index[CIRRUS_ROP_0] = 0;
2932 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2933 rop_to_index[CIRRUS_ROP_NOP] = 2;
2934 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2935 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2936 rop_to_index[CIRRUS_ROP_SRC] = 5;
2937 rop_to_index[CIRRUS_ROP_1] = 6;
2938 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2939 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2940 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2941 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2942 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2943 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2944 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2945 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2946 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2947 }
2948
2949 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2950
2951 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2952 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2953 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2954 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2955
2956 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2957
2958 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2959 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2960 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2961 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2962
2963 vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
2964 cirrus_vga_mem_write, s);
2965 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2966 vga_io_memory);
2967
2968 s->sr[0x06] = 0x0f;
2969 if (device_id == CIRRUS_ID_CLGD5446) {
2970 /* 4MB 64 bit memory config, always PCI */
2971 s->sr[0x1F] = 0x2d; // MemClock
2972 s->gr[0x18] = 0x0f; // fastest memory configuration
2973 #if 1
2974 s->sr[0x0f] = 0x98;
2975 s->sr[0x17] = 0x20;
2976 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2977 s->real_vram_size = 4096 * 1024;
2978 #else
2979 s->sr[0x0f] = 0x18;
2980 s->sr[0x17] = 0x20;
2981 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2982 s->real_vram_size = 2048 * 1024;
2983 #endif
2984 } else {
2985 s->sr[0x1F] = 0x22; // MemClock
2986 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
2987 if (is_pci)
2988 s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
2989 else
2990 s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
2991 s->real_vram_size = 2048 * 1024;
2992 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2993 }
2994 s->cr[0x27] = device_id;
2995
2996 /* Win2K seems to assume that the pattern buffer is at 0xff
2997 initially ! */
2998 memset(s->vram_ptr, 0xff, s->real_vram_size);
2999
3000 s->cirrus_hidden_dac_lockindex = 5;
3001 s->cirrus_hidden_dac_data = 0;
3002
3003 /* I/O handler for LFB */
3004 s->cirrus_linear_io_addr =
3005 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3006 s);
3007 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3008
3009 /* I/O handler for LFB */
3010 s->cirrus_linear_bitblt_io_addr =
3011 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3012 s);
3013
3014 /* I/O handler for memory-mapped I/O */
3015 s->cirrus_mmio_io_addr =
3016 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3017
3018 /* XXX: s->vram_size must be a power of two */
3019 s->cirrus_addr_mask = s->real_vram_size - 1;
3020 s->linear_mmio_mask = s->real_vram_size - 256;
3021
3022 s->get_bpp = cirrus_get_bpp;
3023 s->get_offsets = cirrus_get_offsets;
3024 s->get_resolution = cirrus_get_resolution;
3025 s->cursor_invalidate = cirrus_cursor_invalidate;
3026 s->cursor_draw_line = cirrus_cursor_draw_line;
3027
3028 register_savevm("cirrus_vga", 0, 1, cirrus_vga_save, cirrus_vga_load, s);
3029 }
3030
3031 /***************************************
3032 *
3033 * ISA bus support
3034 *
3035 ***************************************/
3036
3037 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
3038 unsigned long vga_ram_offset, int vga_ram_size)
3039 {
3040 CirrusVGAState *s;
3041
3042 s = qemu_mallocz(sizeof(CirrusVGAState));
3043
3044 vga_common_init((VGAState *)s,
3045 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3046 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3047 /* XXX ISA-LFB support */
3048 }
3049
3050 /***************************************
3051 *
3052 * PCI bus support
3053 *
3054 ***************************************/
3055
3056 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3057 uint32_t addr, uint32_t size, int type)
3058 {
3059 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3060
3061 /* XXX: add byte swapping apertures */
3062 cpu_register_physical_memory(addr, s->vram_size,
3063 s->cirrus_linear_io_addr);
3064 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3065 s->cirrus_linear_bitblt_io_addr);
3066 }
3067
3068 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3069 uint32_t addr, uint32_t size, int type)
3070 {
3071 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3072
3073 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3074 s->cirrus_mmio_io_addr);
3075 }
3076
3077 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
3078 unsigned long vga_ram_offset, int vga_ram_size)
3079 {
3080 PCICirrusVGAState *d;
3081 uint8_t *pci_conf;
3082 CirrusVGAState *s;
3083 int device_id;
3084
3085 device_id = CIRRUS_ID_CLGD5446;
3086
3087 /* setup PCI configuration registers */
3088 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3089 sizeof(PCICirrusVGAState),
3090 -1, NULL, NULL);
3091 pci_conf = d->dev.config;
3092 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3093 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
3094 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3095 pci_conf[0x03] = (uint8_t) (device_id >> 8);
3096 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3097 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3098 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3099 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3100
3101 /* setup VGA */
3102 s = &d->cirrus_vga;
3103 vga_common_init((VGAState *)s,
3104 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3105 cirrus_init_common(s, device_id, 1);
3106
3107 /* setup memory space */
3108 /* memory #0 LFB */
3109 /* memory #1 memory-mapped I/O */
3110 /* XXX: s->vram_size must be a power of two */
3111 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3112 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3113 if (device_id == CIRRUS_ID_CLGD5446) {
3114 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3115 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3116 }
3117 /* XXX: ROM BIOS */
3118 }
Samsung s3c2440 and arm920t support for the mini2440 dev board