4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 /* i82731AB (PIIX4) compatible power management function */
24 #define PM_FREQ 3579545
26 /* XXX: make them variable */
27 #define PM_IO_BASE 0xb000
28 #define SMI_CMD_IO_ADDR 0xb040
29 #define ACPI_DBG_IO_ADDR 0xb044
31 typedef struct PIIX4PMState
{
37 int64_t tmr_overflow_time
;
40 #define RTC_EN (1 << 10)
41 #define PWRBTN_EN (1 << 8)
42 #define GBL_EN (1 << 5)
43 #define TMROF_EN (1 << 0)
45 #define SCI_EN (1 << 0)
47 #define SUS_EN (1 << 13)
49 /* Note: only used for ACPI bios init. Could be deleted when ACPI init
50 is integrated in Bochs BIOS */
51 static PIIX4PMState
*piix4_pm_state
;
53 static uint32_t get_pmtmr(PIIX4PMState
*s
)
56 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
60 static int get_pmsts(PIIX4PMState
*s
)
65 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
66 if (d
>= s
->tmr_overflow_time
)
71 static void pm_update_sci(PIIX4PMState
*s
)
77 sci_level
= (((pmsts
& s
->pmen
) &
78 (RTC_EN
| PWRBTN_EN
| GBL_EN
| TMROF_EN
)) != 0);
79 pci_set_irq(&s
->dev
, 0, sci_level
);
80 /* schedule a timer interruption if needed */
81 if ((s
->pmen
& TMROF_EN
) && !(pmsts
& TMROF_EN
)) {
82 expire_time
= muldiv64(s
->tmr_overflow_time
, ticks_per_sec
, PM_FREQ
);
83 qemu_mod_timer(s
->tmr_timer
, expire_time
);
85 qemu_del_timer(s
->tmr_timer
);
89 static void pm_tmr_timer(void *opaque
)
91 PIIX4PMState
*s
= opaque
;
95 static void pm_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
97 PIIX4PMState
*s
= opaque
;
104 pmsts
= get_pmsts(s
);
105 if (pmsts
& val
& TMROF_EN
) {
106 /* if TMRSTS is reset, then compute the new overflow time */
107 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
108 s
->tmr_overflow_time
= (d
+ 0x800000LL
) & ~0x7fffffLL
;
121 s
->pmcntrl
= val
& ~(SUS_EN
);
123 /* change suspend type */
124 sus_typ
= (val
>> 10) & 3;
126 case 0: /* soft power off */
127 qemu_system_shutdown_request();
139 printf("PM writew port=0x%04x val=0x%04x\n", addr
, val
);
143 static uint32_t pm_ioport_readw(void *opaque
, uint32_t addr
)
145 PIIX4PMState
*s
= opaque
;
164 printf("PM readw port=0x%04x val=0x%04x\n", addr
, val
);
169 static void pm_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
171 // PIIX4PMState *s = opaque;
174 printf("PM writel port=0x%04x val=0x%08x\n", addr
, val
);
178 static uint32_t pm_ioport_readl(void *opaque
, uint32_t addr
)
180 PIIX4PMState
*s
= opaque
;
193 printf("PM readl port=0x%04x val=0x%08x\n", addr
, val
);
198 static void smi_cmd_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
200 PIIX4PMState
*s
= opaque
;
202 printf("SMI cmd val=0x%02x\n", val
);
205 case 0xf0: /* ACPI disable */
206 s
->pmcntrl
&= ~SCI_EN
;
208 case 0xf1: /* ACPI enable */
209 s
->pmcntrl
|= SCI_EN
;
214 static void acpi_dbg_writel(void *opaque
, uint32_t addr
, uint32_t val
)
217 printf("ACPI: DBG: 0x%08x\n", val
);
221 /* XXX: we still add it to the PIIX3 and we count on the fact that
222 OSes are smart enough to accept this strange configuration */
223 void piix4_pm_init(PCIBus
*bus
)
229 s
= (PIIX4PMState
*)pci_register_device(bus
,
230 "PM", sizeof(PIIX4PMState
),
231 ((PCIDevice
*)piix3_state
)->devfn
+ 3,
233 pci_conf
= s
->dev
.config
;
234 pci_conf
[0x00] = 0x86;
235 pci_conf
[0x01] = 0x80;
236 pci_conf
[0x02] = 0x13;
237 pci_conf
[0x03] = 0x71;
238 pci_conf
[0x08] = 0x00; // revision number
239 pci_conf
[0x09] = 0x00;
240 pci_conf
[0x0a] = 0x80; // other bridge device
241 pci_conf
[0x0b] = 0x06; // bridge device
242 pci_conf
[0x0e] = 0x00; // header_type
243 pci_conf
[0x3d] = 0x01; // interrupt pin 1
244 pci_conf
[0x60] = 0x10; // release number
246 pm_io_base
= PM_IO_BASE
;
247 pci_conf
[0x40] = pm_io_base
| 1;
248 pci_conf
[0x41] = pm_io_base
>> 8;
249 register_ioport_write(pm_io_base
, 64, 2, pm_ioport_writew
, s
);
250 register_ioport_read(pm_io_base
, 64, 2, pm_ioport_readw
, s
);
251 register_ioport_write(pm_io_base
, 64, 4, pm_ioport_writel
, s
);
252 register_ioport_read(pm_io_base
, 64, 4, pm_ioport_readl
, s
);
254 register_ioport_write(SMI_CMD_IO_ADDR
, 1, 1, smi_cmd_writeb
, s
);
255 register_ioport_write(ACPI_DBG_IO_ADDR
, 4, 4, acpi_dbg_writel
, s
);
257 s
->tmr_timer
= qemu_new_timer(vm_clock
, pm_tmr_timer
, s
);
262 /* XXX: move them in the Bochs BIOS ? */
264 /*************************************************/
266 /* Table structure from Linux kernel (the ACPI tables are under the
269 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
270 uint8_t signature [4]; /* ACPI signature (4 ASCII characters) */\
271 uint32_t length; /* Length of table, in bytes, including header */\
272 uint8_t revision; /* ACPI Specification minor version # */\
273 uint8_t checksum; /* To make sum of entire table == 0 */\
274 uint8_t oem_id [6]; /* OEM identification */\
275 uint8_t oem_table_id [8]; /* OEM table identification */\
276 uint32_t oem_revision; /* OEM revision number */\
277 uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */\
278 uint32_t asl_compiler_revision; /* ASL compiler revision number */
281 struct acpi_table_header
/* ACPI common table header */
283 ACPI_TABLE_HEADER_DEF
286 struct rsdp_descriptor
/* Root System Descriptor Pointer */
288 uint8_t signature
[8]; /* ACPI signature, contains "RSD PTR " */
289 uint8_t checksum
; /* To make sum of struct == 0 */
290 uint8_t oem_id
[6]; /* OEM identification */
291 uint8_t revision
; /* Must be 0 for 1.0, 2 for 2.0 */
292 uint32_t rsdt_physical_address
; /* 32-bit physical address of RSDT */
293 uint32_t length
; /* XSDT Length in bytes including hdr */
294 uint64_t xsdt_physical_address
; /* 64-bit physical address of XSDT */
295 uint8_t extended_checksum
; /* Checksum of entire table */
296 uint8_t reserved
[3]; /* Reserved field must be 0 */
300 * ACPI 1.0 Root System Description Table (RSDT)
302 struct rsdt_descriptor_rev1
304 ACPI_TABLE_HEADER_DEF
/* ACPI common table header */
305 uint32_t table_offset_entry
[2]; /* Array of pointers to other */
310 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
312 struct facs_descriptor_rev1
314 uint8_t signature
[4]; /* ACPI Signature */
315 uint32_t length
; /* Length of structure, in bytes */
316 uint32_t hardware_signature
; /* Hardware configuration signature */
317 uint32_t firmware_waking_vector
; /* ACPI OS waking vector */
318 uint32_t global_lock
; /* Global Lock */
319 uint32_t S4bios_f
: 1; /* Indicates if S4BIOS support is present */
320 uint32_t reserved1
: 31; /* Must be 0 */
321 uint8_t resverved3
[40]; /* Reserved - must be zero */
326 * ACPI 1.0 Fixed ACPI Description Table (FADT)
328 struct fadt_descriptor_rev1
330 ACPI_TABLE_HEADER_DEF
/* ACPI common table header */
331 uint32_t firmware_ctrl
; /* Physical address of FACS */
332 uint32_t dsdt
; /* Physical address of DSDT */
333 uint8_t model
; /* System Interrupt Model */
334 uint8_t reserved1
; /* Reserved */
335 uint16_t sci_int
; /* System vector of SCI interrupt */
336 uint32_t smi_cmd
; /* Port address of SMI command port */
337 uint8_t acpi_enable
; /* Value to write to smi_cmd to enable ACPI */
338 uint8_t acpi_disable
; /* Value to write to smi_cmd to disable ACPI */
339 uint8_t S4bios_req
; /* Value to write to SMI CMD to enter S4BIOS state */
340 uint8_t reserved2
; /* Reserved - must be zero */
341 uint32_t pm1a_evt_blk
; /* Port address of Power Mgt 1a acpi_event Reg Blk */
342 uint32_t pm1b_evt_blk
; /* Port address of Power Mgt 1b acpi_event Reg Blk */
343 uint32_t pm1a_cnt_blk
; /* Port address of Power Mgt 1a Control Reg Blk */
344 uint32_t pm1b_cnt_blk
; /* Port address of Power Mgt 1b Control Reg Blk */
345 uint32_t pm2_cnt_blk
; /* Port address of Power Mgt 2 Control Reg Blk */
346 uint32_t pm_tmr_blk
; /* Port address of Power Mgt Timer Ctrl Reg Blk */
347 uint32_t gpe0_blk
; /* Port addr of General Purpose acpi_event 0 Reg Blk */
348 uint32_t gpe1_blk
; /* Port addr of General Purpose acpi_event 1 Reg Blk */
349 uint8_t pm1_evt_len
; /* Byte length of ports at pm1_x_evt_blk */
350 uint8_t pm1_cnt_len
; /* Byte length of ports at pm1_x_cnt_blk */
351 uint8_t pm2_cnt_len
; /* Byte Length of ports at pm2_cnt_blk */
352 uint8_t pm_tmr_len
; /* Byte Length of ports at pm_tm_blk */
353 uint8_t gpe0_blk_len
; /* Byte Length of ports at gpe0_blk */
354 uint8_t gpe1_blk_len
; /* Byte Length of ports at gpe1_blk */
355 uint8_t gpe1_base
; /* Offset in gpe model where gpe1 events start */
356 uint8_t reserved3
; /* Reserved */
357 uint16_t plvl2_lat
; /* Worst case HW latency to enter/exit C2 state */
358 uint16_t plvl3_lat
; /* Worst case HW latency to enter/exit C3 state */
359 uint16_t flush_size
; /* Size of area read to flush caches */
360 uint16_t flush_stride
; /* Stride used in flushing caches */
361 uint8_t duty_offset
; /* Bit location of duty cycle field in p_cnt reg */
362 uint8_t duty_width
; /* Bit width of duty cycle field in p_cnt reg */
363 uint8_t day_alrm
; /* Index to day-of-month alarm in RTC CMOS RAM */
364 uint8_t mon_alrm
; /* Index to month-of-year alarm in RTC CMOS RAM */
365 uint8_t century
; /* Index to century in RTC CMOS RAM */
366 uint8_t reserved4
; /* Reserved */
367 uint8_t reserved4a
; /* Reserved */
368 uint8_t reserved4b
; /* Reserved */
370 uint32_t wb_invd
: 1; /* The wbinvd instruction works properly */
371 uint32_t wb_invd_flush
: 1; /* The wbinvd flushes but does not invalidate */
372 uint32_t proc_c1
: 1; /* All processors support C1 state */
373 uint32_t plvl2_up
: 1; /* C2 state works on MP system */
374 uint32_t pwr_button
: 1; /* Power button is handled as a generic feature */
375 uint32_t sleep_button
: 1; /* Sleep button is handled as a generic feature, or not present */
376 uint32_t fixed_rTC
: 1; /* RTC wakeup stat not in fixed register space */
377 uint32_t rtcs4
: 1; /* RTC wakeup stat not possible from S4 */
378 uint32_t tmr_val_ext
: 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
379 uint32_t reserved5
: 23; /* Reserved - must be zero */
386 * MADT values and structures
389 /* Values for MADT PCATCompat */
392 #define MULTIPLE_APIC 1
397 struct multiple_apic_table
399 ACPI_TABLE_HEADER_DEF
/* ACPI common table header */
400 uint32_t local_apic_address
; /* Physical address of local APIC */
402 uint32_t PCATcompat
: 1; /* A one indicates system also has dual 8259s */
403 uint32_t reserved1
: 31;
410 /* Values for Type in APIC_HEADER_DEF */
412 #define APIC_PROCESSOR 0
414 #define APIC_XRUPT_OVERRIDE 2
416 #define APIC_LOCAL_NMI 4
417 #define APIC_ADDRESS_OVERRIDE 5
418 #define APIC_IO_SAPIC 6
419 #define APIC_LOCAL_SAPIC 7
420 #define APIC_XRUPT_SOURCE 8
421 #define APIC_RESERVED 9 /* 9 and greater are reserved */
424 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
426 #define APIC_HEADER_DEF /* Common APIC sub-structure header */\
430 /* Sub-structures for MADT */
432 struct madt_processor_apic
435 uint8_t processor_id
; /* ACPI processor id */
436 uint8_t local_apic_id
; /* Processor's local APIC id */
438 uint32_t processor_enabled
: 1; /* Processor is usable if set */
439 uint32_t reserved2
: 31; /* Reserved, must be zero */
448 uint8_t io_apic_id
; /* I/O APIC ID */
449 uint8_t reserved
; /* Reserved - must be zero */
450 uint32_t address
; /* APIC physical address */
451 uint32_t interrupt
; /* Global system interrupt where INTI
455 #include "acpi-dsdt.hex"
457 static int acpi_checksum(const uint8_t *data
, int len
)
461 for(i
= 0; i
< len
; i
++)
463 return (-sum
) & 0xff;
466 static void acpi_build_table_header(struct acpi_table_header
*h
,
469 memcpy(h
->signature
, sig
, 4);
470 h
->length
= cpu_to_le32(len
);
472 memcpy(h
->oem_id
, "QEMU ", 6);
473 memcpy(h
->oem_table_id
, "QEMU", 4);
474 memcpy(h
->oem_table_id
+ 4, sig
, 4);
475 h
->oem_revision
= cpu_to_le32(1);
476 memcpy(h
->asl_compiler_id
, "QEMU", 4);
477 h
->asl_compiler_revision
= cpu_to_le32(1);
478 h
->checksum
= acpi_checksum((void *)h
, len
);
481 #define ACPI_TABLES_BASE 0x000e8000
483 /* base_addr must be a multiple of 4KB */
484 void acpi_bios_init(void)
486 struct rsdp_descriptor
*rsdp
;
487 struct rsdt_descriptor_rev1
*rsdt
;
488 struct fadt_descriptor_rev1
*fadt
;
489 struct facs_descriptor_rev1
*facs
;
490 struct multiple_apic_table
*madt
;
492 uint32_t base_addr
, rsdt_addr
, fadt_addr
, addr
, facs_addr
, dsdt_addr
;
493 uint32_t pm_io_base
, acpi_tables_size
, madt_addr
, madt_size
;
496 /* compute PCI I/O addresses */
497 pm_io_base
= (piix4_pm_state
->dev
.config
[0x40] |
498 (piix4_pm_state
->dev
.config
[0x41] << 8)) & ~0x3f;
500 base_addr
= ACPI_TABLES_BASE
;
502 /* reserve memory space for tables */
504 rsdp
= (void *)(phys_ram_base
+ addr
);
505 addr
+= sizeof(*rsdp
);
508 rsdt
= (void *)(phys_ram_base
+ addr
);
509 addr
+= sizeof(*rsdt
);
512 fadt
= (void *)(phys_ram_base
+ addr
);
513 addr
+= sizeof(*fadt
);
515 /* XXX: FACS should be in RAM */
516 addr
= (addr
+ 63) & ~63; /* 64 byte alignment for FACS */
518 facs
= (void *)(phys_ram_base
+ addr
);
519 addr
+= sizeof(*facs
);
522 dsdt
= (void *)(phys_ram_base
+ addr
);
523 addr
+= sizeof(AmlCode
);
526 madt_size
= sizeof(*madt
) +
527 sizeof(struct madt_processor_apic
) * smp_cpus
+
528 sizeof(struct madt_io_apic
);
529 madt
= (void *)(phys_ram_base
+ addr
);
532 acpi_tables_size
= addr
- base_addr
;
534 cpu_register_physical_memory(base_addr
, acpi_tables_size
,
535 base_addr
| IO_MEM_ROM
);
538 memset(rsdp
, 0, sizeof(*rsdp
));
539 memcpy(rsdp
->signature
, "RSD PTR ", 8);
540 memcpy(rsdp
->oem_id
, "QEMU ", 6);
541 rsdp
->rsdt_physical_address
= cpu_to_le32(rsdt_addr
);
542 rsdp
->checksum
= acpi_checksum((void *)rsdp
, 20);
545 rsdt
->table_offset_entry
[0] = cpu_to_le32(fadt_addr
);
546 rsdt
->table_offset_entry
[1] = cpu_to_le32(madt_addr
);
547 acpi_build_table_header((struct acpi_table_header
*)rsdt
,
548 "RSDT", sizeof(*rsdt
));
551 memset(fadt
, 0, sizeof(*fadt
));
552 fadt
->firmware_ctrl
= cpu_to_le32(facs_addr
);
553 fadt
->dsdt
= cpu_to_le32(dsdt_addr
);
556 fadt
->sci_int
= cpu_to_le16(piix4_pm_state
->dev
.config
[0x3c]);
557 fadt
->smi_cmd
= cpu_to_le32(SMI_CMD_IO_ADDR
);
558 fadt
->acpi_enable
= 0xf1;
559 fadt
->acpi_disable
= 0xf0;
560 fadt
->pm1a_evt_blk
= cpu_to_le32(pm_io_base
);
561 fadt
->pm1a_cnt_blk
= cpu_to_le32(pm_io_base
+ 0x04);
562 fadt
->pm_tmr_blk
= cpu_to_le32(pm_io_base
+ 0x08);
563 fadt
->pm1_evt_len
= 4;
564 fadt
->pm1_cnt_len
= 2;
565 fadt
->pm_tmr_len
= 4;
566 fadt
->plvl2_lat
= cpu_to_le16(50);
567 fadt
->plvl3_lat
= cpu_to_le16(50);
568 fadt
->plvl3_lat
= cpu_to_le16(50);
569 /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
570 fadt
->flags
= cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
571 acpi_build_table_header((struct acpi_table_header
*)fadt
, "FACP",
575 memset(facs
, 0, sizeof(*facs
));
576 memcpy(facs
->signature
, "FACS", 4);
577 facs
->length
= cpu_to_le32(sizeof(*facs
));
580 memcpy(dsdt
, AmlCode
, sizeof(AmlCode
));
584 struct madt_processor_apic
*apic
;
585 struct madt_io_apic
*io_apic
;
587 memset(madt
, 0, madt_size
);
588 madt
->local_apic_address
= cpu_to_le32(0xfee00000);
589 madt
->flags
= cpu_to_le32(1);
590 apic
= (void *)(madt
+ 1);
591 for(i
=0;i
<smp_cpus
;i
++) {
592 apic
->type
= APIC_PROCESSOR
;
593 apic
->length
= sizeof(*apic
);
594 apic
->processor_id
= i
;
595 apic
->local_apic_id
= i
;
596 apic
->flags
= cpu_to_le32(1);
599 io_apic
= (void *)apic
;
600 io_apic
->type
= APIC_IO
;
601 io_apic
->length
= sizeof(*io_apic
);
602 io_apic
->io_apic_id
= smp_cpus
;
603 io_apic
->address
= cpu_to_le32(0xfec00000);
604 io_apic
->interrupt
= cpu_to_le32(0);
606 acpi_build_table_header((struct acpi_table_header
*)madt
,