4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 /* i82731AB (PIIX4) compatible power management function */
24 #define PM_FREQ 3579545
26 /* XXX: make them variable */
27 #define PM_IO_BASE 0xb000
28 #define SMI_CMD_IO_ADDR 0xb040
29 #define ACPI_DBG_IO_ADDR 0xb044
31 typedef struct PIIX4PMState
{
37 int64_t tmr_overflow_time
;
40 #define RTC_EN (1 << 10)
41 #define PWRBTN_EN (1 << 8)
42 #define GBL_EN (1 << 5)
43 #define TMROF_EN (1 << 0)
45 #define SCI_EN (1 << 0)
47 #define SUS_EN (1 << 13)
49 /* Note: only used for ACPI bios init. Could be deleted when ACPI init
50 is integrated in Bochs BIOS */
51 static PIIX4PMState
*piix4_pm_state
;
53 static uint32_t get_pmtmr(PIIX4PMState
*s
)
56 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
60 static int get_pmsts(PIIX4PMState
*s
)
65 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
66 if (d
>= s
->tmr_overflow_time
)
71 static void pm_update_sci(PIIX4PMState
*s
)
77 sci_level
= (((pmsts
& s
->pmen
) &
78 (RTC_EN
| PWRBTN_EN
| GBL_EN
| TMROF_EN
)) != 0);
79 pci_set_irq(&s
->dev
, 0, sci_level
);
80 /* schedule a timer interruption if needed */
81 if ((s
->pmen
& TMROF_EN
) && !(pmsts
& TMROF_EN
)) {
82 expire_time
= muldiv64(s
->tmr_overflow_time
, ticks_per_sec
, PM_FREQ
);
83 qemu_mod_timer(s
->tmr_timer
, expire_time
);
85 qemu_del_timer(s
->tmr_timer
);
89 static void pm_tmr_timer(void *opaque
)
91 PIIX4PMState
*s
= opaque
;
95 static void pm_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
97 PIIX4PMState
*s
= opaque
;
104 pmsts
= get_pmsts(s
);
105 if (pmsts
& val
& TMROF_EN
) {
106 /* if TMRSTS is reset, then compute the new overflow time */
107 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
108 s
->tmr_overflow_time
= (d
+ 0x800000LL
) & ~0x7fffffLL
;
121 s
->pmcntrl
= val
& ~(SUS_EN
);
123 /* change suspend type */
124 sus_typ
= (val
>> 10) & 3;
126 case 0: /* soft power off */
127 qemu_system_shutdown_request();
139 printf("PM writew port=0x%04x val=0x%04x\n", addr
, val
);
143 static uint32_t pm_ioport_readw(void *opaque
, uint32_t addr
)
145 PIIX4PMState
*s
= opaque
;
164 printf("PM readw port=0x%04x val=0x%04x\n", addr
, val
);
169 static void pm_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
171 // PIIX4PMState *s = opaque;
174 printf("PM writel port=0x%04x val=0x%08x\n", addr
, val
);
178 static uint32_t pm_ioport_readl(void *opaque
, uint32_t addr
)
180 PIIX4PMState
*s
= opaque
;
193 printf("PM readl port=0x%04x val=0x%08x\n", addr
, val
);
198 static void smi_cmd_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
200 PIIX4PMState
*s
= opaque
;
202 printf("SMI cmd val=0x%02x\n", val
);
205 case 0xf0: /* ACPI disable */
206 s
->pmcntrl
&= ~SCI_EN
;
208 case 0xf1: /* ACPI enable */
209 s
->pmcntrl
|= SCI_EN
;
214 static void acpi_dbg_writel(void *opaque
, uint32_t addr
, uint32_t val
)
217 printf("ACPI: DBG: 0x%08x\n", val
);
221 /* XXX: we still add it to the PIIX3 and we count on the fact that
222 OSes are smart enough to accept this strange configuration */
223 void piix4_pm_init(PCIBus
*bus
, int devfn
)
229 s
= (PIIX4PMState
*)pci_register_device(bus
,
230 "PM", sizeof(PIIX4PMState
),
232 pci_conf
= s
->dev
.config
;
233 pci_conf
[0x00] = 0x86;
234 pci_conf
[0x01] = 0x80;
235 pci_conf
[0x02] = 0x13;
236 pci_conf
[0x03] = 0x71;
237 pci_conf
[0x08] = 0x00; // revision number
238 pci_conf
[0x09] = 0x00;
239 pci_conf
[0x0a] = 0x80; // other bridge device
240 pci_conf
[0x0b] = 0x06; // bridge device
241 pci_conf
[0x0e] = 0x00; // header_type
242 pci_conf
[0x3d] = 0x01; // interrupt pin 1
244 pm_io_base
= PM_IO_BASE
;
245 pci_conf
[0x40] = pm_io_base
| 1;
246 pci_conf
[0x41] = pm_io_base
>> 8;
247 register_ioport_write(pm_io_base
, 64, 2, pm_ioport_writew
, s
);
248 register_ioport_read(pm_io_base
, 64, 2, pm_ioport_readw
, s
);
249 register_ioport_write(pm_io_base
, 64, 4, pm_ioport_writel
, s
);
250 register_ioport_read(pm_io_base
, 64, 4, pm_ioport_readl
, s
);
252 register_ioport_write(SMI_CMD_IO_ADDR
, 1, 1, smi_cmd_writeb
, s
);
253 register_ioport_write(ACPI_DBG_IO_ADDR
, 4, 4, acpi_dbg_writel
, s
);
255 /* XXX: which specification is used ? The i82731AB has different
257 pci_conf
[0x5f] = (parallel_hds
[0] != NULL
? 0x80 : 0) | 0x10;
258 pci_conf
[0x63] = 0x60;
259 pci_conf
[0x67] = (serial_hds
[0] != NULL
? 0x08 : 0) |
260 (serial_hds
[1] != NULL
? 0x90 : 0);
262 s
->tmr_timer
= qemu_new_timer(vm_clock
, pm_tmr_timer
, s
);
267 /* XXX: move them in the Bochs BIOS ? */
269 /*************************************************/
271 /* Table structure from Linux kernel (the ACPI tables are under the
274 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
275 uint8_t signature [4]; /* ACPI signature (4 ASCII characters) */\
276 uint32_t length; /* Length of table, in bytes, including header */\
277 uint8_t revision; /* ACPI Specification minor version # */\
278 uint8_t checksum; /* To make sum of entire table == 0 */\
279 uint8_t oem_id [6]; /* OEM identification */\
280 uint8_t oem_table_id [8]; /* OEM table identification */\
281 uint32_t oem_revision; /* OEM revision number */\
282 uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */\
283 uint32_t asl_compiler_revision; /* ASL compiler revision number */
286 struct acpi_table_header
/* ACPI common table header */
288 ACPI_TABLE_HEADER_DEF
291 struct rsdp_descriptor
/* Root System Descriptor Pointer */
293 uint8_t signature
[8]; /* ACPI signature, contains "RSD PTR " */
294 uint8_t checksum
; /* To make sum of struct == 0 */
295 uint8_t oem_id
[6]; /* OEM identification */
296 uint8_t revision
; /* Must be 0 for 1.0, 2 for 2.0 */
297 uint32_t rsdt_physical_address
; /* 32-bit physical address of RSDT */
298 uint32_t length
; /* XSDT Length in bytes including hdr */
299 uint64_t xsdt_physical_address
; /* 64-bit physical address of XSDT */
300 uint8_t extended_checksum
; /* Checksum of entire table */
301 uint8_t reserved
[3]; /* Reserved field must be 0 */
305 * ACPI 1.0 Root System Description Table (RSDT)
307 struct rsdt_descriptor_rev1
309 ACPI_TABLE_HEADER_DEF
/* ACPI common table header */
310 uint32_t table_offset_entry
[2]; /* Array of pointers to other */
315 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
317 struct facs_descriptor_rev1
319 uint8_t signature
[4]; /* ACPI Signature */
320 uint32_t length
; /* Length of structure, in bytes */
321 uint32_t hardware_signature
; /* Hardware configuration signature */
322 uint32_t firmware_waking_vector
; /* ACPI OS waking vector */
323 uint32_t global_lock
; /* Global Lock */
324 uint32_t S4bios_f
: 1; /* Indicates if S4BIOS support is present */
325 uint32_t reserved1
: 31; /* Must be 0 */
326 uint8_t resverved3
[40]; /* Reserved - must be zero */
331 * ACPI 1.0 Fixed ACPI Description Table (FADT)
333 struct fadt_descriptor_rev1
335 ACPI_TABLE_HEADER_DEF
/* ACPI common table header */
336 uint32_t firmware_ctrl
; /* Physical address of FACS */
337 uint32_t dsdt
; /* Physical address of DSDT */
338 uint8_t model
; /* System Interrupt Model */
339 uint8_t reserved1
; /* Reserved */
340 uint16_t sci_int
; /* System vector of SCI interrupt */
341 uint32_t smi_cmd
; /* Port address of SMI command port */
342 uint8_t acpi_enable
; /* Value to write to smi_cmd to enable ACPI */
343 uint8_t acpi_disable
; /* Value to write to smi_cmd to disable ACPI */
344 uint8_t S4bios_req
; /* Value to write to SMI CMD to enter S4BIOS state */
345 uint8_t reserved2
; /* Reserved - must be zero */
346 uint32_t pm1a_evt_blk
; /* Port address of Power Mgt 1a acpi_event Reg Blk */
347 uint32_t pm1b_evt_blk
; /* Port address of Power Mgt 1b acpi_event Reg Blk */
348 uint32_t pm1a_cnt_blk
; /* Port address of Power Mgt 1a Control Reg Blk */
349 uint32_t pm1b_cnt_blk
; /* Port address of Power Mgt 1b Control Reg Blk */
350 uint32_t pm2_cnt_blk
; /* Port address of Power Mgt 2 Control Reg Blk */
351 uint32_t pm_tmr_blk
; /* Port address of Power Mgt Timer Ctrl Reg Blk */
352 uint32_t gpe0_blk
; /* Port addr of General Purpose acpi_event 0 Reg Blk */
353 uint32_t gpe1_blk
; /* Port addr of General Purpose acpi_event 1 Reg Blk */
354 uint8_t pm1_evt_len
; /* Byte length of ports at pm1_x_evt_blk */
355 uint8_t pm1_cnt_len
; /* Byte length of ports at pm1_x_cnt_blk */
356 uint8_t pm2_cnt_len
; /* Byte Length of ports at pm2_cnt_blk */
357 uint8_t pm_tmr_len
; /* Byte Length of ports at pm_tm_blk */
358 uint8_t gpe0_blk_len
; /* Byte Length of ports at gpe0_blk */
359 uint8_t gpe1_blk_len
; /* Byte Length of ports at gpe1_blk */
360 uint8_t gpe1_base
; /* Offset in gpe model where gpe1 events start */
361 uint8_t reserved3
; /* Reserved */
362 uint16_t plvl2_lat
; /* Worst case HW latency to enter/exit C2 state */
363 uint16_t plvl3_lat
; /* Worst case HW latency to enter/exit C3 state */
364 uint16_t flush_size
; /* Size of area read to flush caches */
365 uint16_t flush_stride
; /* Stride used in flushing caches */
366 uint8_t duty_offset
; /* Bit location of duty cycle field in p_cnt reg */
367 uint8_t duty_width
; /* Bit width of duty cycle field in p_cnt reg */
368 uint8_t day_alrm
; /* Index to day-of-month alarm in RTC CMOS RAM */
369 uint8_t mon_alrm
; /* Index to month-of-year alarm in RTC CMOS RAM */
370 uint8_t century
; /* Index to century in RTC CMOS RAM */
371 uint8_t reserved4
; /* Reserved */
372 uint8_t reserved4a
; /* Reserved */
373 uint8_t reserved4b
; /* Reserved */
375 uint32_t wb_invd
: 1; /* The wbinvd instruction works properly */
376 uint32_t wb_invd_flush
: 1; /* The wbinvd flushes but does not invalidate */
377 uint32_t proc_c1
: 1; /* All processors support C1 state */
378 uint32_t plvl2_up
: 1; /* C2 state works on MP system */
379 uint32_t pwr_button
: 1; /* Power button is handled as a generic feature */
380 uint32_t sleep_button
: 1; /* Sleep button is handled as a generic feature, or not present */
381 uint32_t fixed_rTC
: 1; /* RTC wakeup stat not in fixed register space */
382 uint32_t rtcs4
: 1; /* RTC wakeup stat not possible from S4 */
383 uint32_t tmr_val_ext
: 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
384 uint32_t reserved5
: 23; /* Reserved - must be zero */
391 * MADT values and structures
394 /* Values for MADT PCATCompat */
397 #define MULTIPLE_APIC 1
402 struct multiple_apic_table
404 ACPI_TABLE_HEADER_DEF
/* ACPI common table header */
405 uint32_t local_apic_address
; /* Physical address of local APIC */
407 uint32_t PCATcompat
: 1; /* A one indicates system also has dual 8259s */
408 uint32_t reserved1
: 31;
415 /* Values for Type in APIC_HEADER_DEF */
417 #define APIC_PROCESSOR 0
419 #define APIC_XRUPT_OVERRIDE 2
421 #define APIC_LOCAL_NMI 4
422 #define APIC_ADDRESS_OVERRIDE 5
423 #define APIC_IO_SAPIC 6
424 #define APIC_LOCAL_SAPIC 7
425 #define APIC_XRUPT_SOURCE 8
426 #define APIC_RESERVED 9 /* 9 and greater are reserved */
429 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
431 #define APIC_HEADER_DEF /* Common APIC sub-structure header */\
435 /* Sub-structures for MADT */
437 struct madt_processor_apic
440 uint8_t processor_id
; /* ACPI processor id */
441 uint8_t local_apic_id
; /* Processor's local APIC id */
443 uint32_t processor_enabled
: 1; /* Processor is usable if set */
444 uint32_t reserved2
: 31; /* Reserved, must be zero */
453 uint8_t io_apic_id
; /* I/O APIC ID */
454 uint8_t reserved
; /* Reserved - must be zero */
455 uint32_t address
; /* APIC physical address */
456 uint32_t interrupt
; /* Global system interrupt where INTI
460 #include "acpi-dsdt.hex"
462 static int acpi_checksum(const uint8_t *data
, int len
)
466 for(i
= 0; i
< len
; i
++)
468 return (-sum
) & 0xff;
471 static void acpi_build_table_header(struct acpi_table_header
*h
,
474 memcpy(h
->signature
, sig
, 4);
475 h
->length
= cpu_to_le32(len
);
477 memcpy(h
->oem_id
, "QEMU ", 6);
478 memcpy(h
->oem_table_id
, "QEMU", 4);
479 memcpy(h
->oem_table_id
+ 4, sig
, 4);
480 h
->oem_revision
= cpu_to_le32(1);
481 memcpy(h
->asl_compiler_id
, "QEMU", 4);
482 h
->asl_compiler_revision
= cpu_to_le32(1);
483 h
->checksum
= acpi_checksum((void *)h
, len
);
486 #define ACPI_TABLES_BASE 0x000e8000
488 /* base_addr must be a multiple of 4KB */
489 void acpi_bios_init(void)
491 struct rsdp_descriptor
*rsdp
;
492 struct rsdt_descriptor_rev1
*rsdt
;
493 struct fadt_descriptor_rev1
*fadt
;
494 struct facs_descriptor_rev1
*facs
;
495 struct multiple_apic_table
*madt
;
497 uint32_t base_addr
, rsdt_addr
, fadt_addr
, addr
, facs_addr
, dsdt_addr
;
498 uint32_t pm_io_base
, acpi_tables_size
, madt_addr
, madt_size
;
501 /* compute PCI I/O addresses */
502 pm_io_base
= (piix4_pm_state
->dev
.config
[0x40] |
503 (piix4_pm_state
->dev
.config
[0x41] << 8)) & ~0x3f;
505 base_addr
= ACPI_TABLES_BASE
;
507 /* reserve memory space for tables */
509 rsdp
= (void *)(phys_ram_base
+ addr
);
510 addr
+= sizeof(*rsdp
);
513 rsdt
= (void *)(phys_ram_base
+ addr
);
514 addr
+= sizeof(*rsdt
);
517 fadt
= (void *)(phys_ram_base
+ addr
);
518 addr
+= sizeof(*fadt
);
520 /* XXX: FACS should be in RAM */
521 addr
= (addr
+ 63) & ~63; /* 64 byte alignment for FACS */
523 facs
= (void *)(phys_ram_base
+ addr
);
524 addr
+= sizeof(*facs
);
527 dsdt
= (void *)(phys_ram_base
+ addr
);
528 addr
+= sizeof(AmlCode
);
530 addr
= (addr
+ 7) & ~7;
532 madt_size
= sizeof(*madt
) +
533 sizeof(struct madt_processor_apic
) * smp_cpus
+
534 sizeof(struct madt_io_apic
);
535 madt
= (void *)(phys_ram_base
+ addr
);
538 acpi_tables_size
= addr
- base_addr
;
540 cpu_register_physical_memory(base_addr
, acpi_tables_size
,
541 base_addr
| IO_MEM_ROM
);
544 memset(rsdp
, 0, sizeof(*rsdp
));
545 memcpy(rsdp
->signature
, "RSD PTR ", 8);
546 memcpy(rsdp
->oem_id
, "QEMU ", 6);
547 rsdp
->rsdt_physical_address
= cpu_to_le32(rsdt_addr
);
548 rsdp
->checksum
= acpi_checksum((void *)rsdp
, 20);
551 rsdt
->table_offset_entry
[0] = cpu_to_le32(fadt_addr
);
552 rsdt
->table_offset_entry
[1] = cpu_to_le32(madt_addr
);
553 acpi_build_table_header((struct acpi_table_header
*)rsdt
,
554 "RSDT", sizeof(*rsdt
));
557 memset(fadt
, 0, sizeof(*fadt
));
558 fadt
->firmware_ctrl
= cpu_to_le32(facs_addr
);
559 fadt
->dsdt
= cpu_to_le32(dsdt_addr
);
562 fadt
->sci_int
= cpu_to_le16(piix4_pm_state
->dev
.config
[0x3c]);
563 fadt
->smi_cmd
= cpu_to_le32(SMI_CMD_IO_ADDR
);
564 fadt
->acpi_enable
= 0xf1;
565 fadt
->acpi_disable
= 0xf0;
566 fadt
->pm1a_evt_blk
= cpu_to_le32(pm_io_base
);
567 fadt
->pm1a_cnt_blk
= cpu_to_le32(pm_io_base
+ 0x04);
568 fadt
->pm_tmr_blk
= cpu_to_le32(pm_io_base
+ 0x08);
569 fadt
->pm1_evt_len
= 4;
570 fadt
->pm1_cnt_len
= 2;
571 fadt
->pm_tmr_len
= 4;
572 fadt
->plvl2_lat
= cpu_to_le16(50);
573 fadt
->plvl3_lat
= cpu_to_le16(50);
574 fadt
->plvl3_lat
= cpu_to_le16(50);
575 /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
576 fadt
->flags
= cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
577 acpi_build_table_header((struct acpi_table_header
*)fadt
, "FACP",
581 memset(facs
, 0, sizeof(*facs
));
582 memcpy(facs
->signature
, "FACS", 4);
583 facs
->length
= cpu_to_le32(sizeof(*facs
));
586 memcpy(dsdt
, AmlCode
, sizeof(AmlCode
));
590 struct madt_processor_apic
*apic
;
591 struct madt_io_apic
*io_apic
;
593 memset(madt
, 0, madt_size
);
594 madt
->local_apic_address
= cpu_to_le32(0xfee00000);
595 madt
->flags
= cpu_to_le32(1);
596 apic
= (void *)(madt
+ 1);
597 for(i
=0;i
<smp_cpus
;i
++) {
598 apic
->type
= APIC_PROCESSOR
;
599 apic
->length
= sizeof(*apic
);
600 apic
->processor_id
= i
;
601 apic
->local_apic_id
= i
;
602 apic
->flags
= cpu_to_le32(1);
605 io_apic
= (void *)apic
;
606 io_apic
->type
= APIC_IO
;
607 io_apic
->length
= sizeof(*io_apic
);
608 io_apic
->io_apic_id
= smp_cpus
;
609 io_apic
->address
= cpu_to_le32(0xfec00000);
610 io_apic
->interrupt
= cpu_to_le32(0);
612 acpi_build_table_header((struct acpi_table_header
*)madt
,