4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
22 #include "qemu-common.h"
27 #include "host-utils.h"
33 #ifdef CONFIG_KVM_PARA
34 #include <linux/kvm_para.h>
40 #define DPRINTF(fmt, ...) \
41 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
43 #define DPRINTF(fmt, ...) \
47 #define MSR_KVM_WALL_CLOCK 0x11
48 #define MSR_KVM_SYSTEM_TIME 0x12
51 #define BUS_MCEERR_AR 4
54 #define BUS_MCEERR_AO 5
57 static bool has_msr_star
;
58 static bool has_msr_hsave_pa
;
59 static int lm_capable_kernel
;
61 #ifdef KVM_CAP_EXT_CPUID
63 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
65 struct kvm_cpuid2
*cpuid
;
68 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
69 cpuid
= (struct kvm_cpuid2
*)qemu_mallocz(size
);
71 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
72 if (r
== 0 && cpuid
->nent
>= max
) {
80 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
88 uint32_t kvm_arch_get_supported_cpuid(CPUState
*env
, uint32_t function
,
89 uint32_t index
, int reg
)
91 struct kvm_cpuid2
*cpuid
;
96 if (!kvm_check_extension(env
->kvm_state
, KVM_CAP_EXT_CPUID
)) {
101 while ((cpuid
= try_get_cpuid(env
->kvm_state
, max
)) == NULL
) {
105 for (i
= 0; i
< cpuid
->nent
; ++i
) {
106 if (cpuid
->entries
[i
].function
== function
&&
107 cpuid
->entries
[i
].index
== index
) {
110 ret
= cpuid
->entries
[i
].eax
;
113 ret
= cpuid
->entries
[i
].ebx
;
116 ret
= cpuid
->entries
[i
].ecx
;
119 ret
= cpuid
->entries
[i
].edx
;
122 /* KVM before 2.6.30 misreports the following features */
123 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
126 /* On Intel, kvm returns cpuid according to the Intel spec,
127 * so add missing bits according to the AMD spec:
129 cpuid_1_edx
= kvm_arch_get_supported_cpuid(env
, 1, 0, R_EDX
);
130 ret
|= cpuid_1_edx
& 0x183f7ff;
145 uint32_t kvm_arch_get_supported_cpuid(CPUState
*env
, uint32_t function
,
146 uint32_t index
, int reg
)
153 #ifdef CONFIG_KVM_PARA
154 struct kvm_para_features
{
157 } para_features
[] = {
158 #ifdef KVM_CAP_CLOCKSOURCE
159 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
161 #ifdef KVM_CAP_NOP_IO_DELAY
162 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
164 #ifdef KVM_CAP_PV_MMU
165 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
167 #ifdef KVM_CAP_ASYNC_PF
168 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
173 static int get_para_features(CPUState
*env
)
177 for (i
= 0; i
< ARRAY_SIZE(para_features
) - 1; i
++) {
178 if (kvm_check_extension(env
->kvm_state
, para_features
[i
].cap
)) {
179 features
|= (1 << para_features
[i
].feature
);
187 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
192 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
195 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
200 static int kvm_setup_mce(CPUState
*env
, uint64_t *mcg_cap
)
202 return kvm_vcpu_ioctl(env
, KVM_X86_SETUP_MCE
, mcg_cap
);
205 static int kvm_set_mce(CPUState
*env
, struct kvm_x86_mce
*m
)
207 return kvm_vcpu_ioctl(env
, KVM_X86_SET_MCE
, m
);
210 static int kvm_get_msr(CPUState
*env
, struct kvm_msr_entry
*msrs
, int n
)
212 struct kvm_msrs
*kmsrs
= qemu_malloc(sizeof *kmsrs
+ n
* sizeof *msrs
);
216 memcpy(kmsrs
->entries
, msrs
, n
* sizeof *msrs
);
217 r
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, kmsrs
);
218 memcpy(msrs
, kmsrs
->entries
, n
* sizeof *msrs
);
223 /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */
224 static int kvm_mce_in_progress(CPUState
*env
)
226 struct kvm_msr_entry msr_mcg_status
= {
227 .index
= MSR_MCG_STATUS
,
231 r
= kvm_get_msr(env
, &msr_mcg_status
, 1);
232 if (r
== -1 || r
== 0) {
233 fprintf(stderr
, "Failed to get MCE status\n");
236 return !!(msr_mcg_status
.data
& MCG_STATUS_MCIP
);
239 struct kvm_x86_mce_data
242 struct kvm_x86_mce
*mce
;
246 static void kvm_do_inject_x86_mce(void *_data
)
248 struct kvm_x86_mce_data
*data
= _data
;
251 /* If there is an MCE exception being processed, ignore this SRAO MCE */
252 if ((data
->env
->mcg_cap
& MCG_SER_P
) &&
253 !(data
->mce
->status
& MCI_STATUS_AR
)) {
254 if (kvm_mce_in_progress(data
->env
)) {
259 r
= kvm_set_mce(data
->env
, data
->mce
);
261 perror("kvm_set_mce FAILED");
262 if (data
->abort_on_error
) {
268 static void kvm_inject_x86_mce_on(CPUState
*env
, struct kvm_x86_mce
*mce
,
271 struct kvm_x86_mce_data data
= {
274 .abort_on_error
= (flag
& ABORT_ON_ERROR
),
278 fprintf(stderr
, "MCE support is not enabled!\n");
282 run_on_cpu(env
, kvm_do_inject_x86_mce
, &data
);
285 static void kvm_mce_broadcast_rest(CPUState
*env
);
288 void kvm_inject_x86_mce(CPUState
*cenv
, int bank
, uint64_t status
,
289 uint64_t mcg_status
, uint64_t addr
, uint64_t misc
,
293 struct kvm_x86_mce mce
= {
296 .mcg_status
= mcg_status
,
301 if (flag
& MCE_BROADCAST
) {
302 kvm_mce_broadcast_rest(cenv
);
305 kvm_inject_x86_mce_on(cenv
, &mce
, flag
);
307 if (flag
& ABORT_ON_ERROR
) {
313 int kvm_arch_init_vcpu(CPUState
*env
)
316 struct kvm_cpuid2 cpuid
;
317 struct kvm_cpuid_entry2 entries
[100];
318 } __attribute__((packed
)) cpuid_data
;
319 uint32_t limit
, i
, j
, cpuid_i
;
321 struct kvm_cpuid_entry2
*c
;
322 #ifdef KVM_CPUID_SIGNATURE
323 uint32_t signature
[3];
326 env
->cpuid_features
&= kvm_arch_get_supported_cpuid(env
, 1, 0, R_EDX
);
328 i
= env
->cpuid_ext_features
& CPUID_EXT_HYPERVISOR
;
329 env
->cpuid_ext_features
&= kvm_arch_get_supported_cpuid(env
, 1, 0, R_ECX
);
330 env
->cpuid_ext_features
|= i
;
332 env
->cpuid_ext2_features
&= kvm_arch_get_supported_cpuid(env
, 0x80000001,
334 env
->cpuid_ext3_features
&= kvm_arch_get_supported_cpuid(env
, 0x80000001,
336 env
->cpuid_svm_features
&= kvm_arch_get_supported_cpuid(env
, 0x8000000A,
342 #ifdef CONFIG_KVM_PARA
343 /* Paravirtualization CPUIDs */
344 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
345 c
= &cpuid_data
.entries
[cpuid_i
++];
346 memset(c
, 0, sizeof(*c
));
347 c
->function
= KVM_CPUID_SIGNATURE
;
349 c
->ebx
= signature
[0];
350 c
->ecx
= signature
[1];
351 c
->edx
= signature
[2];
353 c
= &cpuid_data
.entries
[cpuid_i
++];
354 memset(c
, 0, sizeof(*c
));
355 c
->function
= KVM_CPUID_FEATURES
;
356 c
->eax
= env
->cpuid_kvm_features
& get_para_features(env
);
359 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
361 for (i
= 0; i
<= limit
; i
++) {
362 c
= &cpuid_data
.entries
[cpuid_i
++];
366 /* Keep reading function 2 till all the input is received */
370 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
371 KVM_CPUID_FLAG_STATE_READ_NEXT
;
372 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
373 times
= c
->eax
& 0xff;
375 for (j
= 1; j
< times
; ++j
) {
376 c
= &cpuid_data
.entries
[cpuid_i
++];
378 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
379 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
388 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
390 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
392 if (i
== 4 && c
->eax
== 0) {
395 if (i
== 0xb && !(c
->ecx
& 0xff00)) {
398 if (i
== 0xd && c
->eax
== 0) {
401 c
= &cpuid_data
.entries
[cpuid_i
++];
407 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
411 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
413 for (i
= 0x80000000; i
<= limit
; i
++) {
414 c
= &cpuid_data
.entries
[cpuid_i
++];
418 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
421 cpuid_data
.cpuid
.nent
= cpuid_i
;
424 if (((env
->cpuid_version
>> 8)&0xF) >= 6
425 && (env
->cpuid_features
&(CPUID_MCE
|CPUID_MCA
)) == (CPUID_MCE
|CPUID_MCA
)
426 && kvm_check_extension(env
->kvm_state
, KVM_CAP_MCE
) > 0) {
430 if (kvm_get_mce_cap_supported(env
->kvm_state
, &mcg_cap
, &banks
)) {
431 perror("kvm_get_mce_cap_supported FAILED");
433 if (banks
> MCE_BANKS_DEF
)
434 banks
= MCE_BANKS_DEF
;
435 mcg_cap
&= MCE_CAP_DEF
;
437 if (kvm_setup_mce(env
, &mcg_cap
)) {
438 perror("kvm_setup_mce FAILED");
440 env
->mcg_cap
= mcg_cap
;
446 return kvm_vcpu_ioctl(env
, KVM_SET_CPUID2
, &cpuid_data
);
449 void kvm_arch_reset_vcpu(CPUState
*env
)
451 env
->exception_injected
= -1;
452 env
->interrupt_injected
= -1;
453 env
->nmi_injected
= 0;
454 env
->nmi_pending
= 0;
456 if (kvm_irqchip_in_kernel()) {
457 env
->mp_state
= cpu_is_bsp(env
) ? KVM_MP_STATE_RUNNABLE
:
458 KVM_MP_STATE_UNINITIALIZED
;
460 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
464 static int kvm_get_supported_msrs(KVMState
*s
)
466 static int kvm_supported_msrs
;
470 if (kvm_supported_msrs
== 0) {
471 struct kvm_msr_list msr_list
, *kvm_msr_list
;
473 kvm_supported_msrs
= -1;
475 /* Obtain MSR list from KVM. These are the MSRs that we must
478 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
479 if (ret
< 0 && ret
!= -E2BIG
) {
482 /* Old kernel modules had a bug and could write beyond the provided
483 memory. Allocate at least a safe amount of 1K. */
484 kvm_msr_list
= qemu_mallocz(MAX(1024, sizeof(msr_list
) +
486 sizeof(msr_list
.indices
[0])));
488 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
489 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
493 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
494 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
498 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
) {
499 has_msr_hsave_pa
= true;
511 static int kvm_init_identity_map_page(KVMState
*s
)
513 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
515 uint64_t addr
= 0xfffbc000;
517 if (!kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
521 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &addr
);
523 fprintf(stderr
, "kvm_set_identity_map_addr: %s\n", strerror(ret
));
530 int kvm_arch_init(KVMState
*s
, int smp_cpus
)
533 struct utsname utsname
;
535 ret
= kvm_get_supported_msrs(s
);
541 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
543 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
544 * directly. In order to use vm86 mode, a TSS is needed. Since this
545 * must be part of guest physical memory, we need to allocate it. Older
546 * versions of KVM just assumed that it would be at the end of physical
547 * memory but that doesn't work with more than 4GB of memory. We simply
548 * refuse to work with those older versions of KVM. */
549 ret
= kvm_check_extension(s
, KVM_CAP_SET_TSS_ADDR
);
551 fprintf(stderr
, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
555 /* this address is 3 pages before the bios, and the bios should present
556 * as unavaible memory. FIXME, need to ensure the e820 map deals with
560 * Tell fw_cfg to notify the BIOS to reserve the range.
562 if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED
) < 0) {
563 perror("e820_add_entry() table is full");
566 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, 0xfffbd000);
571 return kvm_init_identity_map_page(s
);
574 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
576 lhs
->selector
= rhs
->selector
;
577 lhs
->base
= rhs
->base
;
578 lhs
->limit
= rhs
->limit
;
590 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
592 unsigned flags
= rhs
->flags
;
593 lhs
->selector
= rhs
->selector
;
594 lhs
->base
= rhs
->base
;
595 lhs
->limit
= rhs
->limit
;
596 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
597 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
598 lhs
->dpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
599 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
600 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
601 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
602 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
603 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
607 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
609 lhs
->selector
= rhs
->selector
;
610 lhs
->base
= rhs
->base
;
611 lhs
->limit
= rhs
->limit
;
612 lhs
->flags
= (rhs
->type
<< DESC_TYPE_SHIFT
) |
613 (rhs
->present
* DESC_P_MASK
) |
614 (rhs
->dpl
<< DESC_DPL_SHIFT
) |
615 (rhs
->db
<< DESC_B_SHIFT
) |
616 (rhs
->s
* DESC_S_MASK
) |
617 (rhs
->l
<< DESC_L_SHIFT
) |
618 (rhs
->g
* DESC_G_MASK
) |
619 (rhs
->avl
* DESC_AVL_MASK
);
622 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
625 *kvm_reg
= *qemu_reg
;
627 *qemu_reg
= *kvm_reg
;
631 static int kvm_getput_regs(CPUState
*env
, int set
)
633 struct kvm_regs regs
;
637 ret
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
643 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
644 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
645 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
646 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
647 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
648 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
649 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
650 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
652 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
653 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
654 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
655 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
656 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
657 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
658 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
659 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
662 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
663 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
666 ret
= kvm_vcpu_ioctl(env
, KVM_SET_REGS
, ®s
);
672 static int kvm_put_fpu(CPUState
*env
)
677 memset(&fpu
, 0, sizeof fpu
);
678 fpu
.fsw
= env
->fpus
& ~(7 << 11);
679 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
681 for (i
= 0; i
< 8; ++i
) {
682 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
684 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
685 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
686 fpu
.mxcsr
= env
->mxcsr
;
688 return kvm_vcpu_ioctl(env
, KVM_SET_FPU
, &fpu
);
692 #define XSAVE_CWD_RIP 2
693 #define XSAVE_CWD_RDP 4
694 #define XSAVE_MXCSR 6
695 #define XSAVE_ST_SPACE 8
696 #define XSAVE_XMM_SPACE 40
697 #define XSAVE_XSTATE_BV 128
698 #define XSAVE_YMMH_SPACE 144
701 static int kvm_put_xsave(CPUState
*env
)
705 struct kvm_xsave
* xsave
;
706 uint16_t cwd
, swd
, twd
, fop
;
708 if (!kvm_has_xsave()) {
709 return kvm_put_fpu(env
);
712 xsave
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
713 memset(xsave
, 0, sizeof(struct kvm_xsave
));
714 cwd
= swd
= twd
= fop
= 0;
715 swd
= env
->fpus
& ~(7 << 11);
716 swd
|= (env
->fpstt
& 7) << 11;
718 for (i
= 0; i
< 8; ++i
) {
719 twd
|= (!env
->fptags
[i
]) << i
;
721 xsave
->region
[0] = (uint32_t)(swd
<< 16) + cwd
;
722 xsave
->region
[1] = (uint32_t)(fop
<< 16) + twd
;
723 memcpy(&xsave
->region
[XSAVE_ST_SPACE
], env
->fpregs
,
725 memcpy(&xsave
->region
[XSAVE_XMM_SPACE
], env
->xmm_regs
,
726 sizeof env
->xmm_regs
);
727 xsave
->region
[XSAVE_MXCSR
] = env
->mxcsr
;
728 *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
] = env
->xstate_bv
;
729 memcpy(&xsave
->region
[XSAVE_YMMH_SPACE
], env
->ymmh_regs
,
730 sizeof env
->ymmh_regs
);
731 r
= kvm_vcpu_ioctl(env
, KVM_SET_XSAVE
, xsave
);
735 return kvm_put_fpu(env
);
739 static int kvm_put_xcrs(CPUState
*env
)
742 struct kvm_xcrs xcrs
;
744 if (!kvm_has_xcrs()) {
750 xcrs
.xcrs
[0].xcr
= 0;
751 xcrs
.xcrs
[0].value
= env
->xcr0
;
752 return kvm_vcpu_ioctl(env
, KVM_SET_XCRS
, &xcrs
);
758 static int kvm_put_sregs(CPUState
*env
)
760 struct kvm_sregs sregs
;
762 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
763 if (env
->interrupt_injected
>= 0) {
764 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
765 (uint64_t)1 << (env
->interrupt_injected
% 64);
768 if ((env
->eflags
& VM_MASK
)) {
769 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
770 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
771 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
772 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
773 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
774 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
776 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
777 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
778 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
779 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
780 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
781 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
784 set_seg(&sregs
.tr
, &env
->tr
);
785 set_seg(&sregs
.ldt
, &env
->ldt
);
787 sregs
.idt
.limit
= env
->idt
.limit
;
788 sregs
.idt
.base
= env
->idt
.base
;
789 sregs
.gdt
.limit
= env
->gdt
.limit
;
790 sregs
.gdt
.base
= env
->gdt
.base
;
792 sregs
.cr0
= env
->cr
[0];
793 sregs
.cr2
= env
->cr
[2];
794 sregs
.cr3
= env
->cr
[3];
795 sregs
.cr4
= env
->cr
[4];
797 sregs
.cr8
= cpu_get_apic_tpr(env
->apic_state
);
798 sregs
.apic_base
= cpu_get_apic_base(env
->apic_state
);
800 sregs
.efer
= env
->efer
;
802 return kvm_vcpu_ioctl(env
, KVM_SET_SREGS
, &sregs
);
805 static void kvm_msr_entry_set(struct kvm_msr_entry
*entry
,
806 uint32_t index
, uint64_t value
)
808 entry
->index
= index
;
812 static int kvm_put_msrs(CPUState
*env
, int level
)
815 struct kvm_msrs info
;
816 struct kvm_msr_entry entries
[100];
818 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
821 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
822 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
823 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
825 kvm_msr_entry_set(&msrs
[n
++], MSR_STAR
, env
->star
);
827 if (has_msr_hsave_pa
) {
828 kvm_msr_entry_set(&msrs
[n
++], MSR_VM_HSAVE_PA
, env
->vm_hsave
);
831 if (lm_capable_kernel
) {
832 kvm_msr_entry_set(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
833 kvm_msr_entry_set(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
834 kvm_msr_entry_set(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
835 kvm_msr_entry_set(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
838 if (level
== KVM_PUT_FULL_STATE
) {
840 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
841 * writeback. Until this is fixed, we only write the offset to SMP
842 * guests after migration, desynchronizing the VCPUs, but avoiding
843 * huge jump-backs that would occur without any writeback at all.
845 if (smp_cpus
== 1 || env
->tsc
!= 0) {
846 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
850 * The following paravirtual MSRs have side effects on the guest or are
851 * too heavy for normal writeback. Limit them to reset or full state
854 if (level
>= KVM_PUT_RESET_STATE
) {
855 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_SYSTEM_TIME
,
856 env
->system_time_msr
);
857 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
858 #ifdef KVM_CAP_ASYNC_PF
859 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_ASYNC_PF_EN
, env
->async_pf_en_msr
);
866 if (level
== KVM_PUT_RESET_STATE
) {
867 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
868 } else if (level
== KVM_PUT_FULL_STATE
) {
869 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
870 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_CTL
, env
->mcg_ctl
);
871 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
872 kvm_msr_entry_set(&msrs
[n
++], MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
878 msr_data
.info
.nmsrs
= n
;
880 return kvm_vcpu_ioctl(env
, KVM_SET_MSRS
, &msr_data
);
885 static int kvm_get_fpu(CPUState
*env
)
890 ret
= kvm_vcpu_ioctl(env
, KVM_GET_FPU
, &fpu
);
895 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
898 for (i
= 0; i
< 8; ++i
) {
899 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
901 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
902 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
903 env
->mxcsr
= fpu
.mxcsr
;
908 static int kvm_get_xsave(CPUState
*env
)
911 struct kvm_xsave
* xsave
;
913 uint16_t cwd
, swd
, twd
, fop
;
915 if (!kvm_has_xsave()) {
916 return kvm_get_fpu(env
);
919 xsave
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
920 ret
= kvm_vcpu_ioctl(env
, KVM_GET_XSAVE
, xsave
);
926 cwd
= (uint16_t)xsave
->region
[0];
927 swd
= (uint16_t)(xsave
->region
[0] >> 16);
928 twd
= (uint16_t)xsave
->region
[1];
929 fop
= (uint16_t)(xsave
->region
[1] >> 16);
930 env
->fpstt
= (swd
>> 11) & 7;
933 for (i
= 0; i
< 8; ++i
) {
934 env
->fptags
[i
] = !((twd
>> i
) & 1);
936 env
->mxcsr
= xsave
->region
[XSAVE_MXCSR
];
937 memcpy(env
->fpregs
, &xsave
->region
[XSAVE_ST_SPACE
],
939 memcpy(env
->xmm_regs
, &xsave
->region
[XSAVE_XMM_SPACE
],
940 sizeof env
->xmm_regs
);
941 env
->xstate_bv
= *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
];
942 memcpy(env
->ymmh_regs
, &xsave
->region
[XSAVE_YMMH_SPACE
],
943 sizeof env
->ymmh_regs
);
947 return kvm_get_fpu(env
);
951 static int kvm_get_xcrs(CPUState
*env
)
955 struct kvm_xcrs xcrs
;
957 if (!kvm_has_xcrs()) {
961 ret
= kvm_vcpu_ioctl(env
, KVM_GET_XCRS
, &xcrs
);
966 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++) {
967 /* Only support xcr0 now */
968 if (xcrs
.xcrs
[0].xcr
== 0) {
969 env
->xcr0
= xcrs
.xcrs
[0].value
;
979 static int kvm_get_sregs(CPUState
*env
)
981 struct kvm_sregs sregs
;
985 ret
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
990 /* There can only be one pending IRQ set in the bitmap at a time, so try
991 to find it and save its number instead (-1 for none). */
992 env
->interrupt_injected
= -1;
993 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
994 if (sregs
.interrupt_bitmap
[i
]) {
995 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
996 env
->interrupt_injected
= i
* 64 + bit
;
1001 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
1002 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
1003 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
1004 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
1005 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
1006 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
1008 get_seg(&env
->tr
, &sregs
.tr
);
1009 get_seg(&env
->ldt
, &sregs
.ldt
);
1011 env
->idt
.limit
= sregs
.idt
.limit
;
1012 env
->idt
.base
= sregs
.idt
.base
;
1013 env
->gdt
.limit
= sregs
.gdt
.limit
;
1014 env
->gdt
.base
= sregs
.gdt
.base
;
1016 env
->cr
[0] = sregs
.cr0
;
1017 env
->cr
[2] = sregs
.cr2
;
1018 env
->cr
[3] = sregs
.cr3
;
1019 env
->cr
[4] = sregs
.cr4
;
1021 cpu_set_apic_base(env
->apic_state
, sregs
.apic_base
);
1023 env
->efer
= sregs
.efer
;
1024 //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1026 #define HFLAG_COPY_MASK \
1027 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1028 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1029 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1030 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1032 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
1033 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
1034 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
1035 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
1036 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
1037 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
1038 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
1040 if (env
->efer
& MSR_EFER_LMA
) {
1041 hflags
|= HF_LMA_MASK
;
1044 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
1045 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1047 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
1048 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1049 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
1050 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1051 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
1052 !(hflags
& HF_CS32_MASK
)) {
1053 hflags
|= HF_ADDSEG_MASK
;
1055 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
1056 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
1059 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
1064 static int kvm_get_msrs(CPUState
*env
)
1067 struct kvm_msrs info
;
1068 struct kvm_msr_entry entries
[100];
1070 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1074 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
1075 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
1076 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
1078 msrs
[n
++].index
= MSR_STAR
;
1080 if (has_msr_hsave_pa
) {
1081 msrs
[n
++].index
= MSR_VM_HSAVE_PA
;
1083 msrs
[n
++].index
= MSR_IA32_TSC
;
1084 #ifdef TARGET_X86_64
1085 if (lm_capable_kernel
) {
1086 msrs
[n
++].index
= MSR_CSTAR
;
1087 msrs
[n
++].index
= MSR_KERNELGSBASE
;
1088 msrs
[n
++].index
= MSR_FMASK
;
1089 msrs
[n
++].index
= MSR_LSTAR
;
1092 msrs
[n
++].index
= MSR_KVM_SYSTEM_TIME
;
1093 msrs
[n
++].index
= MSR_KVM_WALL_CLOCK
;
1094 #ifdef KVM_CAP_ASYNC_PF
1095 msrs
[n
++].index
= MSR_KVM_ASYNC_PF_EN
;
1100 msrs
[n
++].index
= MSR_MCG_STATUS
;
1101 msrs
[n
++].index
= MSR_MCG_CTL
;
1102 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1103 msrs
[n
++].index
= MSR_MC0_CTL
+ i
;
1108 msr_data
.info
.nmsrs
= n
;
1109 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, &msr_data
);
1114 for (i
= 0; i
< ret
; i
++) {
1115 switch (msrs
[i
].index
) {
1116 case MSR_IA32_SYSENTER_CS
:
1117 env
->sysenter_cs
= msrs
[i
].data
;
1119 case MSR_IA32_SYSENTER_ESP
:
1120 env
->sysenter_esp
= msrs
[i
].data
;
1122 case MSR_IA32_SYSENTER_EIP
:
1123 env
->sysenter_eip
= msrs
[i
].data
;
1126 env
->star
= msrs
[i
].data
;
1128 #ifdef TARGET_X86_64
1130 env
->cstar
= msrs
[i
].data
;
1132 case MSR_KERNELGSBASE
:
1133 env
->kernelgsbase
= msrs
[i
].data
;
1136 env
->fmask
= msrs
[i
].data
;
1139 env
->lstar
= msrs
[i
].data
;
1143 env
->tsc
= msrs
[i
].data
;
1145 case MSR_VM_HSAVE_PA
:
1146 env
->vm_hsave
= msrs
[i
].data
;
1148 case MSR_KVM_SYSTEM_TIME
:
1149 env
->system_time_msr
= msrs
[i
].data
;
1151 case MSR_KVM_WALL_CLOCK
:
1152 env
->wall_clock_msr
= msrs
[i
].data
;
1155 case MSR_MCG_STATUS
:
1156 env
->mcg_status
= msrs
[i
].data
;
1159 env
->mcg_ctl
= msrs
[i
].data
;
1164 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
1165 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
1166 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
1170 #ifdef KVM_CAP_ASYNC_PF
1171 case MSR_KVM_ASYNC_PF_EN
:
1172 env
->async_pf_en_msr
= msrs
[i
].data
;
1181 static int kvm_put_mp_state(CPUState
*env
)
1183 struct kvm_mp_state mp_state
= { .mp_state
= env
->mp_state
};
1185 return kvm_vcpu_ioctl(env
, KVM_SET_MP_STATE
, &mp_state
);
1188 static int kvm_get_mp_state(CPUState
*env
)
1190 struct kvm_mp_state mp_state
;
1193 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MP_STATE
, &mp_state
);
1197 env
->mp_state
= mp_state
.mp_state
;
1198 if (kvm_irqchip_in_kernel()) {
1199 env
->halted
= (mp_state
.mp_state
== KVM_MP_STATE_HALTED
);
1204 static int kvm_put_vcpu_events(CPUState
*env
, int level
)
1206 #ifdef KVM_CAP_VCPU_EVENTS
1207 struct kvm_vcpu_events events
;
1209 if (!kvm_has_vcpu_events()) {
1213 events
.exception
.injected
= (env
->exception_injected
>= 0);
1214 events
.exception
.nr
= env
->exception_injected
;
1215 events
.exception
.has_error_code
= env
->has_error_code
;
1216 events
.exception
.error_code
= env
->error_code
;
1218 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
1219 events
.interrupt
.nr
= env
->interrupt_injected
;
1220 events
.interrupt
.soft
= env
->soft_interrupt
;
1222 events
.nmi
.injected
= env
->nmi_injected
;
1223 events
.nmi
.pending
= env
->nmi_pending
;
1224 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
1226 events
.sipi_vector
= env
->sipi_vector
;
1229 if (level
>= KVM_PUT_RESET_STATE
) {
1231 KVM_VCPUEVENT_VALID_NMI_PENDING
| KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
1234 return kvm_vcpu_ioctl(env
, KVM_SET_VCPU_EVENTS
, &events
);
1240 static int kvm_get_vcpu_events(CPUState
*env
)
1242 #ifdef KVM_CAP_VCPU_EVENTS
1243 struct kvm_vcpu_events events
;
1246 if (!kvm_has_vcpu_events()) {
1250 ret
= kvm_vcpu_ioctl(env
, KVM_GET_VCPU_EVENTS
, &events
);
1254 env
->exception_injected
=
1255 events
.exception
.injected
? events
.exception
.nr
: -1;
1256 env
->has_error_code
= events
.exception
.has_error_code
;
1257 env
->error_code
= events
.exception
.error_code
;
1259 env
->interrupt_injected
=
1260 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
1261 env
->soft_interrupt
= events
.interrupt
.soft
;
1263 env
->nmi_injected
= events
.nmi
.injected
;
1264 env
->nmi_pending
= events
.nmi
.pending
;
1265 if (events
.nmi
.masked
) {
1266 env
->hflags2
|= HF2_NMI_MASK
;
1268 env
->hflags2
&= ~HF2_NMI_MASK
;
1271 env
->sipi_vector
= events
.sipi_vector
;
1277 static int kvm_guest_debug_workarounds(CPUState
*env
)
1280 #ifdef KVM_CAP_SET_GUEST_DEBUG
1281 unsigned long reinject_trap
= 0;
1283 if (!kvm_has_vcpu_events()) {
1284 if (env
->exception_injected
== 1) {
1285 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
1286 } else if (env
->exception_injected
== 3) {
1287 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
1289 env
->exception_injected
= -1;
1293 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1294 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1295 * by updating the debug state once again if single-stepping is on.
1296 * Another reason to call kvm_update_guest_debug here is a pending debug
1297 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1298 * reinject them via SET_GUEST_DEBUG.
1300 if (reinject_trap
||
1301 (!kvm_has_robust_singlestep() && env
->singlestep_enabled
)) {
1302 ret
= kvm_update_guest_debug(env
, reinject_trap
);
1304 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1308 static int kvm_put_debugregs(CPUState
*env
)
1310 #ifdef KVM_CAP_DEBUGREGS
1311 struct kvm_debugregs dbgregs
;
1314 if (!kvm_has_debugregs()) {
1318 for (i
= 0; i
< 4; i
++) {
1319 dbgregs
.db
[i
] = env
->dr
[i
];
1321 dbgregs
.dr6
= env
->dr
[6];
1322 dbgregs
.dr7
= env
->dr
[7];
1325 return kvm_vcpu_ioctl(env
, KVM_SET_DEBUGREGS
, &dbgregs
);
1331 static int kvm_get_debugregs(CPUState
*env
)
1333 #ifdef KVM_CAP_DEBUGREGS
1334 struct kvm_debugregs dbgregs
;
1337 if (!kvm_has_debugregs()) {
1341 ret
= kvm_vcpu_ioctl(env
, KVM_GET_DEBUGREGS
, &dbgregs
);
1345 for (i
= 0; i
< 4; i
++) {
1346 env
->dr
[i
] = dbgregs
.db
[i
];
1348 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
1349 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
1355 int kvm_arch_put_registers(CPUState
*env
, int level
)
1359 assert(cpu_is_stopped(env
) || qemu_cpu_self(env
));
1361 ret
= kvm_getput_regs(env
, 1);
1365 ret
= kvm_put_xsave(env
);
1369 ret
= kvm_put_xcrs(env
);
1373 ret
= kvm_put_sregs(env
);
1377 ret
= kvm_put_msrs(env
, level
);
1381 if (level
>= KVM_PUT_RESET_STATE
) {
1382 ret
= kvm_put_mp_state(env
);
1387 ret
= kvm_put_vcpu_events(env
, level
);
1391 ret
= kvm_put_debugregs(env
);
1396 ret
= kvm_guest_debug_workarounds(env
);
1403 int kvm_arch_get_registers(CPUState
*env
)
1407 assert(cpu_is_stopped(env
) || qemu_cpu_self(env
));
1409 ret
= kvm_getput_regs(env
, 0);
1413 ret
= kvm_get_xsave(env
);
1417 ret
= kvm_get_xcrs(env
);
1421 ret
= kvm_get_sregs(env
);
1425 ret
= kvm_get_msrs(env
);
1429 ret
= kvm_get_mp_state(env
);
1433 ret
= kvm_get_vcpu_events(env
);
1437 ret
= kvm_get_debugregs(env
);
1444 int kvm_arch_pre_run(CPUState
*env
, struct kvm_run
*run
)
1447 if (env
->interrupt_request
& CPU_INTERRUPT_NMI
) {
1448 env
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
1449 DPRINTF("injected NMI\n");
1450 kvm_vcpu_ioctl(env
, KVM_NMI
);
1453 /* Try to inject an interrupt if the guest can accept it */
1454 if (run
->ready_for_interrupt_injection
&&
1455 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1456 (env
->eflags
& IF_MASK
)) {
1459 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
1460 irq
= cpu_get_pic_interrupt(env
);
1462 struct kvm_interrupt intr
;
1465 DPRINTF("injected interrupt %d\n", irq
);
1466 kvm_vcpu_ioctl(env
, KVM_INTERRUPT
, &intr
);
1470 /* If we have an interrupt but the guest is not ready to receive an
1471 * interrupt, request an interrupt window exit. This will
1472 * cause a return to userspace as soon as the guest is ready to
1473 * receive interrupts. */
1474 if ((env
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
1475 run
->request_interrupt_window
= 1;
1477 run
->request_interrupt_window
= 0;
1480 DPRINTF("setting tpr\n");
1481 run
->cr8
= cpu_get_apic_tpr(env
->apic_state
);
1486 int kvm_arch_post_run(CPUState
*env
, struct kvm_run
*run
)
1489 env
->eflags
|= IF_MASK
;
1491 env
->eflags
&= ~IF_MASK
;
1493 cpu_set_apic_tpr(env
->apic_state
, run
->cr8
);
1494 cpu_set_apic_base(env
->apic_state
, run
->apic_base
);
1499 int kvm_arch_process_irqchip_events(CPUState
*env
)
1501 if (env
->interrupt_request
& CPU_INTERRUPT_INIT
) {
1502 kvm_cpu_synchronize_state(env
);
1504 env
->exception_index
= EXCP_HALTED
;
1507 if (env
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
1508 kvm_cpu_synchronize_state(env
);
1515 static int kvm_handle_halt(CPUState
*env
)
1517 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1518 (env
->eflags
& IF_MASK
)) &&
1519 !(env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1521 env
->exception_index
= EXCP_HLT
;
1528 static bool host_supports_vmx(void)
1530 uint32_t ecx
, unused
;
1532 host_cpuid(1, 0, &unused
, &unused
, &ecx
, &unused
);
1533 return ecx
& CPUID_EXT_VMX
;
1536 #define VMX_INVALID_GUEST_STATE 0x80000021
1538 int kvm_arch_handle_exit(CPUState
*env
, struct kvm_run
*run
)
1543 switch (run
->exit_reason
) {
1545 DPRINTF("handle_hlt\n");
1546 ret
= kvm_handle_halt(env
);
1548 case KVM_EXIT_SET_TPR
:
1551 case KVM_EXIT_FAIL_ENTRY
:
1552 code
= run
->fail_entry
.hardware_entry_failure_reason
;
1553 fprintf(stderr
, "KVM: entry failed, hardware error 0x%" PRIx64
"\n",
1555 if (host_supports_vmx() && code
== VMX_INVALID_GUEST_STATE
) {
1557 "\nIf you're runnning a guest on an Intel machine without "
1558 "unrestricted mode\n"
1559 "support, the failure can be most likely due to the guest "
1560 "entering an invalid\n"
1561 "state for Intel VT. For example, the guest maybe running "
1562 "in big real mode\n"
1563 "which is not supported on less recent Intel processors."
1568 case KVM_EXIT_EXCEPTION
:
1569 fprintf(stderr
, "KVM: exception %d exit (error code 0x%x)\n",
1570 run
->ex
.exception
, run
->ex
.error_code
);
1574 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
1582 #ifdef KVM_CAP_SET_GUEST_DEBUG
1583 int kvm_arch_insert_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
1585 static const uint8_t int3
= 0xcc;
1587 if (cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
1588 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&int3
, 1, 1)) {
1594 int kvm_arch_remove_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
1598 if (cpu_memory_rw_debug(env
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
1599 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1)) {
1611 static int nb_hw_breakpoint
;
1613 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
1617 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
1618 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
1619 (hw_breakpoint
[n
].len
== len
|| len
== -1)) {
1626 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
1627 target_ulong len
, int type
)
1630 case GDB_BREAKPOINT_HW
:
1633 case GDB_WATCHPOINT_WRITE
:
1634 case GDB_WATCHPOINT_ACCESS
:
1641 if (addr
& (len
- 1)) {
1653 if (nb_hw_breakpoint
== 4) {
1656 if (find_hw_breakpoint(addr
, len
, type
) >= 0) {
1659 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
1660 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
1661 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
1667 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
1668 target_ulong len
, int type
)
1672 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
1677 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
1682 void kvm_arch_remove_all_hw_breakpoints(void)
1684 nb_hw_breakpoint
= 0;
1687 static CPUWatchpoint hw_watchpoint
;
1689 int kvm_arch_debug(struct kvm_debug_exit_arch
*arch_info
)
1694 if (arch_info
->exception
== 1) {
1695 if (arch_info
->dr6
& (1 << 14)) {
1696 if (cpu_single_env
->singlestep_enabled
) {
1700 for (n
= 0; n
< 4; n
++) {
1701 if (arch_info
->dr6
& (1 << n
)) {
1702 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
1708 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1709 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1710 hw_watchpoint
.flags
= BP_MEM_WRITE
;
1714 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1715 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1716 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
1722 } else if (kvm_find_sw_breakpoint(cpu_single_env
, arch_info
->pc
)) {
1726 cpu_synchronize_state(cpu_single_env
);
1727 assert(cpu_single_env
->exception_injected
== -1);
1729 cpu_single_env
->exception_injected
= arch_info
->exception
;
1730 cpu_single_env
->has_error_code
= 0;
1736 void kvm_arch_update_guest_debug(CPUState
*env
, struct kvm_guest_debug
*dbg
)
1738 const uint8_t type_code
[] = {
1739 [GDB_BREAKPOINT_HW
] = 0x0,
1740 [GDB_WATCHPOINT_WRITE
] = 0x1,
1741 [GDB_WATCHPOINT_ACCESS
] = 0x3
1743 const uint8_t len_code
[] = {
1744 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1748 if (kvm_sw_breakpoints_active(env
)) {
1749 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
1751 if (nb_hw_breakpoint
> 0) {
1752 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
1753 dbg
->arch
.debugreg
[7] = 0x0600;
1754 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
1755 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
1756 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
1757 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
1758 ((uint32_t)len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
1762 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1764 bool kvm_arch_stop_on_emulation_error(CPUState
*env
)
1766 return !(env
->cr
[0] & CR0_PE_MASK
) ||
1767 ((env
->segs
[R_CS
].selector
& 3) != 3);
1770 static void hardware_memory_error(void)
1772 fprintf(stderr
, "Hardware memory error!\n");
1777 static void kvm_mce_broadcast_rest(CPUState
*env
)
1779 struct kvm_x86_mce mce
= {
1781 .status
= MCI_STATUS_VAL
| MCI_STATUS_UC
,
1782 .mcg_status
= MCG_STATUS_MCIP
| MCG_STATUS_RIPV
,
1788 /* Broadcast MCA signal for processor version 06H_EH and above */
1789 if (cpu_x86_support_mca_broadcast(env
)) {
1790 for (cenv
= first_cpu
; cenv
!= NULL
; cenv
= cenv
->next_cpu
) {
1794 kvm_inject_x86_mce_on(cenv
, &mce
, ABORT_ON_ERROR
);
1799 static void kvm_mce_inj_srar_dataload(CPUState
*env
, target_phys_addr_t paddr
)
1801 struct kvm_x86_mce mce
= {
1803 .status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
1804 | MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
1805 | MCI_STATUS_AR
| 0x134,
1806 .mcg_status
= MCG_STATUS_MCIP
| MCG_STATUS_EIPV
,
1808 .misc
= (MCM_ADDR_PHYS
<< 6) | 0xc,
1812 r
= kvm_set_mce(env
, &mce
);
1814 fprintf(stderr
, "kvm_set_mce: %s\n", strerror(errno
));
1817 kvm_mce_broadcast_rest(env
);
1820 static void kvm_mce_inj_srao_memscrub(CPUState
*env
, target_phys_addr_t paddr
)
1822 struct kvm_x86_mce mce
= {
1824 .status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
1825 | MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
1827 .mcg_status
= MCG_STATUS_MCIP
| MCG_STATUS_RIPV
,
1829 .misc
= (MCM_ADDR_PHYS
<< 6) | 0xc,
1833 r
= kvm_set_mce(env
, &mce
);
1835 fprintf(stderr
, "kvm_set_mce: %s\n", strerror(errno
));
1838 kvm_mce_broadcast_rest(env
);
1841 static void kvm_mce_inj_srao_memscrub2(CPUState
*env
, target_phys_addr_t paddr
)
1843 struct kvm_x86_mce mce
= {
1845 .status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
1846 | MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
1848 .mcg_status
= MCG_STATUS_MCIP
| MCG_STATUS_RIPV
,
1850 .misc
= (MCM_ADDR_PHYS
<< 6) | 0xc,
1853 kvm_inject_x86_mce_on(env
, &mce
, ABORT_ON_ERROR
);
1854 kvm_mce_broadcast_rest(env
);
1859 int kvm_on_sigbus_vcpu(CPUState
*env
, int code
, void *addr
)
1861 #if defined(KVM_CAP_MCE)
1863 ram_addr_t ram_addr
;
1864 target_phys_addr_t paddr
;
1866 if ((env
->mcg_cap
& MCG_SER_P
) && addr
1867 && (code
== BUS_MCEERR_AR
1868 || code
== BUS_MCEERR_AO
)) {
1869 vaddr
= (void *)addr
;
1870 if (qemu_ram_addr_from_host(vaddr
, &ram_addr
) ||
1871 !kvm_physical_memory_addr_from_ram(env
->kvm_state
, ram_addr
, &paddr
)) {
1872 fprintf(stderr
, "Hardware memory error for memory used by "
1873 "QEMU itself instead of guest system!\n");
1874 /* Hope we are lucky for AO MCE */
1875 if (code
== BUS_MCEERR_AO
) {
1878 hardware_memory_error();
1882 if (code
== BUS_MCEERR_AR
) {
1883 /* Fake an Intel architectural Data Load SRAR UCR */
1884 kvm_mce_inj_srar_dataload(env
, paddr
);
1887 * If there is an MCE excpetion being processed, ignore
1890 if (!kvm_mce_in_progress(env
)) {
1891 /* Fake an Intel architectural Memory scrubbing UCR */
1892 kvm_mce_inj_srao_memscrub(env
, paddr
);
1898 if (code
== BUS_MCEERR_AO
) {
1900 } else if (code
== BUS_MCEERR_AR
) {
1901 hardware_memory_error();
1909 int kvm_on_sigbus(int code
, void *addr
)
1911 #if defined(KVM_CAP_MCE)
1912 if ((first_cpu
->mcg_cap
& MCG_SER_P
) && addr
&& code
== BUS_MCEERR_AO
) {
1914 ram_addr_t ram_addr
;
1915 target_phys_addr_t paddr
;
1917 /* Hope we are lucky for AO MCE */
1919 if (qemu_ram_addr_from_host(vaddr
, &ram_addr
) ||
1920 !kvm_physical_memory_addr_from_ram(first_cpu
->kvm_state
, ram_addr
, &paddr
)) {
1921 fprintf(stderr
, "Hardware memory error for memory used by "
1922 "QEMU itself instead of guest system!: %p\n", addr
);
1925 kvm_mce_inj_srao_memscrub2(first_cpu
, paddr
);
1929 if (code
== BUS_MCEERR_AO
) {
1931 } else if (code
== BUS_MCEERR_AR
) {
1932 hardware_memory_error();