4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
32 #include "qemu-objects.h"
37 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
39 # define PCI_DPRINTF(format, ...) do { } while (0)
42 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
43 static char *pcibus_get_dev_path(DeviceState
*dev
);
44 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
45 static int pcibus_reset(BusState
*qbus
);
47 struct BusInfo pci_bus_info
= {
49 .size
= sizeof(PCIBus
),
50 .print_dev
= pcibus_dev_print
,
51 .get_dev_path
= pcibus_get_dev_path
,
52 .get_fw_dev_path
= pcibus_get_fw_dev_path
,
53 .reset
= pcibus_reset
,
54 .props
= (Property
[]) {
55 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
56 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
57 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
58 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
59 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
60 DEFINE_PROP_BIT("command_serr_enable", PCIDevice
, cap_present
,
61 QEMU_PCI_CAP_SERR_BITNR
, true),
62 DEFINE_PROP_END_OF_LIST()
66 static void pci_update_mappings(PCIDevice
*d
);
67 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
68 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
);
69 static void pci_del_option_rom(PCIDevice
*pdev
);
71 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
72 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
77 QLIST_ENTRY(PCIHostBus
) next
;
79 static QLIST_HEAD(, PCIHostBus
) host_buses
;
81 static const VMStateDescription vmstate_pcibus
= {
84 .minimum_version_id
= 1,
85 .minimum_version_id_old
= 1,
86 .fields
= (VMStateField
[]) {
87 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
88 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
93 static int pci_bar(PCIDevice
*d
, int reg
)
97 if (reg
!= PCI_ROM_SLOT
)
98 return PCI_BASE_ADDRESS_0
+ reg
* 4;
100 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
101 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
104 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
106 return (d
->irq_state
>> irq_num
) & 0x1;
109 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
111 d
->irq_state
&= ~(0x1 << irq_num
);
112 d
->irq_state
|= level
<< irq_num
;
115 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
120 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
123 pci_dev
= bus
->parent_dev
;
125 bus
->irq_count
[irq_num
] += change
;
126 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
129 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
131 assert(irq_num
>= 0);
132 assert(irq_num
< bus
->nirq
);
133 return !!bus
->irq_count
[irq_num
];
136 /* Update interrupt status bit in config space on interrupt
138 static void pci_update_irq_status(PCIDevice
*dev
)
140 if (dev
->irq_state
) {
141 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
143 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
147 void pci_device_deassert_intx(PCIDevice
*dev
)
150 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
151 qemu_set_irq(dev
->irq
[i
], 0);
156 * This function is called on #RST and FLR.
157 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
159 void pci_device_reset(PCIDevice
*dev
)
162 /* TODO: call the below unconditionally once all pci devices
164 if (dev
->qdev
.info
) {
165 qdev_reset_all(&dev
->qdev
);
169 pci_update_irq_status(dev
);
170 pci_device_deassert_intx(dev
);
171 /* Clear all writable bits */
172 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
173 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
174 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
175 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
176 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
177 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
178 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
179 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
180 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
181 PCIIORegion
*region
= &dev
->io_regions
[r
];
186 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
187 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
188 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
190 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
193 pci_update_mappings(dev
);
197 * Trigger pci bus reset under a given bus.
198 * To be called on RST# assert.
200 void pci_bus_reset(PCIBus
*bus
)
204 for (i
= 0; i
< bus
->nirq
; i
++) {
205 bus
->irq_count
[i
] = 0;
207 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
208 if (bus
->devices
[i
]) {
209 pci_device_reset(bus
->devices
[i
]);
214 static int pcibus_reset(BusState
*qbus
)
216 pci_bus_reset(DO_UPCAST(PCIBus
, qbus
, qbus
));
218 /* topology traverse is done by pci_bus_reset().
219 Tell qbus/qdev walker not to traverse the tree */
223 static void pci_host_bus_register(int domain
, PCIBus
*bus
)
225 struct PCIHostBus
*host
;
226 host
= qemu_mallocz(sizeof(*host
));
227 host
->domain
= domain
;
229 QLIST_INSERT_HEAD(&host_buses
, host
, next
);
232 PCIBus
*pci_find_root_bus(int domain
)
234 struct PCIHostBus
*host
;
236 QLIST_FOREACH(host
, &host_buses
, next
) {
237 if (host
->domain
== domain
) {
245 int pci_find_domain(const PCIBus
*bus
)
248 struct PCIHostBus
*host
;
250 /* obtain root bus */
251 while ((d
= bus
->parent_dev
) != NULL
) {
255 QLIST_FOREACH(host
, &host_buses
, next
) {
256 if (host
->bus
== bus
) {
261 abort(); /* should not be reached */
265 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
267 MemoryRegion
*address_space_mem
,
268 MemoryRegion
*address_space_io
,
271 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
272 assert(PCI_FUNC(devfn_min
) == 0);
273 bus
->devfn_min
= devfn_min
;
274 bus
->address_space_mem
= address_space_mem
;
275 bus
->address_space_io
= address_space_io
;
278 QLIST_INIT(&bus
->child
);
279 pci_host_bus_register(0, bus
); /* for now only pci domain 0 is supported */
281 vmstate_register(NULL
, -1, &vmstate_pcibus
, bus
);
284 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
285 MemoryRegion
*address_space_mem
,
286 MemoryRegion
*address_space_io
,
291 bus
= qemu_mallocz(sizeof(*bus
));
292 bus
->qbus
.qdev_allocated
= 1;
293 pci_bus_new_inplace(bus
, parent
, name
, address_space_mem
,
294 address_space_io
, devfn_min
);
298 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
299 void *irq_opaque
, int nirq
)
301 bus
->set_irq
= set_irq
;
302 bus
->map_irq
= map_irq
;
303 bus
->irq_opaque
= irq_opaque
;
305 bus
->irq_count
= qemu_mallocz(nirq
* sizeof(bus
->irq_count
[0]));
308 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*qdev
)
310 bus
->qbus
.allow_hotplug
= 1;
311 bus
->hotplug
= hotplug
;
312 bus
->hotplug_qdev
= qdev
;
315 void pci_bus_set_mem_base(PCIBus
*bus
, target_phys_addr_t base
)
317 bus
->mem_base
= base
;
320 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
321 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
323 MemoryRegion
*address_space_mem
,
324 MemoryRegion
*address_space_io
,
325 uint8_t devfn_min
, int nirq
)
329 bus
= pci_bus_new(parent
, name
, address_space_mem
,
330 address_space_io
, devfn_min
);
331 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
335 int pci_bus_num(PCIBus
*s
)
338 return 0; /* pci host bridge */
339 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
342 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
344 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
348 assert(size
== pci_config_size(s
));
349 config
= qemu_malloc(size
);
351 qemu_get_buffer(f
, config
, size
);
352 for (i
= 0; i
< size
; ++i
) {
353 if ((config
[i
] ^ s
->config
[i
]) &
354 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
359 memcpy(s
->config
, config
, size
);
361 pci_update_mappings(s
);
367 /* just put buffer */
368 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
370 const uint8_t **v
= pv
;
371 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
372 qemu_put_buffer(f
, *v
, size
);
375 static VMStateInfo vmstate_info_pci_config
= {
376 .name
= "pci config",
377 .get
= get_pci_config_device
,
378 .put
= put_pci_config_device
,
381 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
383 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
384 uint32_t irq_state
[PCI_NUM_PINS
];
386 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
387 irq_state
[i
] = qemu_get_be32(f
);
388 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
389 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
395 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
396 pci_set_irq_state(s
, i
, irq_state
[i
]);
402 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
405 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
407 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
408 qemu_put_be32(f
, pci_irq_state(s
, i
));
412 static VMStateInfo vmstate_info_pci_irq_state
= {
413 .name
= "pci irq state",
414 .get
= get_pci_irq_state
,
415 .put
= put_pci_irq_state
,
418 const VMStateDescription vmstate_pci_device
= {
421 .minimum_version_id
= 1,
422 .minimum_version_id_old
= 1,
423 .fields
= (VMStateField
[]) {
424 VMSTATE_INT32_LE(version_id
, PCIDevice
),
425 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
426 vmstate_info_pci_config
,
427 PCI_CONFIG_SPACE_SIZE
),
428 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
429 vmstate_info_pci_irq_state
,
430 PCI_NUM_PINS
* sizeof(int32_t)),
431 VMSTATE_END_OF_LIST()
435 const VMStateDescription vmstate_pcie_device
= {
438 .minimum_version_id
= 1,
439 .minimum_version_id_old
= 1,
440 .fields
= (VMStateField
[]) {
441 VMSTATE_INT32_LE(version_id
, PCIDevice
),
442 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
443 vmstate_info_pci_config
,
444 PCIE_CONFIG_SPACE_SIZE
),
445 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
446 vmstate_info_pci_irq_state
,
447 PCI_NUM_PINS
* sizeof(int32_t)),
448 VMSTATE_END_OF_LIST()
452 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
454 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
457 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
459 /* Clear interrupt status bit: it is implicit
460 * in irq_state which we are saving.
461 * This makes us compatible with old devices
462 * which never set or clear this bit. */
463 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
464 vmstate_save_state(f
, pci_get_vmstate(s
), s
);
465 /* Restore the interrupt status bit. */
466 pci_update_irq_status(s
);
469 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
472 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
473 /* Restore the interrupt status bit. */
474 pci_update_irq_status(s
);
478 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
480 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
481 pci_default_sub_vendor_id
);
482 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
483 pci_default_sub_device_id
);
487 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
488 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
490 int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
491 unsigned int *slotp
, unsigned int *funcp
)
496 unsigned long dom
= 0, bus
= 0;
497 unsigned int slot
= 0;
498 unsigned int func
= 0;
501 val
= strtoul(p
, &e
, 16);
507 val
= strtoul(p
, &e
, 16);
514 val
= strtoul(p
, &e
, 16);
527 val
= strtoul(p
, &e
, 16);
534 /* if funcp == NULL func is 0 */
535 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
541 /* Note: QEMU doesn't implement domains other than 0 */
542 if (!pci_find_bus(pci_find_root_bus(dom
), bus
))
553 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
556 /* strip legacy tag */
557 if (!strncmp(addr
, "pci_addr=", 9)) {
560 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
, NULL
)) {
561 monitor_printf(mon
, "Invalid pci address\n");
567 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
574 return pci_find_bus(pci_find_root_bus(0), 0);
577 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
, NULL
) < 0) {
581 *devfnp
= PCI_DEVFN(slot
, 0);
582 return pci_find_bus(pci_find_root_bus(dom
), bus
);
585 static void pci_init_cmask(PCIDevice
*dev
)
587 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
588 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
589 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
590 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
591 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
592 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
593 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
594 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
597 static void pci_init_wmask(PCIDevice
*dev
)
599 int config_size
= pci_config_size(dev
);
601 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
602 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
603 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
604 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
605 PCI_COMMAND_INTX_DISABLE
);
606 if (dev
->cap_present
& QEMU_PCI_CAP_SERR
) {
607 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
610 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
611 config_size
- PCI_CONFIG_HEADER_SIZE
);
614 static void pci_init_w1cmask(PCIDevice
*dev
)
617 * Note: It's okay to set w1cmask even for readonly bits as
618 * long as their value is hardwired to 0.
620 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
621 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
622 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
623 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
626 static void pci_init_wmask_bridge(PCIDevice
*d
)
628 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
629 PCI_SEC_LETENCY_TIMER */
630 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
633 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
634 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
635 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
636 PCI_MEMORY_RANGE_MASK
& 0xffff);
637 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
638 PCI_MEMORY_RANGE_MASK
& 0xffff);
639 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
640 PCI_PREF_RANGE_MASK
& 0xffff);
641 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
642 PCI_PREF_RANGE_MASK
& 0xffff);
644 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
645 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
647 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
648 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
649 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
650 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
651 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
652 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
653 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
654 PCI_BRIDGE_CTL_PARITY
|
655 PCI_BRIDGE_CTL_SERR
|
658 PCI_BRIDGE_CTL_VGA_16BIT
|
659 PCI_BRIDGE_CTL_MASTER_ABORT
|
660 PCI_BRIDGE_CTL_BUS_RESET
|
661 PCI_BRIDGE_CTL_FAST_BACK
|
662 PCI_BRIDGE_CTL_DISCARD
|
663 PCI_BRIDGE_CTL_SEC_DISCARD
|
664 PCI_BRIDGE_CTL_DISCARD_SERR
);
665 /* Below does not do anything as we never set this bit, put here for
667 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
668 PCI_BRIDGE_CTL_DISCARD_STATUS
);
671 static int pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
)
673 uint8_t slot
= PCI_SLOT(dev
->devfn
);
676 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
677 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
681 * multifunction bit is interpreted in two ways as follows.
682 * - all functions must set the bit to 1.
684 * - function 0 must set the bit, but the rest function (> 0)
685 * is allowed to leave the bit to 0.
686 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
688 * So OS (at least Linux) checks the bit of only function 0,
689 * and doesn't see the bit of function > 0.
691 * The below check allows both interpretation.
693 if (PCI_FUNC(dev
->devfn
)) {
694 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
695 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
696 /* function 0 should set multifunction bit */
697 error_report("PCI: single function device can't be populated "
698 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
704 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
707 /* function 0 indicates single function, so function > 0 must be NULL */
708 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
709 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
710 error_report("PCI: %x.0 indicates single function, "
711 "but %x.%x is already populated.",
719 static void pci_config_alloc(PCIDevice
*pci_dev
)
721 int config_size
= pci_config_size(pci_dev
);
723 pci_dev
->config
= qemu_mallocz(config_size
);
724 pci_dev
->cmask
= qemu_mallocz(config_size
);
725 pci_dev
->wmask
= qemu_mallocz(config_size
);
726 pci_dev
->w1cmask
= qemu_mallocz(config_size
);
727 pci_dev
->used
= qemu_mallocz(config_size
);
730 static void pci_config_free(PCIDevice
*pci_dev
)
732 qemu_free(pci_dev
->config
);
733 qemu_free(pci_dev
->cmask
);
734 qemu_free(pci_dev
->wmask
);
735 qemu_free(pci_dev
->w1cmask
);
736 qemu_free(pci_dev
->used
);
739 /* -1 for devfn means auto assign */
740 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
741 const char *name
, int devfn
,
742 const PCIDeviceInfo
*info
)
744 PCIConfigReadFunc
*config_read
= info
->config_read
;
745 PCIConfigWriteFunc
*config_write
= info
->config_write
;
748 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
749 devfn
+= PCI_FUNC_MAX
) {
750 if (!bus
->devices
[devfn
])
753 error_report("PCI: no slot/function available for %s, all in use", name
);
756 } else if (bus
->devices
[devfn
]) {
757 error_report("PCI: slot %d function %d not available for %s, in use by %s",
758 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
, bus
->devices
[devfn
]->name
);
762 pci_dev
->devfn
= devfn
;
763 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
764 pci_dev
->irq_state
= 0;
765 pci_config_alloc(pci_dev
);
767 pci_config_set_vendor_id(pci_dev
->config
, info
->vendor_id
);
768 pci_config_set_device_id(pci_dev
->config
, info
->device_id
);
769 pci_config_set_revision(pci_dev
->config
, info
->revision
);
770 pci_config_set_class(pci_dev
->config
, info
->class_id
);
772 if (!info
->is_bridge
) {
773 if (info
->subsystem_vendor_id
|| info
->subsystem_id
) {
774 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
775 info
->subsystem_vendor_id
);
776 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
779 pci_set_default_subsystem_id(pci_dev
);
782 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
783 assert(!info
->subsystem_vendor_id
);
784 assert(!info
->subsystem_id
);
786 pci_init_cmask(pci_dev
);
787 pci_init_wmask(pci_dev
);
788 pci_init_w1cmask(pci_dev
);
789 if (info
->is_bridge
) {
790 pci_init_wmask_bridge(pci_dev
);
792 if (pci_init_multifunction(bus
, pci_dev
)) {
793 pci_config_free(pci_dev
);
798 config_read
= pci_default_read_config
;
800 config_write
= pci_default_write_config
;
801 pci_dev
->config_read
= config_read
;
802 pci_dev
->config_write
= config_write
;
803 bus
->devices
[devfn
] = pci_dev
;
804 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
805 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
809 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
811 qemu_free_irqs(pci_dev
->irq
);
812 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
813 pci_config_free(pci_dev
);
816 /* TODO: obsolete. eliminate this once all pci devices are qdevifed. */
817 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
818 int instance_size
, int devfn
,
819 PCIConfigReadFunc
*config_read
,
820 PCIConfigWriteFunc
*config_write
)
823 PCIDeviceInfo info
= {
824 .config_read
= config_read
,
825 .config_write
= config_write
,
828 pci_dev
= qemu_mallocz(instance_size
);
829 pci_dev
= do_pci_register_device(pci_dev
, bus
, name
, devfn
, &info
);
830 if (pci_dev
== NULL
) {
831 hw_error("PCI: can't register device\n");
836 static target_phys_addr_t
pci_to_cpu_addr(PCIBus
*bus
,
837 target_phys_addr_t addr
)
839 return addr
+ bus
->mem_base
;
842 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
847 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
848 r
= &pci_dev
->io_regions
[i
];
849 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
852 memory_region_del_subregion(r
->address_space
, r
->memory
);
854 if (r
->type
== PCI_BASE_ADDRESS_SPACE_IO
) {
855 isa_unassign_ioport(r
->addr
, r
->filtered_size
);
857 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev
->bus
,
866 static int pci_unregister_device(DeviceState
*dev
)
868 PCIDevice
*pci_dev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
869 PCIDeviceInfo
*info
= DO_UPCAST(PCIDeviceInfo
, qdev
, dev
->info
);
873 ret
= info
->exit(pci_dev
);
877 pci_unregister_io_regions(pci_dev
);
878 pci_del_option_rom(pci_dev
);
879 qemu_free(pci_dev
->romfile
);
880 do_pci_unregister_device(pci_dev
);
884 static void pci_simple_bar_mapfunc_region(PCIDevice
*pci_dev
, int region_num
,
885 pcibus_t addr
, pcibus_t size
,
888 PCIIORegion
*r
= &pci_dev
->io_regions
[region_num
];
890 memory_region_add_subregion_overlap(r
->address_space
,
896 void pci_register_bar_region(PCIDevice
*pci_dev
, int region_num
,
897 uint8_t type
, MemoryRegion
*memory
)
902 pcibus_t size
= memory_region_size(memory
);
904 assert(region_num
>= 0);
905 assert(region_num
< PCI_NUM_REGIONS
);
906 if (size
& (size
-1)) {
907 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
908 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
912 r
= &pci_dev
->io_regions
[region_num
];
913 r
->addr
= PCI_BAR_UNMAPPED
;
915 r
->filtered_size
= size
;
917 r
->map_func
= pci_simple_bar_mapfunc_region
;
921 addr
= pci_bar(pci_dev
, region_num
);
922 if (region_num
== PCI_ROM_SLOT
) {
923 /* ROM enable bit is writable */
924 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
926 pci_set_long(pci_dev
->config
+ addr
, type
);
927 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
928 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
929 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
930 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
932 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
933 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
935 pci_dev
->io_regions
[region_num
].memory
= memory
;
936 pci_dev
->io_regions
[region_num
].address_space
937 = type
& PCI_BASE_ADDRESS_SPACE_IO
938 ? pci_dev
->bus
->address_space_io
939 : pci_dev
->bus
->address_space_mem
;
942 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
944 return pci_dev
->io_regions
[region_num
].addr
;
947 static void pci_bridge_filter(PCIDevice
*d
, pcibus_t
*addr
, pcibus_t
*size
,
950 pcibus_t base
= *addr
;
951 pcibus_t limit
= *addr
+ *size
- 1;
954 for (br
= d
->bus
->parent_dev
; br
; br
= br
->bus
->parent_dev
) {
955 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
957 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
958 if (!(cmd
& PCI_COMMAND_IO
)) {
962 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
967 base
= MAX(base
, pci_bridge_get_base(br
, type
));
968 limit
= MIN(limit
, pci_bridge_get_limit(br
, type
));
975 *size
= limit
- base
+ 1;
978 *addr
= PCI_BAR_UNMAPPED
;
982 static pcibus_t
pci_bar_address(PCIDevice
*d
,
983 int reg
, uint8_t type
, pcibus_t size
)
985 pcibus_t new_addr
, last_addr
;
986 int bar
= pci_bar(d
, reg
);
987 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
989 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
990 if (!(cmd
& PCI_COMMAND_IO
)) {
991 return PCI_BAR_UNMAPPED
;
993 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
994 last_addr
= new_addr
+ size
- 1;
995 /* NOTE: we have only 64K ioports on PC */
996 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
> UINT16_MAX
) {
997 return PCI_BAR_UNMAPPED
;
1002 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
1003 return PCI_BAR_UNMAPPED
;
1005 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1006 new_addr
= pci_get_quad(d
->config
+ bar
);
1008 new_addr
= pci_get_long(d
->config
+ bar
);
1010 /* the ROM slot has a specific enable bit */
1011 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
1012 return PCI_BAR_UNMAPPED
;
1014 new_addr
&= ~(size
- 1);
1015 last_addr
= new_addr
+ size
- 1;
1016 /* NOTE: we do not support wrapping */
1017 /* XXX: as we cannot support really dynamic
1018 mappings, we handle specific values as invalid
1020 if (last_addr
<= new_addr
|| new_addr
== 0 ||
1021 last_addr
== PCI_BAR_UNMAPPED
) {
1022 return PCI_BAR_UNMAPPED
;
1025 /* Now pcibus_t is 64bit.
1026 * Check if 32 bit BAR wraps around explicitly.
1027 * Without this, PC ide doesn't work well.
1028 * TODO: remove this work around.
1030 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
1031 return PCI_BAR_UNMAPPED
;
1035 * OS is allowed to set BAR beyond its addressable
1036 * bits. For example, 32 bit OS can set 64bit bar
1037 * to >4G. Check it. TODO: we might need to support
1038 * it in the future for e.g. PAE.
1040 if (last_addr
>= TARGET_PHYS_ADDR_MAX
) {
1041 return PCI_BAR_UNMAPPED
;
1047 static void pci_update_mappings(PCIDevice
*d
)
1051 pcibus_t new_addr
, filtered_size
;
1053 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1054 r
= &d
->io_regions
[i
];
1056 /* this region isn't registered */
1060 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1062 /* bridge filtering */
1063 filtered_size
= r
->size
;
1064 if (new_addr
!= PCI_BAR_UNMAPPED
) {
1065 pci_bridge_filter(d
, &new_addr
, &filtered_size
, r
->type
);
1068 /* This bar isn't changed */
1069 if (new_addr
== r
->addr
&& filtered_size
== r
->filtered_size
)
1072 /* now do the real mapping */
1073 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1075 memory_region_del_subregion(r
->address_space
, r
->memory
);
1076 } else if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1078 /* NOTE: specific hack for IDE in PC case:
1079 only one byte must be mapped. */
1080 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1081 if (class == 0x0101 && r
->size
== 4) {
1082 isa_unassign_ioport(r
->addr
+ 2, 1);
1084 isa_unassign_ioport(r
->addr
, r
->filtered_size
);
1087 cpu_register_physical_memory(pci_to_cpu_addr(d
->bus
,
1091 qemu_unregister_coalesced_mmio(r
->addr
, r
->filtered_size
);
1095 r
->filtered_size
= filtered_size
;
1096 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1098 * TODO: currently almost all the map funcions assumes
1099 * filtered_size == size and addr & ~(size - 1) == addr.
1100 * However with bridge filtering, they aren't always true.
1101 * Teach them such cases, such that filtered_size < size and
1102 * addr & (size - 1) != 0.
1104 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1105 r
->map_func(d
, i
, r
->addr
, r
->filtered_size
, r
->type
);
1107 r
->map_func(d
, i
, pci_to_cpu_addr(d
->bus
, r
->addr
),
1108 r
->filtered_size
, r
->type
);
1114 static inline int pci_irq_disabled(PCIDevice
*d
)
1116 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1119 /* Called after interrupt disabled field update in config space,
1120 * assert/deassert interrupts if necessary.
1121 * Gets original interrupt disable bit value (before update). */
1122 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1124 int i
, disabled
= pci_irq_disabled(d
);
1125 if (disabled
== was_irq_disabled
)
1127 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1128 int state
= pci_irq_state(d
, i
);
1129 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1133 uint32_t pci_default_read_config(PCIDevice
*d
,
1134 uint32_t address
, int len
)
1138 memcpy(&val
, d
->config
+ address
, len
);
1139 return le32_to_cpu(val
);
1142 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
1144 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1146 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1147 uint8_t wmask
= d
->wmask
[addr
+ i
];
1148 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1149 assert(!(wmask
& w1cmask
));
1150 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1151 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1153 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1154 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1155 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1156 range_covers_byte(addr
, l
, PCI_COMMAND
))
1157 pci_update_mappings(d
);
1159 if (range_covers_byte(addr
, l
, PCI_COMMAND
))
1160 pci_update_irq_disabled(d
, was_irq_disabled
);
1163 /***********************************************************/
1164 /* generic PCI irq support */
1166 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1167 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
1169 PCIDevice
*pci_dev
= opaque
;
1172 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1176 pci_set_irq_state(pci_dev
, irq_num
, level
);
1177 pci_update_irq_status(pci_dev
);
1178 if (pci_irq_disabled(pci_dev
))
1180 pci_change_irq_level(pci_dev
, irq_num
, change
);
1183 /***********************************************************/
1184 /* monitor info on PCI */
1189 const char *fw_name
;
1190 uint16_t fw_ign_bits
;
1193 static const pci_class_desc pci_class_descriptions
[] =
1195 { 0x0001, "VGA controller", "display"},
1196 { 0x0100, "SCSI controller", "scsi"},
1197 { 0x0101, "IDE controller", "ide"},
1198 { 0x0102, "Floppy controller", "fdc"},
1199 { 0x0103, "IPI controller", "ipi"},
1200 { 0x0104, "RAID controller", "raid"},
1201 { 0x0106, "SATA controller"},
1202 { 0x0107, "SAS controller"},
1203 { 0x0180, "Storage controller"},
1204 { 0x0200, "Ethernet controller", "ethernet"},
1205 { 0x0201, "Token Ring controller", "token-ring"},
1206 { 0x0202, "FDDI controller", "fddi"},
1207 { 0x0203, "ATM controller", "atm"},
1208 { 0x0280, "Network controller"},
1209 { 0x0300, "VGA controller", "display", 0x00ff},
1210 { 0x0301, "XGA controller"},
1211 { 0x0302, "3D controller"},
1212 { 0x0380, "Display controller"},
1213 { 0x0400, "Video controller", "video"},
1214 { 0x0401, "Audio controller", "sound"},
1216 { 0x0403, "Audio controller", "sound"},
1217 { 0x0480, "Multimedia controller"},
1218 { 0x0500, "RAM controller", "memory"},
1219 { 0x0501, "Flash controller", "flash"},
1220 { 0x0580, "Memory controller"},
1221 { 0x0600, "Host bridge", "host"},
1222 { 0x0601, "ISA bridge", "isa"},
1223 { 0x0602, "EISA bridge", "eisa"},
1224 { 0x0603, "MC bridge", "mca"},
1225 { 0x0604, "PCI bridge", "pci"},
1226 { 0x0605, "PCMCIA bridge", "pcmcia"},
1227 { 0x0606, "NUBUS bridge", "nubus"},
1228 { 0x0607, "CARDBUS bridge", "cardbus"},
1229 { 0x0608, "RACEWAY bridge"},
1230 { 0x0680, "Bridge"},
1231 { 0x0700, "Serial port", "serial"},
1232 { 0x0701, "Parallel port", "parallel"},
1233 { 0x0800, "Interrupt controller", "interrupt-controller"},
1234 { 0x0801, "DMA controller", "dma-controller"},
1235 { 0x0802, "Timer", "timer"},
1236 { 0x0803, "RTC", "rtc"},
1237 { 0x0900, "Keyboard", "keyboard"},
1238 { 0x0901, "Pen", "pen"},
1239 { 0x0902, "Mouse", "mouse"},
1240 { 0x0A00, "Dock station", "dock", 0x00ff},
1241 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1242 { 0x0c00, "Fireware contorller", "fireware"},
1243 { 0x0c01, "Access bus controller", "access-bus"},
1244 { 0x0c02, "SSA controller", "ssa"},
1245 { 0x0c03, "USB controller", "usb"},
1246 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1250 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1251 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1256 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1257 d
= bus
->devices
[devfn
];
1264 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1265 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1267 bus
= pci_find_bus(bus
, bus_num
);
1270 pci_for_each_device_under_bus(bus
, fn
);
1274 static void pci_device_print(Monitor
*mon
, QDict
*device
)
1278 uint64_t addr
, size
;
1280 monitor_printf(mon
, " Bus %2" PRId64
", ", qdict_get_int(device
, "bus"));
1281 monitor_printf(mon
, "device %3" PRId64
", function %" PRId64
":\n",
1282 qdict_get_int(device
, "slot"),
1283 qdict_get_int(device
, "function"));
1284 monitor_printf(mon
, " ");
1286 qdict
= qdict_get_qdict(device
, "class_info");
1287 if (qdict_haskey(qdict
, "desc")) {
1288 monitor_printf(mon
, "%s", qdict_get_str(qdict
, "desc"));
1290 monitor_printf(mon
, "Class %04" PRId64
, qdict_get_int(qdict
, "class"));
1293 qdict
= qdict_get_qdict(device
, "id");
1294 monitor_printf(mon
, ": PCI device %04" PRIx64
":%04" PRIx64
"\n",
1295 qdict_get_int(qdict
, "device"),
1296 qdict_get_int(qdict
, "vendor"));
1298 if (qdict_haskey(device
, "irq")) {
1299 monitor_printf(mon
, " IRQ %" PRId64
".\n",
1300 qdict_get_int(device
, "irq"));
1303 if (qdict_haskey(device
, "pci_bridge")) {
1306 qdict
= qdict_get_qdict(device
, "pci_bridge");
1308 info
= qdict_get_qdict(qdict
, "bus");
1309 monitor_printf(mon
, " BUS %" PRId64
".\n",
1310 qdict_get_int(info
, "number"));
1311 monitor_printf(mon
, " secondary bus %" PRId64
".\n",
1312 qdict_get_int(info
, "secondary"));
1313 monitor_printf(mon
, " subordinate bus %" PRId64
".\n",
1314 qdict_get_int(info
, "subordinate"));
1316 info
= qdict_get_qdict(qdict
, "io_range");
1317 monitor_printf(mon
, " IO range [0x%04"PRIx64
", 0x%04"PRIx64
"]\n",
1318 qdict_get_int(info
, "base"),
1319 qdict_get_int(info
, "limit"));
1321 info
= qdict_get_qdict(qdict
, "memory_range");
1323 " memory range [0x%08"PRIx64
", 0x%08"PRIx64
"]\n",
1324 qdict_get_int(info
, "base"),
1325 qdict_get_int(info
, "limit"));
1327 info
= qdict_get_qdict(qdict
, "prefetchable_range");
1328 monitor_printf(mon
, " prefetchable memory range "
1329 "[0x%08"PRIx64
", 0x%08"PRIx64
"]\n",
1330 qdict_get_int(info
, "base"),
1331 qdict_get_int(info
, "limit"));
1334 QLIST_FOREACH_ENTRY(qdict_get_qlist(device
, "regions"), entry
) {
1335 qdict
= qobject_to_qdict(qlist_entry_obj(entry
));
1336 monitor_printf(mon
, " BAR%d: ", (int) qdict_get_int(qdict
, "bar"));
1338 addr
= qdict_get_int(qdict
, "address");
1339 size
= qdict_get_int(qdict
, "size");
1341 if (!strcmp(qdict_get_str(qdict
, "type"), "io")) {
1342 monitor_printf(mon
, "I/O at 0x%04"FMT_PCIBUS
1343 " [0x%04"FMT_PCIBUS
"].\n",
1344 addr
, addr
+ size
- 1);
1346 monitor_printf(mon
, "%d bit%s memory at 0x%08"FMT_PCIBUS
1347 " [0x%08"FMT_PCIBUS
"].\n",
1348 qdict_get_bool(qdict
, "mem_type_64") ? 64 : 32,
1349 qdict_get_bool(qdict
, "prefetch") ?
1350 " prefetchable" : "", addr
, addr
+ size
- 1);
1354 monitor_printf(mon
, " id \"%s\"\n", qdict_get_str(device
, "qdev_id"));
1356 if (qdict_haskey(device
, "pci_bridge")) {
1357 qdict
= qdict_get_qdict(device
, "pci_bridge");
1358 if (qdict_haskey(qdict
, "devices")) {
1360 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict
, "devices"), dev
) {
1361 pci_device_print(mon
, qobject_to_qdict(qlist_entry_obj(dev
)));
1367 void do_pci_info_print(Monitor
*mon
, const QObject
*data
)
1369 QListEntry
*bus
, *dev
;
1371 QLIST_FOREACH_ENTRY(qobject_to_qlist(data
), bus
) {
1372 QDict
*qdict
= qobject_to_qdict(qlist_entry_obj(bus
));
1373 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict
, "devices"), dev
) {
1374 pci_device_print(mon
, qobject_to_qdict(qlist_entry_obj(dev
)));
1379 static QObject
*pci_get_dev_class(const PCIDevice
*dev
)
1382 const pci_class_desc
*desc
;
1384 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1385 desc
= pci_class_descriptions
;
1386 while (desc
->desc
&& class != desc
->class)
1390 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1393 return qobject_from_jsonf("{ 'class': %d }", class);
1397 static QObject
*pci_get_dev_id(const PCIDevice
*dev
)
1399 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1400 pci_get_word(dev
->config
+ PCI_VENDOR_ID
),
1401 pci_get_word(dev
->config
+ PCI_DEVICE_ID
));
1404 static QObject
*pci_get_regions_list(const PCIDevice
*dev
)
1407 QList
*regions_list
;
1409 regions_list
= qlist_new();
1411 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1413 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1419 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1420 obj
= qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1421 "'address': %" PRId64
", "
1422 "'size': %" PRId64
" }",
1423 i
, r
->addr
, r
->size
);
1425 int mem_type_64
= r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
;
1427 obj
= qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1428 "'mem_type_64': %i, 'prefetch': %i, "
1429 "'address': %" PRId64
", "
1430 "'size': %" PRId64
" }",
1432 r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
,
1436 qlist_append_obj(regions_list
, obj
);
1439 return QOBJECT(regions_list
);
1442 static QObject
*pci_get_devices_list(PCIBus
*bus
, int bus_num
);
1444 static QObject
*pci_get_dev_dict(PCIDevice
*dev
, PCIBus
*bus
, int bus_num
)
1449 obj
= qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1452 PCI_SLOT(dev
->devfn
), PCI_FUNC(dev
->devfn
),
1453 pci_get_dev_class(dev
), pci_get_dev_id(dev
),
1454 pci_get_regions_list(dev
),
1455 dev
->qdev
.id
? dev
->qdev
.id
: "");
1457 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1458 QDict
*qdict
= qobject_to_qdict(obj
);
1459 qdict_put(qdict
, "irq", qint_from_int(dev
->config
[PCI_INTERRUPT_LINE
]));
1462 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1463 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1465 QObject
*pci_bridge
;
1467 pci_bridge
= qobject_from_jsonf("{ 'bus': "
1468 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1469 "'io_range': { 'base': %" PRId64
", 'limit': %" PRId64
"}, "
1470 "'memory_range': { 'base': %" PRId64
", 'limit': %" PRId64
"}, "
1471 "'prefetchable_range': { 'base': %" PRId64
", 'limit': %" PRId64
"} }",
1472 dev
->config
[PCI_PRIMARY_BUS
], dev
->config
[PCI_SECONDARY_BUS
],
1473 dev
->config
[PCI_SUBORDINATE_BUS
],
1474 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
),
1475 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
),
1476 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
),
1477 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
),
1478 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1479 PCI_BASE_ADDRESS_MEM_PREFETCH
),
1480 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1481 PCI_BASE_ADDRESS_MEM_PREFETCH
));
1483 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1484 PCIBus
*child_bus
= pci_find_bus(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1487 qdict
= qobject_to_qdict(pci_bridge
);
1488 qdict_put_obj(qdict
, "devices",
1489 pci_get_devices_list(child_bus
,
1490 dev
->config
[PCI_SECONDARY_BUS
]));
1493 qdict
= qobject_to_qdict(obj
);
1494 qdict_put_obj(qdict
, "pci_bridge", pci_bridge
);
1500 static QObject
*pci_get_devices_list(PCIBus
*bus
, int bus_num
)
1506 dev_list
= qlist_new();
1508 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1509 dev
= bus
->devices
[devfn
];
1511 qlist_append_obj(dev_list
, pci_get_dev_dict(dev
, bus
, bus_num
));
1515 return QOBJECT(dev_list
);
1518 static QObject
*pci_get_bus_dict(PCIBus
*bus
, int bus_num
)
1520 bus
= pci_find_bus(bus
, bus_num
);
1522 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1523 bus_num
, pci_get_devices_list(bus
, bus_num
));
1529 void do_pci_info(Monitor
*mon
, QObject
**ret_data
)
1532 struct PCIHostBus
*host
;
1534 bus_list
= qlist_new();
1536 QLIST_FOREACH(host
, &host_buses
, next
) {
1537 QObject
*obj
= pci_get_bus_dict(host
->bus
, 0);
1539 qlist_append_obj(bus_list
, obj
);
1543 *ret_data
= QOBJECT(bus_list
);
1546 static const char * const pci_nic_models
[] = {
1558 static const char * const pci_nic_names
[] = {
1570 /* Initialize a PCI NIC. */
1571 /* FIXME callers should check for failure, but don't */
1572 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
1573 const char *default_devaddr
)
1575 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1582 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1586 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
1588 error_report("Invalid PCI device address %s for device %s",
1589 devaddr
, pci_nic_names
[i
]);
1593 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1594 dev
= &pci_dev
->qdev
;
1595 qdev_set_nic_properties(dev
, nd
);
1596 if (qdev_init(dev
) < 0)
1601 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
1602 const char *default_devaddr
)
1606 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
1609 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
1615 static void pci_bridge_update_mappings_fn(PCIBus
*b
, PCIDevice
*d
)
1617 pci_update_mappings(d
);
1620 void pci_bridge_update_mappings(PCIBus
*b
)
1624 pci_for_each_device_under_bus(b
, pci_bridge_update_mappings_fn
);
1626 QLIST_FOREACH(child
, &b
->child
, sibling
) {
1627 pci_bridge_update_mappings(child
);
1631 /* Whether a given bus number is in range of the secondary
1632 * bus of the given bridge device. */
1633 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1635 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1636 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1637 dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1638 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1641 PCIBus
*pci_find_bus(PCIBus
*bus
, int bus_num
)
1649 if (pci_bus_num(bus
) == bus_num
) {
1653 /* Consider all bus numbers in range for the host pci bridge. */
1654 if (bus
->parent_dev
&&
1655 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
1660 for (; bus
; bus
= sec
) {
1661 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1662 assert(sec
->parent_dev
);
1663 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] == bus_num
) {
1666 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
1675 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
1677 bus
= pci_find_bus(bus
, bus_num
);
1682 return bus
->devices
[devfn
];
1685 static int pci_qdev_init(DeviceState
*qdev
, DeviceInfo
*base
)
1687 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1688 PCIDeviceInfo
*info
= container_of(base
, PCIDeviceInfo
, qdev
);
1691 bool is_default_rom
;
1693 /* initialize cap_present for pci_is_express() and pci_config_size() */
1694 if (info
->is_express
) {
1695 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1698 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
1699 pci_dev
= do_pci_register_device(pci_dev
, bus
, base
->name
,
1700 pci_dev
->devfn
, info
);
1701 if (pci_dev
== NULL
)
1703 if (qdev
->hotplugged
&& info
->no_hotplug
) {
1704 qerror_report(QERR_DEVICE_NO_HOTPLUG
, info
->qdev
.name
);
1705 do_pci_unregister_device(pci_dev
);
1709 rc
= info
->init(pci_dev
);
1711 do_pci_unregister_device(pci_dev
);
1717 is_default_rom
= false;
1718 if (pci_dev
->romfile
== NULL
&& info
->romfile
!= NULL
) {
1719 pci_dev
->romfile
= qemu_strdup(info
->romfile
);
1720 is_default_rom
= true;
1722 pci_add_option_rom(pci_dev
, is_default_rom
);
1725 /* Let buses differentiate between hotplug and when device is
1726 * enabled during qemu machine creation. */
1727 rc
= bus
->hotplug(bus
->hotplug_qdev
, pci_dev
,
1728 qdev
->hotplugged
? PCI_HOTPLUG_ENABLED
:
1729 PCI_COLDPLUG_ENABLED
);
1731 int r
= pci_unregister_device(&pci_dev
->qdev
);
1739 static int pci_unplug_device(DeviceState
*qdev
)
1741 PCIDevice
*dev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
1742 PCIDeviceInfo
*info
= container_of(qdev
->info
, PCIDeviceInfo
, qdev
);
1744 if (info
->no_hotplug
) {
1745 qerror_report(QERR_DEVICE_NO_HOTPLUG
, info
->qdev
.name
);
1748 return dev
->bus
->hotplug(dev
->bus
->hotplug_qdev
, dev
,
1749 PCI_HOTPLUG_DISABLED
);
1752 void pci_qdev_register(PCIDeviceInfo
*info
)
1754 info
->qdev
.init
= pci_qdev_init
;
1755 info
->qdev
.unplug
= pci_unplug_device
;
1756 info
->qdev
.exit
= pci_unregister_device
;
1757 info
->qdev
.bus_info
= &pci_bus_info
;
1758 qdev_register(&info
->qdev
);
1761 void pci_qdev_register_many(PCIDeviceInfo
*info
)
1763 while (info
->qdev
.name
) {
1764 pci_qdev_register(info
);
1769 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
1774 dev
= qdev_create(&bus
->qbus
, name
);
1775 qdev_prop_set_uint32(dev
, "addr", devfn
);
1776 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
1777 return DO_UPCAST(PCIDevice
, qdev
, dev
);
1780 PCIDevice
*pci_try_create_multifunction(PCIBus
*bus
, int devfn
,
1786 dev
= qdev_try_create(&bus
->qbus
, name
);
1790 qdev_prop_set_uint32(dev
, "addr", devfn
);
1791 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
1792 return DO_UPCAST(PCIDevice
, qdev
, dev
);
1795 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
1799 PCIDevice
*dev
= pci_create_multifunction(bus
, devfn
, multifunction
, name
);
1800 qdev_init_nofail(&dev
->qdev
);
1804 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1806 return pci_create_multifunction(bus
, devfn
, false, name
);
1809 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1811 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
1814 PCIDevice
*pci_try_create(PCIBus
*bus
, int devfn
, const char *name
)
1816 return pci_try_create_multifunction(bus
, devfn
, false, name
);
1819 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1821 int config_size
= pci_config_size(pdev
);
1822 int offset
= PCI_CONFIG_HEADER_SIZE
;
1824 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< config_size
; ++i
)
1827 else if (i
- offset
+ 1 == size
)
1832 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1837 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1840 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1841 prev
= next
+ PCI_CAP_LIST_NEXT
)
1842 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1850 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1851 This is needed for an option rom which is used for more than one device. */
1852 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, int size
)
1856 uint16_t rom_vendor_id
;
1857 uint16_t rom_device_id
;
1859 uint16_t pcir_offset
;
1862 /* Words in rom data are little endian (like in PCI configuration),
1863 so they can be read / written with pci_get_word / pci_set_word. */
1865 /* Only a valid rom will be patched. */
1866 rom_magic
= pci_get_word(ptr
);
1867 if (rom_magic
!= 0xaa55) {
1868 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
1871 pcir_offset
= pci_get_word(ptr
+ 0x18);
1872 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
1873 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
1877 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
1878 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
1879 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
1880 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
1882 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
1883 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
1887 if (vendor_id
!= rom_vendor_id
) {
1888 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1889 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
1890 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
1891 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1893 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
1896 if (device_id
!= rom_device_id
) {
1897 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1898 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
1899 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
1900 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1902 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
1906 /* Add an option rom for the device */
1907 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
)
1916 if (strlen(pdev
->romfile
) == 0)
1919 if (!pdev
->rom_bar
) {
1921 * Load rom via fw_cfg instead of creating a rom bar,
1922 * for 0.11 compatibility.
1924 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1925 if (class == 0x0300) {
1926 rom_add_vga(pdev
->romfile
);
1928 rom_add_option(pdev
->romfile
, -1);
1933 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
1935 path
= qemu_strdup(pdev
->romfile
);
1938 size
= get_image_size(path
);
1940 error_report("%s: failed to find romfile \"%s\"",
1941 __FUNCTION__
, pdev
->romfile
);
1945 if (size
& (size
- 1)) {
1946 size
= 1 << qemu_fls(size
);
1949 if (pdev
->qdev
.info
->vmsd
)
1950 snprintf(name
, sizeof(name
), "%s.rom", pdev
->qdev
.info
->vmsd
->name
);
1952 snprintf(name
, sizeof(name
), "%s.rom", pdev
->qdev
.info
->name
);
1953 pdev
->has_rom
= true;
1954 memory_region_init_ram(&pdev
->rom
, &pdev
->qdev
, name
, size
);
1955 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
1956 load_image(path
, ptr
);
1959 if (is_default_rom
) {
1960 /* Only the default rom images will be patched (if needed). */
1961 pci_patch_ids(pdev
, ptr
, size
);
1964 qemu_put_ram_ptr(ptr
);
1966 pci_register_bar_region(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
1971 static void pci_del_option_rom(PCIDevice
*pdev
)
1976 memory_region_destroy(&pdev
->rom
);
1977 pdev
->has_rom
= false;
1982 * Reserve space and add capability to the linked list in pci config space
1985 * Find and reserve space and add capability to the linked list
1986 * in pci config space */
1987 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
1988 uint8_t offset
, uint8_t size
)
1992 offset
= pci_find_space(pdev
, size
);
1998 config
= pdev
->config
+ offset
;
1999 config
[PCI_CAP_LIST_ID
] = cap_id
;
2000 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
2001 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
2002 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2003 memset(pdev
->used
+ offset
, 0xFF, size
);
2004 /* Make capability read-only by default */
2005 memset(pdev
->wmask
+ offset
, 0, size
);
2006 /* Check capability by default */
2007 memset(pdev
->cmask
+ offset
, 0xFF, size
);
2011 /* Unlink capability from the pci config space. */
2012 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
2014 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
2017 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
2018 /* Make capability writable again */
2019 memset(pdev
->wmask
+ offset
, 0xff, size
);
2020 memset(pdev
->w1cmask
+ offset
, 0, size
);
2021 /* Clear cmask as device-specific registers can't be checked */
2022 memset(pdev
->cmask
+ offset
, 0, size
);
2023 memset(pdev
->used
+ offset
, 0, size
);
2025 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
2026 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
2029 /* Reserve space for capability at a known offset (to call after load). */
2030 void pci_reserve_capability(PCIDevice
*pdev
, uint8_t offset
, uint8_t size
)
2032 memset(pdev
->used
+ offset
, 0xff, size
);
2035 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
2037 return pci_find_capability_list(pdev
, cap_id
, NULL
);
2040 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
2042 PCIDevice
*d
= (PCIDevice
*)dev
;
2043 const pci_class_desc
*desc
;
2048 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2049 desc
= pci_class_descriptions
;
2050 while (desc
->desc
&& class != desc
->class)
2053 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
2055 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
2058 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
2059 "pci id %04x:%04x (sub %04x:%04x)\n",
2060 indent
, "", ctxt
, pci_bus_num(d
->bus
),
2061 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
2062 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2063 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
2064 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
2065 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
2066 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
2067 r
= &d
->io_regions
[i
];
2070 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2071 " [0x%"FMT_PCIBUS
"]\n",
2073 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
2074 r
->addr
, r
->addr
+ r
->size
- 1);
2078 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
2080 PCIDevice
*d
= (PCIDevice
*)dev
;
2081 const char *name
= NULL
;
2082 const pci_class_desc
*desc
= pci_class_descriptions
;
2083 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2085 while (desc
->desc
&&
2086 (class & ~desc
->fw_ign_bits
) !=
2087 (desc
->class & ~desc
->fw_ign_bits
)) {
2092 name
= desc
->fw_name
;
2096 pstrcpy(buf
, len
, name
);
2098 snprintf(buf
, len
, "pci%04x,%04x",
2099 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2100 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
2106 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
2108 PCIDevice
*d
= (PCIDevice
*)dev
;
2109 char path
[50], name
[33];
2112 off
= snprintf(path
, sizeof(path
), "%s@%x",
2113 pci_dev_fw_name(dev
, name
, sizeof name
),
2114 PCI_SLOT(d
->devfn
));
2115 if (PCI_FUNC(d
->devfn
))
2116 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
2117 return strdup(path
);
2120 static char *pcibus_get_dev_path(DeviceState
*dev
)
2122 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
2125 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2126 * 00 is added here to make this format compatible with
2127 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2128 * Slot.Function list specifies the slot and function numbers for all
2129 * devices on the path from root to the specific device. */
2130 char domain
[] = "DDDD:00";
2131 char slot
[] = ":SS.F";
2132 int domain_len
= sizeof domain
- 1 /* For '\0' */;
2133 int slot_len
= sizeof slot
- 1 /* For '\0' */;
2138 /* Calculate # of slots on path between device and root. */;
2140 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
2144 path_len
= domain_len
+ slot_len
* slot_depth
;
2146 /* Allocate memory, fill in the terminating null byte. */
2147 path
= qemu_malloc(path_len
+ 1 /* For '\0' */);
2148 path
[path_len
] = '\0';
2150 /* First field is the domain. */
2151 s
= snprintf(domain
, sizeof domain
, "%04x:00", pci_find_domain(d
->bus
));
2152 assert(s
== domain_len
);
2153 memcpy(path
, domain
, domain_len
);
2155 /* Fill in slot numbers. We walk up from device to root, so need to print
2156 * them in the reverse order, last to first. */
2157 p
= path
+ path_len
;
2158 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
2160 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
2161 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
2162 assert(s
== slot_len
);
2163 memcpy(p
, slot
, slot_len
);
2169 static int pci_qdev_find_recursive(PCIBus
*bus
,
2170 const char *id
, PCIDevice
**pdev
)
2172 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
2177 /* roughly check if given qdev is pci device */
2178 if (qdev
->info
->init
== &pci_qdev_init
&&
2179 qdev
->parent_bus
->info
== &pci_bus_info
) {
2180 *pdev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
2186 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
2188 struct PCIHostBus
*host
;
2191 QLIST_FOREACH(host
, &host_buses
, next
) {
2192 int tmp
= pci_qdev_find_recursive(host
->bus
, id
, pdev
);
2197 if (tmp
!= -ENODEV
) {