hw/apb_pci.c

   1 /*
   2  * QEMU Ultrasparc APB PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 /* XXX This file and most of its contents are somewhat misnamed.  The
  26    Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
  27    the secondary PCI bridge.  */
  28
  29 #include "sysbus.h"
  30 #include "pci.h"
  31 #include "pci_host.h"
  32 #include "pci_bridge.h"
  33 #include "pci_internals.h"
  34 #include "rwhandler.h"
  35 #include "apb_pci.h"
  36 #include "sysemu.h"
  37 #include "exec-memory.h"
  38
  39 /* debug APB */
  40 //#define DEBUG_APB
  41
  42 #ifdef DEBUG_APB
  43 #define APB_DPRINTF(fmt, ...) \
  44 do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
  45 #else
  46 #define APB_DPRINTF(fmt, ...)
  47 #endif
  48
  49 /*
  50  * Chipset docs:
  51  * PBM: "UltraSPARC IIi User's Manual",
  52  * http://www.sun.com/processors/manuals/805-0087.pdf
  53  *
  54  * APB: "Advanced PCI Bridge (APB) User's Manual",
  55  * http://www.sun.com/processors/manuals/805-1251.pdf
  56  */
  57
  58 #define PBM_PCI_IMR_MASK    0x7fffffff
  59 #define PBM_PCI_IMR_ENABLED 0x80000000
  60
  61 #define POR          (1 << 31)
  62 #define SOFT_POR     (1 << 30)
  63 #define SOFT_XIR     (1 << 29)
  64 #define BTN_POR      (1 << 28)
  65 #define BTN_XIR      (1 << 27)
  66 #define RESET_MASK   0xf8000000
  67 #define RESET_WCMASK 0x98000000
  68 #define RESET_WMASK  0x60000000
  69
  70 typedef struct APBState {
  71     SysBusDevice busdev;
  72     PCIBus      *bus;
  73     ReadWriteHandler pci_config_handler;
  74     uint32_t iommu[4];
  75     uint32_t pci_control[16];
  76     uint32_t pci_irq_map[8];
  77     uint32_t obio_irq_map[32];
  78     qemu_irq pci_irqs[32];
  79     uint32_t reset_control;
  80     unsigned int nr_resets;
  81 } APBState;
  82
  83 static void apb_config_writel (void *opaque, target_phys_addr_t addr,
  84                                uint32_t val)
  85 {
  86     APBState *s = opaque;
  87
  88     APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
  89
  90     switch (addr & 0xffff) {
  91     case 0x30 ... 0x4f: /* DMA error registers */
  92         /* XXX: not implemented yet */
  93         break;
  94     case 0x200 ... 0x20b: /* IOMMU */
  95         s->iommu[(addr & 0xf) >> 2] = val;
  96         break;
  97     case 0x20c ... 0x3ff: /* IOMMU flush */
  98         break;
  99     case 0xc00 ... 0xc3f: /* PCI interrupt control */
 100         if (addr & 4) {
 101             s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
 102             s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
 103         }
 104         break;
 105     case 0x2000 ... 0x202f: /* PCI control */
 106         s->pci_control[(addr & 0x3f) >> 2] = val;
 107         break;
 108     case 0xf020 ... 0xf027: /* Reset control */
 109         if (addr & 4) {
 110             val &= RESET_MASK;
 111             s->reset_control &= ~(val & RESET_WCMASK);
 112             s->reset_control |= val & RESET_WMASK;
 113             if (val & SOFT_POR) {
 114                 s->nr_resets = 0;
 115                 qemu_system_reset_request();
 116             } else if (val & SOFT_XIR) {
 117                 qemu_system_reset_request();
 118             }
 119         }
 120         break;
 121     case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
 122     case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
 123     case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
 124     case 0xf000 ... 0xf01f: /* FFB config, memory control */
 125         /* we don't care */
 126     default:
 127         break;
 128     }
 129 }
 130
 131 static uint32_t apb_config_readl (void *opaque,
 132                                   target_phys_addr_t addr)
 133 {
 134     APBState *s = opaque;
 135     uint32_t val;
 136
 137     switch (addr & 0xffff) {
 138     case 0x30 ... 0x4f: /* DMA error registers */
 139         val = 0;
 140         /* XXX: not implemented yet */
 141         break;
 142     case 0x200 ... 0x20b: /* IOMMU */
 143         val = s->iommu[(addr & 0xf) >> 2];
 144         break;
 145     case 0x20c ... 0x3ff: /* IOMMU flush */
 146         val = 0;
 147         break;
 148     case 0xc00 ... 0xc3f: /* PCI interrupt control */
 149         if (addr & 4) {
 150             val = s->pci_irq_map[(addr & 0x3f) >> 3];
 151         } else {
 152             val = 0;
 153         }
 154         break;
 155     case 0x2000 ... 0x202f: /* PCI control */
 156         val = s->pci_control[(addr & 0x3f) >> 2];
 157         break;
 158     case 0xf020 ... 0xf027: /* Reset control */
 159         if (addr & 4) {
 160             val = s->reset_control;
 161         } else {
 162             val = 0;
 163         }
 164         break;
 165     case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
 166     case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
 167     case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
 168     case 0xf000 ... 0xf01f: /* FFB config, memory control */
 169         /* we don't care */
 170     default:
 171         val = 0;
 172         break;
 173     }
 174     APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);
 175
 176     return val;
 177 }
 178
 179 static CPUWriteMemoryFunc * const apb_config_write[] = {
 180     &apb_config_writel,
 181     &apb_config_writel,
 182     &apb_config_writel,
 183 };
 184
 185 static CPUReadMemoryFunc * const apb_config_read[] = {
 186     &apb_config_readl,
 187     &apb_config_readl,
 188     &apb_config_readl,
 189 };
 190
 191 static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
 192                                  uint32_t val, int size)
 193 {
 194     APBState *s = container_of(h, APBState, pci_config_handler);
 195
 196     val = qemu_bswap_len(val, size);
 197     APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
 198     pci_data_write(s->bus, addr, val, size);
 199 }
 200
 201 static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
 202                                     int size)
 203 {
 204     uint32_t ret;
 205     APBState *s = container_of(h, APBState, pci_config_handler);
 206
 207     ret = pci_data_read(s->bus, addr, size);
 208     ret = qemu_bswap_len(ret, size);
 209     APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
 210     return ret;
 211 }
 212
 213 static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
 214                                   uint32_t val)
 215 {
 216     cpu_outb(addr & IOPORTS_MASK, val);
 217 }
 218
 219 static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
 220                                   uint32_t val)
 221 {
 222     cpu_outw(addr & IOPORTS_MASK, bswap16(val));
 223 }
 224
 225 static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
 226                                 uint32_t val)
 227 {
 228     cpu_outl(addr & IOPORTS_MASK, bswap32(val));
 229 }
 230
 231 static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
 232 {
 233     uint32_t val;
 234
 235     val = cpu_inb(addr & IOPORTS_MASK);
 236     return val;
 237 }
 238
 239 static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
 240 {
 241     uint32_t val;
 242
 243     val = bswap16(cpu_inw(addr & IOPORTS_MASK));
 244     return val;
 245 }
 246
 247 static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
 248 {
 249     uint32_t val;
 250
 251     val = bswap32(cpu_inl(addr & IOPORTS_MASK));
 252     return val;
 253 }
 254
 255 static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
 256     &pci_apb_iowriteb,
 257     &pci_apb_iowritew,
 258     &pci_apb_iowritel,
 259 };
 260
 261 static CPUReadMemoryFunc * const pci_apb_ioread[] = {
 262     &pci_apb_ioreadb,
 263     &pci_apb_ioreadw,
 264     &pci_apb_ioreadl,
 265 };
 266
 267 /* The APB host has an IRQ line for each IRQ line of each slot.  */
 268 static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
 269 {
 270     return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
 271 }
 272
 273 static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
 274 {
 275     int bus_offset;
 276     if (pci_dev->devfn & 1)
 277         bus_offset = 16;
 278     else
 279         bus_offset = 0;
 280     return bus_offset + irq_num;
 281 }
 282
 283 static void pci_apb_set_irq(void *opaque, int irq_num, int level)
 284 {
 285     APBState *s = opaque;
 286
 287     /* PCI IRQ map onto the first 32 INO.  */
 288     if (irq_num < 32) {
 289         if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
 290             APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
 291             qemu_set_irq(s->pci_irqs[irq_num], level);
 292         } else {
 293             APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
 294             qemu_irq_lower(s->pci_irqs[irq_num]);
 295         }
 296     }
 297 }
 298
 299 static int apb_pci_bridge_initfn(PCIDevice *dev)
 300 {
 301     int rc;
 302
 303     rc = pci_bridge_initfn(dev);
 304     if (rc < 0) {
 305         return rc;
 306     }
 307
 308     /*
 309      * command register:
 310      * According to PCI bridge spec, after reset
 311      *   bus master bit is off
 312      *   memory space enable bit is off
 313      * According to manual (805-1251.pdf).
 314      *   the reset value should be zero unless the boot pin is tied high
 315      *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
 316      */
 317     pci_set_word(dev->config + PCI_COMMAND,
 318                  PCI_COMMAND_MEMORY);
 319     pci_set_word(dev->config + PCI_STATUS,
 320                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
 321                  PCI_STATUS_DEVSEL_MEDIUM);
 322     return 0;
 323 }
 324
 325 PCIBus *pci_apb_init(target_phys_addr_t special_base,
 326                      target_phys_addr_t mem_base,
 327                      qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
 328 {
 329     DeviceState *dev;
 330     SysBusDevice *s;
 331     APBState *d;
 332     unsigned int i;
 333     PCIDevice *pci_dev;
 334     PCIBridge *br;
 335
 336     /* Ultrasparc PBM main bus */
 337     dev = qdev_create(NULL, "pbm");
 338     qdev_init_nofail(dev);
 339     s = sysbus_from_qdev(dev);
 340     /* apb_config */
 341     sysbus_mmio_map(s, 0, special_base);
 342     /* PCI configuration space */
 343     sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
 344     /* pci_ioport */
 345     sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
 346     d = FROM_SYSBUS(APBState, s);
 347
 348     d->bus = pci_register_bus(&d->busdev.qdev, "pci",
 349                                          pci_apb_set_irq, pci_pbm_map_irq, d,
 350                                          get_system_memory(),
 351                                          get_system_io(),
 352                                          0, 32);
 353     pci_bus_set_mem_base(d->bus, mem_base);
 354
 355     for (i = 0; i < 32; i++) {
 356         sysbus_connect_irq(s, i, pic[i]);
 357     }
 358
 359     pci_create_simple(d->bus, 0, "pbm");
 360
 361     /* APB secondary busses */
 362     pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
 363                                    "pbm-bridge");
 364     br = DO_UPCAST(PCIBridge, dev, pci_dev);
 365     pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
 366                        pci_apb_map_irq);
 367     qdev_init_nofail(&pci_dev->qdev);
 368     *bus2 = pci_bridge_get_sec_bus(br);
 369
 370     pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true,
 371                                    "pbm-bridge");
 372     br = DO_UPCAST(PCIBridge, dev, pci_dev);
 373     pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
 374                        pci_apb_map_irq);
 375     qdev_init_nofail(&pci_dev->qdev);
 376     *bus3 = pci_bridge_get_sec_bus(br);
 377
 378     return d->bus;
 379 }
 380
 381 static void pci_pbm_reset(DeviceState *d)
 382 {
 383     unsigned int i;
 384     APBState *s = container_of(d, APBState, busdev.qdev);
 385
 386     for (i = 0; i < 8; i++) {
 387         s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
 388     }
 389
 390     if (s->nr_resets++ == 0) {
 391         /* Power on reset */
 392         s->reset_control = POR;
 393     }
 394 }
 395
 396 static int pci_pbm_init_device(SysBusDevice *dev)
 397 {
 398     APBState *s;
 399     int pci_config, apb_config, pci_ioport;
 400     unsigned int i;
 401
 402     s = FROM_SYSBUS(APBState, dev);
 403     for (i = 0; i < 8; i++) {
 404         s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
 405     }
 406     for (i = 0; i < 32; i++) {
 407         sysbus_init_irq(dev, &s->pci_irqs[i]);
 408     }
 409
 410     /* apb_config */
 411     apb_config = cpu_register_io_memory(apb_config_read,
 412                                         apb_config_write, s,
 413                                         DEVICE_NATIVE_ENDIAN);
 414     /* at region 0 */
 415     sysbus_init_mmio(dev, 0x10000ULL, apb_config);
 416
 417     /* PCI configuration space */
 418     s->pci_config_handler.read = apb_pci_config_read;
 419     s->pci_config_handler.write = apb_pci_config_write;
 420     pci_config = cpu_register_io_memory_simple(&s->pci_config_handler,
 421                                                DEVICE_NATIVE_ENDIAN);
 422     assert(pci_config >= 0);
 423     /* at region 1 */
 424     sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
 425
 426     /* pci_ioport */
 427     pci_ioport = cpu_register_io_memory(pci_apb_ioread,
 428                                         pci_apb_iowrite, s,
 429                                         DEVICE_NATIVE_ENDIAN);
 430     /* at region 2 */
 431     sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
 432
 433     return 0;
 434 }
 435
 436 static int pbm_pci_host_init(PCIDevice *d)
 437 {
 438     pci_set_word(d->config + PCI_COMMAND,
 439                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 440     pci_set_word(d->config + PCI_STATUS,
 441                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
 442                  PCI_STATUS_DEVSEL_MEDIUM);
 443     return 0;
 444 }
 445
 446 static PCIDeviceInfo pbm_pci_host_info = {
 447     .qdev.name = "pbm",
 448     .qdev.size = sizeof(PCIDevice),
 449     .init      = pbm_pci_host_init,
 450     .vendor_id = PCI_VENDOR_ID_SUN,
 451     .device_id = PCI_DEVICE_ID_SUN_SABRE,
 452     .class_id  = PCI_CLASS_BRIDGE_HOST,
 453     .is_bridge = 1,
 454 };
 455
 456 static SysBusDeviceInfo pbm_host_info = {
 457     .qdev.name = "pbm",
 458     .qdev.size = sizeof(APBState),
 459     .qdev.reset = pci_pbm_reset,
 460     .init = pci_pbm_init_device,
 461 };
 462
 463 static PCIDeviceInfo pbm_pci_bridge_info = {
 464     .qdev.name = "pbm-bridge",
 465     .qdev.size = sizeof(PCIBridge),
 466     .qdev.vmsd = &vmstate_pci_device,
 467     .qdev.reset = pci_bridge_reset,
 468     .init = apb_pci_bridge_initfn,
 469     .exit = pci_bridge_exitfn,
 470     .vendor_id = PCI_VENDOR_ID_SUN,
 471     .device_id = PCI_DEVICE_ID_SUN_SIMBA,
 472     .revision = 0x11,
 473     .config_write = pci_bridge_write_config,
 474     .is_bridge = 1,
 475 };
 476
 477 static void pbm_register_devices(void)
 478 {
 479     sysbus_register_withprop(&pbm_host_info);
 480     pci_qdev_register(&pbm_pci_host_info);
 481     pci_qdev_register(&pbm_pci_bridge_info);
 482 }
 483
 484 device_init(pbm_register_devices)