hw/prep_pci.c

   1 /*
   2  * QEMU PREP PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pci.h"
  27 #include "pci_host.h"
  28
  29 typedef PCIHostState PREPPCIState;
  30
  31 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
  32 {
  33     int i;
  34
  35     for(i = 0; i < 11; i++) {
  36         if ((addr & (1 << (11 + i))) != 0)
  37             break;
  38     }
  39     return (addr & 0x7ff) |  (i << 11);
  40 }
  41
  42 static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
  43 {
  44     PREPPCIState *s = opaque;
  45     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
  46 }
  47
  48 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
  49 {
  50     PREPPCIState *s = opaque;
  51 #ifdef TARGET_WORDS_BIGENDIAN
  52     val = bswap16(val);
  53 #endif
  54     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
  55 }
  56
  57 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
  58 {
  59     PREPPCIState *s = opaque;
  60 #ifdef TARGET_WORDS_BIGENDIAN
  61     val = bswap32(val);
  62 #endif
  63     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
  64 }
  65
  66 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
  67 {
  68     PREPPCIState *s = opaque;
  69     uint32_t val;
  70     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
  71     return val;
  72 }
  73
  74 static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
  75 {
  76     PREPPCIState *s = opaque;
  77     uint32_t val;
  78     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
  79 #ifdef TARGET_WORDS_BIGENDIAN
  80     val = bswap16(val);
  81 #endif
  82     return val;
  83 }
  84
  85 static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
  86 {
  87     PREPPCIState *s = opaque;
  88     uint32_t val;
  89     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
  90 #ifdef TARGET_WORDS_BIGENDIAN
  91     val = bswap32(val);
  92 #endif
  93     return val;
  94 }
  95
  96 static CPUWriteMemoryFunc * const PPC_PCIIO_write[] = {
  97     &PPC_PCIIO_writeb,
  98     &PPC_PCIIO_writew,
  99     &PPC_PCIIO_writel,
 100 };
 101
 102 static CPUReadMemoryFunc * const PPC_PCIIO_read[] = {
 103     &PPC_PCIIO_readb,
 104     &PPC_PCIIO_readw,
 105     &PPC_PCIIO_readl,
 106 };
 107
 108 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
 109 {
 110     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 111 }
 112
 113 static void prep_set_irq(void *opaque, int irq_num, int level)
 114 {
 115     qemu_irq *pic = opaque;
 116
 117     qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
 118 }
 119
 120 PCIBus *pci_prep_init(qemu_irq *pic)
 121 {
 122     PREPPCIState *s;
 123     PCIDevice *d;
 124     int PPC_io_memory;
 125
 126     s = qemu_mallocz(sizeof(PREPPCIState));
 127     s->bus = pci_register_bus(NULL, "pci",
 128                               prep_set_irq, prep_map_irq, pic, 0, 4);
 129
 130     pci_host_config_register_ioport(0xcf8, s);
 131
 132     pci_host_data_register_ioport(0xcfc, s);
 133
 134     PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read,
 135                                            PPC_PCIIO_write, s);
 136     cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
 137
 138     /* PCI host bridge */
 139     d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
 140                             sizeof(PCIDevice), 0, NULL, NULL);
 141     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
 142     pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
 143     d->config[0x08] = 0x00; // revision
 144     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
 145     d->config[0x0C] = 0x08; // cache_line_size
 146     d->config[0x0D] = 0x10; // latency_timer
 147     d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 148     d->config[0x34] = 0x00; // capabilities_pointer
 149
 150     return s->bus;
 151 }