Merge branch 'master' of git://git.qemu.org/qemu
[qemu/mdroth.git] / hw / pci.h
blobd7ad7fb95fe0cad29d03e762e148f307dfeac5c4
1 #ifndef QEMU_PCI_H
2 #define QEMU_PCI_H
4 #include "qemu-common.h"
5 #include "qobject.h"
7 #include "qdev.h"
8 #include "memory.h"
10 /* PCI includes legacy ISA access. */
11 #include "isa.h"
13 #include "pcie.h"
15 /* PCI bus */
17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
19 #define PCI_FUNC(devfn) ((devfn) & 0x07)
20 #define PCI_SLOT_MAX 32
21 #define PCI_FUNC_MAX 8
23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
24 #include "pci_ids.h"
26 /* QEMU-specific Vendor and Device ID definitions */
28 /* IBM (0x1014) */
29 #define PCI_DEVICE_ID_IBM_440GX 0x027f
30 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
32 /* Hitachi (0x1054) */
33 #define PCI_VENDOR_ID_HITACHI 0x1054
34 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
36 /* Apple (0x106b) */
37 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
41 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
43 /* Realtek (0x10ec) */
44 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
46 /* Xilinx (0x10ee) */
47 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
49 /* Marvell (0x11ab) */
50 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
52 /* QEMU/Bochs VGA (0x1234) */
53 #define PCI_VENDOR_ID_QEMU 0x1234
54 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
56 /* VMWare (0x15ad) */
57 #define PCI_VENDOR_ID_VMWARE 0x15ad
58 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
59 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
60 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
61 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
62 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
64 /* Intel (0x8086) */
65 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
66 #define PCI_DEVICE_ID_INTEL_82557 0x1229
67 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
70 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
72 #define PCI_SUBDEVICE_ID_QEMU 0x1100
74 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
75 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
76 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
79 #define FMT_PCIBUS PRIx64
81 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
82 uint32_t address, uint32_t data, int len);
83 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
84 uint32_t address, int len);
85 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
86 pcibus_t addr, pcibus_t size, int type);
87 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
89 typedef struct PCIIORegion {
90 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
91 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
92 pcibus_t size;
93 pcibus_t filtered_size;
94 uint8_t type;
95 MemoryRegion *memory;
96 MemoryRegion *address_space;
97 } PCIIORegion;
99 #define PCI_ROM_SLOT 6
100 #define PCI_NUM_REGIONS 7
102 #include "pci_regs.h"
104 /* PCI HEADER_TYPE */
105 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
107 /* Size of the standard PCI config header */
108 #define PCI_CONFIG_HEADER_SIZE 0x40
109 /* Size of the standard PCI config space */
110 #define PCI_CONFIG_SPACE_SIZE 0x100
111 /* Size of the standart PCIe config space: 4KB */
112 #define PCIE_CONFIG_SPACE_SIZE 0x1000
114 #define PCI_NUM_PINS 4 /* A-D */
116 /* Bits in cap_present field. */
117 enum {
118 QEMU_PCI_CAP_MSI = 0x1,
119 QEMU_PCI_CAP_MSIX = 0x2,
120 QEMU_PCI_CAP_EXPRESS = 0x4,
122 /* multifunction capable device */
123 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
124 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
126 /* command register SERR bit enabled */
127 #define QEMU_PCI_CAP_SERR_BITNR 4
128 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
131 struct PCIDevice {
132 DeviceState qdev;
133 /* PCI config space */
134 uint8_t *config;
136 /* Used to enable config checks on load. Note that writable bits are
137 * never checked even if set in cmask. */
138 uint8_t *cmask;
140 /* Used to implement R/W bytes */
141 uint8_t *wmask;
143 /* Used to implement RW1C(Write 1 to Clear) bytes */
144 uint8_t *w1cmask;
146 /* Used to allocate config space for capabilities. */
147 uint8_t *used;
149 /* the following fields are read only */
150 PCIBus *bus;
151 uint32_t devfn;
152 char name[64];
153 PCIIORegion io_regions[PCI_NUM_REGIONS];
155 /* do not access the following fields */
156 PCIConfigReadFunc *config_read;
157 PCIConfigWriteFunc *config_write;
159 /* IRQ objects for the INTA-INTD pins. */
160 qemu_irq *irq;
162 /* Current IRQ levels. Used internally by the generic PCI code. */
163 uint8_t irq_state;
165 /* Capability bits */
166 uint32_t cap_present;
168 /* Offset of MSI-X capability in config space */
169 uint8_t msix_cap;
171 /* MSI-X entries */
172 int msix_entries_nr;
174 /* Space to store MSIX table */
175 uint8_t *msix_table_page;
176 /* MMIO index used to map MSIX table and pending bit entries. */
177 MemoryRegion msix_mmio;
178 /* Reference-count for entries actually in use by driver. */
179 unsigned *msix_entry_used;
180 /* Region including the MSI-X table */
181 uint32_t msix_bar_size;
182 /* Version id needed for VMState */
183 int32_t version_id;
185 /* Offset of MSI capability in config space */
186 uint8_t msi_cap;
188 /* PCI Express */
189 PCIExpressDevice exp;
191 /* Location of option rom */
192 char *romfile;
193 bool has_rom;
194 MemoryRegion rom;
195 uint32_t rom_bar;
198 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
199 int instance_size, int devfn,
200 PCIConfigReadFunc *config_read,
201 PCIConfigWriteFunc *config_write);
203 void pci_register_bar(PCIDevice *pci_dev, int region_num,
204 uint8_t attr, MemoryRegion *memory);
205 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
207 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
208 uint8_t offset, uint8_t size);
210 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
212 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
214 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
217 uint32_t pci_default_read_config(PCIDevice *d,
218 uint32_t address, int len);
219 void pci_default_write_config(PCIDevice *d,
220 uint32_t address, uint32_t val, int len);
221 void pci_device_save(PCIDevice *s, QEMUFile *f);
222 int pci_device_load(PCIDevice *s, QEMUFile *f);
224 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
225 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
227 typedef enum {
228 PCI_HOTPLUG_DISABLED,
229 PCI_HOTPLUG_ENABLED,
230 PCI_COLDPLUG_ENABLED,
231 } PCIHotplugState;
233 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
234 PCIHotplugState state);
235 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
236 const char *name,
237 MemoryRegion *address_space_mem,
238 MemoryRegion *address_space_io,
239 uint8_t devfn_min);
240 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
241 MemoryRegion *address_space_mem,
242 MemoryRegion *address_space_io,
243 uint8_t devfn_min);
244 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
245 void *irq_opaque, int nirq);
246 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
247 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
248 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
249 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
250 void *irq_opaque,
251 MemoryRegion *address_space_mem,
252 MemoryRegion *address_space_io,
253 uint8_t devfn_min, int nirq);
254 void pci_device_reset(PCIDevice *dev);
255 void pci_bus_reset(PCIBus *bus);
257 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
259 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
260 const char *default_devaddr);
261 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
262 const char *default_devaddr);
263 int pci_bus_num(PCIBus *s);
264 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
265 PCIBus *pci_find_root_bus(int domain);
266 int pci_find_domain(const PCIBus *bus);
267 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
268 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
269 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
270 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
272 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
273 unsigned int *slotp, unsigned int *funcp);
274 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
275 unsigned *slotp);
277 void do_pci_info_print(Monitor *mon, const QObject *data);
278 void do_pci_info(Monitor *mon, QObject **ret_data);
279 void pci_bridge_update_mappings(PCIBus *b);
281 void pci_device_deassert_intx(PCIDevice *dev);
283 static inline void
284 pci_set_byte(uint8_t *config, uint8_t val)
286 *config = val;
289 static inline uint8_t
290 pci_get_byte(const uint8_t *config)
292 return *config;
295 static inline void
296 pci_set_word(uint8_t *config, uint16_t val)
298 cpu_to_le16wu((uint16_t *)config, val);
301 static inline uint16_t
302 pci_get_word(const uint8_t *config)
304 return le16_to_cpupu((const uint16_t *)config);
307 static inline void
308 pci_set_long(uint8_t *config, uint32_t val)
310 cpu_to_le32wu((uint32_t *)config, val);
313 static inline uint32_t
314 pci_get_long(const uint8_t *config)
316 return le32_to_cpupu((const uint32_t *)config);
319 static inline void
320 pci_set_quad(uint8_t *config, uint64_t val)
322 cpu_to_le64w((uint64_t *)config, val);
325 static inline uint64_t
326 pci_get_quad(const uint8_t *config)
328 return le64_to_cpup((const uint64_t *)config);
331 static inline void
332 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
334 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
337 static inline void
338 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
340 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
343 static inline void
344 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
346 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
349 static inline void
350 pci_config_set_class(uint8_t *pci_config, uint16_t val)
352 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
355 static inline void
356 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
358 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
361 static inline void
362 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
364 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
368 * helper functions to do bit mask operation on configuration space.
369 * Just to set bit, use test-and-set and discard returned value.
370 * Just to clear bit, use test-and-clear and discard returned value.
371 * NOTE: They aren't atomic.
373 static inline uint8_t
374 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
376 uint8_t val = pci_get_byte(config);
377 pci_set_byte(config, val & ~mask);
378 return val & mask;
381 static inline uint8_t
382 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
384 uint8_t val = pci_get_byte(config);
385 pci_set_byte(config, val | mask);
386 return val & mask;
389 static inline uint16_t
390 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
392 uint16_t val = pci_get_word(config);
393 pci_set_word(config, val & ~mask);
394 return val & mask;
397 static inline uint16_t
398 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
400 uint16_t val = pci_get_word(config);
401 pci_set_word(config, val | mask);
402 return val & mask;
405 static inline uint32_t
406 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
408 uint32_t val = pci_get_long(config);
409 pci_set_long(config, val & ~mask);
410 return val & mask;
413 static inline uint32_t
414 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
416 uint32_t val = pci_get_long(config);
417 pci_set_long(config, val | mask);
418 return val & mask;
421 static inline uint64_t
422 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
424 uint64_t val = pci_get_quad(config);
425 pci_set_quad(config, val & ~mask);
426 return val & mask;
429 static inline uint64_t
430 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
432 uint64_t val = pci_get_quad(config);
433 pci_set_quad(config, val | mask);
434 return val & mask;
437 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
438 typedef struct {
439 DeviceInfo qdev;
440 pci_qdev_initfn init;
441 PCIUnregisterFunc *exit;
442 PCIConfigReadFunc *config_read;
443 PCIConfigWriteFunc *config_write;
445 uint16_t vendor_id;
446 uint16_t device_id;
447 uint8_t revision;
448 uint16_t class_id;
449 uint16_t subsystem_vendor_id; /* only for header type = 0 */
450 uint16_t subsystem_id; /* only for header type = 0 */
453 * pci-to-pci bridge or normal device.
454 * This doesn't mean pci host switch.
455 * When card bus bridge is supported, this would be enhanced.
457 int is_bridge;
459 /* pcie stuff */
460 int is_express; /* is this device pci express? */
462 /* device isn't hot-pluggable */
463 int no_hotplug;
465 /* rom bar */
466 const char *romfile;
467 } PCIDeviceInfo;
469 void pci_qdev_register(PCIDeviceInfo *info);
470 void pci_qdev_register_many(PCIDeviceInfo *info);
472 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
473 const char *name);
474 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
475 bool multifunction,
476 const char *name);
477 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
478 bool multifunction,
479 const char *name);
480 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
481 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
482 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name);
484 static inline int pci_is_express(const PCIDevice *d)
486 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
489 static inline uint32_t pci_config_size(const PCIDevice *d)
491 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
494 #endif