hw/ppc_newworld.c

   1 /*
   2  * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  *
  25  * PCI bus layout on a real G5 (U3 based):
  26  *
  27  * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
  28  * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
  29  * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
  30  * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
  31  * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
  32  * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
  33  * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
  34  * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
  35  * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
  36  * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
  37  * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
  38  * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
  39  * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
  40  * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
  41  * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
  42  * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
  43  * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
  44  * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
  45  * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
  46  * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
  47  *
  48  */
  49 #include "hw.h"
  50 #include "ppc.h"
  51 #include "ppc_mac.h"
  52 #include "mac_dbdma.h"
  53 #include "nvram.h"
  54 #include "pc.h"
  55 #include "pci.h"
  56 #include "usb-ohci.h"
  57 #include "net.h"
  58 #include "sysemu.h"
  59 #include "boards.h"
  60 #include "fw_cfg.h"
  61 #include "escc.h"
  62 #include "openpic.h"
  63 #include "ide.h"
  64 #include "loader.h"
  65 #include "elf.h"
  66 #include "kvm.h"
  67 #include "kvm_ppc.h"
  68 #include "hw/usb.h"
  69
  70 #define MAX_IDE_BUS 2
  71 #define VGA_BIOS_SIZE 65536
  72 #define CFG_ADDR 0xf0000510
  73
  74 /* debug UniNorth */
  75 //#define DEBUG_UNIN
  76
  77 #ifdef DEBUG_UNIN
  78 #define UNIN_DPRINTF(fmt, ...)                                  \
  79     do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
  80 #else
  81 #define UNIN_DPRINTF(fmt, ...)
  82 #endif
  83
  84 /* UniN device */
  85 static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
  86 {
  87     UNIN_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n", addr, value);
  88 }
  89
  90 static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
  91 {
  92     uint32_t value;
  93
  94     value = 0;
  95     UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value);
  96
  97     return value;
  98 }
  99
 100 static CPUWriteMemoryFunc * const unin_write[] = {
 101     &unin_writel,
 102     &unin_writel,
 103     &unin_writel,
 104 };
 105
 106 static CPUReadMemoryFunc * const unin_read[] = {
 107     &unin_readl,
 108     &unin_readl,
 109     &unin_readl,
 110 };
 111
 112 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 113 {
 114     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 115     return 0;
 116 }
 117
 118 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
 119 {
 120     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
 121 }
 122
 123 /* PowerPC Mac99 hardware initialisation */
 124 static void ppc_core99_init (ram_addr_t ram_size,
 125                              const char *boot_device,
 126                              const char *kernel_filename,
 127                              const char *kernel_cmdline,
 128                              const char *initrd_filename,
 129                              const char *cpu_model)
 130 {
 131     CPUState *env = NULL, *envs[MAX_CPUS];
 132     char *filename;
 133     qemu_irq *pic, **openpic_irqs;
 134     int unin_memory;
 135     int linux_boot, i;
 136     ram_addr_t ram_offset, bios_offset, vga_bios_offset;
 137     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 138     PCIBus *pci_bus;
 139     MacIONVRAMState *nvr;
 140     int nvram_mem_index;
 141     int vga_bios_size, bios_size;
 142     int pic_mem_index, dbdma_mem_index, cuda_mem_index, escc_mem_index;
 143     int ide_mem_index[3];
 144     int ppc_boot_device;
 145     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 146     void *fw_cfg;
 147     void *dbdma;
 148     uint8_t *vga_bios_ptr;
 149     int machine_arch;
 150
 151     linux_boot = (kernel_filename != NULL);
 152
 153     /* init CPUs */
 154     if (cpu_model == NULL)
 155 #ifdef TARGET_PPC64
 156         cpu_model = "970fx";
 157 #else
 158         cpu_model = "G4";
 159 #endif
 160     for (i = 0; i < smp_cpus; i++) {
 161         env = cpu_init(cpu_model);
 162         if (!env) {
 163             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 164             exit(1);
 165         }
 166         /* Set time-base frequency to 100 Mhz */
 167         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 168 #if 0
 169         env->osi_call = vga_osi_call;
 170 #endif
 171         qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
 172         envs[i] = env;
 173     }
 174
 175     /* allocate RAM */
 176     ram_offset = qemu_ram_alloc(ram_size);
 177     cpu_register_physical_memory(0, ram_size, ram_offset);
 178
 179     /* allocate and load BIOS */
 180     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 181     if (bios_name == NULL)
 182         bios_name = PROM_FILENAME;
 183     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 184     cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
 185
 186     /* Load OpenBIOS (ELF) */
 187     if (filename) {
 188         bios_size = load_elf(filename, NULL, NULL, NULL,
 189                              NULL, NULL, 1, ELF_MACHINE, 0);
 190
 191         qemu_free(filename);
 192     } else {
 193         bios_size = -1;
 194     }
 195     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 196         hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
 197         exit(1);
 198     }
 199
 200     /* allocate and load VGA BIOS */
 201     vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
 202     vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset);
 203     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME);
 204     if (filename) {
 205         vga_bios_size = load_image(filename, vga_bios_ptr + 8);
 206         qemu_free(filename);
 207     } else {
 208         vga_bios_size = -1;
 209     }
 210     if (vga_bios_size < 0) {
 211         /* if no bios is present, we can still work */
 212         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n",
 213                 VGABIOS_FILENAME);
 214         vga_bios_size = 0;
 215     } else {
 216         /* set a specific header (XXX: find real Apple format for NDRV
 217            drivers) */
 218         vga_bios_ptr[0] = 'N';
 219         vga_bios_ptr[1] = 'D';
 220         vga_bios_ptr[2] = 'R';
 221         vga_bios_ptr[3] = 'V';
 222         cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size);
 223         vga_bios_size += 8;
 224
 225         /* Round to page boundary */
 226         vga_bios_size = (vga_bios_size + TARGET_PAGE_SIZE - 1) &
 227             TARGET_PAGE_MASK;
 228     }
 229
 230     if (linux_boot) {
 231         uint64_t lowaddr = 0;
 232         int bswap_needed;
 233
 234 #ifdef BSWAP_NEEDED
 235         bswap_needed = 1;
 236 #else
 237         bswap_needed = 0;
 238 #endif
 239         kernel_base = KERNEL_LOAD_ADDR;
 240
 241         kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
 242                                NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
 243         if (kernel_size < 0)
 244             kernel_size = load_aout(kernel_filename, kernel_base,
 245                                     ram_size - kernel_base, bswap_needed,
 246                                     TARGET_PAGE_SIZE);
 247         if (kernel_size < 0)
 248             kernel_size = load_image_targphys(kernel_filename,
 249                                               kernel_base,
 250                                               ram_size - kernel_base);
 251         if (kernel_size < 0) {
 252             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 253             exit(1);
 254         }
 255         /* load initrd */
 256         if (initrd_filename) {
 257             initrd_base = INITRD_LOAD_ADDR;
 258             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 259                                               ram_size - initrd_base);
 260             if (initrd_size < 0) {
 261                 hw_error("qemu: could not load initial ram disk '%s'\n",
 262                          initrd_filename);
 263                 exit(1);
 264             }
 265         } else {
 266             initrd_base = 0;
 267             initrd_size = 0;
 268         }
 269         ppc_boot_device = 'm';
 270     } else {
 271         kernel_base = 0;
 272         kernel_size = 0;
 273         initrd_base = 0;
 274         initrd_size = 0;
 275         ppc_boot_device = '\0';
 276         /* We consider that NewWorld PowerMac never have any floppy drive
 277          * For now, OHW cannot boot from the network.
 278          */
 279         for (i = 0; boot_device[i] != '\0'; i++) {
 280             if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
 281                 ppc_boot_device = boot_device[i];
 282                 break;
 283             }
 284         }
 285         if (ppc_boot_device == '\0') {
 286             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 287             exit(1);
 288         }
 289     }
 290
 291     isa_mem_base = 0x80000000;
 292
 293     /* Register 8 MB of ISA IO space */
 294     isa_mmio_init(0xf2000000, 0x00800000, 1);
 295
 296     /* UniN init */
 297     unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL);
 298     cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
 299
 300     openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 301     openpic_irqs[0] =
 302         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 303     for (i = 0; i < smp_cpus; i++) {
 304         /* Mac99 IRQ connection between OpenPIC outputs pins
 305          * and PowerPC input pins
 306          */
 307         switch (PPC_INPUT(env)) {
 308         case PPC_FLAGS_INPUT_6xx:
 309             openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
 310             openpic_irqs[i][OPENPIC_OUTPUT_INT] =
 311                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 312             openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
 313                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 314             openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
 315                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
 316             /* Not connected ? */
 317             openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
 318             /* Check this */
 319             openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
 320                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
 321             break;
 322 #if defined(TARGET_PPC64)
 323         case PPC_FLAGS_INPUT_970:
 324             openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
 325             openpic_irqs[i][OPENPIC_OUTPUT_INT] =
 326                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
 327             openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
 328                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
 329             openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
 330                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
 331             /* Not connected ? */
 332             openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
 333             /* Check this */
 334             openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
 335                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
 336             break;
 337 #endif /* defined(TARGET_PPC64) */
 338         default:
 339             hw_error("Bus model not supported on mac99 machine\n");
 340             exit(1);
 341         }
 342     }
 343     pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);
 344     if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
 345         /* 970 gets a U3 bus */
 346         pci_bus = pci_pmac_u3_init(pic);
 347         machine_arch = ARCH_MAC99_U3;
 348     } else {
 349         pci_bus = pci_pmac_init(pic);
 350         machine_arch = ARCH_MAC99;
 351     }
 352     /* init basic PC hardware */
 353     pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size);
 354
 355     escc_mem_index = escc_init(0x80013000, pic[0x25], pic[0x24],
 356                                serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
 357
 358     for(i = 0; i < nb_nics; i++)
 359         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 360
 361     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 362         fprintf(stderr, "qemu: too many IDE bus\n");
 363         exit(1);
 364     }
 365     dbdma = DBDMA_init(&dbdma_mem_index);
 366
 367     /* We only emulate 2 out of 3 IDE controllers for now */
 368     ide_mem_index[0] = -1;
 369     hd[0] = drive_get(IF_IDE, 0, 0);
 370     hd[1] = drive_get(IF_IDE, 0, 1);
 371     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0d], dbdma, 0x16, pic[0x02]);
 372     hd[0] = drive_get(IF_IDE, 1, 0);
 373     hd[1] = drive_get(IF_IDE, 1, 1);
 374     ide_mem_index[2] = pmac_ide_init(hd, pic[0x0e], dbdma, 0x1a, pic[0x02]);
 375
 376     /* cuda also initialize ADB */
 377     if (machine_arch == ARCH_MAC99_U3) {
 378         usb_enabled = 1;
 379     }
 380     cuda_init(&cuda_mem_index, pic[0x19]);
 381
 382     adb_kbd_init(&adb_bus);
 383     adb_mouse_init(&adb_bus);
 384
 385     macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem_index,
 386                dbdma_mem_index, cuda_mem_index, NULL, 3, ide_mem_index,
 387                escc_mem_index);
 388
 389     if (usb_enabled) {
 390         usb_ohci_init_pci(pci_bus, -1);
 391     }
 392
 393     /* U3 needs to use USB for input because Linux doesn't support via-cuda
 394        on PPC64 */
 395     if (machine_arch == ARCH_MAC99_U3) {
 396         usbdevice_create("keyboard");
 397         usbdevice_create("mouse");
 398     }
 399
 400     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 401         graphic_depth = 15;
 402
 403     /* The NewWorld NVRAM is not located in the MacIO device */
 404     nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 1);
 405     pmac_format_nvram_partition(nvr, 0x2000);
 406     macio_nvram_map(nvr, 0xFFF04000);
 407     /* No PCI init: the BIOS will do it */
 408
 409     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 410     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 411     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 412     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
 413     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 414     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 415     if (kernel_cmdline) {
 416         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 417         pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 418     } else {
 419         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 420     }
 421     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 422     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 423     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 424
 425     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 426     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 427     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 428
 429     if (kvm_enabled()) {
 430 #ifdef CONFIG_KVM
 431         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
 432 #endif
 433     } else {
 434         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
 435     }
 436
 437     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 438 }
 439
 440 static QEMUMachine core99_machine = {
 441     .name = "mac99",
 442     .desc = "Mac99 based PowerMAC",
 443     .init = ppc_core99_init,
 444     .max_cpus = MAX_CPUS,
 445 #ifdef TARGET_PPC64
 446     .is_default = 1,
 447 #endif
 448 };
 449
 450 static void core99_machine_init(void)
 451 {
 452     qemu_register_machine(&core99_machine);
 453 }
 454
 455 machine_init(core99_machine_init);