hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29
  30 //#define DEBUG_PCI
  31 #ifdef DEBUG_PCI
  32 # define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
  33 #else
  34 # define PCI_DPRINTF(format, ...)       do { } while (0)
  35 #endif
  36
  37 struct PCIBus {
  38     BusState qbus;
  39     int devfn_min;
  40     pci_set_irq_fn set_irq;
  41     pci_map_irq_fn map_irq;
  42     pci_hotplug_fn hotplug;
  43     uint32_t config_reg; /* XXX: suppress */
  44     void *irq_opaque;
  45     PCIDevice *devices[256];
  46     PCIDevice *parent_dev;
  47
  48     QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
  49     QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
  50
  51     /* The bus IRQ state is the logical OR of the connected devices.
  52        Keep a count of the number of devices with raised IRQs.  */
  53     int nirq;
  54     int *irq_count;
  55 };
  56
  57 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  58
  59 static struct BusInfo pci_bus_info = {
  60     .name       = "PCI",
  61     .size       = sizeof(PCIBus),
  62     .print_dev  = pcibus_dev_print,
  63     .props      = (Property[]) {
  64         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  65         DEFINE_PROP_END_OF_LIST()
  66     }
  67 };
  68
  69 static void pci_update_mappings(PCIDevice *d);
  70 static void pci_set_irq(void *opaque, int irq_num, int level);
  71
  72 target_phys_addr_t pci_mem_base;
  73 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  74 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  75
  76 struct PCIHostBus {
  77     int domain;
  78     struct PCIBus *bus;
  79     QLIST_ENTRY(PCIHostBus) next;
  80 };
  81 static QLIST_HEAD(, PCIHostBus) host_buses;
  82
  83 static const VMStateDescription vmstate_pcibus = {
  84     .name = "PCIBUS",
  85     .version_id = 1,
  86     .minimum_version_id = 1,
  87     .minimum_version_id_old = 1,
  88     .fields      = (VMStateField []) {
  89         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  90         VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
  91         VMSTATE_END_OF_LIST()
  92     }
  93 };
  94
  95 static int pci_bar(PCIDevice *d, int reg)
  96 {
  97     uint8_t type;
  98
  99     if (reg != PCI_ROM_SLOT)
 100         return PCI_BASE_ADDRESS_0 + reg * 4;
 101
 102     type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
 103     return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
 104 }
 105
 106 static void pci_device_reset(PCIDevice *dev)
 107 {
 108     int r;
 109
 110     memset(dev->irq_state, 0, sizeof dev->irq_state);
 111     dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 112                                   PCI_COMMAND_MASTER);
 113     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
 114     dev->config[PCI_INTERRUPT_LINE] = 0x0;
 115     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
 116         if (!dev->io_regions[r].size) {
 117             continue;
 118         }
 119         pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
 120     }
 121     pci_update_mappings(dev);
 122 }
 123
 124 static void pci_bus_reset(void *opaque)
 125 {
 126     PCIBus *bus = opaque;
 127     int i;
 128
 129     for (i = 0; i < bus->nirq; i++) {
 130         bus->irq_count[i] = 0;
 131     }
 132     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 133         if (bus->devices[i]) {
 134             pci_device_reset(bus->devices[i]);
 135         }
 136     }
 137 }
 138
 139 static void pci_host_bus_register(int domain, PCIBus *bus)
 140 {
 141     struct PCIHostBus *host;
 142     host = qemu_mallocz(sizeof(*host));
 143     host->domain = domain;
 144     host->bus = bus;
 145     QLIST_INSERT_HEAD(&host_buses, host, next);
 146 }
 147
 148 PCIBus *pci_find_host_bus(int domain)
 149 {
 150     struct PCIHostBus *host;
 151
 152     QLIST_FOREACH(host, &host_buses, next) {
 153         if (host->domain == domain) {
 154             return host->bus;
 155         }
 156     }
 157
 158     return NULL;
 159 }
 160
 161 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 162                          const char *name, int devfn_min)
 163 {
 164     static int nbus = 0;
 165
 166     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 167     bus->devfn_min = devfn_min;
 168
 169     /* host bridge */
 170     QLIST_INIT(&bus->child);
 171     pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
 172
 173     vmstate_register(nbus++, &vmstate_pcibus, bus);
 174     qemu_register_reset(pci_bus_reset, bus);
 175 }
 176
 177 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 178 {
 179     PCIBus *bus;
 180
 181     bus = qemu_mallocz(sizeof(*bus));
 182     bus->qbus.qdev_allocated = 1;
 183     pci_bus_new_inplace(bus, parent, name, devfn_min);
 184     return bus;
 185 }
 186
 187 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 188                   void *irq_opaque, int nirq)
 189 {
 190     bus->set_irq = set_irq;
 191     bus->map_irq = map_irq;
 192     bus->irq_opaque = irq_opaque;
 193     bus->nirq = nirq;
 194     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 195 }
 196
 197 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
 198 {
 199     bus->qbus.allow_hotplug = 1;
 200     bus->hotplug = hotplug;
 201 }
 202
 203 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 204                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 205                          void *irq_opaque, int devfn_min, int nirq)
 206 {
 207     PCIBus *bus;
 208
 209     bus = pci_bus_new(parent, name, devfn_min);
 210     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 211     return bus;
 212 }
 213
 214 static void pci_register_secondary_bus(PCIBus *parent,
 215                                        PCIBus *bus,
 216                                        PCIDevice *dev,
 217                                        pci_map_irq_fn map_irq,
 218                                        const char *name)
 219 {
 220     qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
 221     bus->map_irq = map_irq;
 222     bus->parent_dev = dev;
 223
 224     QLIST_INIT(&bus->child);
 225     QLIST_INSERT_HEAD(&parent->child, bus, sibling);
 226 }
 227
 228 static void pci_unregister_secondary_bus(PCIBus *bus)
 229 {
 230     assert(QLIST_EMPTY(&bus->child));
 231     QLIST_REMOVE(bus, sibling);
 232 }
 233
 234 int pci_bus_num(PCIBus *s)
 235 {
 236     if (!s->parent_dev)
 237         return 0;       /* pci host bridge */
 238     return s->parent_dev->config[PCI_SECONDARY_BUS];
 239 }
 240
 241 static uint8_t pci_sub_bus(PCIBus *s)
 242 {
 243     if (!s->parent_dev)
 244         return 255;     /* pci host bridge */
 245     return s->parent_dev->config[PCI_SUBORDINATE_BUS];
 246 }
 247
 248 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 249 {
 250     PCIDevice *s = container_of(pv, PCIDevice, config);
 251     uint8_t config[PCI_CONFIG_SPACE_SIZE];
 252     int i;
 253
 254     assert(size == sizeof config);
 255     qemu_get_buffer(f, config, sizeof config);
 256     for (i = 0; i < sizeof config; ++i)
 257         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
 258             return -EINVAL;
 259     memcpy(s->config, config, sizeof config);
 260
 261     pci_update_mappings(s);
 262
 263     return 0;
 264 }
 265
 266 /* just put buffer */
 267 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 268 {
 269     const uint8_t *v = pv;
 270     qemu_put_buffer(f, v, size);
 271 }
 272
 273 static VMStateInfo vmstate_info_pci_config = {
 274     .name = "pci config",
 275     .get  = get_pci_config_device,
 276     .put  = put_pci_config_device,
 277 };
 278
 279 const VMStateDescription vmstate_pci_device = {
 280     .name = "PCIDevice",
 281     .version_id = 2,
 282     .minimum_version_id = 1,
 283     .minimum_version_id_old = 1,
 284     .fields      = (VMStateField []) {
 285         VMSTATE_INT32_LE(version_id, PCIDevice),
 286         VMSTATE_SINGLE(config, PCIDevice, 0, vmstate_info_pci_config,
 287                        typeof_field(PCIDevice,config)),
 288         VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
 289         VMSTATE_END_OF_LIST()
 290     }
 291 };
 292
 293 void pci_device_save(PCIDevice *s, QEMUFile *f)
 294 {
 295     vmstate_save_state(f, &vmstate_pci_device, s);
 296 }
 297
 298 int pci_device_load(PCIDevice *s, QEMUFile *f)
 299 {
 300     return vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
 301 }
 302
 303 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 304 {
 305     uint16_t *id;
 306
 307     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 308     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 309     id[1] = cpu_to_le16(pci_default_sub_device_id);
 310     return 0;
 311 }
 312
 313 /*
 314  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 315  */
 316 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 317 {
 318     const char *p;
 319     char *e;
 320     unsigned long val;
 321     unsigned long dom = 0, bus = 0;
 322     unsigned slot = 0;
 323
 324     p = addr;
 325     val = strtoul(p, &e, 16);
 326     if (e == p)
 327         return -1;
 328     if (*e == ':') {
 329         bus = val;
 330         p = e + 1;
 331         val = strtoul(p, &e, 16);
 332         if (e == p)
 333             return -1;
 334         if (*e == ':') {
 335             dom = bus;
 336             bus = val;
 337             p = e + 1;
 338             val = strtoul(p, &e, 16);
 339             if (e == p)
 340                 return -1;
 341         }
 342     }
 343
 344     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 345         return -1;
 346
 347     slot = val;
 348
 349     if (*e)
 350         return -1;
 351
 352     /* Note: QEMU doesn't implement domains other than 0 */
 353     if (!pci_find_bus(pci_find_host_bus(dom), bus))
 354         return -1;
 355
 356     *domp = dom;
 357     *busp = bus;
 358     *slotp = slot;
 359     return 0;
 360 }
 361
 362 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 363                      unsigned *slotp)
 364 {
 365     /* strip legacy tag */
 366     if (!strncmp(addr, "pci_addr=", 9)) {
 367         addr += 9;
 368     }
 369     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 370         monitor_printf(mon, "Invalid pci address\n");
 371         return -1;
 372     }
 373     return 0;
 374 }
 375
 376 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 377 {
 378     int dom, bus;
 379     unsigned slot;
 380
 381     if (!devaddr) {
 382         *devfnp = -1;
 383         return pci_find_bus(pci_find_host_bus(0), 0);
 384     }
 385
 386     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 387         return NULL;
 388     }
 389
 390     *devfnp = slot << 3;
 391     return pci_find_bus(pci_find_host_bus(0), bus);
 392 }
 393
 394 static void pci_init_cmask(PCIDevice *dev)
 395 {
 396     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 397     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 398     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 399     dev->cmask[PCI_REVISION_ID] = 0xff;
 400     dev->cmask[PCI_CLASS_PROG] = 0xff;
 401     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 402     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 403     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 404 }
 405
 406 static void pci_init_wmask(PCIDevice *dev)
 407 {
 408     int i;
 409     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 410     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 411     pci_set_word(dev->wmask + PCI_COMMAND,
 412                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 413     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 414         dev->wmask[i] = 0xff;
 415 }
 416
 417 /* -1 for devfn means auto assign */
 418 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 419                                          const char *name, int devfn,
 420                                          PCIConfigReadFunc *config_read,
 421                                          PCIConfigWriteFunc *config_write)
 422 {
 423     if (devfn < 0) {
 424         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 425             if (!bus->devices[devfn])
 426                 goto found;
 427         }
 428         return NULL;
 429     found: ;
 430     } else if (bus->devices[devfn]) {
 431         return NULL;
 432     }
 433     pci_dev->bus = bus;
 434     pci_dev->devfn = devfn;
 435     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 436     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 437     pci_set_default_subsystem_id(pci_dev);
 438     pci_init_cmask(pci_dev);
 439     pci_init_wmask(pci_dev);
 440
 441     if (!config_read)
 442         config_read = pci_default_read_config;
 443     if (!config_write)
 444         config_write = pci_default_write_config;
 445     pci_dev->config_read = config_read;
 446     pci_dev->config_write = config_write;
 447     bus->devices[devfn] = pci_dev;
 448     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
 449     pci_dev->version_id = 2; /* Current pci device vmstate version */
 450     return pci_dev;
 451 }
 452
 453 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 454                                int instance_size, int devfn,
 455                                PCIConfigReadFunc *config_read,
 456                                PCIConfigWriteFunc *config_write)
 457 {
 458     PCIDevice *pci_dev;
 459
 460     pci_dev = qemu_mallocz(instance_size);
 461     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 462                                      config_read, config_write);
 463     return pci_dev;
 464 }
 465 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 466 {
 467     return addr + pci_mem_base;
 468 }
 469
 470 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 471 {
 472     PCIIORegion *r;
 473     int i;
 474
 475     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 476         r = &pci_dev->io_regions[i];
 477         if (!r->size || r->addr == PCI_BAR_UNMAPPED)
 478             continue;
 479         if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
 480             isa_unassign_ioport(r->addr, r->size);
 481         } else {
 482             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 483                                                      r->size,
 484                                                      IO_MEM_UNASSIGNED);
 485         }
 486     }
 487 }
 488
 489 static int pci_unregister_device(DeviceState *dev)
 490 {
 491     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 492     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 493     int ret = 0;
 494
 495     if (info->exit)
 496         ret = info->exit(pci_dev);
 497     if (ret)
 498         return ret;
 499
 500     pci_unregister_io_regions(pci_dev);
 501
 502     qemu_free_irqs(pci_dev->irq);
 503     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 504     return 0;
 505 }
 506
 507 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 508                             pcibus_t size, int type,
 509                             PCIMapIORegionFunc *map_func)
 510 {
 511     PCIIORegion *r;
 512     uint32_t addr;
 513     pcibus_t wmask;
 514
 515     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 516         return;
 517
 518     if (size & (size-1)) {
 519         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 520                     "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
 521         exit(1);
 522     }
 523
 524     r = &pci_dev->io_regions[region_num];
 525     r->addr = PCI_BAR_UNMAPPED;
 526     r->size = size;
 527     r->type = type;
 528     r->map_func = map_func;
 529
 530     wmask = ~(size - 1);
 531     addr = pci_bar(pci_dev, region_num);
 532     if (region_num == PCI_ROM_SLOT) {
 533         /* ROM enable bit is writeable */
 534         wmask |= PCI_ROM_ADDRESS_ENABLE;
 535     }
 536     pci_set_long(pci_dev->config + addr, type);
 537     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 538         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 539         pci_set_quad(pci_dev->wmask + addr, wmask);
 540         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
 541     } else {
 542         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
 543         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
 544     }
 545 }
 546
 547 static void pci_update_mappings(PCIDevice *d)
 548 {
 549     PCIIORegion *r;
 550     int cmd, i;
 551     pcibus_t last_addr, new_addr;
 552
 553     cmd = pci_get_word(d->config + PCI_COMMAND);
 554     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 555         r = &d->io_regions[i];
 556         if (r->size != 0) {
 557             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 558                 if (cmd & PCI_COMMAND_IO) {
 559                     new_addr = pci_get_long(d->config + pci_bar(d, i));
 560                     new_addr = new_addr & ~(r->size - 1);
 561                     last_addr = new_addr + r->size - 1;
 562                     /* NOTE: we have only 64K ioports on PC */
 563                     if (last_addr <= new_addr || new_addr == 0 ||
 564                         last_addr >= 0x10000) {
 565                         new_addr = PCI_BAR_UNMAPPED;
 566                     }
 567                 } else {
 568                     new_addr = PCI_BAR_UNMAPPED;
 569                 }
 570             } else {
 571                 if (cmd & PCI_COMMAND_MEMORY) {
 572                     if (r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 573                         new_addr = pci_get_quad(d->config + pci_bar(d, i));
 574                     } else {
 575                         new_addr = pci_get_long(d->config + pci_bar(d, i));
 576                     }
 577                     /* the ROM slot has a specific enable bit */
 578                     if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE))
 579                         goto no_mem_map;
 580                     new_addr = new_addr & ~(r->size - 1);
 581                     last_addr = new_addr + r->size - 1;
 582                     /* NOTE: we do not support wrapping */
 583                     /* XXX: as we cannot support really dynamic
 584                        mappings, we handle specific values as invalid
 585                        mappings. */
 586                     if (last_addr <= new_addr || new_addr == 0 ||
 587                         last_addr == PCI_BAR_UNMAPPED ||
 588
 589                         /* Now pcibus_t is 64bit.
 590                          * Check if 32 bit BAR wrap around explicitly.
 591                          * Without this, PC ide doesn't work well.
 592                          * TODO: remove this work around.
 593                          */
 594                         (!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) &&
 595                          last_addr >= UINT32_MAX) ||
 596
 597                         /*
 598                          * OS is allowed to set BAR beyond its addressable
 599                          * bits. For example, 32 bit OS can set 64bit bar
 600                          * to >4G. Check it.
 601                          */
 602                         last_addr >= TARGET_PHYS_ADDR_MAX) {
 603                         new_addr = PCI_BAR_UNMAPPED;
 604                     }
 605                 } else {
 606                 no_mem_map:
 607                     new_addr = PCI_BAR_UNMAPPED;
 608                 }
 609             }
 610             /* now do the real mapping */
 611             if (new_addr != r->addr) {
 612                 if (r->addr != PCI_BAR_UNMAPPED) {
 613                     if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 614                         int class;
 615                         /* NOTE: specific hack for IDE in PC case:
 616                            only one byte must be mapped. */
 617                         class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 618                         if (class == 0x0101 && r->size == 4) {
 619                             isa_unassign_ioport(r->addr + 2, 1);
 620                         } else {
 621                             isa_unassign_ioport(r->addr, r->size);
 622                         }
 623                     } else {
 624                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 625                                                      r->size,
 626                                                      IO_MEM_UNASSIGNED);
 627                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 628                     }
 629                 }
 630                 r->addr = new_addr;
 631                 if (r->addr != PCI_BAR_UNMAPPED) {
 632                     r->map_func(d, i, r->addr, r->size, r->type);
 633                 }
 634             }
 635         }
 636     }
 637 }
 638
 639 uint32_t pci_default_read_config(PCIDevice *d,
 640                                  uint32_t address, int len)
 641 {
 642     uint32_t val = 0;
 643     assert(len == 1 || len == 2 || len == 4);
 644     len = MIN(len, PCI_CONFIG_SPACE_SIZE - address);
 645     memcpy(&val, d->config + address, len);
 646     return le32_to_cpu(val);
 647 }
 648
 649 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 650 {
 651     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 652     int i;
 653
 654     /* not efficient, but simple */
 655     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 656     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 657         uint8_t wmask = d->wmask[addr];
 658         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 659     }
 660     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 661         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 662             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 663         pci_update_mappings(d);
 664 }
 665
 666 /***********************************************************/
 667 /* generic PCI irq support */
 668
 669 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 670 static void pci_set_irq(void *opaque, int irq_num, int level)
 671 {
 672     PCIDevice *pci_dev = opaque;
 673     PCIBus *bus;
 674     int change;
 675
 676     change = level - pci_dev->irq_state[irq_num];
 677     if (!change)
 678         return;
 679
 680     pci_dev->irq_state[irq_num] = level;
 681     for (;;) {
 682         bus = pci_dev->bus;
 683         irq_num = bus->map_irq(pci_dev, irq_num);
 684         if (bus->set_irq)
 685             break;
 686         pci_dev = bus->parent_dev;
 687     }
 688     bus->irq_count[irq_num] += change;
 689     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 690 }
 691
 692 /***********************************************************/
 693 /* monitor info on PCI */
 694
 695 typedef struct {
 696     uint16_t class;
 697     const char *desc;
 698 } pci_class_desc;
 699
 700 static const pci_class_desc pci_class_descriptions[] =
 701 {
 702     { 0x0100, "SCSI controller"},
 703     { 0x0101, "IDE controller"},
 704     { 0x0102, "Floppy controller"},
 705     { 0x0103, "IPI controller"},
 706     { 0x0104, "RAID controller"},
 707     { 0x0106, "SATA controller"},
 708     { 0x0107, "SAS controller"},
 709     { 0x0180, "Storage controller"},
 710     { 0x0200, "Ethernet controller"},
 711     { 0x0201, "Token Ring controller"},
 712     { 0x0202, "FDDI controller"},
 713     { 0x0203, "ATM controller"},
 714     { 0x0280, "Network controller"},
 715     { 0x0300, "VGA controller"},
 716     { 0x0301, "XGA controller"},
 717     { 0x0302, "3D controller"},
 718     { 0x0380, "Display controller"},
 719     { 0x0400, "Video controller"},
 720     { 0x0401, "Audio controller"},
 721     { 0x0402, "Phone"},
 722     { 0x0480, "Multimedia controller"},
 723     { 0x0500, "RAM controller"},
 724     { 0x0501, "Flash controller"},
 725     { 0x0580, "Memory controller"},
 726     { 0x0600, "Host bridge"},
 727     { 0x0601, "ISA bridge"},
 728     { 0x0602, "EISA bridge"},
 729     { 0x0603, "MC bridge"},
 730     { 0x0604, "PCI bridge"},
 731     { 0x0605, "PCMCIA bridge"},
 732     { 0x0606, "NUBUS bridge"},
 733     { 0x0607, "CARDBUS bridge"},
 734     { 0x0608, "RACEWAY bridge"},
 735     { 0x0680, "Bridge"},
 736     { 0x0c03, "USB controller"},
 737     { 0, NULL}
 738 };
 739
 740 static void pci_info_device(PCIBus *bus, PCIDevice *d)
 741 {
 742     Monitor *mon = cur_mon;
 743     int i, class;
 744     PCIIORegion *r;
 745     const pci_class_desc *desc;
 746
 747     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 748                    pci_bus_num(d->bus),
 749                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
 750     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 751     monitor_printf(mon, "    ");
 752     desc = pci_class_descriptions;
 753     while (desc->desc && class != desc->class)
 754         desc++;
 755     if (desc->desc) {
 756         monitor_printf(mon, "%s", desc->desc);
 757     } else {
 758         monitor_printf(mon, "Class %04x", class);
 759     }
 760     monitor_printf(mon, ": PCI device %04x:%04x\n",
 761            pci_get_word(d->config + PCI_VENDOR_ID),
 762            pci_get_word(d->config + PCI_DEVICE_ID));
 763
 764     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 765         monitor_printf(mon, "      IRQ %d.\n",
 766                        d->config[PCI_INTERRUPT_LINE]);
 767     }
 768     if (class == 0x0604) {
 769         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 770     }
 771     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 772         r = &d->io_regions[i];
 773         if (r->size != 0) {
 774             monitor_printf(mon, "      BAR%d: ", i);
 775             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 776                 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
 777                                " [0x%04"FMT_PCIBUS"].\n",
 778                                r->addr, r->addr + r->size - 1);
 779             } else {
 780                 const char *type = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64 ?
 781                     "64 bit" : "32 bit";
 782                 const char *prefetch =
 783                     r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ?
 784                     " prefetchable" : "";
 785
 786                 monitor_printf(mon, "%s%s memory at 0x%08"FMT_PCIBUS
 787                                " [0x%08"FMT_PCIBUS"].\n",
 788                                type, prefetch,
 789                                r->addr, r->addr + r->size - 1);
 790             }
 791         }
 792     }
 793     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
 794     if (class == 0x0604 && d->config[0x19] != 0) {
 795         pci_for_each_device(bus, d->config[0x19], pci_info_device);
 796     }
 797 }
 798
 799 void pci_for_each_device(PCIBus *bus, int bus_num,
 800                          void (*fn)(PCIBus *b, PCIDevice *d))
 801 {
 802     PCIDevice *d;
 803     int devfn;
 804
 805     bus = pci_find_bus(bus, bus_num);
 806     if (bus) {
 807         for(devfn = 0; devfn < 256; devfn++) {
 808             d = bus->devices[devfn];
 809             if (d)
 810                 fn(bus, d);
 811         }
 812     }
 813 }
 814
 815 void pci_info(Monitor *mon)
 816 {
 817     struct PCIHostBus *host;
 818     QLIST_FOREACH(host, &host_buses, next) {
 819         pci_for_each_device(host->bus, 0, pci_info_device);
 820     }
 821 }
 822
 823 static const char * const pci_nic_models[] = {
 824     "ne2k_pci",
 825     "i82551",
 826     "i82557b",
 827     "i82559er",
 828     "rtl8139",
 829     "e1000",
 830     "pcnet",
 831     "virtio",
 832     NULL
 833 };
 834
 835 static const char * const pci_nic_names[] = {
 836     "ne2k_pci",
 837     "i82551",
 838     "i82557b",
 839     "i82559er",
 840     "rtl8139",
 841     "e1000",
 842     "pcnet",
 843     "virtio-net-pci",
 844     NULL
 845 };
 846
 847 /* Initialize a PCI NIC.  */
 848 /* FIXME callers should check for failure, but don't */
 849 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 850                         const char *default_devaddr)
 851 {
 852     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 853     PCIBus *bus;
 854     int devfn;
 855     PCIDevice *pci_dev;
 856     DeviceState *dev;
 857     int i;
 858
 859     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
 860     if (i < 0)
 861         return NULL;
 862
 863     bus = pci_get_bus_devfn(&devfn, devaddr);
 864     if (!bus) {
 865         qemu_error("Invalid PCI device address %s for device %s\n",
 866                    devaddr, pci_nic_names[i]);
 867         return NULL;
 868     }
 869
 870     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
 871     dev = &pci_dev->qdev;
 872     if (nd->name)
 873         dev->id = qemu_strdup(nd->name);
 874     qdev_set_nic_properties(dev, nd);
 875     if (qdev_init(dev) < 0)
 876         return NULL;
 877     return pci_dev;
 878 }
 879
 880 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 881                                const char *default_devaddr)
 882 {
 883     PCIDevice *res;
 884
 885     if (qemu_show_nic_models(nd->model, pci_nic_models))
 886         exit(0);
 887
 888     res = pci_nic_init(nd, default_model, default_devaddr);
 889     if (!res)
 890         exit(1);
 891     return res;
 892 }
 893
 894 typedef struct {
 895     PCIDevice dev;
 896     PCIBus bus;
 897     uint32_t vid;
 898     uint32_t did;
 899 } PCIBridge;
 900
 901 static void pci_bridge_write_config(PCIDevice *d,
 902                              uint32_t address, uint32_t val, int len)
 903 {
 904     pci_default_write_config(d, address, val, len);
 905 }
 906
 907 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
 908 {
 909     PCIBus *sec;
 910
 911     if (!bus)
 912         return NULL;
 913
 914     if (pci_bus_num(bus) == bus_num) {
 915         return bus;
 916     }
 917
 918     /* try child bus */
 919     QLIST_FOREACH(sec, &bus->child, sibling) {
 920         if (pci_bus_num(sec) <= bus_num && bus_num <= pci_sub_bus(sec)) {
 921             return pci_find_bus(sec, bus_num);
 922         }
 923     }
 924
 925     return NULL;
 926 }
 927
 928 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
 929 {
 930     bus = pci_find_bus(bus, bus_num);
 931
 932     if (!bus)
 933         return NULL;
 934
 935     return bus->devices[PCI_DEVFN(slot, function)];
 936 }
 937
 938 static int pci_bridge_initfn(PCIDevice *dev)
 939 {
 940     PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
 941
 942     pci_config_set_vendor_id(s->dev.config, s->vid);
 943     pci_config_set_device_id(s->dev.config, s->did);
 944
 945     /* TODO: intial value
 946      * command register:
 947      * According to PCI bridge spec, after reset
 948      *   bus master bit is off
 949      *   memory space enable bit is off
 950      * According to manual (805-1251.pdf).(See abp_pbi.c for its links.)
 951      *   the reset value should be zero unless the boot pin is tied high
 952      *   (which is tru) and thus it should be PCI_COMMAND_MEMORY.
 953      *
 954      * For now, don't touch the value.
 955      * Later command register will be set to zero and apb_pci.c will
 956      * override the value.
 957      * Same for latency timer, and multi function bit of header type.
 958      */
 959     pci_set_word(dev->config + PCI_COMMAND,
 960                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 961
 962     pci_set_word(dev->config + PCI_STATUS,
 963                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 964     pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
 965     dev->config[PCI_LATENCY_TIMER] = 0x10;
 966     dev->config[PCI_HEADER_TYPE] =
 967         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE;
 968     pci_set_word(dev->config + PCI_SEC_STATUS,
 969                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 970     return 0;
 971 }
 972
 973 static int pci_bridge_exitfn(PCIDevice *pci_dev)
 974 {
 975     PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
 976     PCIBus *bus = &s->bus;
 977     pci_unregister_secondary_bus(bus);
 978     return 0;
 979 }
 980
 981 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 982                         pci_map_irq_fn map_irq, const char *name)
 983 {
 984     PCIDevice *dev;
 985     PCIBridge *s;
 986
 987     dev = pci_create(bus, devfn, "pci-bridge");
 988     qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
 989     qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
 990     qdev_init_nofail(&dev->qdev);
 991
 992     s = DO_UPCAST(PCIBridge, dev, dev);
 993     pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
 994     return &s->bus;
 995 }
 996
 997 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
 998 {
 999     PCIDevice *pci_dev = (PCIDevice *)qdev;
1000     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1001     PCIBus *bus;
1002     int devfn, rc;
1003
1004     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1005     devfn = pci_dev->devfn;
1006     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1007                                      info->config_read, info->config_write);
1008     assert(pci_dev);
1009     rc = info->init(pci_dev);
1010     if (rc != 0)
1011         return rc;
1012     if (qdev->hotplugged)
1013         bus->hotplug(pci_dev, 1);
1014     return 0;
1015 }
1016
1017 static int pci_unplug_device(DeviceState *qdev)
1018 {
1019     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1020
1021     dev->bus->hotplug(dev, 0);
1022     return 0;
1023 }
1024
1025 void pci_qdev_register(PCIDeviceInfo *info)
1026 {
1027     info->qdev.init = pci_qdev_init;
1028     info->qdev.unplug = pci_unplug_device;
1029     info->qdev.exit = pci_unregister_device;
1030     info->qdev.bus_info = &pci_bus_info;
1031     qdev_register(&info->qdev);
1032 }
1033
1034 void pci_qdev_register_many(PCIDeviceInfo *info)
1035 {
1036     while (info->qdev.name) {
1037         pci_qdev_register(info);
1038         info++;
1039     }
1040 }
1041
1042 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1043 {
1044     DeviceState *dev;
1045
1046     dev = qdev_create(&bus->qbus, name);
1047     qdev_prop_set_uint32(dev, "addr", devfn);
1048     return DO_UPCAST(PCIDevice, qdev, dev);
1049 }
1050
1051 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1052 {
1053     PCIDevice *dev = pci_create(bus, devfn, name);
1054     qdev_init_nofail(&dev->qdev);
1055     return dev;
1056 }
1057
1058 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1059 {
1060     int offset = PCI_CONFIG_HEADER_SIZE;
1061     int i;
1062     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
1063         if (pdev->used[i])
1064             offset = i + 1;
1065         else if (i - offset + 1 == size)
1066             return offset;
1067     return 0;
1068 }
1069
1070 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1071                                         uint8_t *prev_p)
1072 {
1073     uint8_t next, prev;
1074
1075     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1076         return 0;
1077
1078     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1079          prev = next + PCI_CAP_LIST_NEXT)
1080         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1081             break;
1082
1083     if (prev_p)
1084         *prev_p = prev;
1085     return next;
1086 }
1087
1088 /* Reserve space and add capability to the linked list in pci config space */
1089 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1090 {
1091     uint8_t offset = pci_find_space(pdev, size);
1092     uint8_t *config = pdev->config + offset;
1093     if (!offset)
1094         return -ENOSPC;
1095     config[PCI_CAP_LIST_ID] = cap_id;
1096     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1097     pdev->config[PCI_CAPABILITY_LIST] = offset;
1098     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1099     memset(pdev->used + offset, 0xFF, size);
1100     /* Make capability read-only by default */
1101     memset(pdev->wmask + offset, 0, size);
1102     /* Check capability by default */
1103     memset(pdev->cmask + offset, 0xFF, size);
1104     return offset;
1105 }
1106
1107 /* Unlink capability from the pci config space. */
1108 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1109 {
1110     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1111     if (!offset)
1112         return;
1113     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1114     /* Make capability writeable again */
1115     memset(pdev->wmask + offset, 0xff, size);
1116     /* Clear cmask as device-specific registers can't be checked */
1117     memset(pdev->cmask + offset, 0, size);
1118     memset(pdev->used + offset, 0, size);
1119
1120     if (!pdev->config[PCI_CAPABILITY_LIST])
1121         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1122 }
1123
1124 /* Reserve space for capability at a known offset (to call after load). */
1125 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1126 {
1127     memset(pdev->used + offset, 0xff, size);
1128 }
1129
1130 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1131 {
1132     return pci_find_capability_list(pdev, cap_id, NULL);
1133 }
1134
1135 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1136 {
1137     PCIDevice *d = (PCIDevice *)dev;
1138     const pci_class_desc *desc;
1139     char ctxt[64];
1140     PCIIORegion *r;
1141     int i, class;
1142
1143     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1144     desc = pci_class_descriptions;
1145     while (desc->desc && class != desc->class)
1146         desc++;
1147     if (desc->desc) {
1148         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1149     } else {
1150         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1151     }
1152
1153     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1154                    "pci id %04x:%04x (sub %04x:%04x)\n",
1155                    indent, "", ctxt,
1156                    d->config[PCI_SECONDARY_BUS],
1157                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1158                    pci_get_word(d->config + PCI_VENDOR_ID),
1159                    pci_get_word(d->config + PCI_DEVICE_ID),
1160                    pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1161                    pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1162     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1163         r = &d->io_regions[i];
1164         if (!r->size)
1165             continue;
1166         monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1167                        " [0x%"FMT_PCIBUS"]\n",
1168                        indent, "",
1169                        i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1170                        r->addr, r->addr + r->size - 1);
1171     }
1172 }
1173
1174 static PCIDeviceInfo bridge_info = {
1175     .qdev.name    = "pci-bridge",
1176     .qdev.size    = sizeof(PCIBridge),
1177     .init         = pci_bridge_initfn,
1178     .exit         = pci_bridge_exitfn,
1179     .config_write = pci_bridge_write_config,
1180     .qdev.props   = (Property[]) {
1181         DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1182         DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1183         DEFINE_PROP_END_OF_LIST(),
1184     }
1185 };
1186
1187 static void pci_register_devices(void)
1188 {
1189     pci_qdev_register(&bridge_info);
1190 }
1191
1192 device_init(pci_register_devices)