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eepro100: convert to memory API
[qemu/mdroth.git] / hw / ppc405_boards.c
blobad2718102f8edc6194ea97b924243414f8c3a43f
1 /*
2 * QEMU PowerPC 405 evaluation boards emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc405.h"
27 #include "nvram.h"
28 #include "flash.h"
29 #include "sysemu.h"
30 #include "block.h"
31 #include "boards.h"
32 #include "qemu-log.h"
33 #include "loader.h"
34 #include "blockdev.h"
35
36 #define BIOS_FILENAME "ppc405_rom.bin"
37 #define BIOS_SIZE (2048 * 1024)
38
39 #define KERNEL_LOAD_ADDR 0x00000000
40 #define INITRD_LOAD_ADDR 0x01800000
41
42 #define USE_FLASH_BIOS
43
44 #define DEBUG_BOARD_INIT
45
46 /*****************************************************************************/
47 /* PPC405EP reference board (IBM) */
48 /* Standalone board with:
49 * - PowerPC 405EP CPU
50 * - SDRAM (0x00000000)
51 * - Flash (0xFFF80000)
52 * - SRAM (0xFFF00000)
53 * - NVRAM (0xF0000000)
54 * - FPGA (0xF0300000)
55 */
56 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
57 struct ref405ep_fpga_t {
58 uint8_t reg0;
59 uint8_t reg1;
60 };
61
62 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
63 {
64 ref405ep_fpga_t *fpga;
65 uint32_t ret;
66
67 fpga = opaque;
68 switch (addr) {
69 case 0x0:
70 ret = fpga->reg0;
71 break;
72 case 0x1:
73 ret = fpga->reg1;
74 break;
75 default:
76 ret = 0;
77 break;
78 }
79
80 return ret;
81 }
82
83 static void ref405ep_fpga_writeb (void *opaque,
84 target_phys_addr_t addr, uint32_t value)
85 {
86 ref405ep_fpga_t *fpga;
87
88 fpga = opaque;
89 switch (addr) {
90 case 0x0:
91 /* Read only */
92 break;
93 case 0x1:
94 fpga->reg1 = value;
95 break;
96 default:
97 break;
98 }
99 }
100
101 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
102 {
103 uint32_t ret;
104
105 ret = ref405ep_fpga_readb(opaque, addr) << 8;
106 ret |= ref405ep_fpga_readb(opaque, addr + 1);
107
108 return ret;
109 }
110
111 static void ref405ep_fpga_writew (void *opaque,
112 target_phys_addr_t addr, uint32_t value)
113 {
114 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
115 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
116 }
117
118 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
119 {
120 uint32_t ret;
121
122 ret = ref405ep_fpga_readb(opaque, addr) << 24;
123 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
124 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
125 ret |= ref405ep_fpga_readb(opaque, addr + 3);
126
127 return ret;
128 }
129
130 static void ref405ep_fpga_writel (void *opaque,
131 target_phys_addr_t addr, uint32_t value)
132 {
133 ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
134 ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
135 ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
136 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
137 }
138
139 static CPUReadMemoryFunc * const ref405ep_fpga_read[] = {
140 &ref405ep_fpga_readb,
141 &ref405ep_fpga_readw,
142 &ref405ep_fpga_readl,
143 };
144
145 static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
146 &ref405ep_fpga_writeb,
147 &ref405ep_fpga_writew,
148 &ref405ep_fpga_writel,
149 };
150
151 static void ref405ep_fpga_reset (void *opaque)
152 {
153 ref405ep_fpga_t *fpga;
154
155 fpga = opaque;
156 fpga->reg0 = 0x00;
157 fpga->reg1 = 0x0F;
158 }
159
160 static void ref405ep_fpga_init (uint32_t base)
161 {
162 ref405ep_fpga_t *fpga;
163 int fpga_memory;
164
165 fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
166 fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
167 ref405ep_fpga_write, fpga,
168 DEVICE_NATIVE_ENDIAN);
169 cpu_register_physical_memory(base, 0x00000100, fpga_memory);
170 qemu_register_reset(&ref405ep_fpga_reset, fpga);
171 }
172
173 static void ref405ep_init (ram_addr_t ram_size,
174 const char *boot_device,
175 const char *kernel_filename,
176 const char *kernel_cmdline,
177 const char *initrd_filename,
178 const char *cpu_model)
179 {
180 char *filename;
181 ppc4xx_bd_info_t bd;
182 CPUPPCState *env;
183 qemu_irq *pic;
184 ram_addr_t sram_offset, bios_offset, bdloc;
185 target_phys_addr_t ram_bases[2], ram_sizes[2];
186 target_ulong sram_size;
187 long bios_size;
188 //int phy_addr = 0;
189 //static int phy_addr = 1;
190 target_ulong kernel_base, initrd_base;
191 long kernel_size, initrd_size;
192 int linux_boot;
193 int fl_idx, fl_sectors, len;
194 DriveInfo *dinfo;
195
196 /* XXX: fix this */
197 ram_bases[0] = qemu_ram_alloc(NULL, "ef405ep.ram", 0x08000000);
198 ram_sizes[0] = 0x08000000;
199 ram_bases[1] = 0x00000000;
200 ram_sizes[1] = 0x00000000;
201 ram_size = 128 * 1024 * 1024;
202 #ifdef DEBUG_BOARD_INIT
203 printf("%s: register cpu\n", __func__);
204 #endif
205 env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
206 kernel_filename == NULL ? 0 : 1);
207 /* allocate SRAM */
208 sram_size = 512 * 1024;
209 sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size);
210 #ifdef DEBUG_BOARD_INIT
211 printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
212 #endif
213 cpu_register_physical_memory(0xFFF00000, sram_size,
214 sram_offset | IO_MEM_RAM);
215 /* allocate and load BIOS */
216 #ifdef DEBUG_BOARD_INIT
217 printf("%s: register BIOS\n", __func__);
218 #endif
219 fl_idx = 0;
220 #ifdef USE_FLASH_BIOS
221 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
222 if (dinfo) {
223 bios_size = bdrv_getlength(dinfo->bdrv);
224 bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", bios_size);
225 fl_sectors = (bios_size + 65535) >> 16;
226 #ifdef DEBUG_BOARD_INIT
227 printf("Register parallel flash %d size %lx"
228 " at offset %08lx addr %lx '%s' %d\n",
229 fl_idx, bios_size, bios_offset, -bios_size,
230 bdrv_get_device_name(dinfo->bdrv), fl_sectors);
231 #endif
232 pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
233 dinfo->bdrv, 65536, fl_sectors, 1,
234 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
235 1);
236 fl_idx++;
237 } else
238 #endif
239 {
240 #ifdef DEBUG_BOARD_INIT
241 printf("Load BIOS from file\n");
242 #endif
243 bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", BIOS_SIZE);
244 if (bios_name == NULL)
245 bios_name = BIOS_FILENAME;
246 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
247 if (filename) {
248 bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
249 qemu_free(filename);
250 } else {
251 bios_size = -1;
252 }
253 if (bios_size < 0 || bios_size > BIOS_SIZE) {
254 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
255 bios_name);
256 exit(1);
257 }
258 bios_size = (bios_size + 0xfff) & ~0xfff;
259 cpu_register_physical_memory((uint32_t)(-bios_size),
260 bios_size, bios_offset | IO_MEM_ROM);
261 }
262 /* Register FPGA */
263 #ifdef DEBUG_BOARD_INIT
264 printf("%s: register FPGA\n", __func__);
265 #endif
266 ref405ep_fpga_init(0xF0300000);
267 /* Register NVRAM */
268 #ifdef DEBUG_BOARD_INIT
269 printf("%s: register NVRAM\n", __func__);
270 #endif
271 m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
272 /* Load kernel */
273 linux_boot = (kernel_filename != NULL);
274 if (linux_boot) {
275 #ifdef DEBUG_BOARD_INIT
276 printf("%s: load kernel\n", __func__);
277 #endif
278 memset(&bd, 0, sizeof(bd));
279 bd.bi_memstart = 0x00000000;
280 bd.bi_memsize = ram_size;
281 bd.bi_flashstart = -bios_size;
282 bd.bi_flashsize = -bios_size;
283 bd.bi_flashoffset = 0;
284 bd.bi_sramstart = 0xFFF00000;
285 bd.bi_sramsize = sram_size;
286 bd.bi_bootflags = 0;
287 bd.bi_intfreq = 133333333;
288 bd.bi_busfreq = 33333333;
289 bd.bi_baudrate = 115200;
290 bd.bi_s_version[0] = 'Q';
291 bd.bi_s_version[1] = 'M';
292 bd.bi_s_version[2] = 'U';
293 bd.bi_s_version[3] = '\0';
294 bd.bi_r_version[0] = 'Q';
295 bd.bi_r_version[1] = 'E';
296 bd.bi_r_version[2] = 'M';
297 bd.bi_r_version[3] = 'U';
298 bd.bi_r_version[4] = '\0';
299 bd.bi_procfreq = 133333333;
300 bd.bi_plb_busfreq = 33333333;
301 bd.bi_pci_busfreq = 33333333;
302 bd.bi_opbfreq = 33333333;
303 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
304 env->gpr[3] = bdloc;
305 kernel_base = KERNEL_LOAD_ADDR;
306 /* now we can load the kernel */
307 kernel_size = load_image_targphys(kernel_filename, kernel_base,
308 ram_size - kernel_base);
309 if (kernel_size < 0) {
310 fprintf(stderr, "qemu: could not load kernel '%s'\n",
311 kernel_filename);
312 exit(1);
313 }
314 printf("Load kernel size %ld at " TARGET_FMT_lx,
315 kernel_size, kernel_base);
316 /* load initrd */
317 if (initrd_filename) {
318 initrd_base = INITRD_LOAD_ADDR;
319 initrd_size = load_image_targphys(initrd_filename, initrd_base,
320 ram_size - initrd_base);
321 if (initrd_size < 0) {
322 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
323 initrd_filename);
324 exit(1);
325 }
326 } else {
327 initrd_base = 0;
328 initrd_size = 0;
329 }
330 env->gpr[4] = initrd_base;
331 env->gpr[5] = initrd_size;
332 if (kernel_cmdline != NULL) {
333 len = strlen(kernel_cmdline);
334 bdloc -= ((len + 255) & ~255);
335 cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
336 env->gpr[6] = bdloc;
337 env->gpr[7] = bdloc + len;
338 } else {
339 env->gpr[6] = 0;
340 env->gpr[7] = 0;
341 }
342 env->nip = KERNEL_LOAD_ADDR;
343 } else {
344 kernel_base = 0;
345 kernel_size = 0;
346 initrd_base = 0;
347 initrd_size = 0;
348 bdloc = 0;
349 }
350 #ifdef DEBUG_BOARD_INIT
351 printf("%s: Done\n", __func__);
352 #endif
353 printf("bdloc %016lx\n", (unsigned long)bdloc);
354 }
355
356 static QEMUMachine ref405ep_machine = {
357 .name = "ref405ep",
358 .desc = "ref405ep",
359 .init = ref405ep_init,
360 };
361
362 /*****************************************************************************/
363 /* AMCC Taihu evaluation board */
364 /* - PowerPC 405EP processor
365 * - SDRAM 128 MB at 0x00000000
366 * - Boot flash 2 MB at 0xFFE00000
367 * - Application flash 32 MB at 0xFC000000
368 * - 2 serial ports
369 * - 2 ethernet PHY
370 * - 1 USB 1.1 device 0x50000000
371 * - 1 LCD display 0x50100000
372 * - 1 CPLD 0x50100000
373 * - 1 I2C EEPROM
374 * - 1 I2C thermal sensor
375 * - a set of LEDs
376 * - bit-bang SPI port using GPIOs
377 * - 1 EBC interface connector 0 0x50200000
378 * - 1 cardbus controller + expansion slot.
379 * - 1 PCI expansion slot.
380 */
381 typedef struct taihu_cpld_t taihu_cpld_t;
382 struct taihu_cpld_t {
383 uint8_t reg0;
384 uint8_t reg1;
385 };
386
387 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
388 {
389 taihu_cpld_t *cpld;
390 uint32_t ret;
391
392 cpld = opaque;
393 switch (addr) {
394 case 0x0:
395 ret = cpld->reg0;
396 break;
397 case 0x1:
398 ret = cpld->reg1;
399 break;
400 default:
401 ret = 0;
402 break;
403 }
404
405 return ret;
406 }
407
408 static void taihu_cpld_writeb (void *opaque,
409 target_phys_addr_t addr, uint32_t value)
410 {
411 taihu_cpld_t *cpld;
412
413 cpld = opaque;
414 switch (addr) {
415 case 0x0:
416 /* Read only */
417 break;
418 case 0x1:
419 cpld->reg1 = value;
420 break;
421 default:
422 break;
423 }
424 }
425
426 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
427 {
428 uint32_t ret;
429
430 ret = taihu_cpld_readb(opaque, addr) << 8;
431 ret |= taihu_cpld_readb(opaque, addr + 1);
432
433 return ret;
434 }
435
436 static void taihu_cpld_writew (void *opaque,
437 target_phys_addr_t addr, uint32_t value)
438 {
439 taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
440 taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
441 }
442
443 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
444 {
445 uint32_t ret;
446
447 ret = taihu_cpld_readb(opaque, addr) << 24;
448 ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
449 ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
450 ret |= taihu_cpld_readb(opaque, addr + 3);
451
452 return ret;
453 }
454
455 static void taihu_cpld_writel (void *opaque,
456 target_phys_addr_t addr, uint32_t value)
457 {
458 taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
459 taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
460 taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
461 taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
462 }
463
464 static CPUReadMemoryFunc * const taihu_cpld_read[] = {
465 &taihu_cpld_readb,
466 &taihu_cpld_readw,
467 &taihu_cpld_readl,
468 };
469
470 static CPUWriteMemoryFunc * const taihu_cpld_write[] = {
471 &taihu_cpld_writeb,
472 &taihu_cpld_writew,
473 &taihu_cpld_writel,
474 };
475
476 static void taihu_cpld_reset (void *opaque)
477 {
478 taihu_cpld_t *cpld;
479
480 cpld = opaque;
481 cpld->reg0 = 0x01;
482 cpld->reg1 = 0x80;
483 }
484
485 static void taihu_cpld_init (uint32_t base)
486 {
487 taihu_cpld_t *cpld;
488 int cpld_memory;
489
490 cpld = qemu_mallocz(sizeof(taihu_cpld_t));
491 cpld_memory = cpu_register_io_memory(taihu_cpld_read,
492 taihu_cpld_write, cpld,
493 DEVICE_NATIVE_ENDIAN);
494 cpu_register_physical_memory(base, 0x00000100, cpld_memory);
495 qemu_register_reset(&taihu_cpld_reset, cpld);
496 }
497
498 static void taihu_405ep_init(ram_addr_t ram_size,
499 const char *boot_device,
500 const char *kernel_filename,
501 const char *kernel_cmdline,
502 const char *initrd_filename,
503 const char *cpu_model)
504 {
505 char *filename;
506 qemu_irq *pic;
507 ram_addr_t bios_offset;
508 target_phys_addr_t ram_bases[2], ram_sizes[2];
509 long bios_size;
510 target_ulong kernel_base, initrd_base;
511 long kernel_size, initrd_size;
512 int linux_boot;
513 int fl_idx, fl_sectors;
514 DriveInfo *dinfo;
515
516 /* RAM is soldered to the board so the size cannot be changed */
517 ram_bases[0] = qemu_ram_alloc(NULL, "taihu_405ep.ram-0", 0x04000000);
518 ram_sizes[0] = 0x04000000;
519 ram_bases[1] = qemu_ram_alloc(NULL, "taihu_405ep.ram-1", 0x04000000);
520 ram_sizes[1] = 0x04000000;
521 ram_size = 0x08000000;
522 #ifdef DEBUG_BOARD_INIT
523 printf("%s: register cpu\n", __func__);
524 #endif
525 ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
526 kernel_filename == NULL ? 0 : 1);
527 /* allocate and load BIOS */
528 #ifdef DEBUG_BOARD_INIT
529 printf("%s: register BIOS\n", __func__);
530 #endif
531 fl_idx = 0;
532 #if defined(USE_FLASH_BIOS)
533 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
534 if (dinfo) {
535 bios_size = bdrv_getlength(dinfo->bdrv);
536 /* XXX: should check that size is 2MB */
537 // bios_size = 2 * 1024 * 1024;
538 fl_sectors = (bios_size + 65535) >> 16;
539 bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", bios_size);
540 #ifdef DEBUG_BOARD_INIT
541 printf("Register parallel flash %d size %lx"
542 " at offset %08lx addr %lx '%s' %d\n",
543 fl_idx, bios_size, bios_offset, -bios_size,
544 bdrv_get_device_name(dinfo->bdrv), fl_sectors);
545 #endif
546 pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
547 dinfo->bdrv, 65536, fl_sectors, 1,
548 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
549 1);
550 fl_idx++;
551 } else
552 #endif
553 {
554 #ifdef DEBUG_BOARD_INIT
555 printf("Load BIOS from file\n");
556 #endif
557 if (bios_name == NULL)
558 bios_name = BIOS_FILENAME;
559 bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", BIOS_SIZE);
560 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
561 if (filename) {
562 bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
563 qemu_free(filename);
564 } else {
565 bios_size = -1;
566 }
567 if (bios_size < 0 || bios_size > BIOS_SIZE) {
568 fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
569 bios_name);
570 exit(1);
571 }
572 bios_size = (bios_size + 0xfff) & ~0xfff;
573 cpu_register_physical_memory((uint32_t)(-bios_size),
574 bios_size, bios_offset | IO_MEM_ROM);
575 }
576 /* Register Linux flash */
577 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
578 if (dinfo) {
579 bios_size = bdrv_getlength(dinfo->bdrv);
580 /* XXX: should check that size is 32MB */
581 bios_size = 32 * 1024 * 1024;
582 fl_sectors = (bios_size + 65535) >> 16;
583 #ifdef DEBUG_BOARD_INIT
584 printf("Register parallel flash %d size %lx"
585 " at offset %08lx addr " TARGET_FMT_lx " '%s'\n",
586 fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
587 bdrv_get_device_name(dinfo->bdrv));
588 #endif
589 bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.flash", bios_size);
590 pflash_cfi02_register(0xfc000000, bios_offset,
591 dinfo->bdrv, 65536, fl_sectors, 1,
592 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
593 1);
594 fl_idx++;
595 }
596 /* Register CLPD & LCD display */
597 #ifdef DEBUG_BOARD_INIT
598 printf("%s: register CPLD\n", __func__);
599 #endif
600 taihu_cpld_init(0x50100000);
601 /* Load kernel */
602 linux_boot = (kernel_filename != NULL);
603 if (linux_boot) {
604 #ifdef DEBUG_BOARD_INIT
605 printf("%s: load kernel\n", __func__);
606 #endif
607 kernel_base = KERNEL_LOAD_ADDR;
608 /* now we can load the kernel */
609 kernel_size = load_image_targphys(kernel_filename, kernel_base,
610 ram_size - kernel_base);
611 if (kernel_size < 0) {
612 fprintf(stderr, "qemu: could not load kernel '%s'\n",
613 kernel_filename);
614 exit(1);
615 }
616 /* load initrd */
617 if (initrd_filename) {
618 initrd_base = INITRD_LOAD_ADDR;
619 initrd_size = load_image_targphys(initrd_filename, initrd_base,
620 ram_size - initrd_base);
621 if (initrd_size < 0) {
622 fprintf(stderr,
623 "qemu: could not load initial ram disk '%s'\n",
624 initrd_filename);
625 exit(1);
626 }
627 } else {
628 initrd_base = 0;
629 initrd_size = 0;
630 }
631 } else {
632 kernel_base = 0;
633 kernel_size = 0;
634 initrd_base = 0;
635 initrd_size = 0;
636 }
637 #ifdef DEBUG_BOARD_INIT
638 printf("%s: Done\n", __func__);
639 #endif
640 }
641
642 static QEMUMachine taihu_machine = {
643 .name = "taihu",
644 .desc = "taihu",
645 .init = taihu_405ep_init,
646 };
647
648 static void ppc405_machine_init(void)
649 {
650 qemu_register_machine(&ref405ep_machine);
651 qemu_register_machine(&taihu_machine);
652 }
653
654 machine_init(ppc405_machine_init);
various patches