4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
42 #define X86_64_ONLY(x) x
43 #define X86_64_DEF(...) __VA_ARGS__
44 #define CODE64(s) ((s)->code64)
45 #define REX_X(s) ((s)->rex_x)
46 #define REX_B(s) ((s)->rex_b)
47 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
49 #define BUGGY_64(x) NULL
52 #define X86_64_ONLY(x) NULL
53 #define X86_64_DEF(...)
59 //#define MACRO_TEST 1
61 /* global register indexes */
62 static TCGv_ptr cpu_env
;
63 static TCGv cpu_A0
, cpu_cc_src
, cpu_cc_dst
, cpu_cc_tmp
;
64 static TCGv_i32 cpu_cc_op
;
65 static TCGv cpu_regs
[CPU_NB_REGS
];
67 static TCGv cpu_T
[2], cpu_T3
;
68 /* local register indexes (only used inside old micro ops) */
69 static TCGv cpu_tmp0
, cpu_tmp4
;
70 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
71 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
72 static TCGv_i64 cpu_tmp1_i64
;
75 #include "gen-icount.h"
78 static int x86_64_hregs
;
81 typedef struct DisasContext
{
82 /* current insn context */
83 int override
; /* -1 if no override */
86 target_ulong pc
; /* pc = eip + cs_base */
87 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
88 static state change (stop translation) */
89 /* current block context */
90 target_ulong cs_base
; /* base of CS segment */
91 int pe
; /* protected mode */
92 int code32
; /* 32 bit code segment */
94 int lma
; /* long mode active */
95 int code64
; /* 64 bit code segment */
98 int ss32
; /* 32 bit stack segment */
99 int cc_op
; /* current CC operation */
100 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
101 int f_st
; /* currently unused */
102 int vm86
; /* vm86 mode */
105 int tf
; /* TF cpu flag */
106 int singlestep_enabled
; /* "hardware" single step enabled */
107 int jmp_opt
; /* use direct block chaining for direct jumps */
108 int mem_index
; /* select memory access functions */
109 uint64_t flags
; /* all execution flags */
110 struct TranslationBlock
*tb
;
111 int popl_esp_hack
; /* for correct popl with esp base handling */
112 int rip_offset
; /* only used in x86_64, but left for simplicity */
114 int cpuid_ext_features
;
115 int cpuid_ext2_features
;
116 int cpuid_ext3_features
;
119 static void gen_eob(DisasContext
*s
);
120 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
121 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
123 /* i386 arith/logic operations */
143 OP_SHL1
, /* undocumented */
167 /* I386 int registers */
168 OR_EAX
, /* MUST be even numbered */
177 OR_TMP0
= 16, /* temporary operand register */
179 OR_A0
, /* temporary register used when doing address evaluation */
182 static inline void gen_op_movl_T0_0(void)
184 tcg_gen_movi_tl(cpu_T
[0], 0);
187 static inline void gen_op_movl_T0_im(int32_t val
)
189 tcg_gen_movi_tl(cpu_T
[0], val
);
192 static inline void gen_op_movl_T0_imu(uint32_t val
)
194 tcg_gen_movi_tl(cpu_T
[0], val
);
197 static inline void gen_op_movl_T1_im(int32_t val
)
199 tcg_gen_movi_tl(cpu_T
[1], val
);
202 static inline void gen_op_movl_T1_imu(uint32_t val
)
204 tcg_gen_movi_tl(cpu_T
[1], val
);
207 static inline void gen_op_movl_A0_im(uint32_t val
)
209 tcg_gen_movi_tl(cpu_A0
, val
);
213 static inline void gen_op_movq_A0_im(int64_t val
)
215 tcg_gen_movi_tl(cpu_A0
, val
);
219 static inline void gen_movtl_T0_im(target_ulong val
)
221 tcg_gen_movi_tl(cpu_T
[0], val
);
224 static inline void gen_movtl_T1_im(target_ulong val
)
226 tcg_gen_movi_tl(cpu_T
[1], val
);
229 static inline void gen_op_andl_T0_ffff(void)
231 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
234 static inline void gen_op_andl_T0_im(uint32_t val
)
236 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], val
);
239 static inline void gen_op_movl_T0_T1(void)
241 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
244 static inline void gen_op_andl_A0_ffff(void)
246 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffff);
251 #define NB_OP_SIZES 4
253 #else /* !TARGET_X86_64 */
255 #define NB_OP_SIZES 3
257 #endif /* !TARGET_X86_64 */
259 #if defined(HOST_WORDS_BIGENDIAN)
260 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
261 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
262 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
263 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
264 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
266 #define REG_B_OFFSET 0
267 #define REG_H_OFFSET 1
268 #define REG_W_OFFSET 0
269 #define REG_L_OFFSET 0
270 #define REG_LH_OFFSET 4
273 static inline void gen_op_mov_reg_v(int ot
, int reg
, TCGv t0
)
279 tmp
= tcg_temp_new();
280 tcg_gen_ext8u_tl(tmp
, t0
);
281 if (reg
< 4 X86_64_DEF( || reg
>= 8 || x86_64_hregs
)) {
282 tcg_gen_andi_tl(cpu_regs
[reg
], cpu_regs
[reg
], ~0xff);
283 tcg_gen_or_tl(cpu_regs
[reg
], cpu_regs
[reg
], tmp
);
285 tcg_gen_shli_tl(tmp
, tmp
, 8);
286 tcg_gen_andi_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], ~0xff00);
287 tcg_gen_or_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], tmp
);
292 tmp
= tcg_temp_new();
293 tcg_gen_ext16u_tl(tmp
, t0
);
294 tcg_gen_andi_tl(cpu_regs
[reg
], cpu_regs
[reg
], ~0xffff);
295 tcg_gen_or_tl(cpu_regs
[reg
], cpu_regs
[reg
], tmp
);
298 default: /* XXX this shouldn't be reached; abort? */
300 /* For x86_64, this sets the higher half of register to zero.
301 For i386, this is equivalent to a mov. */
302 tcg_gen_ext32u_tl(cpu_regs
[reg
], t0
);
306 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
312 static inline void gen_op_mov_reg_T0(int ot
, int reg
)
314 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
317 static inline void gen_op_mov_reg_T1(int ot
, int reg
)
319 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
322 static inline void gen_op_mov_reg_A0(int size
, int reg
)
328 tmp
= tcg_temp_new();
329 tcg_gen_ext16u_tl(tmp
, cpu_A0
);
330 tcg_gen_andi_tl(cpu_regs
[reg
], cpu_regs
[reg
], ~0xffff);
331 tcg_gen_or_tl(cpu_regs
[reg
], cpu_regs
[reg
], tmp
);
334 default: /* XXX this shouldn't be reached; abort? */
336 /* For x86_64, this sets the higher half of register to zero.
337 For i386, this is equivalent to a mov. */
338 tcg_gen_ext32u_tl(cpu_regs
[reg
], cpu_A0
);
342 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_A0
);
348 static inline void gen_op_mov_v_reg(int ot
, TCGv t0
, int reg
)
352 if (reg
< 4 X86_64_DEF( || reg
>= 8 || x86_64_hregs
)) {
355 tcg_gen_shri_tl(t0
, cpu_regs
[reg
- 4], 8);
356 tcg_gen_ext8u_tl(t0
, t0
);
361 tcg_gen_mov_tl(t0
, cpu_regs
[reg
]);
366 static inline void gen_op_mov_TN_reg(int ot
, int t_index
, int reg
)
368 gen_op_mov_v_reg(ot
, cpu_T
[t_index
], reg
);
371 static inline void gen_op_movl_A0_reg(int reg
)
373 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
376 static inline void gen_op_addl_A0_im(int32_t val
)
378 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
380 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
385 static inline void gen_op_addq_A0_im(int64_t val
)
387 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
391 static void gen_add_A0_im(DisasContext
*s
, int val
)
395 gen_op_addq_A0_im(val
);
398 gen_op_addl_A0_im(val
);
401 static inline void gen_op_addl_T0_T1(void)
403 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
406 static inline void gen_op_jmp_T0(void)
408 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUState
, eip
));
411 static inline void gen_op_add_reg_im(int size
, int reg
, int32_t val
)
415 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
416 tcg_gen_ext16u_tl(cpu_tmp0
, cpu_tmp0
);
417 tcg_gen_andi_tl(cpu_regs
[reg
], cpu_regs
[reg
], ~0xffff);
418 tcg_gen_or_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
);
421 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
422 /* For x86_64, this sets the higher half of register to zero.
423 For i386, this is equivalent to a nop. */
424 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
425 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
429 tcg_gen_addi_tl(cpu_regs
[reg
], cpu_regs
[reg
], val
);
435 static inline void gen_op_add_reg_T0(int size
, int reg
)
439 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
440 tcg_gen_ext16u_tl(cpu_tmp0
, cpu_tmp0
);
441 tcg_gen_andi_tl(cpu_regs
[reg
], cpu_regs
[reg
], ~0xffff);
442 tcg_gen_or_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
);
445 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
446 /* For x86_64, this sets the higher half of register to zero.
447 For i386, this is equivalent to a nop. */
448 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
449 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
453 tcg_gen_add_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_T
[0]);
459 static inline void gen_op_set_cc_op(int32_t val
)
461 tcg_gen_movi_i32(cpu_cc_op
, val
);
464 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
466 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
468 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
469 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
470 /* For x86_64, this sets the higher half of register to zero.
471 For i386, this is equivalent to a nop. */
472 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
475 static inline void gen_op_movl_A0_seg(int reg
)
477 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
) + REG_L_OFFSET
);
480 static inline void gen_op_addl_A0_seg(int reg
)
482 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
));
483 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
485 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
490 static inline void gen_op_movq_A0_seg(int reg
)
492 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
));
495 static inline void gen_op_addq_A0_seg(int reg
)
497 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
));
498 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
501 static inline void gen_op_movq_A0_reg(int reg
)
503 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
506 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
508 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
510 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
511 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
515 static inline void gen_op_lds_T0_A0(int idx
)
517 int mem_index
= (idx
>> 2) - 1;
520 tcg_gen_qemu_ld8s(cpu_T
[0], cpu_A0
, mem_index
);
523 tcg_gen_qemu_ld16s(cpu_T
[0], cpu_A0
, mem_index
);
527 tcg_gen_qemu_ld32s(cpu_T
[0], cpu_A0
, mem_index
);
532 static inline void gen_op_ld_v(int idx
, TCGv t0
, TCGv a0
)
534 int mem_index
= (idx
>> 2) - 1;
537 tcg_gen_qemu_ld8u(t0
, a0
, mem_index
);
540 tcg_gen_qemu_ld16u(t0
, a0
, mem_index
);
543 tcg_gen_qemu_ld32u(t0
, a0
, mem_index
);
547 /* Should never happen on 32-bit targets. */
549 tcg_gen_qemu_ld64(t0
, a0
, mem_index
);
555 /* XXX: always use ldu or lds */
556 static inline void gen_op_ld_T0_A0(int idx
)
558 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
561 static inline void gen_op_ldu_T0_A0(int idx
)
563 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
566 static inline void gen_op_ld_T1_A0(int idx
)
568 gen_op_ld_v(idx
, cpu_T
[1], cpu_A0
);
571 static inline void gen_op_st_v(int idx
, TCGv t0
, TCGv a0
)
573 int mem_index
= (idx
>> 2) - 1;
576 tcg_gen_qemu_st8(t0
, a0
, mem_index
);
579 tcg_gen_qemu_st16(t0
, a0
, mem_index
);
582 tcg_gen_qemu_st32(t0
, a0
, mem_index
);
586 /* Should never happen on 32-bit targets. */
588 tcg_gen_qemu_st64(t0
, a0
, mem_index
);
594 static inline void gen_op_st_T0_A0(int idx
)
596 gen_op_st_v(idx
, cpu_T
[0], cpu_A0
);
599 static inline void gen_op_st_T1_A0(int idx
)
601 gen_op_st_v(idx
, cpu_T
[1], cpu_A0
);
604 static inline void gen_jmp_im(target_ulong pc
)
606 tcg_gen_movi_tl(cpu_tmp0
, pc
);
607 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, eip
));
610 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
614 override
= s
->override
;
618 gen_op_movq_A0_seg(override
);
619 gen_op_addq_A0_reg_sN(0, R_ESI
);
621 gen_op_movq_A0_reg(R_ESI
);
627 if (s
->addseg
&& override
< 0)
630 gen_op_movl_A0_seg(override
);
631 gen_op_addl_A0_reg_sN(0, R_ESI
);
633 gen_op_movl_A0_reg(R_ESI
);
636 /* 16 address, always override */
639 gen_op_movl_A0_reg(R_ESI
);
640 gen_op_andl_A0_ffff();
641 gen_op_addl_A0_seg(override
);
645 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
649 gen_op_movq_A0_reg(R_EDI
);
654 gen_op_movl_A0_seg(R_ES
);
655 gen_op_addl_A0_reg_sN(0, R_EDI
);
657 gen_op_movl_A0_reg(R_EDI
);
660 gen_op_movl_A0_reg(R_EDI
);
661 gen_op_andl_A0_ffff();
662 gen_op_addl_A0_seg(R_ES
);
666 static inline void gen_op_movl_T0_Dshift(int ot
)
668 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUState
, df
));
669 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
672 static void gen_extu(int ot
, TCGv reg
)
676 tcg_gen_ext8u_tl(reg
, reg
);
679 tcg_gen_ext16u_tl(reg
, reg
);
682 tcg_gen_ext32u_tl(reg
, reg
);
689 static void gen_exts(int ot
, TCGv reg
)
693 tcg_gen_ext8s_tl(reg
, reg
);
696 tcg_gen_ext16s_tl(reg
, reg
);
699 tcg_gen_ext32s_tl(reg
, reg
);
706 static inline void gen_op_jnz_ecx(int size
, int label1
)
708 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
709 gen_extu(size
+ 1, cpu_tmp0
);
710 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
713 static inline void gen_op_jz_ecx(int size
, int label1
)
715 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
716 gen_extu(size
+ 1, cpu_tmp0
);
717 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
720 static void gen_helper_in_func(int ot
, TCGv v
, TCGv_i32 n
)
723 case 0: gen_helper_inb(v
, n
); break;
724 case 1: gen_helper_inw(v
, n
); break;
725 case 2: gen_helper_inl(v
, n
); break;
730 static void gen_helper_out_func(int ot
, TCGv_i32 v
, TCGv_i32 n
)
733 case 0: gen_helper_outb(v
, n
); break;
734 case 1: gen_helper_outw(v
, n
); break;
735 case 2: gen_helper_outl(v
, n
); break;
740 static void gen_check_io(DisasContext
*s
, int ot
, target_ulong cur_eip
,
744 target_ulong next_eip
;
747 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
748 if (s
->cc_op
!= CC_OP_DYNAMIC
)
749 gen_op_set_cc_op(s
->cc_op
);
752 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
754 case 0: gen_helper_check_iob(cpu_tmp2_i32
); break;
755 case 1: gen_helper_check_iow(cpu_tmp2_i32
); break;
756 case 2: gen_helper_check_iol(cpu_tmp2_i32
); break;
759 if(s
->flags
& HF_SVMI_MASK
) {
761 if (s
->cc_op
!= CC_OP_DYNAMIC
)
762 gen_op_set_cc_op(s
->cc_op
);
766 svm_flags
|= (1 << (4 + ot
));
767 next_eip
= s
->pc
- s
->cs_base
;
768 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
769 gen_helper_svm_check_io(cpu_tmp2_i32
, tcg_const_i32(svm_flags
),
770 tcg_const_i32(next_eip
- cur_eip
));
774 static inline void gen_movs(DisasContext
*s
, int ot
)
776 gen_string_movl_A0_ESI(s
);
777 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
778 gen_string_movl_A0_EDI(s
);
779 gen_op_st_T0_A0(ot
+ s
->mem_index
);
780 gen_op_movl_T0_Dshift(ot
);
781 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
782 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
785 static inline void gen_update_cc_op(DisasContext
*s
)
787 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
788 gen_op_set_cc_op(s
->cc_op
);
789 s
->cc_op
= CC_OP_DYNAMIC
;
793 static void gen_op_update1_cc(void)
795 tcg_gen_discard_tl(cpu_cc_src
);
796 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
799 static void gen_op_update2_cc(void)
801 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
802 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
805 static inline void gen_op_cmpl_T0_T1_cc(void)
807 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
808 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
811 static inline void gen_op_testl_T0_T1_cc(void)
813 tcg_gen_discard_tl(cpu_cc_src
);
814 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
817 static void gen_op_update_neg_cc(void)
819 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
820 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
823 /* compute eflags.C to reg */
824 static void gen_compute_eflags_c(TCGv reg
)
826 gen_helper_cc_compute_c(cpu_tmp2_i32
, cpu_cc_op
);
827 tcg_gen_extu_i32_tl(reg
, cpu_tmp2_i32
);
830 /* compute all eflags to cc_src */
831 static void gen_compute_eflags(TCGv reg
)
833 gen_helper_cc_compute_all(cpu_tmp2_i32
, cpu_cc_op
);
834 tcg_gen_extu_i32_tl(reg
, cpu_tmp2_i32
);
837 static inline void gen_setcc_slow_T0(DisasContext
*s
, int jcc_op
)
839 if (s
->cc_op
!= CC_OP_DYNAMIC
)
840 gen_op_set_cc_op(s
->cc_op
);
843 gen_compute_eflags(cpu_T
[0]);
844 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 11);
845 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
848 gen_compute_eflags_c(cpu_T
[0]);
851 gen_compute_eflags(cpu_T
[0]);
852 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 6);
853 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
856 gen_compute_eflags(cpu_tmp0
);
857 tcg_gen_shri_tl(cpu_T
[0], cpu_tmp0
, 6);
858 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
859 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
862 gen_compute_eflags(cpu_T
[0]);
863 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 7);
864 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
867 gen_compute_eflags(cpu_T
[0]);
868 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 2);
869 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
872 gen_compute_eflags(cpu_tmp0
);
873 tcg_gen_shri_tl(cpu_T
[0], cpu_tmp0
, 11); /* CC_O */
874 tcg_gen_shri_tl(cpu_tmp0
, cpu_tmp0
, 7); /* CC_S */
875 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
876 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
880 gen_compute_eflags(cpu_tmp0
);
881 tcg_gen_shri_tl(cpu_T
[0], cpu_tmp0
, 11); /* CC_O */
882 tcg_gen_shri_tl(cpu_tmp4
, cpu_tmp0
, 7); /* CC_S */
883 tcg_gen_shri_tl(cpu_tmp0
, cpu_tmp0
, 6); /* CC_Z */
884 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
885 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
886 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
891 /* return true if setcc_slow is not needed (WARNING: must be kept in
892 sync with gen_jcc1) */
893 static int is_fast_jcc_case(DisasContext
*s
, int b
)
896 jcc_op
= (b
>> 1) & 7;
898 /* we optimize the cmp/jcc case */
903 if (jcc_op
== JCC_O
|| jcc_op
== JCC_P
)
907 /* some jumps are easy to compute */
932 if (jcc_op
!= JCC_Z
&& jcc_op
!= JCC_S
)
942 /* generate a conditional jump to label 'l1' according to jump opcode
943 value 'b'. In the fast case, T0 is guaranted not to be used. */
944 static inline void gen_jcc1(DisasContext
*s
, int cc_op
, int b
, int l1
)
946 int inv
, jcc_op
, size
, cond
;
950 jcc_op
= (b
>> 1) & 7;
953 /* we optimize the cmp/jcc case */
959 size
= cc_op
- CC_OP_SUBB
;
965 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0xff);
969 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0xffff);
974 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0xffffffff);
982 tcg_gen_brcondi_tl(inv
? TCG_COND_NE
: TCG_COND_EQ
, t0
, 0, l1
);
988 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0x80);
989 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, cpu_tmp0
,
993 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0x8000);
994 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, cpu_tmp0
,
999 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0x80000000);
1000 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, cpu_tmp0
,
1005 tcg_gen_brcondi_tl(inv
? TCG_COND_GE
: TCG_COND_LT
, cpu_cc_dst
,
1012 cond
= inv
? TCG_COND_GEU
: TCG_COND_LTU
;
1015 cond
= inv
? TCG_COND_GTU
: TCG_COND_LEU
;
1017 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1021 tcg_gen_andi_tl(cpu_tmp4
, cpu_tmp4
, 0xff);
1022 tcg_gen_andi_tl(t0
, cpu_cc_src
, 0xff);
1026 tcg_gen_andi_tl(cpu_tmp4
, cpu_tmp4
, 0xffff);
1027 tcg_gen_andi_tl(t0
, cpu_cc_src
, 0xffff);
1029 #ifdef TARGET_X86_64
1032 tcg_gen_andi_tl(cpu_tmp4
, cpu_tmp4
, 0xffffffff);
1033 tcg_gen_andi_tl(t0
, cpu_cc_src
, 0xffffffff);
1040 tcg_gen_brcond_tl(cond
, cpu_tmp4
, t0
, l1
);
1044 cond
= inv
? TCG_COND_GE
: TCG_COND_LT
;
1047 cond
= inv
? TCG_COND_GT
: TCG_COND_LE
;
1049 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1053 tcg_gen_ext8s_tl(cpu_tmp4
, cpu_tmp4
);
1054 tcg_gen_ext8s_tl(t0
, cpu_cc_src
);
1058 tcg_gen_ext16s_tl(cpu_tmp4
, cpu_tmp4
);
1059 tcg_gen_ext16s_tl(t0
, cpu_cc_src
);
1061 #ifdef TARGET_X86_64
1064 tcg_gen_ext32s_tl(cpu_tmp4
, cpu_tmp4
);
1065 tcg_gen_ext32s_tl(t0
, cpu_cc_src
);
1072 tcg_gen_brcond_tl(cond
, cpu_tmp4
, t0
, l1
);
1080 /* some jumps are easy to compute */
1122 size
= (cc_op
- CC_OP_ADDB
) & 3;
1125 size
= (cc_op
- CC_OP_ADDB
) & 3;
1133 gen_setcc_slow_T0(s
, jcc_op
);
1134 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
,
1140 /* XXX: does not work with gdbstub "ice" single step - not a
1142 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1146 l1
= gen_new_label();
1147 l2
= gen_new_label();
1148 gen_op_jnz_ecx(s
->aflag
, l1
);
1150 gen_jmp_tb(s
, next_eip
, 1);
1155 static inline void gen_stos(DisasContext
*s
, int ot
)
1157 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1158 gen_string_movl_A0_EDI(s
);
1159 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1160 gen_op_movl_T0_Dshift(ot
);
1161 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1164 static inline void gen_lods(DisasContext
*s
, int ot
)
1166 gen_string_movl_A0_ESI(s
);
1167 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1168 gen_op_mov_reg_T0(ot
, R_EAX
);
1169 gen_op_movl_T0_Dshift(ot
);
1170 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1173 static inline void gen_scas(DisasContext
*s
, int ot
)
1175 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1176 gen_string_movl_A0_EDI(s
);
1177 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1178 gen_op_cmpl_T0_T1_cc();
1179 gen_op_movl_T0_Dshift(ot
);
1180 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1183 static inline void gen_cmps(DisasContext
*s
, int ot
)
1185 gen_string_movl_A0_ESI(s
);
1186 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1187 gen_string_movl_A0_EDI(s
);
1188 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1189 gen_op_cmpl_T0_T1_cc();
1190 gen_op_movl_T0_Dshift(ot
);
1191 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1192 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1195 static inline void gen_ins(DisasContext
*s
, int ot
)
1199 gen_string_movl_A0_EDI(s
);
1200 /* Note: we must do this dummy write first to be restartable in
1201 case of page fault. */
1203 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1204 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1205 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1206 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1207 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1208 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1209 gen_op_movl_T0_Dshift(ot
);
1210 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1215 static inline void gen_outs(DisasContext
*s
, int ot
)
1219 gen_string_movl_A0_ESI(s
);
1220 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1222 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1223 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1224 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1225 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1226 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1228 gen_op_movl_T0_Dshift(ot
);
1229 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1234 /* same method as Valgrind : we generate jumps to current or next
1236 #define GEN_REPZ(op) \
1237 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1238 target_ulong cur_eip, target_ulong next_eip) \
1241 gen_update_cc_op(s); \
1242 l2 = gen_jz_ecx_string(s, next_eip); \
1243 gen_ ## op(s, ot); \
1244 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1245 /* a loop would cause two single step exceptions if ECX = 1 \
1246 before rep string_insn */ \
1248 gen_op_jz_ecx(s->aflag, l2); \
1249 gen_jmp(s, cur_eip); \
1252 #define GEN_REPZ2(op) \
1253 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1254 target_ulong cur_eip, \
1255 target_ulong next_eip, \
1259 gen_update_cc_op(s); \
1260 l2 = gen_jz_ecx_string(s, next_eip); \
1261 gen_ ## op(s, ot); \
1262 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1263 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1264 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1266 gen_op_jz_ecx(s->aflag, l2); \
1267 gen_jmp(s, cur_eip); \
1278 static void gen_helper_fp_arith_ST0_FT0(int op
)
1281 case 0: gen_helper_fadd_ST0_FT0(); break;
1282 case 1: gen_helper_fmul_ST0_FT0(); break;
1283 case 2: gen_helper_fcom_ST0_FT0(); break;
1284 case 3: gen_helper_fcom_ST0_FT0(); break;
1285 case 4: gen_helper_fsub_ST0_FT0(); break;
1286 case 5: gen_helper_fsubr_ST0_FT0(); break;
1287 case 6: gen_helper_fdiv_ST0_FT0(); break;
1288 case 7: gen_helper_fdivr_ST0_FT0(); break;
1292 /* NOTE the exception in "r" op ordering */
1293 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1295 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1297 case 0: gen_helper_fadd_STN_ST0(tmp
); break;
1298 case 1: gen_helper_fmul_STN_ST0(tmp
); break;
1299 case 4: gen_helper_fsubr_STN_ST0(tmp
); break;
1300 case 5: gen_helper_fsub_STN_ST0(tmp
); break;
1301 case 6: gen_helper_fdivr_STN_ST0(tmp
); break;
1302 case 7: gen_helper_fdiv_STN_ST0(tmp
); break;
1306 /* if d == OR_TMP0, it means memory operand (address in A0) */
1307 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
)
1310 gen_op_mov_TN_reg(ot
, 0, d
);
1312 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1316 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1317 gen_op_set_cc_op(s1
->cc_op
);
1318 gen_compute_eflags_c(cpu_tmp4
);
1319 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1320 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1322 gen_op_mov_reg_T0(ot
, d
);
1324 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1325 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1326 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1327 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1328 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1329 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_ADDB
+ ot
);
1330 s1
->cc_op
= CC_OP_DYNAMIC
;
1333 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1334 gen_op_set_cc_op(s1
->cc_op
);
1335 gen_compute_eflags_c(cpu_tmp4
);
1336 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1337 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1339 gen_op_mov_reg_T0(ot
, d
);
1341 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1342 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1343 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1344 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1345 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1346 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_SUBB
+ ot
);
1347 s1
->cc_op
= CC_OP_DYNAMIC
;
1350 gen_op_addl_T0_T1();
1352 gen_op_mov_reg_T0(ot
, d
);
1354 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1355 gen_op_update2_cc();
1356 s1
->cc_op
= CC_OP_ADDB
+ ot
;
1359 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1361 gen_op_mov_reg_T0(ot
, d
);
1363 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1364 gen_op_update2_cc();
1365 s1
->cc_op
= CC_OP_SUBB
+ ot
;
1369 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1371 gen_op_mov_reg_T0(ot
, d
);
1373 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1374 gen_op_update1_cc();
1375 s1
->cc_op
= CC_OP_LOGICB
+ ot
;
1378 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1380 gen_op_mov_reg_T0(ot
, d
);
1382 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1383 gen_op_update1_cc();
1384 s1
->cc_op
= CC_OP_LOGICB
+ ot
;
1387 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1389 gen_op_mov_reg_T0(ot
, d
);
1391 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1392 gen_op_update1_cc();
1393 s1
->cc_op
= CC_OP_LOGICB
+ ot
;
1396 gen_op_cmpl_T0_T1_cc();
1397 s1
->cc_op
= CC_OP_SUBB
+ ot
;
1402 /* if d == OR_TMP0, it means memory operand (address in A0) */
1403 static void gen_inc(DisasContext
*s1
, int ot
, int d
, int c
)
1406 gen_op_mov_TN_reg(ot
, 0, d
);
1408 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1409 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1410 gen_op_set_cc_op(s1
->cc_op
);
1412 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1413 s1
->cc_op
= CC_OP_INCB
+ ot
;
1415 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1416 s1
->cc_op
= CC_OP_DECB
+ ot
;
1419 gen_op_mov_reg_T0(ot
, d
);
1421 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1422 gen_compute_eflags_c(cpu_cc_src
);
1423 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1426 static void gen_shift_rm_T1(DisasContext
*s
, int ot
, int op1
,
1427 int is_right
, int is_arith
)
1440 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1442 gen_op_mov_TN_reg(ot
, 0, op1
);
1444 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1446 tcg_gen_addi_tl(cpu_tmp5
, cpu_T
[1], -1);
1450 gen_exts(ot
, cpu_T
[0]);
1451 tcg_gen_sar_tl(cpu_T3
, cpu_T
[0], cpu_tmp5
);
1452 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1454 gen_extu(ot
, cpu_T
[0]);
1455 tcg_gen_shr_tl(cpu_T3
, cpu_T
[0], cpu_tmp5
);
1456 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1459 tcg_gen_shl_tl(cpu_T3
, cpu_T
[0], cpu_tmp5
);
1460 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1465 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1467 gen_op_mov_reg_T0(ot
, op1
);
1469 /* update eflags if non zero shift */
1470 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1471 gen_op_set_cc_op(s
->cc_op
);
1473 /* XXX: inefficient */
1474 t0
= tcg_temp_local_new();
1475 t1
= tcg_temp_local_new();
1477 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1478 tcg_gen_mov_tl(t1
, cpu_T3
);
1480 shift_label
= gen_new_label();
1481 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_T
[1], 0, shift_label
);
1483 tcg_gen_mov_tl(cpu_cc_src
, t1
);
1484 tcg_gen_mov_tl(cpu_cc_dst
, t0
);
1486 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1488 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
1490 gen_set_label(shift_label
);
1491 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1497 static void gen_shift_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1498 int is_right
, int is_arith
)
1509 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1511 gen_op_mov_TN_reg(ot
, 0, op1
);
1517 gen_exts(ot
, cpu_T
[0]);
1518 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1519 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1521 gen_extu(ot
, cpu_T
[0]);
1522 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1523 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1526 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1527 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1533 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1535 gen_op_mov_reg_T0(ot
, op1
);
1537 /* update eflags if non zero shift */
1539 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1540 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1542 s
->cc_op
= CC_OP_SARB
+ ot
;
1544 s
->cc_op
= CC_OP_SHLB
+ ot
;
1548 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1551 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1553 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1556 static void gen_rot_rm_T1(DisasContext
*s
, int ot
, int op1
,
1560 int label1
, label2
, data_bits
;
1561 TCGv t0
, t1
, t2
, a0
;
1563 /* XXX: inefficient, but we must use local temps */
1564 t0
= tcg_temp_local_new();
1565 t1
= tcg_temp_local_new();
1566 t2
= tcg_temp_local_new();
1567 a0
= tcg_temp_local_new();
1575 if (op1
== OR_TMP0
) {
1576 tcg_gen_mov_tl(a0
, cpu_A0
);
1577 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1579 gen_op_mov_v_reg(ot
, t0
, op1
);
1582 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1584 tcg_gen_andi_tl(t1
, t1
, mask
);
1586 /* Must test zero case to avoid using undefined behaviour in TCG
1588 label1
= gen_new_label();
1589 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label1
);
1592 tcg_gen_andi_tl(cpu_tmp0
, t1
, (1 << (3 + ot
)) - 1);
1594 tcg_gen_mov_tl(cpu_tmp0
, t1
);
1597 tcg_gen_mov_tl(t2
, t0
);
1599 data_bits
= 8 << ot
;
1600 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1601 fix TCG definition) */
1603 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1604 tcg_gen_subfi_tl(cpu_tmp0
, data_bits
, cpu_tmp0
);
1605 tcg_gen_shl_tl(t0
, t0
, cpu_tmp0
);
1607 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1608 tcg_gen_subfi_tl(cpu_tmp0
, data_bits
, cpu_tmp0
);
1609 tcg_gen_shr_tl(t0
, t0
, cpu_tmp0
);
1611 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1613 gen_set_label(label1
);
1615 if (op1
== OR_TMP0
) {
1616 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1618 gen_op_mov_reg_v(ot
, op1
, t0
);
1622 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1623 gen_op_set_cc_op(s
->cc_op
);
1625 label2
= gen_new_label();
1626 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label2
);
1628 gen_compute_eflags(cpu_cc_src
);
1629 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1630 tcg_gen_xor_tl(cpu_tmp0
, t2
, t0
);
1631 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1632 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1633 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1635 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1637 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1638 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1640 tcg_gen_discard_tl(cpu_cc_dst
);
1641 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_EFLAGS
);
1643 gen_set_label(label2
);
1644 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1652 static void gen_rot_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1659 /* XXX: inefficient, but we must use local temps */
1660 t0
= tcg_temp_local_new();
1661 t1
= tcg_temp_local_new();
1662 a0
= tcg_temp_local_new();
1670 if (op1
== OR_TMP0
) {
1671 tcg_gen_mov_tl(a0
, cpu_A0
);
1672 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1674 gen_op_mov_v_reg(ot
, t0
, op1
);
1678 tcg_gen_mov_tl(t1
, t0
);
1681 data_bits
= 8 << ot
;
1683 int shift
= op2
& ((1 << (3 + ot
)) - 1);
1685 tcg_gen_shri_tl(cpu_tmp4
, t0
, shift
);
1686 tcg_gen_shli_tl(t0
, t0
, data_bits
- shift
);
1689 tcg_gen_shli_tl(cpu_tmp4
, t0
, shift
);
1690 tcg_gen_shri_tl(t0
, t0
, data_bits
- shift
);
1692 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1696 if (op1
== OR_TMP0
) {
1697 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1699 gen_op_mov_reg_v(ot
, op1
, t0
);
1704 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1705 gen_op_set_cc_op(s
->cc_op
);
1707 gen_compute_eflags(cpu_cc_src
);
1708 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1709 tcg_gen_xor_tl(cpu_tmp0
, t1
, t0
);
1710 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1711 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1712 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1714 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1716 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1717 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1719 tcg_gen_discard_tl(cpu_cc_dst
);
1720 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_EFLAGS
);
1721 s
->cc_op
= CC_OP_EFLAGS
;
1729 /* XXX: add faster immediate = 1 case */
1730 static void gen_rotc_rm_T1(DisasContext
*s
, int ot
, int op1
,
1735 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1736 gen_op_set_cc_op(s
->cc_op
);
1740 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1742 gen_op_mov_TN_reg(ot
, 0, op1
);
1746 case 0: gen_helper_rcrb(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1747 case 1: gen_helper_rcrw(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1748 case 2: gen_helper_rcrl(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1749 #ifdef TARGET_X86_64
1750 case 3: gen_helper_rcrq(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1755 case 0: gen_helper_rclb(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1756 case 1: gen_helper_rclw(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1757 case 2: gen_helper_rcll(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1758 #ifdef TARGET_X86_64
1759 case 3: gen_helper_rclq(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1765 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1767 gen_op_mov_reg_T0(ot
, op1
);
1770 label1
= gen_new_label();
1771 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_cc_tmp
, -1, label1
);
1773 tcg_gen_mov_tl(cpu_cc_src
, cpu_cc_tmp
);
1774 tcg_gen_discard_tl(cpu_cc_dst
);
1775 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_EFLAGS
);
1777 gen_set_label(label1
);
1778 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1781 /* XXX: add faster immediate case */
1782 static void gen_shiftd_rm_T1_T3(DisasContext
*s
, int ot
, int op1
,
1785 int label1
, label2
, data_bits
;
1787 TCGv t0
, t1
, t2
, a0
;
1789 t0
= tcg_temp_local_new();
1790 t1
= tcg_temp_local_new();
1791 t2
= tcg_temp_local_new();
1792 a0
= tcg_temp_local_new();
1800 if (op1
== OR_TMP0
) {
1801 tcg_gen_mov_tl(a0
, cpu_A0
);
1802 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1804 gen_op_mov_v_reg(ot
, t0
, op1
);
1807 tcg_gen_andi_tl(cpu_T3
, cpu_T3
, mask
);
1809 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1810 tcg_gen_mov_tl(t2
, cpu_T3
);
1812 /* Must test zero case to avoid using undefined behaviour in TCG
1814 label1
= gen_new_label();
1815 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
1817 tcg_gen_addi_tl(cpu_tmp5
, t2
, -1);
1818 if (ot
== OT_WORD
) {
1819 /* Note: we implement the Intel behaviour for shift count > 16 */
1821 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1822 tcg_gen_shli_tl(cpu_tmp0
, t1
, 16);
1823 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1824 tcg_gen_ext32u_tl(t0
, t0
);
1826 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1828 /* only needed if count > 16, but a test would complicate */
1829 tcg_gen_subfi_tl(cpu_tmp5
, 32, t2
);
1830 tcg_gen_shl_tl(cpu_tmp0
, t0
, cpu_tmp5
);
1832 tcg_gen_shr_tl(t0
, t0
, t2
);
1834 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1836 /* XXX: not optimal */
1837 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1838 tcg_gen_shli_tl(t1
, t1
, 16);
1839 tcg_gen_or_tl(t1
, t1
, t0
);
1840 tcg_gen_ext32u_tl(t1
, t1
);
1842 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1843 tcg_gen_subfi_tl(cpu_tmp0
, 32, cpu_tmp5
);
1844 tcg_gen_shr_tl(cpu_tmp5
, t1
, cpu_tmp0
);
1845 tcg_gen_or_tl(cpu_tmp4
, cpu_tmp4
, cpu_tmp5
);
1847 tcg_gen_shl_tl(t0
, t0
, t2
);
1848 tcg_gen_subfi_tl(cpu_tmp5
, 32, t2
);
1849 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
1850 tcg_gen_or_tl(t0
, t0
, t1
);
1853 data_bits
= 8 << ot
;
1856 tcg_gen_ext32u_tl(t0
, t0
);
1858 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1860 tcg_gen_shr_tl(t0
, t0
, t2
);
1861 tcg_gen_subfi_tl(cpu_tmp5
, data_bits
, t2
);
1862 tcg_gen_shl_tl(t1
, t1
, cpu_tmp5
);
1863 tcg_gen_or_tl(t0
, t0
, t1
);
1867 tcg_gen_ext32u_tl(t1
, t1
);
1869 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1871 tcg_gen_shl_tl(t0
, t0
, t2
);
1872 tcg_gen_subfi_tl(cpu_tmp5
, data_bits
, t2
);
1873 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
1874 tcg_gen_or_tl(t0
, t0
, t1
);
1877 tcg_gen_mov_tl(t1
, cpu_tmp4
);
1879 gen_set_label(label1
);
1881 if (op1
== OR_TMP0
) {
1882 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1884 gen_op_mov_reg_v(ot
, op1
, t0
);
1888 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1889 gen_op_set_cc_op(s
->cc_op
);
1891 label2
= gen_new_label();
1892 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label2
);
1894 tcg_gen_mov_tl(cpu_cc_src
, t1
);
1895 tcg_gen_mov_tl(cpu_cc_dst
, t0
);
1897 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1899 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
1901 gen_set_label(label2
);
1902 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1910 static void gen_shift(DisasContext
*s1
, int op
, int ot
, int d
, int s
)
1913 gen_op_mov_TN_reg(ot
, 1, s
);
1916 gen_rot_rm_T1(s1
, ot
, d
, 0);
1919 gen_rot_rm_T1(s1
, ot
, d
, 1);
1923 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
1926 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
1929 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
1932 gen_rotc_rm_T1(s1
, ot
, d
, 0);
1935 gen_rotc_rm_T1(s1
, ot
, d
, 1);
1940 static void gen_shifti(DisasContext
*s1
, int op
, int ot
, int d
, int c
)
1944 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
1947 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
1951 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
1954 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
1957 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
1960 /* currently not optimized */
1961 gen_op_movl_T1_im(c
);
1962 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
1967 static void gen_lea_modrm(DisasContext
*s
, int modrm
, int *reg_ptr
, int *offset_ptr
)
1975 int mod
, rm
, code
, override
, must_add_seg
;
1977 override
= s
->override
;
1978 must_add_seg
= s
->addseg
;
1981 mod
= (modrm
>> 6) & 3;
1993 code
= ldub_code(s
->pc
++);
1994 scale
= (code
>> 6) & 3;
1995 index
= ((code
>> 3) & 7) | REX_X(s
);
2002 if ((base
& 7) == 5) {
2004 disp
= (int32_t)ldl_code(s
->pc
);
2006 if (CODE64(s
) && !havesib
) {
2007 disp
+= s
->pc
+ s
->rip_offset
;
2014 disp
= (int8_t)ldub_code(s
->pc
++);
2018 disp
= ldl_code(s
->pc
);
2024 /* for correct popl handling with esp */
2025 if (base
== 4 && s
->popl_esp_hack
)
2026 disp
+= s
->popl_esp_hack
;
2027 #ifdef TARGET_X86_64
2028 if (s
->aflag
== 2) {
2029 gen_op_movq_A0_reg(base
);
2031 gen_op_addq_A0_im(disp
);
2036 gen_op_movl_A0_reg(base
);
2038 gen_op_addl_A0_im(disp
);
2041 #ifdef TARGET_X86_64
2042 if (s
->aflag
== 2) {
2043 gen_op_movq_A0_im(disp
);
2047 gen_op_movl_A0_im(disp
);
2050 /* index == 4 means no index */
2051 if (havesib
&& (index
!= 4)) {
2052 #ifdef TARGET_X86_64
2053 if (s
->aflag
== 2) {
2054 gen_op_addq_A0_reg_sN(scale
, index
);
2058 gen_op_addl_A0_reg_sN(scale
, index
);
2063 if (base
== R_EBP
|| base
== R_ESP
)
2068 #ifdef TARGET_X86_64
2069 if (s
->aflag
== 2) {
2070 gen_op_addq_A0_seg(override
);
2074 gen_op_addl_A0_seg(override
);
2081 disp
= lduw_code(s
->pc
);
2083 gen_op_movl_A0_im(disp
);
2084 rm
= 0; /* avoid SS override */
2091 disp
= (int8_t)ldub_code(s
->pc
++);
2095 disp
= lduw_code(s
->pc
);
2101 gen_op_movl_A0_reg(R_EBX
);
2102 gen_op_addl_A0_reg_sN(0, R_ESI
);
2105 gen_op_movl_A0_reg(R_EBX
);
2106 gen_op_addl_A0_reg_sN(0, R_EDI
);
2109 gen_op_movl_A0_reg(R_EBP
);
2110 gen_op_addl_A0_reg_sN(0, R_ESI
);
2113 gen_op_movl_A0_reg(R_EBP
);
2114 gen_op_addl_A0_reg_sN(0, R_EDI
);
2117 gen_op_movl_A0_reg(R_ESI
);
2120 gen_op_movl_A0_reg(R_EDI
);
2123 gen_op_movl_A0_reg(R_EBP
);
2127 gen_op_movl_A0_reg(R_EBX
);
2131 gen_op_addl_A0_im(disp
);
2132 gen_op_andl_A0_ffff();
2136 if (rm
== 2 || rm
== 3 || rm
== 6)
2141 gen_op_addl_A0_seg(override
);
2151 static void gen_nop_modrm(DisasContext
*s
, int modrm
)
2153 int mod
, rm
, base
, code
;
2155 mod
= (modrm
>> 6) & 3;
2165 code
= ldub_code(s
->pc
++);
2201 /* used for LEA and MOV AX, mem */
2202 static void gen_add_A0_ds_seg(DisasContext
*s
)
2204 int override
, must_add_seg
;
2205 must_add_seg
= s
->addseg
;
2207 if (s
->override
>= 0) {
2208 override
= s
->override
;
2212 #ifdef TARGET_X86_64
2214 gen_op_addq_A0_seg(override
);
2218 gen_op_addl_A0_seg(override
);
2223 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2225 static void gen_ldst_modrm(DisasContext
*s
, int modrm
, int ot
, int reg
, int is_store
)
2227 int mod
, rm
, opreg
, disp
;
2229 mod
= (modrm
>> 6) & 3;
2230 rm
= (modrm
& 7) | REX_B(s
);
2234 gen_op_mov_TN_reg(ot
, 0, reg
);
2235 gen_op_mov_reg_T0(ot
, rm
);
2237 gen_op_mov_TN_reg(ot
, 0, rm
);
2239 gen_op_mov_reg_T0(ot
, reg
);
2242 gen_lea_modrm(s
, modrm
, &opreg
, &disp
);
2245 gen_op_mov_TN_reg(ot
, 0, reg
);
2246 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2248 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
2250 gen_op_mov_reg_T0(ot
, reg
);
2255 static inline uint32_t insn_get(DisasContext
*s
, int ot
)
2261 ret
= ldub_code(s
->pc
);
2265 ret
= lduw_code(s
->pc
);
2270 ret
= ldl_code(s
->pc
);
2277 static inline int insn_const_size(unsigned int ot
)
2285 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2287 TranslationBlock
*tb
;
2290 pc
= s
->cs_base
+ eip
;
2292 /* NOTE: we handle the case where the TB spans two pages here */
2293 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2294 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2295 /* jump to same page: we can use a direct jump */
2296 tcg_gen_goto_tb(tb_num
);
2298 tcg_gen_exit_tb((long)tb
+ tb_num
);
2300 /* jump to another page: currently not optimized */
2306 static inline void gen_jcc(DisasContext
*s
, int b
,
2307 target_ulong val
, target_ulong next_eip
)
2312 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
2313 gen_op_set_cc_op(s
->cc_op
);
2314 s
->cc_op
= CC_OP_DYNAMIC
;
2317 l1
= gen_new_label();
2318 gen_jcc1(s
, cc_op
, b
, l1
);
2320 gen_goto_tb(s
, 0, next_eip
);
2323 gen_goto_tb(s
, 1, val
);
2327 l1
= gen_new_label();
2328 l2
= gen_new_label();
2329 gen_jcc1(s
, cc_op
, b
, l1
);
2331 gen_jmp_im(next_eip
);
2341 static void gen_setcc(DisasContext
*s
, int b
)
2343 int inv
, jcc_op
, l1
;
2346 if (is_fast_jcc_case(s
, b
)) {
2347 /* nominal case: we use a jump */
2348 /* XXX: make it faster by adding new instructions in TCG */
2349 t0
= tcg_temp_local_new();
2350 tcg_gen_movi_tl(t0
, 0);
2351 l1
= gen_new_label();
2352 gen_jcc1(s
, s
->cc_op
, b
^ 1, l1
);
2353 tcg_gen_movi_tl(t0
, 1);
2355 tcg_gen_mov_tl(cpu_T
[0], t0
);
2358 /* slow case: it is more efficient not to generate a jump,
2359 although it is questionnable whether this optimization is
2362 jcc_op
= (b
>> 1) & 7;
2363 gen_setcc_slow_T0(s
, jcc_op
);
2365 tcg_gen_xori_tl(cpu_T
[0], cpu_T
[0], 1);
2370 static inline void gen_op_movl_T0_seg(int seg_reg
)
2372 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2373 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2376 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2378 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2379 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2380 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2381 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2382 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2383 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2386 /* move T0 to seg_reg and compute if the CPU state may change. Never
2387 call this function with seg_reg == R_CS */
2388 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2390 if (s
->pe
&& !s
->vm86
) {
2391 /* XXX: optimize by finding processor state dynamically */
2392 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2393 gen_op_set_cc_op(s
->cc_op
);
2394 gen_jmp_im(cur_eip
);
2395 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2396 gen_helper_load_seg(tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2397 /* abort translation because the addseg value may change or
2398 because ss32 may change. For R_SS, translation must always
2399 stop as a special handling must be done to disable hardware
2400 interrupts for the next instruction */
2401 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2404 gen_op_movl_seg_T0_vm(seg_reg
);
2405 if (seg_reg
== R_SS
)
2410 static inline int svm_is_rep(int prefixes
)
2412 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2416 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2417 uint32_t type
, uint64_t param
)
2419 /* no SVM activated; fast case */
2420 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2422 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2423 gen_op_set_cc_op(s
->cc_op
);
2424 gen_jmp_im(pc_start
- s
->cs_base
);
2425 gen_helper_svm_check_intercept_param(tcg_const_i32(type
),
2426 tcg_const_i64(param
));
2430 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2432 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2435 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2437 #ifdef TARGET_X86_64
2439 gen_op_add_reg_im(2, R_ESP
, addend
);
2443 gen_op_add_reg_im(1, R_ESP
, addend
);
2445 gen_op_add_reg_im(0, R_ESP
, addend
);
2449 /* generate a push. It depends on ss32, addseg and dflag */
2450 static void gen_push_T0(DisasContext
*s
)
2452 #ifdef TARGET_X86_64
2454 gen_op_movq_A0_reg(R_ESP
);
2456 gen_op_addq_A0_im(-8);
2457 gen_op_st_T0_A0(OT_QUAD
+ s
->mem_index
);
2459 gen_op_addq_A0_im(-2);
2460 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2462 gen_op_mov_reg_A0(2, R_ESP
);
2466 gen_op_movl_A0_reg(R_ESP
);
2468 gen_op_addl_A0_im(-2);
2470 gen_op_addl_A0_im(-4);
2473 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2474 gen_op_addl_A0_seg(R_SS
);
2477 gen_op_andl_A0_ffff();
2478 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2479 gen_op_addl_A0_seg(R_SS
);
2481 gen_op_st_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2482 if (s
->ss32
&& !s
->addseg
)
2483 gen_op_mov_reg_A0(1, R_ESP
);
2485 gen_op_mov_reg_T1(s
->ss32
+ 1, R_ESP
);
2489 /* generate a push. It depends on ss32, addseg and dflag */
2490 /* slower version for T1, only used for call Ev */
2491 static void gen_push_T1(DisasContext
*s
)
2493 #ifdef TARGET_X86_64
2495 gen_op_movq_A0_reg(R_ESP
);
2497 gen_op_addq_A0_im(-8);
2498 gen_op_st_T1_A0(OT_QUAD
+ s
->mem_index
);
2500 gen_op_addq_A0_im(-2);
2501 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2503 gen_op_mov_reg_A0(2, R_ESP
);
2507 gen_op_movl_A0_reg(R_ESP
);
2509 gen_op_addl_A0_im(-2);
2511 gen_op_addl_A0_im(-4);
2514 gen_op_addl_A0_seg(R_SS
);
2517 gen_op_andl_A0_ffff();
2518 gen_op_addl_A0_seg(R_SS
);
2520 gen_op_st_T1_A0(s
->dflag
+ 1 + s
->mem_index
);
2522 if (s
->ss32
&& !s
->addseg
)
2523 gen_op_mov_reg_A0(1, R_ESP
);
2525 gen_stack_update(s
, (-2) << s
->dflag
);
2529 /* two step pop is necessary for precise exceptions */
2530 static void gen_pop_T0(DisasContext
*s
)
2532 #ifdef TARGET_X86_64
2534 gen_op_movq_A0_reg(R_ESP
);
2535 gen_op_ld_T0_A0((s
->dflag
? OT_QUAD
: OT_WORD
) + s
->mem_index
);
2539 gen_op_movl_A0_reg(R_ESP
);
2542 gen_op_addl_A0_seg(R_SS
);
2544 gen_op_andl_A0_ffff();
2545 gen_op_addl_A0_seg(R_SS
);
2547 gen_op_ld_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2551 static void gen_pop_update(DisasContext
*s
)
2553 #ifdef TARGET_X86_64
2554 if (CODE64(s
) && s
->dflag
) {
2555 gen_stack_update(s
, 8);
2559 gen_stack_update(s
, 2 << s
->dflag
);
2563 static void gen_stack_A0(DisasContext
*s
)
2565 gen_op_movl_A0_reg(R_ESP
);
2567 gen_op_andl_A0_ffff();
2568 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2570 gen_op_addl_A0_seg(R_SS
);
2573 /* NOTE: wrap around in 16 bit not fully handled */
2574 static void gen_pusha(DisasContext
*s
)
2577 gen_op_movl_A0_reg(R_ESP
);
2578 gen_op_addl_A0_im(-16 << s
->dflag
);
2580 gen_op_andl_A0_ffff();
2581 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2583 gen_op_addl_A0_seg(R_SS
);
2584 for(i
= 0;i
< 8; i
++) {
2585 gen_op_mov_TN_reg(OT_LONG
, 0, 7 - i
);
2586 gen_op_st_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2587 gen_op_addl_A0_im(2 << s
->dflag
);
2589 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2592 /* NOTE: wrap around in 16 bit not fully handled */
2593 static void gen_popa(DisasContext
*s
)
2596 gen_op_movl_A0_reg(R_ESP
);
2598 gen_op_andl_A0_ffff();
2599 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2600 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 16 << s
->dflag
);
2602 gen_op_addl_A0_seg(R_SS
);
2603 for(i
= 0;i
< 8; i
++) {
2604 /* ESP is not reloaded */
2606 gen_op_ld_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2607 gen_op_mov_reg_T0(OT_WORD
+ s
->dflag
, 7 - i
);
2609 gen_op_addl_A0_im(2 << s
->dflag
);
2611 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2614 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2619 #ifdef TARGET_X86_64
2621 ot
= s
->dflag
? OT_QUAD
: OT_WORD
;
2624 gen_op_movl_A0_reg(R_ESP
);
2625 gen_op_addq_A0_im(-opsize
);
2626 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2629 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2630 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2632 /* XXX: must save state */
2633 gen_helper_enter64_level(tcg_const_i32(level
),
2634 tcg_const_i32((ot
== OT_QUAD
)),
2637 gen_op_mov_reg_T1(ot
, R_EBP
);
2638 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2639 gen_op_mov_reg_T1(OT_QUAD
, R_ESP
);
2643 ot
= s
->dflag
+ OT_WORD
;
2644 opsize
= 2 << s
->dflag
;
2646 gen_op_movl_A0_reg(R_ESP
);
2647 gen_op_addl_A0_im(-opsize
);
2649 gen_op_andl_A0_ffff();
2650 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2652 gen_op_addl_A0_seg(R_SS
);
2654 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2655 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2657 /* XXX: must save state */
2658 gen_helper_enter_level(tcg_const_i32(level
),
2659 tcg_const_i32(s
->dflag
),
2662 gen_op_mov_reg_T1(ot
, R_EBP
);
2663 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2664 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2668 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2670 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2671 gen_op_set_cc_op(s
->cc_op
);
2672 gen_jmp_im(cur_eip
);
2673 gen_helper_raise_exception(tcg_const_i32(trapno
));
2677 /* an interrupt is different from an exception because of the
2679 static void gen_interrupt(DisasContext
*s
, int intno
,
2680 target_ulong cur_eip
, target_ulong next_eip
)
2682 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2683 gen_op_set_cc_op(s
->cc_op
);
2684 gen_jmp_im(cur_eip
);
2685 gen_helper_raise_interrupt(tcg_const_i32(intno
),
2686 tcg_const_i32(next_eip
- cur_eip
));
2690 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2692 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2693 gen_op_set_cc_op(s
->cc_op
);
2694 gen_jmp_im(cur_eip
);
2699 /* generate a generic end of block. Trace exception is also generated
2701 static void gen_eob(DisasContext
*s
)
2703 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2704 gen_op_set_cc_op(s
->cc_op
);
2705 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2706 gen_helper_reset_inhibit_irq();
2708 if (s
->tb
->flags
& HF_RF_MASK
) {
2709 gen_helper_reset_rf();
2711 if (s
->singlestep_enabled
) {
2714 gen_helper_single_step();
2721 /* generate a jump to eip. No segment change must happen before as a
2722 direct call to the next block may occur */
2723 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2726 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
2727 gen_op_set_cc_op(s
->cc_op
);
2728 s
->cc_op
= CC_OP_DYNAMIC
;
2730 gen_goto_tb(s
, tb_num
, eip
);
2738 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2740 gen_jmp_tb(s
, eip
, 0);
2743 static inline void gen_ldq_env_A0(int idx
, int offset
)
2745 int mem_index
= (idx
>> 2) - 1;
2746 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2747 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2750 static inline void gen_stq_env_A0(int idx
, int offset
)
2752 int mem_index
= (idx
>> 2) - 1;
2753 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2754 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2757 static inline void gen_ldo_env_A0(int idx
, int offset
)
2759 int mem_index
= (idx
>> 2) - 1;
2760 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2761 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2762 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2763 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2764 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2767 static inline void gen_sto_env_A0(int idx
, int offset
)
2769 int mem_index
= (idx
>> 2) - 1;
2770 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2771 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2772 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2773 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2774 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2777 static inline void gen_op_movo(int d_offset
, int s_offset
)
2779 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2780 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2781 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2782 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2785 static inline void gen_op_movq(int d_offset
, int s_offset
)
2787 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2788 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2791 static inline void gen_op_movl(int d_offset
, int s_offset
)
2793 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2794 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2797 static inline void gen_op_movq_env_0(int d_offset
)
2799 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2800 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2803 #define SSE_SPECIAL ((void *)1)
2804 #define SSE_DUMMY ((void *)2)
2806 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2807 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2808 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2810 static void *sse_op_table1
[256][4] = {
2811 /* 3DNow! extensions */
2812 [0x0e] = { SSE_DUMMY
}, /* femms */
2813 [0x0f] = { SSE_DUMMY
}, /* pf... */
2814 /* pure SSE operations */
2815 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2816 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2817 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2818 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2819 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2820 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2821 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2822 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2824 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2825 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2826 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2827 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd, movntss, movntsd */
2828 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2829 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2830 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2831 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2832 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2833 [0x51] = SSE_FOP(sqrt
),
2834 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2835 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
2836 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
2837 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
2838 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
2839 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
2840 [0x58] = SSE_FOP(add
),
2841 [0x59] = SSE_FOP(mul
),
2842 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
2843 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
2844 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
2845 [0x5c] = SSE_FOP(sub
),
2846 [0x5d] = SSE_FOP(min
),
2847 [0x5e] = SSE_FOP(div
),
2848 [0x5f] = SSE_FOP(max
),
2850 [0xc2] = SSE_FOP(cmpeq
),
2851 [0xc6] = { gen_helper_shufps
, gen_helper_shufpd
},
2853 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
2854 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
2856 /* MMX ops and their SSE extensions */
2857 [0x60] = MMX_OP2(punpcklbw
),
2858 [0x61] = MMX_OP2(punpcklwd
),
2859 [0x62] = MMX_OP2(punpckldq
),
2860 [0x63] = MMX_OP2(packsswb
),
2861 [0x64] = MMX_OP2(pcmpgtb
),
2862 [0x65] = MMX_OP2(pcmpgtw
),
2863 [0x66] = MMX_OP2(pcmpgtl
),
2864 [0x67] = MMX_OP2(packuswb
),
2865 [0x68] = MMX_OP2(punpckhbw
),
2866 [0x69] = MMX_OP2(punpckhwd
),
2867 [0x6a] = MMX_OP2(punpckhdq
),
2868 [0x6b] = MMX_OP2(packssdw
),
2869 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
2870 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
2871 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
2872 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
2873 [0x70] = { gen_helper_pshufw_mmx
,
2874 gen_helper_pshufd_xmm
,
2875 gen_helper_pshufhw_xmm
,
2876 gen_helper_pshuflw_xmm
},
2877 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
2878 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
2879 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
2880 [0x74] = MMX_OP2(pcmpeqb
),
2881 [0x75] = MMX_OP2(pcmpeqw
),
2882 [0x76] = MMX_OP2(pcmpeql
),
2883 [0x77] = { SSE_DUMMY
}, /* emms */
2884 [0x78] = { NULL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* extrq_i, insertq_i */
2885 [0x79] = { NULL
, gen_helper_extrq_r
, NULL
, gen_helper_insertq_r
},
2886 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
2887 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
2888 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
2889 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
2890 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
2891 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
2892 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
2893 [0xd1] = MMX_OP2(psrlw
),
2894 [0xd2] = MMX_OP2(psrld
),
2895 [0xd3] = MMX_OP2(psrlq
),
2896 [0xd4] = MMX_OP2(paddq
),
2897 [0xd5] = MMX_OP2(pmullw
),
2898 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2899 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
2900 [0xd8] = MMX_OP2(psubusb
),
2901 [0xd9] = MMX_OP2(psubusw
),
2902 [0xda] = MMX_OP2(pminub
),
2903 [0xdb] = MMX_OP2(pand
),
2904 [0xdc] = MMX_OP2(paddusb
),
2905 [0xdd] = MMX_OP2(paddusw
),
2906 [0xde] = MMX_OP2(pmaxub
),
2907 [0xdf] = MMX_OP2(pandn
),
2908 [0xe0] = MMX_OP2(pavgb
),
2909 [0xe1] = MMX_OP2(psraw
),
2910 [0xe2] = MMX_OP2(psrad
),
2911 [0xe3] = MMX_OP2(pavgw
),
2912 [0xe4] = MMX_OP2(pmulhuw
),
2913 [0xe5] = MMX_OP2(pmulhw
),
2914 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
2915 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
2916 [0xe8] = MMX_OP2(psubsb
),
2917 [0xe9] = MMX_OP2(psubsw
),
2918 [0xea] = MMX_OP2(pminsw
),
2919 [0xeb] = MMX_OP2(por
),
2920 [0xec] = MMX_OP2(paddsb
),
2921 [0xed] = MMX_OP2(paddsw
),
2922 [0xee] = MMX_OP2(pmaxsw
),
2923 [0xef] = MMX_OP2(pxor
),
2924 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
2925 [0xf1] = MMX_OP2(psllw
),
2926 [0xf2] = MMX_OP2(pslld
),
2927 [0xf3] = MMX_OP2(psllq
),
2928 [0xf4] = MMX_OP2(pmuludq
),
2929 [0xf5] = MMX_OP2(pmaddwd
),
2930 [0xf6] = MMX_OP2(psadbw
),
2931 [0xf7] = MMX_OP2(maskmov
),
2932 [0xf8] = MMX_OP2(psubb
),
2933 [0xf9] = MMX_OP2(psubw
),
2934 [0xfa] = MMX_OP2(psubl
),
2935 [0xfb] = MMX_OP2(psubq
),
2936 [0xfc] = MMX_OP2(paddb
),
2937 [0xfd] = MMX_OP2(paddw
),
2938 [0xfe] = MMX_OP2(paddl
),
2941 static void *sse_op_table2
[3 * 8][2] = {
2942 [0 + 2] = MMX_OP2(psrlw
),
2943 [0 + 4] = MMX_OP2(psraw
),
2944 [0 + 6] = MMX_OP2(psllw
),
2945 [8 + 2] = MMX_OP2(psrld
),
2946 [8 + 4] = MMX_OP2(psrad
),
2947 [8 + 6] = MMX_OP2(pslld
),
2948 [16 + 2] = MMX_OP2(psrlq
),
2949 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
2950 [16 + 6] = MMX_OP2(psllq
),
2951 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
2954 static void *sse_op_table3
[4 * 3] = {
2955 gen_helper_cvtsi2ss
,
2956 gen_helper_cvtsi2sd
,
2957 X86_64_ONLY(gen_helper_cvtsq2ss
),
2958 X86_64_ONLY(gen_helper_cvtsq2sd
),
2960 gen_helper_cvttss2si
,
2961 gen_helper_cvttsd2si
,
2962 X86_64_ONLY(gen_helper_cvttss2sq
),
2963 X86_64_ONLY(gen_helper_cvttsd2sq
),
2965 gen_helper_cvtss2si
,
2966 gen_helper_cvtsd2si
,
2967 X86_64_ONLY(gen_helper_cvtss2sq
),
2968 X86_64_ONLY(gen_helper_cvtsd2sq
),
2971 static void *sse_op_table4
[8][4] = {
2982 static void *sse_op_table5
[256] = {
2983 [0x0c] = gen_helper_pi2fw
,
2984 [0x0d] = gen_helper_pi2fd
,
2985 [0x1c] = gen_helper_pf2iw
,
2986 [0x1d] = gen_helper_pf2id
,
2987 [0x8a] = gen_helper_pfnacc
,
2988 [0x8e] = gen_helper_pfpnacc
,
2989 [0x90] = gen_helper_pfcmpge
,
2990 [0x94] = gen_helper_pfmin
,
2991 [0x96] = gen_helper_pfrcp
,
2992 [0x97] = gen_helper_pfrsqrt
,
2993 [0x9a] = gen_helper_pfsub
,
2994 [0x9e] = gen_helper_pfadd
,
2995 [0xa0] = gen_helper_pfcmpgt
,
2996 [0xa4] = gen_helper_pfmax
,
2997 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
2998 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
2999 [0xaa] = gen_helper_pfsubr
,
3000 [0xae] = gen_helper_pfacc
,
3001 [0xb0] = gen_helper_pfcmpeq
,
3002 [0xb4] = gen_helper_pfmul
,
3003 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
3004 [0xb7] = gen_helper_pmulhrw_mmx
,
3005 [0xbb] = gen_helper_pswapd
,
3006 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
3009 struct sse_op_helper_s
{
3010 void *op
[2]; uint32_t ext_mask
;
3012 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3013 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3014 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3015 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3016 static struct sse_op_helper_s sse_op_table6
[256] = {
3017 [0x00] = SSSE3_OP(pshufb
),
3018 [0x01] = SSSE3_OP(phaddw
),
3019 [0x02] = SSSE3_OP(phaddd
),
3020 [0x03] = SSSE3_OP(phaddsw
),
3021 [0x04] = SSSE3_OP(pmaddubsw
),
3022 [0x05] = SSSE3_OP(phsubw
),
3023 [0x06] = SSSE3_OP(phsubd
),
3024 [0x07] = SSSE3_OP(phsubsw
),
3025 [0x08] = SSSE3_OP(psignb
),
3026 [0x09] = SSSE3_OP(psignw
),
3027 [0x0a] = SSSE3_OP(psignd
),
3028 [0x0b] = SSSE3_OP(pmulhrsw
),
3029 [0x10] = SSE41_OP(pblendvb
),
3030 [0x14] = SSE41_OP(blendvps
),
3031 [0x15] = SSE41_OP(blendvpd
),
3032 [0x17] = SSE41_OP(ptest
),
3033 [0x1c] = SSSE3_OP(pabsb
),
3034 [0x1d] = SSSE3_OP(pabsw
),
3035 [0x1e] = SSSE3_OP(pabsd
),
3036 [0x20] = SSE41_OP(pmovsxbw
),
3037 [0x21] = SSE41_OP(pmovsxbd
),
3038 [0x22] = SSE41_OP(pmovsxbq
),
3039 [0x23] = SSE41_OP(pmovsxwd
),
3040 [0x24] = SSE41_OP(pmovsxwq
),
3041 [0x25] = SSE41_OP(pmovsxdq
),
3042 [0x28] = SSE41_OP(pmuldq
),
3043 [0x29] = SSE41_OP(pcmpeqq
),
3044 [0x2a] = SSE41_SPECIAL
, /* movntqda */
3045 [0x2b] = SSE41_OP(packusdw
),
3046 [0x30] = SSE41_OP(pmovzxbw
),
3047 [0x31] = SSE41_OP(pmovzxbd
),
3048 [0x32] = SSE41_OP(pmovzxbq
),
3049 [0x33] = SSE41_OP(pmovzxwd
),
3050 [0x34] = SSE41_OP(pmovzxwq
),
3051 [0x35] = SSE41_OP(pmovzxdq
),
3052 [0x37] = SSE42_OP(pcmpgtq
),
3053 [0x38] = SSE41_OP(pminsb
),
3054 [0x39] = SSE41_OP(pminsd
),
3055 [0x3a] = SSE41_OP(pminuw
),
3056 [0x3b] = SSE41_OP(pminud
),
3057 [0x3c] = SSE41_OP(pmaxsb
),
3058 [0x3d] = SSE41_OP(pmaxsd
),
3059 [0x3e] = SSE41_OP(pmaxuw
),
3060 [0x3f] = SSE41_OP(pmaxud
),
3061 [0x40] = SSE41_OP(pmulld
),
3062 [0x41] = SSE41_OP(phminposuw
),
3065 static struct sse_op_helper_s sse_op_table7
[256] = {
3066 [0x08] = SSE41_OP(roundps
),
3067 [0x09] = SSE41_OP(roundpd
),
3068 [0x0a] = SSE41_OP(roundss
),
3069 [0x0b] = SSE41_OP(roundsd
),
3070 [0x0c] = SSE41_OP(blendps
),
3071 [0x0d] = SSE41_OP(blendpd
),
3072 [0x0e] = SSE41_OP(pblendw
),
3073 [0x0f] = SSSE3_OP(palignr
),
3074 [0x14] = SSE41_SPECIAL
, /* pextrb */
3075 [0x15] = SSE41_SPECIAL
, /* pextrw */
3076 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
3077 [0x17] = SSE41_SPECIAL
, /* extractps */
3078 [0x20] = SSE41_SPECIAL
, /* pinsrb */
3079 [0x21] = SSE41_SPECIAL
, /* insertps */
3080 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
3081 [0x40] = SSE41_OP(dpps
),
3082 [0x41] = SSE41_OP(dppd
),
3083 [0x42] = SSE41_OP(mpsadbw
),
3084 [0x60] = SSE42_OP(pcmpestrm
),
3085 [0x61] = SSE42_OP(pcmpestri
),
3086 [0x62] = SSE42_OP(pcmpistrm
),
3087 [0x63] = SSE42_OP(pcmpistri
),
3090 static void gen_sse(DisasContext
*s
, int b
, target_ulong pc_start
, int rex_r
)
3092 int b1
, op1_offset
, op2_offset
, is_xmm
, val
, ot
;
3093 int modrm
, mod
, rm
, reg
, reg_addr
, offset_addr
;
3097 if (s
->prefix
& PREFIX_DATA
)
3099 else if (s
->prefix
& PREFIX_REPZ
)
3101 else if (s
->prefix
& PREFIX_REPNZ
)
3105 sse_op2
= sse_op_table1
[b
][b1
];
3108 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3118 /* simple MMX/SSE operation */
3119 if (s
->flags
& HF_TS_MASK
) {
3120 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3123 if (s
->flags
& HF_EM_MASK
) {
3125 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3128 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3129 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3132 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3143 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3144 the static cpu state) */
3146 gen_helper_enter_mmx();
3149 modrm
= ldub_code(s
->pc
++);
3150 reg
= ((modrm
>> 3) & 7);
3153 mod
= (modrm
>> 6) & 3;
3154 if (sse_op2
== SSE_SPECIAL
) {
3157 case 0x0e7: /* movntq */
3160 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3161 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3163 case 0x1e7: /* movntdq */
3164 case 0x02b: /* movntps */
3165 case 0x12b: /* movntps */
3168 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3169 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3171 case 0x3f0: /* lddqu */
3174 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3175 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3177 case 0x22b: /* movntss */
3178 case 0x32b: /* movntsd */
3181 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3183 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,
3186 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3187 xmm_regs
[reg
].XMM_L(0)));
3188 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3191 case 0x6e: /* movd mm, ea */
3192 #ifdef TARGET_X86_64
3193 if (s
->dflag
== 2) {
3194 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3195 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3199 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3200 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3201 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3202 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3203 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3206 case 0x16e: /* movd xmm, ea */
3207 #ifdef TARGET_X86_64
3208 if (s
->dflag
== 2) {
3209 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3210 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3211 offsetof(CPUX86State
,xmm_regs
[reg
]));
3212 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3216 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3217 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3218 offsetof(CPUX86State
,xmm_regs
[reg
]));
3219 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3220 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3223 case 0x6f: /* movq mm, ea */
3225 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3226 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3229 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3230 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3231 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3232 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3235 case 0x010: /* movups */
3236 case 0x110: /* movupd */
3237 case 0x028: /* movaps */
3238 case 0x128: /* movapd */
3239 case 0x16f: /* movdqa xmm, ea */
3240 case 0x26f: /* movdqu xmm, ea */
3242 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3243 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3245 rm
= (modrm
& 7) | REX_B(s
);
3246 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3247 offsetof(CPUX86State
,xmm_regs
[rm
]));
3250 case 0x210: /* movss xmm, ea */
3252 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3253 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3254 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3256 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3257 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3258 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3260 rm
= (modrm
& 7) | REX_B(s
);
3261 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3262 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3265 case 0x310: /* movsd xmm, ea */
3267 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3268 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3270 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3271 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3273 rm
= (modrm
& 7) | REX_B(s
);
3274 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3275 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3278 case 0x012: /* movlps */
3279 case 0x112: /* movlpd */
3281 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3282 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3285 rm
= (modrm
& 7) | REX_B(s
);
3286 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3287 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3290 case 0x212: /* movsldup */
3292 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3293 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3295 rm
= (modrm
& 7) | REX_B(s
);
3296 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3297 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3298 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3299 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3301 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3302 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3303 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3304 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3306 case 0x312: /* movddup */
3308 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3309 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3311 rm
= (modrm
& 7) | REX_B(s
);
3312 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3313 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3315 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3316 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3318 case 0x016: /* movhps */
3319 case 0x116: /* movhpd */
3321 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3322 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3325 rm
= (modrm
& 7) | REX_B(s
);
3326 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3327 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3330 case 0x216: /* movshdup */
3332 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3333 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3335 rm
= (modrm
& 7) | REX_B(s
);
3336 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3337 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3338 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3339 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3341 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3342 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3343 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3344 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3349 int bit_index
, field_length
;
3351 if (b1
== 1 && reg
!= 0)
3353 field_length
= ldub_code(s
->pc
++) & 0x3F;
3354 bit_index
= ldub_code(s
->pc
++) & 0x3F;
3355 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3356 offsetof(CPUX86State
,xmm_regs
[reg
]));
3358 gen_helper_extrq_i(cpu_ptr0
, tcg_const_i32(bit_index
),
3359 tcg_const_i32(field_length
));
3361 gen_helper_insertq_i(cpu_ptr0
, tcg_const_i32(bit_index
),
3362 tcg_const_i32(field_length
));
3365 case 0x7e: /* movd ea, mm */
3366 #ifdef TARGET_X86_64
3367 if (s
->dflag
== 2) {
3368 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3369 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3370 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3374 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3375 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3376 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3379 case 0x17e: /* movd ea, xmm */
3380 #ifdef TARGET_X86_64
3381 if (s
->dflag
== 2) {
3382 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3383 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3384 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3388 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3389 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3390 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3393 case 0x27e: /* movq xmm, ea */
3395 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3396 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3398 rm
= (modrm
& 7) | REX_B(s
);
3399 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3400 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3402 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3404 case 0x7f: /* movq ea, mm */
3406 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3407 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3410 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3411 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3414 case 0x011: /* movups */
3415 case 0x111: /* movupd */
3416 case 0x029: /* movaps */
3417 case 0x129: /* movapd */
3418 case 0x17f: /* movdqa ea, xmm */
3419 case 0x27f: /* movdqu ea, xmm */
3421 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3422 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3424 rm
= (modrm
& 7) | REX_B(s
);
3425 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3426 offsetof(CPUX86State
,xmm_regs
[reg
]));
3429 case 0x211: /* movss ea, xmm */
3431 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3432 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3433 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3435 rm
= (modrm
& 7) | REX_B(s
);
3436 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3437 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3440 case 0x311: /* movsd ea, xmm */
3442 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3443 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3445 rm
= (modrm
& 7) | REX_B(s
);
3446 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3447 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3450 case 0x013: /* movlps */
3451 case 0x113: /* movlpd */
3453 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3454 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3459 case 0x017: /* movhps */
3460 case 0x117: /* movhpd */
3462 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3463 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3468 case 0x71: /* shift mm, im */
3471 case 0x171: /* shift xmm, im */
3474 val
= ldub_code(s
->pc
++);
3476 gen_op_movl_T0_im(val
);
3477 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3479 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3480 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3482 gen_op_movl_T0_im(val
);
3483 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3485 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3486 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3488 sse_op2
= sse_op_table2
[((b
- 1) & 3) * 8 + (((modrm
>> 3)) & 7)][b1
];
3492 rm
= (modrm
& 7) | REX_B(s
);
3493 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3496 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3498 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3499 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3500 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
3502 case 0x050: /* movmskps */
3503 rm
= (modrm
& 7) | REX_B(s
);
3504 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3505 offsetof(CPUX86State
,xmm_regs
[rm
]));
3506 gen_helper_movmskps(cpu_tmp2_i32
, cpu_ptr0
);
3507 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3508 gen_op_mov_reg_T0(OT_LONG
, reg
);
3510 case 0x150: /* movmskpd */
3511 rm
= (modrm
& 7) | REX_B(s
);
3512 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3513 offsetof(CPUX86State
,xmm_regs
[rm
]));
3514 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_ptr0
);
3515 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3516 gen_op_mov_reg_T0(OT_LONG
, reg
);
3518 case 0x02a: /* cvtpi2ps */
3519 case 0x12a: /* cvtpi2pd */
3520 gen_helper_enter_mmx();
3522 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3523 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3524 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3527 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3529 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3530 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3531 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3534 gen_helper_cvtpi2ps(cpu_ptr0
, cpu_ptr1
);
3538 gen_helper_cvtpi2pd(cpu_ptr0
, cpu_ptr1
);
3542 case 0x22a: /* cvtsi2ss */
3543 case 0x32a: /* cvtsi2sd */
3544 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3545 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
3546 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3547 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3548 sse_op2
= sse_op_table3
[(s
->dflag
== 2) * 2 + ((b
>> 8) - 2)];
3549 if (ot
== OT_LONG
) {
3550 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3551 ((void (*)(TCGv_ptr
, TCGv_i32
))sse_op2
)(cpu_ptr0
, cpu_tmp2_i32
);
3553 ((void (*)(TCGv_ptr
, TCGv
))sse_op2
)(cpu_ptr0
, cpu_T
[0]);
3556 case 0x02c: /* cvttps2pi */
3557 case 0x12c: /* cvttpd2pi */
3558 case 0x02d: /* cvtps2pi */
3559 case 0x12d: /* cvtpd2pi */
3560 gen_helper_enter_mmx();
3562 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3563 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3564 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3566 rm
= (modrm
& 7) | REX_B(s
);
3567 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3569 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3570 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3571 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3574 gen_helper_cvttps2pi(cpu_ptr0
, cpu_ptr1
);
3577 gen_helper_cvttpd2pi(cpu_ptr0
, cpu_ptr1
);
3580 gen_helper_cvtps2pi(cpu_ptr0
, cpu_ptr1
);
3583 gen_helper_cvtpd2pi(cpu_ptr0
, cpu_ptr1
);
3587 case 0x22c: /* cvttss2si */
3588 case 0x32c: /* cvttsd2si */
3589 case 0x22d: /* cvtss2si */
3590 case 0x32d: /* cvtsd2si */
3591 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3593 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3595 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_Q(0)));
3597 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3598 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3600 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3602 rm
= (modrm
& 7) | REX_B(s
);
3603 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3605 sse_op2
= sse_op_table3
[(s
->dflag
== 2) * 2 + ((b
>> 8) - 2) + 4 +
3607 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3608 if (ot
== OT_LONG
) {
3609 ((void (*)(TCGv_i32
, TCGv_ptr
))sse_op2
)(cpu_tmp2_i32
, cpu_ptr0
);
3610 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3612 ((void (*)(TCGv
, TCGv_ptr
))sse_op2
)(cpu_T
[0], cpu_ptr0
);
3614 gen_op_mov_reg_T0(ot
, reg
);
3616 case 0xc4: /* pinsrw */
3619 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
3620 val
= ldub_code(s
->pc
++);
3623 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3624 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3627 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3628 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3631 case 0xc5: /* pextrw */
3635 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3636 val
= ldub_code(s
->pc
++);
3639 rm
= (modrm
& 7) | REX_B(s
);
3640 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3641 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3645 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3646 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3648 reg
= ((modrm
>> 3) & 7) | rex_r
;
3649 gen_op_mov_reg_T0(ot
, reg
);
3651 case 0x1d6: /* movq ea, xmm */
3653 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3654 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3656 rm
= (modrm
& 7) | REX_B(s
);
3657 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3658 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3659 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3662 case 0x2d6: /* movq2dq */
3663 gen_helper_enter_mmx();
3665 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3666 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3667 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3669 case 0x3d6: /* movdq2q */
3670 gen_helper_enter_mmx();
3671 rm
= (modrm
& 7) | REX_B(s
);
3672 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3673 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3675 case 0xd7: /* pmovmskb */
3680 rm
= (modrm
& 7) | REX_B(s
);
3681 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3682 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_ptr0
);
3685 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3686 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_ptr0
);
3688 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3689 reg
= ((modrm
>> 3) & 7) | rex_r
;
3690 gen_op_mov_reg_T0(OT_LONG
, reg
);
3693 if (s
->prefix
& PREFIX_REPNZ
)
3697 modrm
= ldub_code(s
->pc
++);
3699 reg
= ((modrm
>> 3) & 7) | rex_r
;
3700 mod
= (modrm
>> 6) & 3;
3702 sse_op2
= sse_op_table6
[b
].op
[b1
];
3705 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3709 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3711 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3713 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3714 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3716 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3717 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3718 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3719 gen_ldq_env_A0(s
->mem_index
, op2_offset
+
3720 offsetof(XMMReg
, XMM_Q(0)));
3722 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3723 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3724 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
3725 (s
->mem_index
>> 2) - 1);
3726 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
3727 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3728 offsetof(XMMReg
, XMM_L(0)));
3730 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3731 tcg_gen_qemu_ld16u(cpu_tmp0
, cpu_A0
,
3732 (s
->mem_index
>> 2) - 1);
3733 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3734 offsetof(XMMReg
, XMM_W(0)));
3736 case 0x2a: /* movntqda */
3737 gen_ldo_env_A0(s
->mem_index
, op1_offset
);
3740 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3744 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3746 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3748 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3749 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3750 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3753 if (sse_op2
== SSE_SPECIAL
)
3756 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3757 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3758 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
3761 s
->cc_op
= CC_OP_EFLAGS
;
3763 case 0x338: /* crc32 */
3766 modrm
= ldub_code(s
->pc
++);
3767 reg
= ((modrm
>> 3) & 7) | rex_r
;
3769 if (b
!= 0xf0 && b
!= 0xf1)
3771 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
))
3776 else if (b
== 0xf1 && s
->dflag
!= 2)
3777 if (s
->prefix
& PREFIX_DATA
)
3784 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
3785 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3786 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
3787 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
3788 cpu_T
[0], tcg_const_i32(8 << ot
));
3790 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3791 gen_op_mov_reg_T0(ot
, reg
);
3796 modrm
= ldub_code(s
->pc
++);
3798 reg
= ((modrm
>> 3) & 7) | rex_r
;
3799 mod
= (modrm
>> 6) & 3;
3801 sse_op2
= sse_op_table7
[b
].op
[b1
];
3804 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
3807 if (sse_op2
== SSE_SPECIAL
) {
3808 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3809 rm
= (modrm
& 7) | REX_B(s
);
3811 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3812 reg
= ((modrm
>> 3) & 7) | rex_r
;
3813 val
= ldub_code(s
->pc
++);
3815 case 0x14: /* pextrb */
3816 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3817 xmm_regs
[reg
].XMM_B(val
& 15)));
3819 gen_op_mov_reg_T0(ot
, rm
);
3821 tcg_gen_qemu_st8(cpu_T
[0], cpu_A0
,
3822 (s
->mem_index
>> 2) - 1);
3824 case 0x15: /* pextrw */
3825 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3826 xmm_regs
[reg
].XMM_W(val
& 7)));
3828 gen_op_mov_reg_T0(ot
, rm
);
3830 tcg_gen_qemu_st16(cpu_T
[0], cpu_A0
,
3831 (s
->mem_index
>> 2) - 1);
3834 if (ot
== OT_LONG
) { /* pextrd */
3835 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
3836 offsetof(CPUX86State
,
3837 xmm_regs
[reg
].XMM_L(val
& 3)));
3838 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3840 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
3842 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
3843 (s
->mem_index
>> 2) - 1);
3844 } else { /* pextrq */
3845 #ifdef TARGET_X86_64
3846 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3847 offsetof(CPUX86State
,
3848 xmm_regs
[reg
].XMM_Q(val
& 1)));
3850 gen_op_mov_reg_v(ot
, rm
, cpu_tmp1_i64
);
3852 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
3853 (s
->mem_index
>> 2) - 1);
3859 case 0x17: /* extractps */
3860 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3861 xmm_regs
[reg
].XMM_L(val
& 3)));
3863 gen_op_mov_reg_T0(ot
, rm
);
3865 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
3866 (s
->mem_index
>> 2) - 1);
3868 case 0x20: /* pinsrb */
3870 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
3872 tcg_gen_qemu_ld8u(cpu_tmp0
, cpu_A0
,
3873 (s
->mem_index
>> 2) - 1);
3874 tcg_gen_st8_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
,
3875 xmm_regs
[reg
].XMM_B(val
& 15)));
3877 case 0x21: /* insertps */
3879 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
3880 offsetof(CPUX86State
,xmm_regs
[rm
]
3881 .XMM_L((val
>> 6) & 3)));
3883 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
3884 (s
->mem_index
>> 2) - 1);
3885 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
3887 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
3888 offsetof(CPUX86State
,xmm_regs
[reg
]
3889 .XMM_L((val
>> 4) & 3)));
3891 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3892 cpu_env
, offsetof(CPUX86State
,
3893 xmm_regs
[reg
].XMM_L(0)));
3895 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3896 cpu_env
, offsetof(CPUX86State
,
3897 xmm_regs
[reg
].XMM_L(1)));
3899 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3900 cpu_env
, offsetof(CPUX86State
,
3901 xmm_regs
[reg
].XMM_L(2)));
3903 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3904 cpu_env
, offsetof(CPUX86State
,
3905 xmm_regs
[reg
].XMM_L(3)));
3908 if (ot
== OT_LONG
) { /* pinsrd */
3910 gen_op_mov_v_reg(ot
, cpu_tmp0
, rm
);
3912 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
3913 (s
->mem_index
>> 2) - 1);
3914 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
3915 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
3916 offsetof(CPUX86State
,
3917 xmm_regs
[reg
].XMM_L(val
& 3)));
3918 } else { /* pinsrq */
3919 #ifdef TARGET_X86_64
3921 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
3923 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
3924 (s
->mem_index
>> 2) - 1);
3925 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3926 offsetof(CPUX86State
,
3927 xmm_regs
[reg
].XMM_Q(val
& 1)));
3938 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3940 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3942 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3943 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3944 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3947 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3949 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3951 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3952 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3953 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3956 val
= ldub_code(s
->pc
++);
3958 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
3959 s
->cc_op
= CC_OP_EFLAGS
;
3962 /* The helper must use entire 64-bit gp registers */
3966 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3967 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3968 ((void (*)(TCGv_ptr
, TCGv_ptr
, TCGv_i32
))sse_op2
)(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
3974 /* generic MMX or SSE operation */
3976 case 0x70: /* pshufx insn */
3977 case 0xc6: /* pshufx insn */
3978 case 0xc2: /* compare insns */
3985 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3987 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3988 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3989 if (b1
>= 2 && ((b
>= 0x50 && b
<= 0x5f && b
!= 0x5b) ||
3991 /* specific case for SSE single instructions */
3994 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3995 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3998 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_D(0)));
4001 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
4004 rm
= (modrm
& 7) | REX_B(s
);
4005 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
4008 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4010 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4011 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4012 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
4015 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4019 case 0x0f: /* 3DNow! data insns */
4020 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
4022 val
= ldub_code(s
->pc
++);
4023 sse_op2
= sse_op_table5
[val
];
4026 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4027 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4028 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
4030 case 0x70: /* pshufx insn */
4031 case 0xc6: /* pshufx insn */
4032 val
= ldub_code(s
->pc
++);
4033 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4034 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4035 ((void (*)(TCGv_ptr
, TCGv_ptr
, TCGv_i32
))sse_op2
)(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4039 val
= ldub_code(s
->pc
++);
4042 sse_op2
= sse_op_table4
[val
][b1
];
4043 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4044 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4045 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
4048 /* maskmov : we must prepare A0 */
4051 #ifdef TARGET_X86_64
4052 if (s
->aflag
== 2) {
4053 gen_op_movq_A0_reg(R_EDI
);
4057 gen_op_movl_A0_reg(R_EDI
);
4059 gen_op_andl_A0_ffff();
4061 gen_add_A0_ds_seg(s
);
4063 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4064 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4065 ((void (*)(TCGv_ptr
, TCGv_ptr
, TCGv
))sse_op2
)(cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4068 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4069 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4070 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
4073 if (b
== 0x2e || b
== 0x2f) {
4074 s
->cc_op
= CC_OP_EFLAGS
;
4079 /* convert one instruction. s->is_jmp is set if the translation must
4080 be stopped. Return the next pc value */
4081 static target_ulong
disas_insn(DisasContext
*s
, target_ulong pc_start
)
4083 int b
, prefixes
, aflag
, dflag
;
4085 int modrm
, reg
, rm
, mod
, reg_addr
, op
, opreg
, offset_addr
, val
;
4086 target_ulong next_eip
, tval
;
4089 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)))
4090 tcg_gen_debug_insn_start(pc_start
);
4098 #ifdef TARGET_X86_64
4103 s
->rip_offset
= 0; /* for relative ip address */
4105 b
= ldub_code(s
->pc
);
4107 /* check prefixes */
4108 #ifdef TARGET_X86_64
4112 prefixes
|= PREFIX_REPZ
;
4115 prefixes
|= PREFIX_REPNZ
;
4118 prefixes
|= PREFIX_LOCK
;
4139 prefixes
|= PREFIX_DATA
;
4142 prefixes
|= PREFIX_ADR
;
4146 rex_w
= (b
>> 3) & 1;
4147 rex_r
= (b
& 0x4) << 1;
4148 s
->rex_x
= (b
& 0x2) << 2;
4149 REX_B(s
) = (b
& 0x1) << 3;
4150 x86_64_hregs
= 1; /* select uniform byte register addressing */
4154 /* 0x66 is ignored if rex.w is set */
4157 if (prefixes
& PREFIX_DATA
)
4160 if (!(prefixes
& PREFIX_ADR
))
4167 prefixes
|= PREFIX_REPZ
;
4170 prefixes
|= PREFIX_REPNZ
;
4173 prefixes
|= PREFIX_LOCK
;
4194 prefixes
|= PREFIX_DATA
;
4197 prefixes
|= PREFIX_ADR
;
4200 if (prefixes
& PREFIX_DATA
)
4202 if (prefixes
& PREFIX_ADR
)
4206 s
->prefix
= prefixes
;
4210 /* lock generation */
4211 if (prefixes
& PREFIX_LOCK
)
4214 /* now check op code */
4218 /**************************/
4219 /* extended op code */
4220 b
= ldub_code(s
->pc
++) | 0x100;
4223 /**************************/
4241 ot
= dflag
+ OT_WORD
;
4244 case 0: /* OP Ev, Gv */
4245 modrm
= ldub_code(s
->pc
++);
4246 reg
= ((modrm
>> 3) & 7) | rex_r
;
4247 mod
= (modrm
>> 6) & 3;
4248 rm
= (modrm
& 7) | REX_B(s
);
4250 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4252 } else if (op
== OP_XORL
&& rm
== reg
) {
4254 /* xor reg, reg optimisation */
4256 s
->cc_op
= CC_OP_LOGICB
+ ot
;
4257 gen_op_mov_reg_T0(ot
, reg
);
4258 gen_op_update1_cc();
4263 gen_op_mov_TN_reg(ot
, 1, reg
);
4264 gen_op(s
, op
, ot
, opreg
);
4266 case 1: /* OP Gv, Ev */
4267 modrm
= ldub_code(s
->pc
++);
4268 mod
= (modrm
>> 6) & 3;
4269 reg
= ((modrm
>> 3) & 7) | rex_r
;
4270 rm
= (modrm
& 7) | REX_B(s
);
4272 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4273 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4274 } else if (op
== OP_XORL
&& rm
== reg
) {
4277 gen_op_mov_TN_reg(ot
, 1, rm
);
4279 gen_op(s
, op
, ot
, reg
);
4281 case 2: /* OP A, Iv */
4282 val
= insn_get(s
, ot
);
4283 gen_op_movl_T1_im(val
);
4284 gen_op(s
, op
, ot
, OR_EAX
);
4293 case 0x80: /* GRP1 */
4302 ot
= dflag
+ OT_WORD
;
4304 modrm
= ldub_code(s
->pc
++);
4305 mod
= (modrm
>> 6) & 3;
4306 rm
= (modrm
& 7) | REX_B(s
);
4307 op
= (modrm
>> 3) & 7;
4313 s
->rip_offset
= insn_const_size(ot
);
4314 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4325 val
= insn_get(s
, ot
);
4328 val
= (int8_t)insn_get(s
, OT_BYTE
);
4331 gen_op_movl_T1_im(val
);
4332 gen_op(s
, op
, ot
, opreg
);
4336 /**************************/
4337 /* inc, dec, and other misc arith */
4338 case 0x40 ... 0x47: /* inc Gv */
4339 ot
= dflag
? OT_LONG
: OT_WORD
;
4340 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4342 case 0x48 ... 0x4f: /* dec Gv */
4343 ot
= dflag
? OT_LONG
: OT_WORD
;
4344 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4346 case 0xf6: /* GRP3 */
4351 ot
= dflag
+ OT_WORD
;
4353 modrm
= ldub_code(s
->pc
++);
4354 mod
= (modrm
>> 6) & 3;
4355 rm
= (modrm
& 7) | REX_B(s
);
4356 op
= (modrm
>> 3) & 7;
4359 s
->rip_offset
= insn_const_size(ot
);
4360 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4361 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4363 gen_op_mov_TN_reg(ot
, 0, rm
);
4368 val
= insn_get(s
, ot
);
4369 gen_op_movl_T1_im(val
);
4370 gen_op_testl_T0_T1_cc();
4371 s
->cc_op
= CC_OP_LOGICB
+ ot
;
4374 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4376 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4378 gen_op_mov_reg_T0(ot
, rm
);
4382 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4384 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4386 gen_op_mov_reg_T0(ot
, rm
);
4388 gen_op_update_neg_cc();
4389 s
->cc_op
= CC_OP_SUBB
+ ot
;
4394 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4395 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4396 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4397 /* XXX: use 32 bit mul which could be faster */
4398 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4399 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4400 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4401 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4402 s
->cc_op
= CC_OP_MULB
;
4405 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4406 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4407 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4408 /* XXX: use 32 bit mul which could be faster */
4409 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4410 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4411 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4412 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4413 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4414 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4415 s
->cc_op
= CC_OP_MULW
;
4419 #ifdef TARGET_X86_64
4420 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4421 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
4422 tcg_gen_ext32u_tl(cpu_T
[1], cpu_T
[1]);
4423 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4424 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4425 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4426 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4427 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4428 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4432 t0
= tcg_temp_new_i64();
4433 t1
= tcg_temp_new_i64();
4434 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4435 tcg_gen_extu_i32_i64(t0
, cpu_T
[0]);
4436 tcg_gen_extu_i32_i64(t1
, cpu_T
[1]);
4437 tcg_gen_mul_i64(t0
, t0
, t1
);
4438 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4439 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4440 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4441 tcg_gen_shri_i64(t0
, t0
, 32);
4442 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4443 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4444 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4447 s
->cc_op
= CC_OP_MULL
;
4449 #ifdef TARGET_X86_64
4451 gen_helper_mulq_EAX_T0(cpu_T
[0]);
4452 s
->cc_op
= CC_OP_MULQ
;
4460 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4461 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4462 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4463 /* XXX: use 32 bit mul which could be faster */
4464 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4465 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4466 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4467 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4468 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4469 s
->cc_op
= CC_OP_MULB
;
4472 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4473 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4474 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4475 /* XXX: use 32 bit mul which could be faster */
4476 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4477 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4478 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4479 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4480 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4481 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4482 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4483 s
->cc_op
= CC_OP_MULW
;
4487 #ifdef TARGET_X86_64
4488 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4489 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4490 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4491 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4492 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4493 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4494 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4495 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4496 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4497 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4501 t0
= tcg_temp_new_i64();
4502 t1
= tcg_temp_new_i64();
4503 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4504 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4505 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4506 tcg_gen_mul_i64(t0
, t0
, t1
);
4507 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4508 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4509 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4510 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4511 tcg_gen_shri_i64(t0
, t0
, 32);
4512 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4513 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4514 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4517 s
->cc_op
= CC_OP_MULL
;
4519 #ifdef TARGET_X86_64
4521 gen_helper_imulq_EAX_T0(cpu_T
[0]);
4522 s
->cc_op
= CC_OP_MULQ
;
4530 gen_jmp_im(pc_start
- s
->cs_base
);
4531 gen_helper_divb_AL(cpu_T
[0]);
4534 gen_jmp_im(pc_start
- s
->cs_base
);
4535 gen_helper_divw_AX(cpu_T
[0]);
4539 gen_jmp_im(pc_start
- s
->cs_base
);
4540 gen_helper_divl_EAX(cpu_T
[0]);
4542 #ifdef TARGET_X86_64
4544 gen_jmp_im(pc_start
- s
->cs_base
);
4545 gen_helper_divq_EAX(cpu_T
[0]);
4553 gen_jmp_im(pc_start
- s
->cs_base
);
4554 gen_helper_idivb_AL(cpu_T
[0]);
4557 gen_jmp_im(pc_start
- s
->cs_base
);
4558 gen_helper_idivw_AX(cpu_T
[0]);
4562 gen_jmp_im(pc_start
- s
->cs_base
);
4563 gen_helper_idivl_EAX(cpu_T
[0]);
4565 #ifdef TARGET_X86_64
4567 gen_jmp_im(pc_start
- s
->cs_base
);
4568 gen_helper_idivq_EAX(cpu_T
[0]);
4578 case 0xfe: /* GRP4 */
4579 case 0xff: /* GRP5 */
4583 ot
= dflag
+ OT_WORD
;
4585 modrm
= ldub_code(s
->pc
++);
4586 mod
= (modrm
>> 6) & 3;
4587 rm
= (modrm
& 7) | REX_B(s
);
4588 op
= (modrm
>> 3) & 7;
4589 if (op
>= 2 && b
== 0xfe) {
4593 if (op
== 2 || op
== 4) {
4594 /* operand size for jumps is 64 bit */
4596 } else if (op
== 3 || op
== 5) {
4597 ot
= dflag
? OT_LONG
+ (rex_w
== 1) : OT_WORD
;
4598 } else if (op
== 6) {
4599 /* default push size is 64 bit */
4600 ot
= dflag
? OT_QUAD
: OT_WORD
;
4604 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4605 if (op
>= 2 && op
!= 3 && op
!= 5)
4606 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4608 gen_op_mov_TN_reg(ot
, 0, rm
);
4612 case 0: /* inc Ev */
4617 gen_inc(s
, ot
, opreg
, 1);
4619 case 1: /* dec Ev */
4624 gen_inc(s
, ot
, opreg
, -1);
4626 case 2: /* call Ev */
4627 /* XXX: optimize if memory (no 'and' is necessary) */
4629 gen_op_andl_T0_ffff();
4630 next_eip
= s
->pc
- s
->cs_base
;
4631 gen_movtl_T1_im(next_eip
);
4636 case 3: /* lcall Ev */
4637 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4638 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4639 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4641 if (s
->pe
&& !s
->vm86
) {
4642 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4643 gen_op_set_cc_op(s
->cc_op
);
4644 gen_jmp_im(pc_start
- s
->cs_base
);
4645 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4646 gen_helper_lcall_protected(cpu_tmp2_i32
, cpu_T
[1],
4647 tcg_const_i32(dflag
),
4648 tcg_const_i32(s
->pc
- pc_start
));
4650 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4651 gen_helper_lcall_real(cpu_tmp2_i32
, cpu_T
[1],
4652 tcg_const_i32(dflag
),
4653 tcg_const_i32(s
->pc
- s
->cs_base
));
4657 case 4: /* jmp Ev */
4659 gen_op_andl_T0_ffff();
4663 case 5: /* ljmp Ev */
4664 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4665 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4666 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4668 if (s
->pe
&& !s
->vm86
) {
4669 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4670 gen_op_set_cc_op(s
->cc_op
);
4671 gen_jmp_im(pc_start
- s
->cs_base
);
4672 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4673 gen_helper_ljmp_protected(cpu_tmp2_i32
, cpu_T
[1],
4674 tcg_const_i32(s
->pc
- pc_start
));
4676 gen_op_movl_seg_T0_vm(R_CS
);
4677 gen_op_movl_T0_T1();
4682 case 6: /* push Ev */
4690 case 0x84: /* test Ev, Gv */
4695 ot
= dflag
+ OT_WORD
;
4697 modrm
= ldub_code(s
->pc
++);
4698 reg
= ((modrm
>> 3) & 7) | rex_r
;
4700 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
4701 gen_op_mov_TN_reg(ot
, 1, reg
);
4702 gen_op_testl_T0_T1_cc();
4703 s
->cc_op
= CC_OP_LOGICB
+ ot
;
4706 case 0xa8: /* test eAX, Iv */
4711 ot
= dflag
+ OT_WORD
;
4712 val
= insn_get(s
, ot
);
4714 gen_op_mov_TN_reg(ot
, 0, OR_EAX
);
4715 gen_op_movl_T1_im(val
);
4716 gen_op_testl_T0_T1_cc();
4717 s
->cc_op
= CC_OP_LOGICB
+ ot
;
4720 case 0x98: /* CWDE/CBW */
4721 #ifdef TARGET_X86_64
4723 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4724 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4725 gen_op_mov_reg_T0(OT_QUAD
, R_EAX
);
4729 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4730 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4731 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4733 gen_op_mov_TN_reg(OT_BYTE
, 0, R_EAX
);
4734 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4735 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4738 case 0x99: /* CDQ/CWD */
4739 #ifdef TARGET_X86_64
4741 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
4742 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
4743 gen_op_mov_reg_T0(OT_QUAD
, R_EDX
);
4747 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4748 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4749 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
4750 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4752 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4753 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4754 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
4755 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4758 case 0x1af: /* imul Gv, Ev */
4759 case 0x69: /* imul Gv, Ev, I */
4761 ot
= dflag
+ OT_WORD
;
4762 modrm
= ldub_code(s
->pc
++);
4763 reg
= ((modrm
>> 3) & 7) | rex_r
;
4765 s
->rip_offset
= insn_const_size(ot
);
4768 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
4770 val
= insn_get(s
, ot
);
4771 gen_op_movl_T1_im(val
);
4772 } else if (b
== 0x6b) {
4773 val
= (int8_t)insn_get(s
, OT_BYTE
);
4774 gen_op_movl_T1_im(val
);
4776 gen_op_mov_TN_reg(ot
, 1, reg
);
4779 #ifdef TARGET_X86_64
4780 if (ot
== OT_QUAD
) {
4781 gen_helper_imulq_T0_T1(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4784 if (ot
== OT_LONG
) {
4785 #ifdef TARGET_X86_64
4786 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4787 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4788 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4789 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4790 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4791 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4795 t0
= tcg_temp_new_i64();
4796 t1
= tcg_temp_new_i64();
4797 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4798 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4799 tcg_gen_mul_i64(t0
, t0
, t1
);
4800 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4801 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4802 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4803 tcg_gen_shri_i64(t0
, t0
, 32);
4804 tcg_gen_trunc_i64_i32(cpu_T
[1], t0
);
4805 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[1], cpu_tmp0
);
4809 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4810 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4811 /* XXX: use 32 bit mul which could be faster */
4812 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4813 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4814 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4815 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4817 gen_op_mov_reg_T0(ot
, reg
);
4818 s
->cc_op
= CC_OP_MULB
+ ot
;
4821 case 0x1c1: /* xadd Ev, Gv */
4825 ot
= dflag
+ OT_WORD
;
4826 modrm
= ldub_code(s
->pc
++);
4827 reg
= ((modrm
>> 3) & 7) | rex_r
;
4828 mod
= (modrm
>> 6) & 3;
4830 rm
= (modrm
& 7) | REX_B(s
);
4831 gen_op_mov_TN_reg(ot
, 0, reg
);
4832 gen_op_mov_TN_reg(ot
, 1, rm
);
4833 gen_op_addl_T0_T1();
4834 gen_op_mov_reg_T1(ot
, reg
);
4835 gen_op_mov_reg_T0(ot
, rm
);
4837 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4838 gen_op_mov_TN_reg(ot
, 0, reg
);
4839 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4840 gen_op_addl_T0_T1();
4841 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4842 gen_op_mov_reg_T1(ot
, reg
);
4844 gen_op_update2_cc();
4845 s
->cc_op
= CC_OP_ADDB
+ ot
;
4848 case 0x1b1: /* cmpxchg Ev, Gv */
4851 TCGv t0
, t1
, t2
, a0
;
4856 ot
= dflag
+ OT_WORD
;
4857 modrm
= ldub_code(s
->pc
++);
4858 reg
= ((modrm
>> 3) & 7) | rex_r
;
4859 mod
= (modrm
>> 6) & 3;
4860 t0
= tcg_temp_local_new();
4861 t1
= tcg_temp_local_new();
4862 t2
= tcg_temp_local_new();
4863 a0
= tcg_temp_local_new();
4864 gen_op_mov_v_reg(ot
, t1
, reg
);
4866 rm
= (modrm
& 7) | REX_B(s
);
4867 gen_op_mov_v_reg(ot
, t0
, rm
);
4869 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4870 tcg_gen_mov_tl(a0
, cpu_A0
);
4871 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
4872 rm
= 0; /* avoid warning */
4874 label1
= gen_new_label();
4875 tcg_gen_sub_tl(t2
, cpu_regs
[R_EAX
], t0
);
4877 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
4879 label2
= gen_new_label();
4880 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
4882 gen_set_label(label1
);
4883 gen_op_mov_reg_v(ot
, rm
, t1
);
4884 gen_set_label(label2
);
4886 tcg_gen_mov_tl(t1
, t0
);
4887 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
4888 gen_set_label(label1
);
4890 gen_op_st_v(ot
+ s
->mem_index
, t1
, a0
);
4892 tcg_gen_mov_tl(cpu_cc_src
, t0
);
4893 tcg_gen_mov_tl(cpu_cc_dst
, t2
);
4894 s
->cc_op
= CC_OP_SUBB
+ ot
;
4901 case 0x1c7: /* cmpxchg8b */
4902 modrm
= ldub_code(s
->pc
++);
4903 mod
= (modrm
>> 6) & 3;
4904 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
4906 #ifdef TARGET_X86_64
4908 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
4910 gen_jmp_im(pc_start
- s
->cs_base
);
4911 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4912 gen_op_set_cc_op(s
->cc_op
);
4913 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4914 gen_helper_cmpxchg16b(cpu_A0
);
4918 if (!(s
->cpuid_features
& CPUID_CX8
))
4920 gen_jmp_im(pc_start
- s
->cs_base
);
4921 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4922 gen_op_set_cc_op(s
->cc_op
);
4923 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4924 gen_helper_cmpxchg8b(cpu_A0
);
4926 s
->cc_op
= CC_OP_EFLAGS
;
4929 /**************************/
4931 case 0x50 ... 0x57: /* push */
4932 gen_op_mov_TN_reg(OT_LONG
, 0, (b
& 7) | REX_B(s
));
4935 case 0x58 ... 0x5f: /* pop */
4937 ot
= dflag
? OT_QUAD
: OT_WORD
;
4939 ot
= dflag
+ OT_WORD
;
4942 /* NOTE: order is important for pop %sp */
4944 gen_op_mov_reg_T0(ot
, (b
& 7) | REX_B(s
));
4946 case 0x60: /* pusha */
4951 case 0x61: /* popa */
4956 case 0x68: /* push Iv */
4959 ot
= dflag
? OT_QUAD
: OT_WORD
;
4961 ot
= dflag
+ OT_WORD
;
4964 val
= insn_get(s
, ot
);
4966 val
= (int8_t)insn_get(s
, OT_BYTE
);
4967 gen_op_movl_T0_im(val
);
4970 case 0x8f: /* pop Ev */
4972 ot
= dflag
? OT_QUAD
: OT_WORD
;
4974 ot
= dflag
+ OT_WORD
;
4976 modrm
= ldub_code(s
->pc
++);
4977 mod
= (modrm
>> 6) & 3;
4980 /* NOTE: order is important for pop %sp */
4982 rm
= (modrm
& 7) | REX_B(s
);
4983 gen_op_mov_reg_T0(ot
, rm
);
4985 /* NOTE: order is important too for MMU exceptions */
4986 s
->popl_esp_hack
= 1 << ot
;
4987 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
4988 s
->popl_esp_hack
= 0;
4992 case 0xc8: /* enter */
4995 val
= lduw_code(s
->pc
);
4997 level
= ldub_code(s
->pc
++);
4998 gen_enter(s
, val
, level
);
5001 case 0xc9: /* leave */
5002 /* XXX: exception not precise (ESP is updated before potential exception) */
5004 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EBP
);
5005 gen_op_mov_reg_T0(OT_QUAD
, R_ESP
);
5006 } else if (s
->ss32
) {
5007 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
5008 gen_op_mov_reg_T0(OT_LONG
, R_ESP
);
5010 gen_op_mov_TN_reg(OT_WORD
, 0, R_EBP
);
5011 gen_op_mov_reg_T0(OT_WORD
, R_ESP
);
5015 ot
= dflag
? OT_QUAD
: OT_WORD
;
5017 ot
= dflag
+ OT_WORD
;
5019 gen_op_mov_reg_T0(ot
, R_EBP
);
5022 case 0x06: /* push es */
5023 case 0x0e: /* push cs */
5024 case 0x16: /* push ss */
5025 case 0x1e: /* push ds */
5028 gen_op_movl_T0_seg(b
>> 3);
5031 case 0x1a0: /* push fs */
5032 case 0x1a8: /* push gs */
5033 gen_op_movl_T0_seg((b
>> 3) & 7);
5036 case 0x07: /* pop es */
5037 case 0x17: /* pop ss */
5038 case 0x1f: /* pop ds */
5043 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5046 /* if reg == SS, inhibit interrupts/trace. */
5047 /* If several instructions disable interrupts, only the
5049 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5050 gen_helper_set_inhibit_irq();
5054 gen_jmp_im(s
->pc
- s
->cs_base
);
5058 case 0x1a1: /* pop fs */
5059 case 0x1a9: /* pop gs */
5061 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5064 gen_jmp_im(s
->pc
- s
->cs_base
);
5069 /**************************/
5072 case 0x89: /* mov Gv, Ev */
5076 ot
= dflag
+ OT_WORD
;
5077 modrm
= ldub_code(s
->pc
++);
5078 reg
= ((modrm
>> 3) & 7) | rex_r
;
5080 /* generate a generic store */
5081 gen_ldst_modrm(s
, modrm
, ot
, reg
, 1);
5084 case 0xc7: /* mov Ev, Iv */
5088 ot
= dflag
+ OT_WORD
;
5089 modrm
= ldub_code(s
->pc
++);
5090 mod
= (modrm
>> 6) & 3;
5092 s
->rip_offset
= insn_const_size(ot
);
5093 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5095 val
= insn_get(s
, ot
);
5096 gen_op_movl_T0_im(val
);
5098 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5100 gen_op_mov_reg_T0(ot
, (modrm
& 7) | REX_B(s
));
5103 case 0x8b: /* mov Ev, Gv */
5107 ot
= OT_WORD
+ dflag
;
5108 modrm
= ldub_code(s
->pc
++);
5109 reg
= ((modrm
>> 3) & 7) | rex_r
;
5111 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
5112 gen_op_mov_reg_T0(ot
, reg
);
5114 case 0x8e: /* mov seg, Gv */
5115 modrm
= ldub_code(s
->pc
++);
5116 reg
= (modrm
>> 3) & 7;
5117 if (reg
>= 6 || reg
== R_CS
)
5119 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
5120 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5122 /* if reg == SS, inhibit interrupts/trace */
5123 /* If several instructions disable interrupts, only the
5125 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5126 gen_helper_set_inhibit_irq();
5130 gen_jmp_im(s
->pc
- s
->cs_base
);
5134 case 0x8c: /* mov Gv, seg */
5135 modrm
= ldub_code(s
->pc
++);
5136 reg
= (modrm
>> 3) & 7;
5137 mod
= (modrm
>> 6) & 3;
5140 gen_op_movl_T0_seg(reg
);
5142 ot
= OT_WORD
+ dflag
;
5145 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
5148 case 0x1b6: /* movzbS Gv, Eb */
5149 case 0x1b7: /* movzwS Gv, Eb */
5150 case 0x1be: /* movsbS Gv, Eb */
5151 case 0x1bf: /* movswS Gv, Eb */
5154 /* d_ot is the size of destination */
5155 d_ot
= dflag
+ OT_WORD
;
5156 /* ot is the size of source */
5157 ot
= (b
& 1) + OT_BYTE
;
5158 modrm
= ldub_code(s
->pc
++);
5159 reg
= ((modrm
>> 3) & 7) | rex_r
;
5160 mod
= (modrm
>> 6) & 3;
5161 rm
= (modrm
& 7) | REX_B(s
);
5164 gen_op_mov_TN_reg(ot
, 0, rm
);
5165 switch(ot
| (b
& 8)) {
5167 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5170 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5173 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5177 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5180 gen_op_mov_reg_T0(d_ot
, reg
);
5182 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5184 gen_op_lds_T0_A0(ot
+ s
->mem_index
);
5186 gen_op_ldu_T0_A0(ot
+ s
->mem_index
);
5188 gen_op_mov_reg_T0(d_ot
, reg
);
5193 case 0x8d: /* lea */
5194 ot
= dflag
+ OT_WORD
;
5195 modrm
= ldub_code(s
->pc
++);
5196 mod
= (modrm
>> 6) & 3;
5199 reg
= ((modrm
>> 3) & 7) | rex_r
;
5200 /* we must ensure that no segment is added */
5204 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5206 gen_op_mov_reg_A0(ot
- OT_WORD
, reg
);
5209 case 0xa0: /* mov EAX, Ov */
5211 case 0xa2: /* mov Ov, EAX */
5214 target_ulong offset_addr
;
5219 ot
= dflag
+ OT_WORD
;
5220 #ifdef TARGET_X86_64
5221 if (s
->aflag
== 2) {
5222 offset_addr
= ldq_code(s
->pc
);
5224 gen_op_movq_A0_im(offset_addr
);
5229 offset_addr
= insn_get(s
, OT_LONG
);
5231 offset_addr
= insn_get(s
, OT_WORD
);
5233 gen_op_movl_A0_im(offset_addr
);
5235 gen_add_A0_ds_seg(s
);
5237 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
5238 gen_op_mov_reg_T0(ot
, R_EAX
);
5240 gen_op_mov_TN_reg(ot
, 0, R_EAX
);
5241 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5245 case 0xd7: /* xlat */
5246 #ifdef TARGET_X86_64
5247 if (s
->aflag
== 2) {
5248 gen_op_movq_A0_reg(R_EBX
);
5249 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
5250 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5251 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5255 gen_op_movl_A0_reg(R_EBX
);
5256 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
5257 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5258 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5260 gen_op_andl_A0_ffff();
5262 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
5264 gen_add_A0_ds_seg(s
);
5265 gen_op_ldu_T0_A0(OT_BYTE
+ s
->mem_index
);
5266 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
5268 case 0xb0 ... 0xb7: /* mov R, Ib */
5269 val
= insn_get(s
, OT_BYTE
);
5270 gen_op_movl_T0_im(val
);
5271 gen_op_mov_reg_T0(OT_BYTE
, (b
& 7) | REX_B(s
));
5273 case 0xb8 ... 0xbf: /* mov R, Iv */
5274 #ifdef TARGET_X86_64
5278 tmp
= ldq_code(s
->pc
);
5280 reg
= (b
& 7) | REX_B(s
);
5281 gen_movtl_T0_im(tmp
);
5282 gen_op_mov_reg_T0(OT_QUAD
, reg
);
5286 ot
= dflag
? OT_LONG
: OT_WORD
;
5287 val
= insn_get(s
, ot
);
5288 reg
= (b
& 7) | REX_B(s
);
5289 gen_op_movl_T0_im(val
);
5290 gen_op_mov_reg_T0(ot
, reg
);
5294 case 0x91 ... 0x97: /* xchg R, EAX */
5295 ot
= dflag
+ OT_WORD
;
5296 reg
= (b
& 7) | REX_B(s
);
5300 case 0x87: /* xchg Ev, Gv */
5304 ot
= dflag
+ OT_WORD
;
5305 modrm
= ldub_code(s
->pc
++);
5306 reg
= ((modrm
>> 3) & 7) | rex_r
;
5307 mod
= (modrm
>> 6) & 3;
5309 rm
= (modrm
& 7) | REX_B(s
);
5311 gen_op_mov_TN_reg(ot
, 0, reg
);
5312 gen_op_mov_TN_reg(ot
, 1, rm
);
5313 gen_op_mov_reg_T0(ot
, rm
);
5314 gen_op_mov_reg_T1(ot
, reg
);
5316 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5317 gen_op_mov_TN_reg(ot
, 0, reg
);
5318 /* for xchg, lock is implicit */
5319 if (!(prefixes
& PREFIX_LOCK
))
5321 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5322 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5323 if (!(prefixes
& PREFIX_LOCK
))
5324 gen_helper_unlock();
5325 gen_op_mov_reg_T1(ot
, reg
);
5328 case 0xc4: /* les Gv */
5333 case 0xc5: /* lds Gv */
5338 case 0x1b2: /* lss Gv */
5341 case 0x1b4: /* lfs Gv */
5344 case 0x1b5: /* lgs Gv */
5347 ot
= dflag
? OT_LONG
: OT_WORD
;
5348 modrm
= ldub_code(s
->pc
++);
5349 reg
= ((modrm
>> 3) & 7) | rex_r
;
5350 mod
= (modrm
>> 6) & 3;
5353 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5354 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5355 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
5356 /* load the segment first to handle exceptions properly */
5357 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
5358 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5359 /* then put the data */
5360 gen_op_mov_reg_T1(ot
, reg
);
5362 gen_jmp_im(s
->pc
- s
->cs_base
);
5367 /************************/
5378 ot
= dflag
+ OT_WORD
;
5380 modrm
= ldub_code(s
->pc
++);
5381 mod
= (modrm
>> 6) & 3;
5382 op
= (modrm
>> 3) & 7;
5388 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5391 opreg
= (modrm
& 7) | REX_B(s
);
5396 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5399 shift
= ldub_code(s
->pc
++);
5401 gen_shifti(s
, op
, ot
, opreg
, shift
);
5416 case 0x1a4: /* shld imm */
5420 case 0x1a5: /* shld cl */
5424 case 0x1ac: /* shrd imm */
5428 case 0x1ad: /* shrd cl */
5432 ot
= dflag
+ OT_WORD
;
5433 modrm
= ldub_code(s
->pc
++);
5434 mod
= (modrm
>> 6) & 3;
5435 rm
= (modrm
& 7) | REX_B(s
);
5436 reg
= ((modrm
>> 3) & 7) | rex_r
;
5438 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5443 gen_op_mov_TN_reg(ot
, 1, reg
);
5446 val
= ldub_code(s
->pc
++);
5447 tcg_gen_movi_tl(cpu_T3
, val
);
5449 tcg_gen_mov_tl(cpu_T3
, cpu_regs
[R_ECX
]);
5451 gen_shiftd_rm_T1_T3(s
, ot
, opreg
, op
);
5454 /************************/
5457 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5458 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5459 /* XXX: what to do if illegal op ? */
5460 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5463 modrm
= ldub_code(s
->pc
++);
5464 mod
= (modrm
>> 6) & 3;
5466 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5469 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5471 case 0x00 ... 0x07: /* fxxxs */
5472 case 0x10 ... 0x17: /* fixxxl */
5473 case 0x20 ... 0x27: /* fxxxl */
5474 case 0x30 ... 0x37: /* fixxx */
5481 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5482 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5483 gen_helper_flds_FT0(cpu_tmp2_i32
);
5486 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5487 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5488 gen_helper_fildl_FT0(cpu_tmp2_i32
);
5491 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5492 (s
->mem_index
>> 2) - 1);
5493 gen_helper_fldl_FT0(cpu_tmp1_i64
);
5497 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5498 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5499 gen_helper_fildl_FT0(cpu_tmp2_i32
);
5503 gen_helper_fp_arith_ST0_FT0(op1
);
5505 /* fcomp needs pop */
5510 case 0x08: /* flds */
5511 case 0x0a: /* fsts */
5512 case 0x0b: /* fstps */
5513 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5514 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5515 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5520 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5521 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5522 gen_helper_flds_ST0(cpu_tmp2_i32
);
5525 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5526 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5527 gen_helper_fildl_ST0(cpu_tmp2_i32
);
5530 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5531 (s
->mem_index
>> 2) - 1);
5532 gen_helper_fldl_ST0(cpu_tmp1_i64
);
5536 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5537 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5538 gen_helper_fildl_ST0(cpu_tmp2_i32
);
5543 /* XXX: the corresponding CPUID bit must be tested ! */
5546 gen_helper_fisttl_ST0(cpu_tmp2_i32
);
5547 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5548 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5551 gen_helper_fisttll_ST0(cpu_tmp1_i64
);
5552 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5553 (s
->mem_index
>> 2) - 1);
5557 gen_helper_fistt_ST0(cpu_tmp2_i32
);
5558 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5559 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5567 gen_helper_fsts_ST0(cpu_tmp2_i32
);
5568 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5569 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5572 gen_helper_fistl_ST0(cpu_tmp2_i32
);
5573 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5574 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5577 gen_helper_fstl_ST0(cpu_tmp1_i64
);
5578 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5579 (s
->mem_index
>> 2) - 1);
5583 gen_helper_fist_ST0(cpu_tmp2_i32
);
5584 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5585 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5593 case 0x0c: /* fldenv mem */
5594 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5595 gen_op_set_cc_op(s
->cc_op
);
5596 gen_jmp_im(pc_start
- s
->cs_base
);
5598 cpu_A0
, tcg_const_i32(s
->dflag
));
5600 case 0x0d: /* fldcw mem */
5601 gen_op_ld_T0_A0(OT_WORD
+ s
->mem_index
);
5602 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5603 gen_helper_fldcw(cpu_tmp2_i32
);
5605 case 0x0e: /* fnstenv mem */
5606 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5607 gen_op_set_cc_op(s
->cc_op
);
5608 gen_jmp_im(pc_start
- s
->cs_base
);
5609 gen_helper_fstenv(cpu_A0
, tcg_const_i32(s
->dflag
));
5611 case 0x0f: /* fnstcw mem */
5612 gen_helper_fnstcw(cpu_tmp2_i32
);
5613 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5614 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5616 case 0x1d: /* fldt mem */
5617 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5618 gen_op_set_cc_op(s
->cc_op
);
5619 gen_jmp_im(pc_start
- s
->cs_base
);
5620 gen_helper_fldt_ST0(cpu_A0
);
5622 case 0x1f: /* fstpt mem */
5623 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5624 gen_op_set_cc_op(s
->cc_op
);
5625 gen_jmp_im(pc_start
- s
->cs_base
);
5626 gen_helper_fstt_ST0(cpu_A0
);
5629 case 0x2c: /* frstor mem */
5630 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5631 gen_op_set_cc_op(s
->cc_op
);
5632 gen_jmp_im(pc_start
- s
->cs_base
);
5633 gen_helper_frstor(cpu_A0
, tcg_const_i32(s
->dflag
));
5635 case 0x2e: /* fnsave mem */
5636 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5637 gen_op_set_cc_op(s
->cc_op
);
5638 gen_jmp_im(pc_start
- s
->cs_base
);
5639 gen_helper_fsave(cpu_A0
, tcg_const_i32(s
->dflag
));
5641 case 0x2f: /* fnstsw mem */
5642 gen_helper_fnstsw(cpu_tmp2_i32
);
5643 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5644 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5646 case 0x3c: /* fbld */
5647 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5648 gen_op_set_cc_op(s
->cc_op
);
5649 gen_jmp_im(pc_start
- s
->cs_base
);
5650 gen_helper_fbld_ST0(cpu_A0
);
5652 case 0x3e: /* fbstp */
5653 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5654 gen_op_set_cc_op(s
->cc_op
);
5655 gen_jmp_im(pc_start
- s
->cs_base
);
5656 gen_helper_fbst_ST0(cpu_A0
);
5659 case 0x3d: /* fildll */
5660 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5661 (s
->mem_index
>> 2) - 1);
5662 gen_helper_fildll_ST0(cpu_tmp1_i64
);
5664 case 0x3f: /* fistpll */
5665 gen_helper_fistll_ST0(cpu_tmp1_i64
);
5666 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5667 (s
->mem_index
>> 2) - 1);
5674 /* register float ops */
5678 case 0x08: /* fld sti */
5680 gen_helper_fmov_ST0_STN(tcg_const_i32((opreg
+ 1) & 7));
5682 case 0x09: /* fxchg sti */
5683 case 0x29: /* fxchg4 sti, undocumented op */
5684 case 0x39: /* fxchg7 sti, undocumented op */
5685 gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg
));
5687 case 0x0a: /* grp d9/2 */
5690 /* check exceptions (FreeBSD FPU probe) */
5691 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5692 gen_op_set_cc_op(s
->cc_op
);
5693 gen_jmp_im(pc_start
- s
->cs_base
);
5700 case 0x0c: /* grp d9/4 */
5703 gen_helper_fchs_ST0();
5706 gen_helper_fabs_ST0();
5709 gen_helper_fldz_FT0();
5710 gen_helper_fcom_ST0_FT0();
5713 gen_helper_fxam_ST0();
5719 case 0x0d: /* grp d9/5 */
5724 gen_helper_fld1_ST0();
5728 gen_helper_fldl2t_ST0();
5732 gen_helper_fldl2e_ST0();
5736 gen_helper_fldpi_ST0();
5740 gen_helper_fldlg2_ST0();
5744 gen_helper_fldln2_ST0();
5748 gen_helper_fldz_ST0();
5755 case 0x0e: /* grp d9/6 */
5766 case 3: /* fpatan */
5767 gen_helper_fpatan();
5769 case 4: /* fxtract */
5770 gen_helper_fxtract();
5772 case 5: /* fprem1 */
5773 gen_helper_fprem1();
5775 case 6: /* fdecstp */
5776 gen_helper_fdecstp();
5779 case 7: /* fincstp */
5780 gen_helper_fincstp();
5784 case 0x0f: /* grp d9/7 */
5789 case 1: /* fyl2xp1 */
5790 gen_helper_fyl2xp1();
5795 case 3: /* fsincos */
5796 gen_helper_fsincos();
5798 case 5: /* fscale */
5799 gen_helper_fscale();
5801 case 4: /* frndint */
5802 gen_helper_frndint();
5813 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5814 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5815 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5821 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
5825 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5826 gen_helper_fp_arith_ST0_FT0(op1
);
5830 case 0x02: /* fcom */
5831 case 0x22: /* fcom2, undocumented op */
5832 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5833 gen_helper_fcom_ST0_FT0();
5835 case 0x03: /* fcomp */
5836 case 0x23: /* fcomp3, undocumented op */
5837 case 0x32: /* fcomp5, undocumented op */
5838 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5839 gen_helper_fcom_ST0_FT0();
5842 case 0x15: /* da/5 */
5844 case 1: /* fucompp */
5845 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5846 gen_helper_fucom_ST0_FT0();
5856 case 0: /* feni (287 only, just do nop here) */
5858 case 1: /* fdisi (287 only, just do nop here) */
5863 case 3: /* fninit */
5864 gen_helper_fninit();
5866 case 4: /* fsetpm (287 only, just do nop here) */
5872 case 0x1d: /* fucomi */
5873 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5874 gen_op_set_cc_op(s
->cc_op
);
5875 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5876 gen_helper_fucomi_ST0_FT0();
5877 s
->cc_op
= CC_OP_EFLAGS
;
5879 case 0x1e: /* fcomi */
5880 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5881 gen_op_set_cc_op(s
->cc_op
);
5882 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5883 gen_helper_fcomi_ST0_FT0();
5884 s
->cc_op
= CC_OP_EFLAGS
;
5886 case 0x28: /* ffree sti */
5887 gen_helper_ffree_STN(tcg_const_i32(opreg
));
5889 case 0x2a: /* fst sti */
5890 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg
));
5892 case 0x2b: /* fstp sti */
5893 case 0x0b: /* fstp1 sti, undocumented op */
5894 case 0x3a: /* fstp8 sti, undocumented op */
5895 case 0x3b: /* fstp9 sti, undocumented op */
5896 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg
));
5899 case 0x2c: /* fucom st(i) */
5900 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5901 gen_helper_fucom_ST0_FT0();
5903 case 0x2d: /* fucomp st(i) */
5904 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5905 gen_helper_fucom_ST0_FT0();
5908 case 0x33: /* de/3 */
5910 case 1: /* fcompp */
5911 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5912 gen_helper_fcom_ST0_FT0();
5920 case 0x38: /* ffreep sti, undocumented op */
5921 gen_helper_ffree_STN(tcg_const_i32(opreg
));
5924 case 0x3c: /* df/4 */
5927 gen_helper_fnstsw(cpu_tmp2_i32
);
5928 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5929 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
5935 case 0x3d: /* fucomip */
5936 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5937 gen_op_set_cc_op(s
->cc_op
);
5938 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5939 gen_helper_fucomi_ST0_FT0();
5941 s
->cc_op
= CC_OP_EFLAGS
;
5943 case 0x3e: /* fcomip */
5944 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5945 gen_op_set_cc_op(s
->cc_op
);
5946 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5947 gen_helper_fcomi_ST0_FT0();
5949 s
->cc_op
= CC_OP_EFLAGS
;
5951 case 0x10 ... 0x13: /* fcmovxx */
5955 static const uint8_t fcmov_cc
[8] = {
5961 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
5962 l1
= gen_new_label();
5963 gen_jcc1(s
, s
->cc_op
, op1
, l1
);
5964 gen_helper_fmov_ST0_STN(tcg_const_i32(opreg
));
5973 /************************/
5976 case 0xa4: /* movsS */
5981 ot
= dflag
+ OT_WORD
;
5983 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
5984 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
5990 case 0xaa: /* stosS */
5995 ot
= dflag
+ OT_WORD
;
5997 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
5998 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6003 case 0xac: /* lodsS */
6008 ot
= dflag
+ OT_WORD
;
6009 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6010 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6015 case 0xae: /* scasS */
6020 ot
= dflag
+ OT_WORD
;
6021 if (prefixes
& PREFIX_REPNZ
) {
6022 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6023 } else if (prefixes
& PREFIX_REPZ
) {
6024 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6027 s
->cc_op
= CC_OP_SUBB
+ ot
;
6031 case 0xa6: /* cmpsS */
6036 ot
= dflag
+ OT_WORD
;
6037 if (prefixes
& PREFIX_REPNZ
) {
6038 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6039 } else if (prefixes
& PREFIX_REPZ
) {
6040 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6043 s
->cc_op
= CC_OP_SUBB
+ ot
;
6046 case 0x6c: /* insS */
6051 ot
= dflag
? OT_LONG
: OT_WORD
;
6052 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6053 gen_op_andl_T0_ffff();
6054 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6055 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6056 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6057 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6061 gen_jmp(s
, s
->pc
- s
->cs_base
);
6065 case 0x6e: /* outsS */
6070 ot
= dflag
? OT_LONG
: OT_WORD
;
6071 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6072 gen_op_andl_T0_ffff();
6073 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6074 svm_is_rep(prefixes
) | 4);
6075 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6076 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6080 gen_jmp(s
, s
->pc
- s
->cs_base
);
6085 /************************/
6093 ot
= dflag
? OT_LONG
: OT_WORD
;
6094 val
= ldub_code(s
->pc
++);
6095 gen_op_movl_T0_im(val
);
6096 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6097 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6100 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6101 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6102 gen_op_mov_reg_T1(ot
, R_EAX
);
6105 gen_jmp(s
, s
->pc
- s
->cs_base
);
6113 ot
= dflag
? OT_LONG
: OT_WORD
;
6114 val
= ldub_code(s
->pc
++);
6115 gen_op_movl_T0_im(val
);
6116 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6117 svm_is_rep(prefixes
));
6118 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6122 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6123 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
6124 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6125 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6128 gen_jmp(s
, s
->pc
- s
->cs_base
);
6136 ot
= dflag
? OT_LONG
: OT_WORD
;
6137 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6138 gen_op_andl_T0_ffff();
6139 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6140 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6143 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6144 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6145 gen_op_mov_reg_T1(ot
, R_EAX
);
6148 gen_jmp(s
, s
->pc
- s
->cs_base
);
6156 ot
= dflag
? OT_LONG
: OT_WORD
;
6157 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6158 gen_op_andl_T0_ffff();
6159 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6160 svm_is_rep(prefixes
));
6161 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6165 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6166 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
6167 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6168 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6171 gen_jmp(s
, s
->pc
- s
->cs_base
);
6175 /************************/
6177 case 0xc2: /* ret im */
6178 val
= ldsw_code(s
->pc
);
6181 if (CODE64(s
) && s
->dflag
)
6183 gen_stack_update(s
, val
+ (2 << s
->dflag
));
6185 gen_op_andl_T0_ffff();
6189 case 0xc3: /* ret */
6193 gen_op_andl_T0_ffff();
6197 case 0xca: /* lret im */
6198 val
= ldsw_code(s
->pc
);
6201 if (s
->pe
&& !s
->vm86
) {
6202 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6203 gen_op_set_cc_op(s
->cc_op
);
6204 gen_jmp_im(pc_start
- s
->cs_base
);
6205 gen_helper_lret_protected(tcg_const_i32(s
->dflag
),
6206 tcg_const_i32(val
));
6210 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6212 gen_op_andl_T0_ffff();
6213 /* NOTE: keeping EIP updated is not a problem in case of
6217 gen_op_addl_A0_im(2 << s
->dflag
);
6218 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6219 gen_op_movl_seg_T0_vm(R_CS
);
6220 /* add stack offset */
6221 gen_stack_update(s
, val
+ (4 << s
->dflag
));
6225 case 0xcb: /* lret */
6228 case 0xcf: /* iret */
6229 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6232 gen_helper_iret_real(tcg_const_i32(s
->dflag
));
6233 s
->cc_op
= CC_OP_EFLAGS
;
6234 } else if (s
->vm86
) {
6236 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6238 gen_helper_iret_real(tcg_const_i32(s
->dflag
));
6239 s
->cc_op
= CC_OP_EFLAGS
;
6242 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6243 gen_op_set_cc_op(s
->cc_op
);
6244 gen_jmp_im(pc_start
- s
->cs_base
);
6245 gen_helper_iret_protected(tcg_const_i32(s
->dflag
),
6246 tcg_const_i32(s
->pc
- s
->cs_base
));
6247 s
->cc_op
= CC_OP_EFLAGS
;
6251 case 0xe8: /* call im */
6254 tval
= (int32_t)insn_get(s
, OT_LONG
);
6256 tval
= (int16_t)insn_get(s
, OT_WORD
);
6257 next_eip
= s
->pc
- s
->cs_base
;
6263 gen_movtl_T0_im(next_eip
);
6268 case 0x9a: /* lcall im */
6270 unsigned int selector
, offset
;
6274 ot
= dflag
? OT_LONG
: OT_WORD
;
6275 offset
= insn_get(s
, ot
);
6276 selector
= insn_get(s
, OT_WORD
);
6278 gen_op_movl_T0_im(selector
);
6279 gen_op_movl_T1_imu(offset
);
6282 case 0xe9: /* jmp im */
6284 tval
= (int32_t)insn_get(s
, OT_LONG
);
6286 tval
= (int16_t)insn_get(s
, OT_WORD
);
6287 tval
+= s
->pc
- s
->cs_base
;
6294 case 0xea: /* ljmp im */
6296 unsigned int selector
, offset
;
6300 ot
= dflag
? OT_LONG
: OT_WORD
;
6301 offset
= insn_get(s
, ot
);
6302 selector
= insn_get(s
, OT_WORD
);
6304 gen_op_movl_T0_im(selector
);
6305 gen_op_movl_T1_imu(offset
);
6308 case 0xeb: /* jmp Jb */
6309 tval
= (int8_t)insn_get(s
, OT_BYTE
);
6310 tval
+= s
->pc
- s
->cs_base
;
6315 case 0x70 ... 0x7f: /* jcc Jb */
6316 tval
= (int8_t)insn_get(s
, OT_BYTE
);
6318 case 0x180 ... 0x18f: /* jcc Jv */
6320 tval
= (int32_t)insn_get(s
, OT_LONG
);
6322 tval
= (int16_t)insn_get(s
, OT_WORD
);
6325 next_eip
= s
->pc
- s
->cs_base
;
6329 gen_jcc(s
, b
, tval
, next_eip
);
6332 case 0x190 ... 0x19f: /* setcc Gv */
6333 modrm
= ldub_code(s
->pc
++);
6335 gen_ldst_modrm(s
, modrm
, OT_BYTE
, OR_TMP0
, 1);
6337 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6342 ot
= dflag
+ OT_WORD
;
6343 modrm
= ldub_code(s
->pc
++);
6344 reg
= ((modrm
>> 3) & 7) | rex_r
;
6345 mod
= (modrm
>> 6) & 3;
6346 t0
= tcg_temp_local_new();
6348 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6349 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
6351 rm
= (modrm
& 7) | REX_B(s
);
6352 gen_op_mov_v_reg(ot
, t0
, rm
);
6354 #ifdef TARGET_X86_64
6355 if (ot
== OT_LONG
) {
6356 /* XXX: specific Intel behaviour ? */
6357 l1
= gen_new_label();
6358 gen_jcc1(s
, s
->cc_op
, b
^ 1, l1
);
6359 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
6361 tcg_gen_ext32u_tl(cpu_regs
[reg
], cpu_regs
[reg
]);
6365 l1
= gen_new_label();
6366 gen_jcc1(s
, s
->cc_op
, b
^ 1, l1
);
6367 gen_op_mov_reg_v(ot
, reg
, t0
);
6374 /************************/
6376 case 0x9c: /* pushf */
6377 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6378 if (s
->vm86
&& s
->iopl
!= 3) {
6379 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6381 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6382 gen_op_set_cc_op(s
->cc_op
);
6383 gen_helper_read_eflags(cpu_T
[0]);
6387 case 0x9d: /* popf */
6388 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6389 if (s
->vm86
&& s
->iopl
!= 3) {
6390 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6395 gen_helper_write_eflags(cpu_T
[0],
6396 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
| IOPL_MASK
)));
6398 gen_helper_write_eflags(cpu_T
[0],
6399 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
| IOPL_MASK
) & 0xffff));
6402 if (s
->cpl
<= s
->iopl
) {
6404 gen_helper_write_eflags(cpu_T
[0],
6405 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
)));
6407 gen_helper_write_eflags(cpu_T
[0],
6408 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
) & 0xffff));
6412 gen_helper_write_eflags(cpu_T
[0],
6413 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
)));
6415 gen_helper_write_eflags(cpu_T
[0],
6416 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
) & 0xffff));
6421 s
->cc_op
= CC_OP_EFLAGS
;
6422 /* abort translation because TF flag may change */
6423 gen_jmp_im(s
->pc
- s
->cs_base
);
6427 case 0x9e: /* sahf */
6428 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6430 gen_op_mov_TN_reg(OT_BYTE
, 0, R_AH
);
6431 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6432 gen_op_set_cc_op(s
->cc_op
);
6433 gen_compute_eflags(cpu_cc_src
);
6434 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6435 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6436 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6437 s
->cc_op
= CC_OP_EFLAGS
;
6439 case 0x9f: /* lahf */
6440 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6442 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6443 gen_op_set_cc_op(s
->cc_op
);
6444 gen_compute_eflags(cpu_T
[0]);
6445 /* Note: gen_compute_eflags() only gives the condition codes */
6446 tcg_gen_ori_tl(cpu_T
[0], cpu_T
[0], 0x02);
6447 gen_op_mov_reg_T0(OT_BYTE
, R_AH
);
6449 case 0xf5: /* cmc */
6450 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6451 gen_op_set_cc_op(s
->cc_op
);
6452 gen_compute_eflags(cpu_cc_src
);
6453 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6454 s
->cc_op
= CC_OP_EFLAGS
;
6456 case 0xf8: /* clc */
6457 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6458 gen_op_set_cc_op(s
->cc_op
);
6459 gen_compute_eflags(cpu_cc_src
);
6460 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6461 s
->cc_op
= CC_OP_EFLAGS
;
6463 case 0xf9: /* stc */
6464 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6465 gen_op_set_cc_op(s
->cc_op
);
6466 gen_compute_eflags(cpu_cc_src
);
6467 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6468 s
->cc_op
= CC_OP_EFLAGS
;
6470 case 0xfc: /* cld */
6471 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6472 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUState
, df
));
6474 case 0xfd: /* std */
6475 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6476 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUState
, df
));
6479 /************************/
6480 /* bit operations */
6481 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6482 ot
= dflag
+ OT_WORD
;
6483 modrm
= ldub_code(s
->pc
++);
6484 op
= (modrm
>> 3) & 7;
6485 mod
= (modrm
>> 6) & 3;
6486 rm
= (modrm
& 7) | REX_B(s
);
6489 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6490 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6492 gen_op_mov_TN_reg(ot
, 0, rm
);
6495 val
= ldub_code(s
->pc
++);
6496 gen_op_movl_T1_im(val
);
6501 case 0x1a3: /* bt Gv, Ev */
6504 case 0x1ab: /* bts */
6507 case 0x1b3: /* btr */
6510 case 0x1bb: /* btc */
6513 ot
= dflag
+ OT_WORD
;
6514 modrm
= ldub_code(s
->pc
++);
6515 reg
= ((modrm
>> 3) & 7) | rex_r
;
6516 mod
= (modrm
>> 6) & 3;
6517 rm
= (modrm
& 7) | REX_B(s
);
6518 gen_op_mov_TN_reg(OT_LONG
, 1, reg
);
6520 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6521 /* specific case: we need to add a displacement */
6522 gen_exts(ot
, cpu_T
[1]);
6523 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6524 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6525 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6526 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6528 gen_op_mov_TN_reg(ot
, 0, rm
);
6531 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6534 tcg_gen_shr_tl(cpu_cc_src
, cpu_T
[0], cpu_T
[1]);
6535 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6538 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6539 tcg_gen_movi_tl(cpu_tmp0
, 1);
6540 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6541 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6544 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6545 tcg_gen_movi_tl(cpu_tmp0
, 1);
6546 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6547 tcg_gen_not_tl(cpu_tmp0
, cpu_tmp0
);
6548 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6552 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6553 tcg_gen_movi_tl(cpu_tmp0
, 1);
6554 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6555 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6558 s
->cc_op
= CC_OP_SARB
+ ot
;
6561 gen_op_st_T0_A0(ot
+ s
->mem_index
);
6563 gen_op_mov_reg_T0(ot
, rm
);
6564 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6565 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6568 case 0x1bc: /* bsf */
6569 case 0x1bd: /* bsr */
6574 ot
= dflag
+ OT_WORD
;
6575 modrm
= ldub_code(s
->pc
++);
6576 reg
= ((modrm
>> 3) & 7) | rex_r
;
6577 gen_ldst_modrm(s
,modrm
, ot
, OR_TMP0
, 0);
6578 gen_extu(ot
, cpu_T
[0]);
6579 t0
= tcg_temp_local_new();
6580 tcg_gen_mov_tl(t0
, cpu_T
[0]);
6581 if ((b
& 1) && (prefixes
& PREFIX_REPZ
) &&
6582 (s
->cpuid_ext3_features
& CPUID_EXT3_ABM
)) {
6584 case OT_WORD
: gen_helper_lzcnt(cpu_T
[0], t0
,
6585 tcg_const_i32(16)); break;
6586 case OT_LONG
: gen_helper_lzcnt(cpu_T
[0], t0
,
6587 tcg_const_i32(32)); break;
6588 case OT_QUAD
: gen_helper_lzcnt(cpu_T
[0], t0
,
6589 tcg_const_i32(64)); break;
6591 gen_op_mov_reg_T0(ot
, reg
);
6593 label1
= gen_new_label();
6594 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6595 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, label1
);
6597 gen_helper_bsr(cpu_T
[0], t0
);
6599 gen_helper_bsf(cpu_T
[0], t0
);
6601 gen_op_mov_reg_T0(ot
, reg
);
6602 tcg_gen_movi_tl(cpu_cc_dst
, 1);
6603 gen_set_label(label1
);
6604 tcg_gen_discard_tl(cpu_cc_src
);
6605 s
->cc_op
= CC_OP_LOGICB
+ ot
;
6610 /************************/
6612 case 0x27: /* daa */
6615 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6616 gen_op_set_cc_op(s
->cc_op
);
6618 s
->cc_op
= CC_OP_EFLAGS
;
6620 case 0x2f: /* das */
6623 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6624 gen_op_set_cc_op(s
->cc_op
);
6626 s
->cc_op
= CC_OP_EFLAGS
;
6628 case 0x37: /* aaa */
6631 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6632 gen_op_set_cc_op(s
->cc_op
);
6634 s
->cc_op
= CC_OP_EFLAGS
;
6636 case 0x3f: /* aas */
6639 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6640 gen_op_set_cc_op(s
->cc_op
);
6642 s
->cc_op
= CC_OP_EFLAGS
;
6644 case 0xd4: /* aam */
6647 val
= ldub_code(s
->pc
++);
6649 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
6651 gen_helper_aam(tcg_const_i32(val
));
6652 s
->cc_op
= CC_OP_LOGICB
;
6655 case 0xd5: /* aad */
6658 val
= ldub_code(s
->pc
++);
6659 gen_helper_aad(tcg_const_i32(val
));
6660 s
->cc_op
= CC_OP_LOGICB
;
6662 /************************/
6664 case 0x90: /* nop */
6665 /* XXX: xchg + rex handling */
6666 /* XXX: correct lock test for all insn */
6667 if (prefixes
& PREFIX_LOCK
)
6669 if (prefixes
& PREFIX_REPZ
) {
6670 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PAUSE
);
6673 case 0x9b: /* fwait */
6674 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
6675 (HF_MP_MASK
| HF_TS_MASK
)) {
6676 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
6678 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6679 gen_op_set_cc_op(s
->cc_op
);
6680 gen_jmp_im(pc_start
- s
->cs_base
);
6684 case 0xcc: /* int3 */
6685 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6687 case 0xcd: /* int N */
6688 val
= ldub_code(s
->pc
++);
6689 if (s
->vm86
&& s
->iopl
!= 3) {
6690 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6692 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6695 case 0xce: /* into */
6698 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6699 gen_op_set_cc_op(s
->cc_op
);
6700 gen_jmp_im(pc_start
- s
->cs_base
);
6701 gen_helper_into(tcg_const_i32(s
->pc
- pc_start
));
6704 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6705 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
6707 gen_debug(s
, pc_start
- s
->cs_base
);
6710 tb_flush(cpu_single_env
);
6711 cpu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
6715 case 0xfa: /* cli */
6717 if (s
->cpl
<= s
->iopl
) {
6720 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6726 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6730 case 0xfb: /* sti */
6732 if (s
->cpl
<= s
->iopl
) {
6735 /* interruptions are enabled only the first insn after sti */
6736 /* If several instructions disable interrupts, only the
6738 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
6739 gen_helper_set_inhibit_irq();
6740 /* give a chance to handle pending irqs */
6741 gen_jmp_im(s
->pc
- s
->cs_base
);
6744 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6750 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6754 case 0x62: /* bound */
6757 ot
= dflag
? OT_LONG
: OT_WORD
;
6758 modrm
= ldub_code(s
->pc
++);
6759 reg
= (modrm
>> 3) & 7;
6760 mod
= (modrm
>> 6) & 3;
6763 gen_op_mov_TN_reg(ot
, 0, reg
);
6764 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6765 gen_jmp_im(pc_start
- s
->cs_base
);
6766 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6768 gen_helper_boundw(cpu_A0
, cpu_tmp2_i32
);
6770 gen_helper_boundl(cpu_A0
, cpu_tmp2_i32
);
6772 case 0x1c8 ... 0x1cf: /* bswap reg */
6773 reg
= (b
& 7) | REX_B(s
);
6774 #ifdef TARGET_X86_64
6776 gen_op_mov_TN_reg(OT_QUAD
, 0, reg
);
6777 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
6778 gen_op_mov_reg_T0(OT_QUAD
, reg
);
6782 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
6783 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
6784 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
6785 gen_op_mov_reg_T0(OT_LONG
, reg
);
6788 case 0xd6: /* salc */
6791 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6792 gen_op_set_cc_op(s
->cc_op
);
6793 gen_compute_eflags_c(cpu_T
[0]);
6794 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
6795 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
6797 case 0xe0: /* loopnz */
6798 case 0xe1: /* loopz */
6799 case 0xe2: /* loop */
6800 case 0xe3: /* jecxz */
6804 tval
= (int8_t)insn_get(s
, OT_BYTE
);
6805 next_eip
= s
->pc
- s
->cs_base
;
6810 l1
= gen_new_label();
6811 l2
= gen_new_label();
6812 l3
= gen_new_label();
6815 case 0: /* loopnz */
6817 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6818 gen_op_set_cc_op(s
->cc_op
);
6819 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6820 gen_op_jz_ecx(s
->aflag
, l3
);
6821 gen_compute_eflags(cpu_tmp0
);
6822 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_Z
);
6824 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, l1
);
6826 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, l1
);
6830 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6831 gen_op_jnz_ecx(s
->aflag
, l1
);
6835 gen_op_jz_ecx(s
->aflag
, l1
);
6840 gen_jmp_im(next_eip
);
6849 case 0x130: /* wrmsr */
6850 case 0x132: /* rdmsr */
6852 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6854 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6855 gen_op_set_cc_op(s
->cc_op
);
6856 gen_jmp_im(pc_start
- s
->cs_base
);
6864 case 0x131: /* rdtsc */
6865 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6866 gen_op_set_cc_op(s
->cc_op
);
6867 gen_jmp_im(pc_start
- s
->cs_base
);
6873 gen_jmp(s
, s
->pc
- s
->cs_base
);
6876 case 0x133: /* rdpmc */
6877 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6878 gen_op_set_cc_op(s
->cc_op
);
6879 gen_jmp_im(pc_start
- s
->cs_base
);
6882 case 0x134: /* sysenter */
6883 /* For Intel SYSENTER is valid on 64-bit */
6884 if (CODE64(s
) && cpu_single_env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
6887 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6889 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6890 gen_op_set_cc_op(s
->cc_op
);
6891 s
->cc_op
= CC_OP_DYNAMIC
;
6893 gen_jmp_im(pc_start
- s
->cs_base
);
6894 gen_helper_sysenter();
6898 case 0x135: /* sysexit */
6899 /* For Intel SYSEXIT is valid on 64-bit */
6900 if (CODE64(s
) && cpu_single_env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
6903 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6905 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6906 gen_op_set_cc_op(s
->cc_op
);
6907 s
->cc_op
= CC_OP_DYNAMIC
;
6909 gen_jmp_im(pc_start
- s
->cs_base
);
6910 gen_helper_sysexit(tcg_const_i32(dflag
));
6914 #ifdef TARGET_X86_64
6915 case 0x105: /* syscall */
6916 /* XXX: is it usable in real mode ? */
6917 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6918 gen_op_set_cc_op(s
->cc_op
);
6919 s
->cc_op
= CC_OP_DYNAMIC
;
6921 gen_jmp_im(pc_start
- s
->cs_base
);
6922 gen_helper_syscall(tcg_const_i32(s
->pc
- pc_start
));
6925 case 0x107: /* sysret */
6927 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6929 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6930 gen_op_set_cc_op(s
->cc_op
);
6931 s
->cc_op
= CC_OP_DYNAMIC
;
6933 gen_jmp_im(pc_start
- s
->cs_base
);
6934 gen_helper_sysret(tcg_const_i32(s
->dflag
));
6935 /* condition codes are modified only in long mode */
6937 s
->cc_op
= CC_OP_EFLAGS
;
6942 case 0x1a2: /* cpuid */
6943 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6944 gen_op_set_cc_op(s
->cc_op
);
6945 gen_jmp_im(pc_start
- s
->cs_base
);
6948 case 0xf4: /* hlt */
6950 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6952 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6953 gen_op_set_cc_op(s
->cc_op
);
6954 gen_jmp_im(pc_start
- s
->cs_base
);
6955 gen_helper_hlt(tcg_const_i32(s
->pc
- pc_start
));
6960 modrm
= ldub_code(s
->pc
++);
6961 mod
= (modrm
>> 6) & 3;
6962 op
= (modrm
>> 3) & 7;
6965 if (!s
->pe
|| s
->vm86
)
6967 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
6968 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
6972 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
6975 if (!s
->pe
|| s
->vm86
)
6978 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6980 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
6981 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
6982 gen_jmp_im(pc_start
- s
->cs_base
);
6983 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6984 gen_helper_lldt(cpu_tmp2_i32
);
6988 if (!s
->pe
|| s
->vm86
)
6990 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
6991 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
6995 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
6998 if (!s
->pe
|| s
->vm86
)
7001 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7003 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
7004 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7005 gen_jmp_im(pc_start
- s
->cs_base
);
7006 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7007 gen_helper_ltr(cpu_tmp2_i32
);
7012 if (!s
->pe
|| s
->vm86
)
7014 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7015 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7016 gen_op_set_cc_op(s
->cc_op
);
7018 gen_helper_verr(cpu_T
[0]);
7020 gen_helper_verw(cpu_T
[0]);
7021 s
->cc_op
= CC_OP_EFLAGS
;
7028 modrm
= ldub_code(s
->pc
++);
7029 mod
= (modrm
>> 6) & 3;
7030 op
= (modrm
>> 3) & 7;
7036 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
7037 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7038 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
7039 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
7040 gen_add_A0_im(s
, 2);
7041 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
7043 gen_op_andl_T0_im(0xffffff);
7044 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7049 case 0: /* monitor */
7050 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7053 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7054 gen_op_set_cc_op(s
->cc_op
);
7055 gen_jmp_im(pc_start
- s
->cs_base
);
7056 #ifdef TARGET_X86_64
7057 if (s
->aflag
== 2) {
7058 gen_op_movq_A0_reg(R_EAX
);
7062 gen_op_movl_A0_reg(R_EAX
);
7064 gen_op_andl_A0_ffff();
7066 gen_add_A0_ds_seg(s
);
7067 gen_helper_monitor(cpu_A0
);
7070 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7073 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
7074 gen_op_set_cc_op(s
->cc_op
);
7075 s
->cc_op
= CC_OP_DYNAMIC
;
7077 gen_jmp_im(pc_start
- s
->cs_base
);
7078 gen_helper_mwait(tcg_const_i32(s
->pc
- pc_start
));
7085 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7086 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7087 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7088 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
7089 gen_add_A0_im(s
, 2);
7090 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7092 gen_op_andl_T0_im(0xffffff);
7093 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7099 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7100 gen_op_set_cc_op(s
->cc_op
);
7101 gen_jmp_im(pc_start
- s
->cs_base
);
7104 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7107 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7110 gen_helper_vmrun(tcg_const_i32(s
->aflag
),
7111 tcg_const_i32(s
->pc
- pc_start
));
7116 case 1: /* VMMCALL */
7117 if (!(s
->flags
& HF_SVME_MASK
))
7119 gen_helper_vmmcall();
7121 case 2: /* VMLOAD */
7122 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7125 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7128 gen_helper_vmload(tcg_const_i32(s
->aflag
));
7131 case 3: /* VMSAVE */
7132 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7135 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7138 gen_helper_vmsave(tcg_const_i32(s
->aflag
));
7142 if ((!(s
->flags
& HF_SVME_MASK
) &&
7143 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7147 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7154 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7157 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7163 case 6: /* SKINIT */
7164 if ((!(s
->flags
& HF_SVME_MASK
) &&
7165 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7168 gen_helper_skinit();
7170 case 7: /* INVLPGA */
7171 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7174 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7177 gen_helper_invlpga(tcg_const_i32(s
->aflag
));
7183 } else if (s
->cpl
!= 0) {
7184 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7186 gen_svm_check_intercept(s
, pc_start
,
7187 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7188 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7189 gen_op_ld_T1_A0(OT_WORD
+ s
->mem_index
);
7190 gen_add_A0_im(s
, 2);
7191 gen_op_ld_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7193 gen_op_andl_T0_im(0xffffff);
7195 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7196 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7198 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7199 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7204 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7205 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7206 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7208 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7210 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 1);
7214 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7216 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7217 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7218 gen_helper_lmsw(cpu_T
[0]);
7219 gen_jmp_im(s
->pc
- s
->cs_base
);
7224 if (mod
!= 3) { /* invlpg */
7226 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7228 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7229 gen_op_set_cc_op(s
->cc_op
);
7230 gen_jmp_im(pc_start
- s
->cs_base
);
7231 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7232 gen_helper_invlpg(cpu_A0
);
7233 gen_jmp_im(s
->pc
- s
->cs_base
);
7238 case 0: /* swapgs */
7239 #ifdef TARGET_X86_64
7242 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7244 tcg_gen_ld_tl(cpu_T
[0], cpu_env
,
7245 offsetof(CPUX86State
,segs
[R_GS
].base
));
7246 tcg_gen_ld_tl(cpu_T
[1], cpu_env
,
7247 offsetof(CPUX86State
,kernelgsbase
));
7248 tcg_gen_st_tl(cpu_T
[1], cpu_env
,
7249 offsetof(CPUX86State
,segs
[R_GS
].base
));
7250 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
7251 offsetof(CPUX86State
,kernelgsbase
));
7259 case 1: /* rdtscp */
7260 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_RDTSCP
))
7262 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7263 gen_op_set_cc_op(s
->cc_op
);
7264 gen_jmp_im(pc_start
- s
->cs_base
);
7267 gen_helper_rdtscp();
7270 gen_jmp(s
, s
->pc
- s
->cs_base
);
7282 case 0x108: /* invd */
7283 case 0x109: /* wbinvd */
7285 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7287 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7291 case 0x63: /* arpl or movslS (x86_64) */
7292 #ifdef TARGET_X86_64
7295 /* d_ot is the size of destination */
7296 d_ot
= dflag
+ OT_WORD
;
7298 modrm
= ldub_code(s
->pc
++);
7299 reg
= ((modrm
>> 3) & 7) | rex_r
;
7300 mod
= (modrm
>> 6) & 3;
7301 rm
= (modrm
& 7) | REX_B(s
);
7304 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
7306 if (d_ot
== OT_QUAD
)
7307 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7308 gen_op_mov_reg_T0(d_ot
, reg
);
7310 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7311 if (d_ot
== OT_QUAD
) {
7312 gen_op_lds_T0_A0(OT_LONG
+ s
->mem_index
);
7314 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7316 gen_op_mov_reg_T0(d_ot
, reg
);
7322 TCGv t0
, t1
, t2
, a0
;
7324 if (!s
->pe
|| s
->vm86
)
7326 t0
= tcg_temp_local_new();
7327 t1
= tcg_temp_local_new();
7328 t2
= tcg_temp_local_new();
7330 modrm
= ldub_code(s
->pc
++);
7331 reg
= (modrm
>> 3) & 7;
7332 mod
= (modrm
>> 6) & 3;
7335 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7336 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
7337 a0
= tcg_temp_local_new();
7338 tcg_gen_mov_tl(a0
, cpu_A0
);
7340 gen_op_mov_v_reg(ot
, t0
, rm
);
7343 gen_op_mov_v_reg(ot
, t1
, reg
);
7344 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7345 tcg_gen_andi_tl(t1
, t1
, 3);
7346 tcg_gen_movi_tl(t2
, 0);
7347 label1
= gen_new_label();
7348 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7349 tcg_gen_andi_tl(t0
, t0
, ~3);
7350 tcg_gen_or_tl(t0
, t0
, t1
);
7351 tcg_gen_movi_tl(t2
, CC_Z
);
7352 gen_set_label(label1
);
7354 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
7357 gen_op_mov_reg_v(ot
, rm
, t0
);
7359 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7360 gen_op_set_cc_op(s
->cc_op
);
7361 gen_compute_eflags(cpu_cc_src
);
7362 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7363 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7364 s
->cc_op
= CC_OP_EFLAGS
;
7370 case 0x102: /* lar */
7371 case 0x103: /* lsl */
7375 if (!s
->pe
|| s
->vm86
)
7377 ot
= dflag
? OT_LONG
: OT_WORD
;
7378 modrm
= ldub_code(s
->pc
++);
7379 reg
= ((modrm
>> 3) & 7) | rex_r
;
7380 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7381 t0
= tcg_temp_local_new();
7382 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7383 gen_op_set_cc_op(s
->cc_op
);
7385 gen_helper_lar(t0
, cpu_T
[0]);
7387 gen_helper_lsl(t0
, cpu_T
[0]);
7388 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7389 label1
= gen_new_label();
7390 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7391 gen_op_mov_reg_v(ot
, reg
, t0
);
7392 gen_set_label(label1
);
7393 s
->cc_op
= CC_OP_EFLAGS
;
7398 modrm
= ldub_code(s
->pc
++);
7399 mod
= (modrm
>> 6) & 3;
7400 op
= (modrm
>> 3) & 7;
7402 case 0: /* prefetchnta */
7403 case 1: /* prefetchnt0 */
7404 case 2: /* prefetchnt0 */
7405 case 3: /* prefetchnt0 */
7408 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7409 /* nothing more to do */
7411 default: /* nop (multi byte) */
7412 gen_nop_modrm(s
, modrm
);
7416 case 0x119 ... 0x11f: /* nop (multi byte) */
7417 modrm
= ldub_code(s
->pc
++);
7418 gen_nop_modrm(s
, modrm
);
7420 case 0x120: /* mov reg, crN */
7421 case 0x122: /* mov crN, reg */
7423 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7425 modrm
= ldub_code(s
->pc
++);
7426 if ((modrm
& 0xc0) != 0xc0)
7428 rm
= (modrm
& 7) | REX_B(s
);
7429 reg
= ((modrm
>> 3) & 7) | rex_r
;
7434 if ((prefixes
& PREFIX_LOCK
) && (reg
== 0) &&
7435 (s
->cpuid_ext3_features
& CPUID_EXT3_CR8LEG
)) {
7444 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7445 gen_op_set_cc_op(s
->cc_op
);
7446 gen_jmp_im(pc_start
- s
->cs_base
);
7448 gen_op_mov_TN_reg(ot
, 0, rm
);
7449 gen_helper_write_crN(tcg_const_i32(reg
), cpu_T
[0]);
7450 gen_jmp_im(s
->pc
- s
->cs_base
);
7453 gen_helper_read_crN(cpu_T
[0], tcg_const_i32(reg
));
7454 gen_op_mov_reg_T0(ot
, rm
);
7462 case 0x121: /* mov reg, drN */
7463 case 0x123: /* mov drN, reg */
7465 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7467 modrm
= ldub_code(s
->pc
++);
7468 if ((modrm
& 0xc0) != 0xc0)
7470 rm
= (modrm
& 7) | REX_B(s
);
7471 reg
= ((modrm
>> 3) & 7) | rex_r
;
7476 /* XXX: do it dynamically with CR4.DE bit */
7477 if (reg
== 4 || reg
== 5 || reg
>= 8)
7480 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7481 gen_op_mov_TN_reg(ot
, 0, rm
);
7482 gen_helper_movl_drN_T0(tcg_const_i32(reg
), cpu_T
[0]);
7483 gen_jmp_im(s
->pc
- s
->cs_base
);
7486 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7487 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7488 gen_op_mov_reg_T0(ot
, rm
);
7492 case 0x106: /* clts */
7494 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7496 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7498 /* abort block because static cpu state changed */
7499 gen_jmp_im(s
->pc
- s
->cs_base
);
7503 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7504 case 0x1c3: /* MOVNTI reg, mem */
7505 if (!(s
->cpuid_features
& CPUID_SSE2
))
7507 ot
= s
->dflag
== 2 ? OT_QUAD
: OT_LONG
;
7508 modrm
= ldub_code(s
->pc
++);
7509 mod
= (modrm
>> 6) & 3;
7512 reg
= ((modrm
>> 3) & 7) | rex_r
;
7513 /* generate a generic store */
7514 gen_ldst_modrm(s
, modrm
, ot
, reg
, 1);
7517 modrm
= ldub_code(s
->pc
++);
7518 mod
= (modrm
>> 6) & 3;
7519 op
= (modrm
>> 3) & 7;
7521 case 0: /* fxsave */
7522 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7523 (s
->prefix
& PREFIX_LOCK
))
7525 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7526 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7529 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7530 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7531 gen_op_set_cc_op(s
->cc_op
);
7532 gen_jmp_im(pc_start
- s
->cs_base
);
7533 gen_helper_fxsave(cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7535 case 1: /* fxrstor */
7536 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7537 (s
->prefix
& PREFIX_LOCK
))
7539 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7540 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7543 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7544 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7545 gen_op_set_cc_op(s
->cc_op
);
7546 gen_jmp_im(pc_start
- s
->cs_base
);
7547 gen_helper_fxrstor(cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7549 case 2: /* ldmxcsr */
7550 case 3: /* stmxcsr */
7551 if (s
->flags
& HF_TS_MASK
) {
7552 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7555 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7558 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7560 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7561 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7563 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7564 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
7567 case 5: /* lfence */
7568 case 6: /* mfence */
7569 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE
))
7572 case 7: /* sfence / clflush */
7573 if ((modrm
& 0xc7) == 0xc0) {
7575 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7576 if (!(s
->cpuid_features
& CPUID_SSE
))
7580 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7582 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7589 case 0x10d: /* 3DNow! prefetch(w) */
7590 modrm
= ldub_code(s
->pc
++);
7591 mod
= (modrm
>> 6) & 3;
7594 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7595 /* ignore for now */
7597 case 0x1aa: /* rsm */
7598 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7599 if (!(s
->flags
& HF_SMM_MASK
))
7601 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
7602 gen_op_set_cc_op(s
->cc_op
);
7603 s
->cc_op
= CC_OP_DYNAMIC
;
7605 gen_jmp_im(s
->pc
- s
->cs_base
);
7609 case 0x1b8: /* SSE4.2 popcnt */
7610 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
7613 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
7616 modrm
= ldub_code(s
->pc
++);
7617 reg
= ((modrm
>> 3) & 7);
7619 if (s
->prefix
& PREFIX_DATA
)
7621 else if (s
->dflag
!= 2)
7626 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
7627 gen_helper_popcnt(cpu_T
[0], cpu_T
[0], tcg_const_i32(ot
));
7628 gen_op_mov_reg_T0(ot
, reg
);
7630 s
->cc_op
= CC_OP_EFLAGS
;
7632 case 0x10e ... 0x10f:
7633 /* 3DNow! instructions, ignore prefixes */
7634 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7635 case 0x110 ... 0x117:
7636 case 0x128 ... 0x12f:
7637 case 0x138 ... 0x13a:
7638 case 0x150 ... 0x179:
7639 case 0x17c ... 0x17f:
7641 case 0x1c4 ... 0x1c6:
7642 case 0x1d0 ... 0x1fe:
7643 gen_sse(s
, b
, pc_start
, rex_r
);
7648 /* lock generation */
7649 if (s
->prefix
& PREFIX_LOCK
)
7650 gen_helper_unlock();
7653 if (s
->prefix
& PREFIX_LOCK
)
7654 gen_helper_unlock();
7655 /* XXX: ensure that no lock was generated */
7656 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
7660 void optimize_flags_init(void)
7662 #if TCG_TARGET_REG_BITS == 32
7663 assert(sizeof(CCTable
) == (1 << 3));
7665 assert(sizeof(CCTable
) == (1 << 4));
7667 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
7668 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
7669 offsetof(CPUState
, cc_op
), "cc_op");
7670 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUState
, cc_src
),
7672 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUState
, cc_dst
),
7674 cpu_cc_tmp
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUState
, cc_tmp
),
7677 #ifdef TARGET_X86_64
7678 cpu_regs
[R_EAX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7679 offsetof(CPUState
, regs
[R_EAX
]), "rax");
7680 cpu_regs
[R_ECX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7681 offsetof(CPUState
, regs
[R_ECX
]), "rcx");
7682 cpu_regs
[R_EDX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7683 offsetof(CPUState
, regs
[R_EDX
]), "rdx");
7684 cpu_regs
[R_EBX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7685 offsetof(CPUState
, regs
[R_EBX
]), "rbx");
7686 cpu_regs
[R_ESP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7687 offsetof(CPUState
, regs
[R_ESP
]), "rsp");
7688 cpu_regs
[R_EBP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7689 offsetof(CPUState
, regs
[R_EBP
]), "rbp");
7690 cpu_regs
[R_ESI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7691 offsetof(CPUState
, regs
[R_ESI
]), "rsi");
7692 cpu_regs
[R_EDI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7693 offsetof(CPUState
, regs
[R_EDI
]), "rdi");
7694 cpu_regs
[8] = tcg_global_mem_new_i64(TCG_AREG0
,
7695 offsetof(CPUState
, regs
[8]), "r8");
7696 cpu_regs
[9] = tcg_global_mem_new_i64(TCG_AREG0
,
7697 offsetof(CPUState
, regs
[9]), "r9");
7698 cpu_regs
[10] = tcg_global_mem_new_i64(TCG_AREG0
,
7699 offsetof(CPUState
, regs
[10]), "r10");
7700 cpu_regs
[11] = tcg_global_mem_new_i64(TCG_AREG0
,
7701 offsetof(CPUState
, regs
[11]), "r11");
7702 cpu_regs
[12] = tcg_global_mem_new_i64(TCG_AREG0
,
7703 offsetof(CPUState
, regs
[12]), "r12");
7704 cpu_regs
[13] = tcg_global_mem_new_i64(TCG_AREG0
,
7705 offsetof(CPUState
, regs
[13]), "r13");
7706 cpu_regs
[14] = tcg_global_mem_new_i64(TCG_AREG0
,
7707 offsetof(CPUState
, regs
[14]), "r14");
7708 cpu_regs
[15] = tcg_global_mem_new_i64(TCG_AREG0
,
7709 offsetof(CPUState
, regs
[15]), "r15");
7711 cpu_regs
[R_EAX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7712 offsetof(CPUState
, regs
[R_EAX
]), "eax");
7713 cpu_regs
[R_ECX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7714 offsetof(CPUState
, regs
[R_ECX
]), "ecx");
7715 cpu_regs
[R_EDX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7716 offsetof(CPUState
, regs
[R_EDX
]), "edx");
7717 cpu_regs
[R_EBX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7718 offsetof(CPUState
, regs
[R_EBX
]), "ebx");
7719 cpu_regs
[R_ESP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7720 offsetof(CPUState
, regs
[R_ESP
]), "esp");
7721 cpu_regs
[R_EBP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7722 offsetof(CPUState
, regs
[R_EBP
]), "ebp");
7723 cpu_regs
[R_ESI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7724 offsetof(CPUState
, regs
[R_ESI
]), "esi");
7725 cpu_regs
[R_EDI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7726 offsetof(CPUState
, regs
[R_EDI
]), "edi");
7729 /* register helpers */
7730 #define GEN_HELPER 2
7734 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7735 basic block 'tb'. If search_pc is TRUE, also generate PC
7736 information for each intermediate instruction. */
7737 static inline void gen_intermediate_code_internal(CPUState
*env
,
7738 TranslationBlock
*tb
,
7741 DisasContext dc1
, *dc
= &dc1
;
7742 target_ulong pc_ptr
;
7743 uint16_t *gen_opc_end
;
7747 target_ulong pc_start
;
7748 target_ulong cs_base
;
7752 /* generate intermediate code */
7754 cs_base
= tb
->cs_base
;
7756 cflags
= tb
->cflags
;
7758 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
7759 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
7760 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
7761 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
7763 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
7764 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
7765 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
7766 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
7767 dc
->singlestep_enabled
= env
->singlestep_enabled
;
7768 dc
->cc_op
= CC_OP_DYNAMIC
;
7769 dc
->cs_base
= cs_base
;
7771 dc
->popl_esp_hack
= 0;
7772 /* select memory access functions */
7774 if (flags
& HF_SOFTMMU_MASK
) {
7776 dc
->mem_index
= 2 * 4;
7778 dc
->mem_index
= 1 * 4;
7780 dc
->cpuid_features
= env
->cpuid_features
;
7781 dc
->cpuid_ext_features
= env
->cpuid_ext_features
;
7782 dc
->cpuid_ext2_features
= env
->cpuid_ext2_features
;
7783 dc
->cpuid_ext3_features
= env
->cpuid_ext3_features
;
7784 #ifdef TARGET_X86_64
7785 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
7786 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
7789 dc
->jmp_opt
= !(dc
->tf
|| env
->singlestep_enabled
||
7790 (flags
& HF_INHIBIT_IRQ_MASK
)
7791 #ifndef CONFIG_SOFTMMU
7792 || (flags
& HF_SOFTMMU_MASK
)
7796 /* check addseg logic */
7797 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
7798 printf("ERROR addseg\n");
7801 cpu_T
[0] = tcg_temp_new();
7802 cpu_T
[1] = tcg_temp_new();
7803 cpu_A0
= tcg_temp_new();
7804 cpu_T3
= tcg_temp_new();
7806 cpu_tmp0
= tcg_temp_new();
7807 cpu_tmp1_i64
= tcg_temp_new_i64();
7808 cpu_tmp2_i32
= tcg_temp_new_i32();
7809 cpu_tmp3_i32
= tcg_temp_new_i32();
7810 cpu_tmp4
= tcg_temp_new();
7811 cpu_tmp5
= tcg_temp_new();
7812 cpu_ptr0
= tcg_temp_new_ptr();
7813 cpu_ptr1
= tcg_temp_new_ptr();
7815 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
7817 dc
->is_jmp
= DISAS_NEXT
;
7821 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7823 max_insns
= CF_COUNT_MASK
;
7827 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
7828 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
7829 if (bp
->pc
== pc_ptr
&&
7830 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
7831 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
7837 j
= gen_opc_ptr
- gen_opc_buf
;
7841 gen_opc_instr_start
[lj
++] = 0;
7843 gen_opc_pc
[lj
] = pc_ptr
;
7844 gen_opc_cc_op
[lj
] = dc
->cc_op
;
7845 gen_opc_instr_start
[lj
] = 1;
7846 gen_opc_icount
[lj
] = num_insns
;
7848 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
7851 pc_ptr
= disas_insn(dc
, pc_ptr
);
7853 /* stop translation if indicated */
7856 /* if single step mode, we generate only one instruction and
7857 generate an exception */
7858 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7859 the flag and abort the translation to give the irqs a
7860 change to be happen */
7861 if (dc
->tf
|| dc
->singlestep_enabled
||
7862 (flags
& HF_INHIBIT_IRQ_MASK
)) {
7863 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7867 /* if too long translation, stop generation too */
7868 if (gen_opc_ptr
>= gen_opc_end
||
7869 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
7870 num_insns
>= max_insns
) {
7871 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7876 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7881 if (tb
->cflags
& CF_LAST_IO
)
7883 gen_icount_end(tb
, num_insns
);
7884 *gen_opc_ptr
= INDEX_op_end
;
7885 /* we don't forget to fill the last values */
7887 j
= gen_opc_ptr
- gen_opc_buf
;
7890 gen_opc_instr_start
[lj
++] = 0;
7894 log_cpu_state_mask(CPU_LOG_TB_CPU
, env
, X86_DUMP_CCOP
);
7895 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
7897 qemu_log("----------------\n");
7898 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
7899 #ifdef TARGET_X86_64
7904 disas_flags
= !dc
->code32
;
7905 log_target_disas(pc_start
, pc_ptr
- pc_start
, disas_flags
);
7911 tb
->size
= pc_ptr
- pc_start
;
7912 tb
->icount
= num_insns
;
7916 void gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
7918 gen_intermediate_code_internal(env
, tb
, 0);
7921 void gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
7923 gen_intermediate_code_internal(env
, tb
, 1);
7926 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
7927 unsigned long searched_pc
, int pc_pos
, void *puc
)
7931 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
7933 qemu_log("RESTORE:\n");
7934 for(i
= 0;i
<= pc_pos
; i
++) {
7935 if (gen_opc_instr_start
[i
]) {
7936 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
, gen_opc_pc
[i
]);
7939 qemu_log("spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
7940 searched_pc
, pc_pos
, gen_opc_pc
[pc_pos
] - tb
->cs_base
,
7941 (uint32_t)tb
->cs_base
);
7944 env
->eip
= gen_opc_pc
[pc_pos
] - tb
->cs_base
;
7945 cc_op
= gen_opc_cc_op
[pc_pos
];
7946 if (cc_op
!= CC_OP_DYNAMIC
)