4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "pcie_regs.h"
33 # define PCIE_DPRINTF(fmt, ...) \
34 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
36 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
38 #define PCIE_DEV_PRINTF(dev, fmt, ...) \
39 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
42 /***************************************************************************
43 * pci express capability helper functions
45 int pcie_cap_init(PCIDevice
*dev
, uint8_t offset
, uint8_t type
, uint8_t port
)
50 assert(pci_is_express(dev
));
52 pos
= pci_add_capability(dev
, PCI_CAP_ID_EXP
, offset
,
57 dev
->exp
.exp_cap
= pos
;
58 exp_cap
= dev
->config
+ pos
;
60 /* capability register
61 interrupt message number defaults to 0 */
62 pci_set_word(exp_cap
+ PCI_EXP_FLAGS
,
63 ((type
<< PCI_EXP_FLAGS_TYPE_SHIFT
) & PCI_EXP_FLAGS_TYPE
) |
66 /* device capability register
68 * roll based error reporting bit must be set by all
69 * Functions conforming to the ECN, PCI Express Base
70 * Specification, Revision 1.1., or subsequent PCI Express Base
71 * Specification revisions.
73 pci_set_long(exp_cap
+ PCI_EXP_DEVCAP
, PCI_EXP_DEVCAP_RBER
);
75 pci_set_long(exp_cap
+ PCI_EXP_LNKCAP
,
76 (port
<< PCI_EXP_LNKCAP_PN_SHIFT
) |
77 PCI_EXP_LNKCAP_ASPMS_0S
|
81 pci_set_word(exp_cap
+ PCI_EXP_LNKSTA
,
82 PCI_EXP_LNK_MLW_1
| PCI_EXP_LNK_LS_25
);
84 pci_set_long(exp_cap
+ PCI_EXP_DEVCAP2
,
85 PCI_EXP_DEVCAP2_EFF
| PCI_EXP_DEVCAP2_EETLPP
);
87 pci_set_word(dev
->wmask
+ pos
, PCI_EXP_DEVCTL2_EETLPPB
);
91 void pcie_cap_exit(PCIDevice
*dev
)
93 pci_del_capability(dev
, PCI_CAP_ID_EXP
, PCI_EXP_VER2_SIZEOF
);
96 uint8_t pcie_cap_get_type(const PCIDevice
*dev
)
98 uint32_t pos
= dev
->exp
.exp_cap
;
100 return (pci_get_word(dev
->config
+ pos
+ PCI_EXP_FLAGS
) &
101 PCI_EXP_FLAGS_TYPE
) >> PCI_EXP_FLAGS_TYPE_SHIFT
;
105 /* pci express interrupt message number */
106 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
107 void pcie_cap_flags_set_vector(PCIDevice
*dev
, uint8_t vector
)
109 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
111 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_FLAGS
, PCI_EXP_FLAGS_IRQ
);
112 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_FLAGS
,
113 vector
<< PCI_EXP_FLAGS_IRQ_SHIFT
);
116 uint8_t pcie_cap_flags_get_vector(PCIDevice
*dev
)
118 return (pci_get_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_FLAGS
) &
119 PCI_EXP_FLAGS_IRQ
) >> PCI_EXP_FLAGS_IRQ_SHIFT
;
122 void pcie_cap_deverr_init(PCIDevice
*dev
)
124 uint32_t pos
= dev
->exp
.exp_cap
;
125 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_DEVCAP
,
126 PCI_EXP_DEVCAP_RBER
);
127 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL
,
128 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
129 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
130 pci_long_test_and_set_mask(dev
->w1cmask
+ pos
+ PCI_EXP_DEVSTA
,
131 PCI_EXP_DEVSTA_CED
| PCI_EXP_DEVSTA_NFED
|
132 PCI_EXP_DEVSTA_URD
| PCI_EXP_DEVSTA_URD
);
135 void pcie_cap_deverr_reset(PCIDevice
*dev
)
137 uint8_t *devctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
;
138 pci_long_test_and_clear_mask(devctl
,
139 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
140 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
143 static void hotplug_event_update_event_status(PCIDevice
*dev
)
145 uint32_t pos
= dev
->exp
.exp_cap
;
146 uint8_t *exp_cap
= dev
->config
+ pos
;
147 uint16_t sltctl
= pci_get_word(exp_cap
+ PCI_EXP_SLTCTL
);
148 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
150 dev
->exp
.hpev_notified
= (sltctl
& PCI_EXP_SLTCTL_HPIE
) &&
151 (sltsta
& sltctl
& PCI_EXP_HP_EV_SUPPORTED
);
154 static void hotplug_event_notify(PCIDevice
*dev
)
156 bool prev
= dev
->exp
.hpev_notified
;
158 hotplug_event_update_event_status(dev
);
160 if (prev
== dev
->exp
.hpev_notified
) {
164 /* Note: the logic above does not take into account whether interrupts
165 * are masked. The result is that interrupt will be sent when it is
166 * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
167 * The Port may optionally send an MSI when there are hot-plug events that
168 * occur while interrupt generation is disabled, and interrupt generation is
169 * subsequently enabled. */
170 if (!pci_msi_enabled(dev
)) {
171 qemu_set_irq(dev
->irq
[dev
->exp
.hpev_intx
], dev
->exp
.hpev_notified
);
172 } else if (dev
->exp
.hpev_notified
) {
173 pci_msi_notify(dev
, pcie_cap_flags_get_vector(dev
));
178 * A PCI Express Hot-Plug Event has occured, so update slot status register
179 * and notify OS of the event if necessary.
181 * 6.7.3 PCI Express Hot-Plug Events
182 * 6.7.3.4 Software Notification of Hot-Plug Events
184 static void pcie_cap_slot_event(PCIDevice
*dev
, PCIExpressHotPlugEvent event
)
186 /* Minor optimization: if nothing changed - no event is needed. */
187 if (pci_word_test_and_set_mask(dev
->config
+ dev
->exp
.exp_cap
+
188 PCI_EXP_SLTSTA
, event
)) {
191 hotplug_event_notify(dev
);
194 static int pcie_cap_slot_hotplug(DeviceState
*qdev
,
195 PCIDevice
*pci_dev
, PCIHotplugState state
)
197 PCIDevice
*d
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
198 uint8_t *exp_cap
= d
->config
+ d
->exp
.exp_cap
;
199 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
201 /* Don't send event when device is enabled during qemu machine creation:
202 * it is present on boot, no hotplug event is necessary. We do send an
203 * event when the device is disabled later. */
204 if (state
== PCI_COLDPLUG_ENABLED
) {
205 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
210 PCIE_DEV_PRINTF(pci_dev
, "hotplug state: %d\n", state
);
211 if (sltsta
& PCI_EXP_SLTSTA_EIS
) {
212 /* the slot is electromechanically locked.
213 * This error is propagated up to qdev and then to HMP/QMP.
218 /* TODO: multifunction hot-plug.
219 * Right now, only a device of function = 0 is allowed to be
220 * hot plugged/unplugged.
222 assert(PCI_FUNC(pci_dev
->devfn
) == 0);
224 if (state
== PCI_HOTPLUG_ENABLED
) {
225 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
227 pcie_cap_slot_event(d
, PCI_EXP_HP_EV_PDC
);
229 qdev_free(&pci_dev
->qdev
);
230 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTSTA
,
232 pcie_cap_slot_event(d
, PCI_EXP_HP_EV_PDC
);
237 /* pci express slot for pci express root/downstream port
238 PCI express capability slot registers */
239 void pcie_cap_slot_init(PCIDevice
*dev
, uint16_t slot
)
241 uint32_t pos
= dev
->exp
.exp_cap
;
243 pci_word_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_FLAGS
,
246 pci_long_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
247 ~PCI_EXP_SLTCAP_PSN
);
248 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
249 (slot
<< PCI_EXP_SLTCAP_PSN_SHIFT
) |
257 pci_word_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
260 pci_word_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
261 PCI_EXP_SLTCTL_PIC_OFF
|
262 PCI_EXP_SLTCTL_AIC_OFF
);
263 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
266 PCI_EXP_SLTCTL_HPIE
|
267 PCI_EXP_SLTCTL_CCIE
|
268 PCI_EXP_SLTCTL_PDCE
|
269 PCI_EXP_SLTCTL_ABPE
);
270 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
271 * make the bit writable here in order to detect 1b is written.
272 * pcie_cap_slot_write_config() test-and-clear the bit, so
273 * this bit always returns 0 to the guest.
275 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
278 pci_word_test_and_set_mask(dev
->w1cmask
+ pos
+ PCI_EXP_SLTSTA
,
279 PCI_EXP_HP_EV_SUPPORTED
);
281 dev
->exp
.hpev_notified
= false;
283 pci_bus_hotplug(pci_bridge_get_sec_bus(DO_UPCAST(PCIBridge
, dev
, dev
)),
284 pcie_cap_slot_hotplug
, &dev
->qdev
);
287 void pcie_cap_slot_reset(PCIDevice
*dev
)
289 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
291 PCIE_DEV_PRINTF(dev
, "reset\n");
293 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
297 PCI_EXP_SLTCTL_HPIE
|
298 PCI_EXP_SLTCTL_CCIE
|
299 PCI_EXP_SLTCTL_PDCE
|
300 PCI_EXP_SLTCTL_ABPE
);
301 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
,
302 PCI_EXP_SLTCTL_PIC_OFF
|
303 PCI_EXP_SLTCTL_AIC_OFF
);
305 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTSTA
,
306 PCI_EXP_SLTSTA_EIS
|/* on reset,
307 the lock is released */
312 hotplug_event_update_event_status(dev
);
315 void pcie_cap_slot_write_config(PCIDevice
*dev
,
316 uint32_t addr
, uint32_t val
, int len
)
318 uint32_t pos
= dev
->exp
.exp_cap
;
319 uint8_t *exp_cap
= dev
->config
+ pos
;
320 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
322 if (!ranges_overlap(addr
, len
, pos
+ PCI_EXP_SLTCTL
, 2)) {
326 if (pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
327 PCI_EXP_SLTCTL_EIC
)) {
328 sltsta
^= PCI_EXP_SLTSTA_EIS
; /* toggle PCI_EXP_SLTSTA_EIS bit */
329 pci_set_word(exp_cap
+ PCI_EXP_SLTSTA
, sltsta
);
330 PCIE_DEV_PRINTF(dev
, "PCI_EXP_SLTCTL_EIC: "
331 "sltsta -> 0x%02"PRIx16
"\n",
335 hotplug_event_notify(dev
);
338 * 6.7.3.2 Command Completed Events
340 * Software issues a command to a hot-plug capable Downstream Port by
341 * issuing a write transaction that targets any portion of the Port’s Slot
342 * Control register. A single write to the Slot Control register is
343 * considered to be a single command, even if the write affects more than
344 * one field in the Slot Control register. In response to this transaction,
345 * the Port must carry out the requested actions and then set the
346 * associated status field for the command completed event. */
348 /* Real hardware might take a while to complete requested command because
349 * physical movement would be involved like locking the electromechanical
350 * lock. However in our case, command is completed instantaneously above,
351 * so send a command completion event right now.
353 pcie_cap_slot_event(dev
, PCI_EXP_HP_EV_CCI
);
356 int pcie_cap_slot_post_load(void *opaque
, int version_id
)
358 PCIDevice
*dev
= opaque
;
359 hotplug_event_update_event_status(dev
);
363 void pcie_cap_slot_push_attention_button(PCIDevice
*dev
)
365 pcie_cap_slot_event(dev
, PCI_EXP_HP_EV_ABP
);
368 /* root control/capabilities/status. PME isn't emulated for now */
369 void pcie_cap_root_init(PCIDevice
*dev
)
371 pci_set_word(dev
->wmask
+ dev
->exp
.exp_cap
+ PCI_EXP_RTCTL
,
372 PCI_EXP_RTCTL_SECEE
| PCI_EXP_RTCTL_SENFEE
|
373 PCI_EXP_RTCTL_SEFEE
);
376 void pcie_cap_root_reset(PCIDevice
*dev
)
378 pci_set_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_RTCTL
, 0);
382 * TODO: implement FLR:
383 * Right now sets the bit which indicates FLR is supported.
385 /* function level reset(FLR) */
386 void pcie_cap_flr_init(PCIDevice
*dev
)
388 pci_long_test_and_set_mask(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCAP
,
391 /* Although reading BCR_FLR returns always 0,
392 * the bit is made writable here in order to detect the 1b is written
393 * pcie_cap_flr_write_config() test-and-clear the bit, so
394 * this bit always returns 0 to the guest.
396 pci_word_test_and_set_mask(dev
->wmask
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
,
397 PCI_EXP_DEVCTL_BCR_FLR
);
400 void pcie_cap_flr_write_config(PCIDevice
*dev
,
401 uint32_t addr
, uint32_t val
, int len
)
403 uint8_t *devctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
;
404 if (pci_word_test_and_clear_mask(devctl
, PCI_EXP_DEVCTL_BCR_FLR
)) {
405 /* TODO: implement FLR */
409 /* Alternative Routing-ID Interpretation (ARI) */
410 /* ari forwarding support for down stream port */
411 void pcie_cap_ari_init(PCIDevice
*dev
)
413 uint32_t pos
= dev
->exp
.exp_cap
;
414 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_DEVCAP2
,
415 PCI_EXP_DEVCAP2_ARI
);
416 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL2
,
417 PCI_EXP_DEVCTL2_ARI
);
420 void pcie_cap_ari_reset(PCIDevice
*dev
)
422 uint8_t *devctl2
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
;
423 pci_long_test_and_clear_mask(devctl2
, PCI_EXP_DEVCTL2_ARI
);
426 bool pcie_cap_is_ari_enabled(const PCIDevice
*dev
)
428 if (!pci_is_express(dev
)) {
431 if (!dev
->exp
.exp_cap
) {
435 return pci_get_long(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
) &
439 /**************************************************************************
440 * pci express extended capability allocation functions
441 * uint16_t ext_cap_id (16 bit)
442 * uint8_t cap_ver (4 bit)
443 * uint16_t cap_offset (12 bit)
444 * uint16_t ext_cap_size
447 static uint16_t pcie_find_capability_list(PCIDevice
*dev
, uint16_t cap_id
,
452 uint32_t header
= pci_get_long(dev
->config
+ PCI_CONFIG_SPACE_SIZE
);
455 /* no extended capability */
459 for (next
= PCI_CONFIG_SPACE_SIZE
; next
;
460 prev
= next
, next
= PCI_EXT_CAP_NEXT(header
)) {
462 assert(next
>= PCI_CONFIG_SPACE_SIZE
);
463 assert(next
<= PCIE_CONFIG_SPACE_SIZE
- 8);
465 header
= pci_get_long(dev
->config
+ next
);
466 if (PCI_EXT_CAP_ID(header
) == cap_id
) {
478 uint16_t pcie_find_capability(PCIDevice
*dev
, uint16_t cap_id
)
480 return pcie_find_capability_list(dev
, cap_id
, NULL
);
483 static void pcie_ext_cap_set_next(PCIDevice
*dev
, uint16_t pos
, uint16_t next
)
485 uint16_t header
= pci_get_long(dev
->config
+ pos
);
486 assert(!(next
& (PCI_EXT_CAP_ALIGN
- 1)));
487 header
= (header
& ~PCI_EXT_CAP_NEXT_MASK
) |
488 ((next
<< PCI_EXT_CAP_NEXT_SHIFT
) & PCI_EXT_CAP_NEXT_MASK
);
489 pci_set_long(dev
->config
+ pos
, header
);
493 * caller must supply valid (offset, size) * such that the range shouldn't
494 * overlap with other capability or other registers.
495 * This function doesn't check it.
497 void pcie_add_capability(PCIDevice
*dev
,
498 uint16_t cap_id
, uint8_t cap_ver
,
499 uint16_t offset
, uint16_t size
)
504 assert(offset
>= PCI_CONFIG_SPACE_SIZE
);
505 assert(offset
< offset
+ size
);
506 assert(offset
+ size
< PCIE_CONFIG_SPACE_SIZE
);
508 assert(pci_is_express(dev
));
510 if (offset
== PCI_CONFIG_SPACE_SIZE
) {
511 header
= pci_get_long(dev
->config
+ offset
);
512 next
= PCI_EXT_CAP_NEXT(header
);
516 /* 0 is reserved cap id. use internally to find the last capability
517 in the linked list */
518 next
= pcie_find_capability_list(dev
, 0, &prev
);
520 assert(prev
>= PCI_CONFIG_SPACE_SIZE
);
522 pcie_ext_cap_set_next(dev
, prev
, offset
);
524 pci_set_long(dev
->config
+ offset
, PCI_EXT_CAP(cap_id
, cap_ver
, next
));
526 /* Make capability read-only by default */
527 memset(dev
->wmask
+ offset
, 0, size
);
528 memset(dev
->w1cmask
+ offset
, 0, size
);
529 /* Check capability by default */
530 memset(dev
->cmask
+ offset
, 0xFF, size
);
533 /**************************************************************************
534 * pci express extended capability helper functions
538 void pcie_ari_init(PCIDevice
*dev
, uint16_t offset
, uint16_t nextfn
)
540 pcie_add_capability(dev
, PCI_EXT_CAP_ID_ARI
, PCI_ARI_VER
,
541 offset
, PCI_ARI_SIZEOF
);
542 pci_set_long(dev
->config
+ offset
+ PCI_ARI_CAP
, PCI_ARI_CAP_NFN(nextfn
));