target-s390x/helper.c

   1 /*
   2  *  S/390 helpers
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *  Copyright (c) 2011 Alexander Graf
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <stdio.h>
  22 #include <stdlib.h>
  23 #include <string.h>
  24
  25 #include "cpu.h"
  26 #include "exec-all.h"
  27 #include "gdbstub.h"
  28 #include "qemu-common.h"
  29 #include "qemu-timer.h"
  30
  31 //#define DEBUG_S390
  32 //#define DEBUG_S390_PTE
  33 //#define DEBUG_S390_STDOUT
  34
  35 #ifdef DEBUG_S390
  36 #ifdef DEBUG_S390_STDOUT
  37 #define DPRINTF(fmt, ...) \
  38     do { fprintf(stderr, fmt, ## __VA_ARGS__); \
  39          qemu_log(fmt, ##__VA_ARGS__); } while (0)
  40 #else
  41 #define DPRINTF(fmt, ...) \
  42     do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
  43 #endif
  44 #else
  45 #define DPRINTF(fmt, ...) \
  46     do { } while (0)
  47 #endif
  48
  49 #ifdef DEBUG_S390_PTE
  50 #define PTE_DPRINTF DPRINTF
  51 #else
  52 #define PTE_DPRINTF(fmt, ...) \
  53     do { } while (0)
  54 #endif
  55
  56 #ifndef CONFIG_USER_ONLY
  57 static void s390x_tod_timer(void *opaque)
  58 {
  59     CPUState *env = opaque;
  60
  61     env->pending_int |= INTERRUPT_TOD;
  62     cpu_interrupt(env, CPU_INTERRUPT_HARD);
  63 }
  64
  65 static void s390x_cpu_timer(void *opaque)
  66 {
  67     CPUState *env = opaque;
  68
  69     env->pending_int |= INTERRUPT_CPUTIMER;
  70     cpu_interrupt(env, CPU_INTERRUPT_HARD);
  71 }
  72 #endif
  73
  74 CPUS390XState *cpu_s390x_init(const char *cpu_model)
  75 {
  76     CPUS390XState *env;
  77 #if !defined (CONFIG_USER_ONLY)
  78     struct tm tm;
  79 #endif
  80     static int inited = 0;
  81     static int cpu_num = 0;
  82
  83     env = qemu_mallocz(sizeof(CPUS390XState));
  84     cpu_exec_init(env);
  85     if (!inited) {
  86         inited = 1;
  87         s390x_translate_init();
  88     }
  89
  90 #if !defined(CONFIG_USER_ONLY)
  91     qemu_get_timedate(&tm, 0);
  92     env->tod_offset = TOD_UNIX_EPOCH +
  93                       (time2tod(mktimegm(&tm)) * 1000000000ULL);
  94     env->tod_basetime = 0;
  95     env->tod_timer = qemu_new_timer_ns(vm_clock, s390x_tod_timer, env);
  96     env->cpu_timer = qemu_new_timer_ns(vm_clock, s390x_cpu_timer, env);
  97 #endif
  98     env->cpu_model_str = cpu_model;
  99     env->cpu_num = cpu_num++;
 100     env->ext_index = -1;
 101     cpu_reset(env);
 102     qemu_init_vcpu(env);
 103     return env;
 104 }
 105
 106 #if defined(CONFIG_USER_ONLY)
 107
 108 void do_interrupt (CPUState *env)
 109 {
 110     env->exception_index = -1;
 111 }
 112
 113 int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 114                               int mmu_idx, int is_softmmu)
 115 {
 116     /* fprintf(stderr,"%s: address 0x%lx rw %d mmu_idx %d is_softmmu %d\n",
 117             __FUNCTION__, address, rw, mmu_idx, is_softmmu); */
 118     env->exception_index = EXCP_ADDR;
 119     env->__excp_addr = address; /* FIXME: find out how this works on a real machine */
 120     return 1;
 121 }
 122
 123 #endif /* CONFIG_USER_ONLY */
 124
 125 void cpu_reset(CPUS390XState *env)
 126 {
 127     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
 128         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
 129         log_cpu_state(env, 0);
 130     }
 131
 132     memset(env, 0, offsetof(CPUS390XState, breakpoints));
 133     /* FIXME: reset vector? */
 134     tlb_flush(env, 1);
 135 }
 136
 137 #ifndef CONFIG_USER_ONLY
 138
 139 /* Ensure to exit the TB after this call! */
 140 static void trigger_pgm_exception(CPUState *env, uint32_t code, uint32_t ilc)
 141 {
 142     env->exception_index = EXCP_PGM;
 143     env->int_pgm_code = code;
 144     env->int_pgm_ilc = ilc;
 145 }
 146
 147 static int trans_bits(CPUState *env, uint64_t mode)
 148 {
 149     int bits = 0;
 150
 151     switch (mode) {
 152     case PSW_ASC_PRIMARY:
 153         bits = 1;
 154         break;
 155     case PSW_ASC_SECONDARY:
 156         bits = 2;
 157         break;
 158     case PSW_ASC_HOME:
 159         bits = 3;
 160         break;
 161     default:
 162         cpu_abort(env, "unknown asc mode\n");
 163         break;
 164     }
 165
 166     return bits;
 167 }
 168
 169 static void trigger_prot_fault(CPUState *env, target_ulong vaddr, uint64_t mode)
 170 {
 171     int ilc = ILC_LATER_INC_2;
 172     int bits = trans_bits(env, mode) | 4;
 173
 174     DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __FUNCTION__, vaddr, bits);
 175
 176     stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
 177     trigger_pgm_exception(env, PGM_PROTECTION, ilc);
 178 }
 179
 180 static void trigger_page_fault(CPUState *env, target_ulong vaddr, uint32_t type,
 181                                uint64_t asc, int rw)
 182 {
 183     int ilc = ILC_LATER;
 184     int bits = trans_bits(env, asc);
 185
 186     if (rw == 2) {
 187         /* code has is undefined ilc */
 188         ilc = 2;
 189     }
 190
 191     DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __FUNCTION__, vaddr, bits);
 192
 193     stq_phys(env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
 194     trigger_pgm_exception(env, type, ilc);
 195 }
 196
 197 static int mmu_translate_asce(CPUState *env, target_ulong vaddr, uint64_t asc,
 198                               uint64_t asce, int level, target_ulong *raddr,
 199                               int *flags, int rw)
 200 {
 201     uint64_t offs = 0;
 202     uint64_t origin;
 203     uint64_t new_asce;
 204
 205     PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __FUNCTION__, asce);
 206
 207     if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
 208         ((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
 209         /* XXX different regions have different faults */
 210         DPRINTF("%s: invalid region\n", __FUNCTION__);
 211         trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
 212         return -1;
 213     }
 214
 215     if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) {
 216         trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 217         return -1;
 218     }
 219
 220     if (asce & _ASCE_REAL_SPACE) {
 221         /* direct mapping */
 222
 223         *raddr = vaddr;
 224         return 0;
 225     }
 226
 227     origin = asce & _ASCE_ORIGIN;
 228
 229     switch (level) {
 230     case _ASCE_TYPE_REGION1 + 4:
 231         offs = (vaddr >> 50) & 0x3ff8;
 232         break;
 233     case _ASCE_TYPE_REGION1:
 234         offs = (vaddr >> 39) & 0x3ff8;
 235         break;
 236     case _ASCE_TYPE_REGION2:
 237         offs = (vaddr >> 28) & 0x3ff8;
 238         break;
 239     case _ASCE_TYPE_REGION3:
 240         offs = (vaddr >> 17) & 0x3ff8;
 241         break;
 242     case _ASCE_TYPE_SEGMENT:
 243         offs = (vaddr >> 9) & 0x07f8;
 244         origin = asce & _SEGMENT_ENTRY_ORIGIN;
 245         break;
 246     }
 247
 248     /* XXX region protection flags */
 249     /* *flags &= ~PAGE_WRITE */
 250
 251     new_asce = ldq_phys(origin + offs);
 252     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 253                 __FUNCTION__, origin, offs, new_asce);
 254
 255     if (level != _ASCE_TYPE_SEGMENT) {
 256         /* yet another region */
 257         return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr,
 258                                   flags, rw);
 259     }
 260
 261     /* PTE */
 262     if (new_asce & _PAGE_INVALID) {
 263         DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __FUNCTION__, new_asce);
 264         trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
 265         return -1;
 266     }
 267
 268     if (new_asce & _PAGE_RO) {
 269         *flags &= ~PAGE_WRITE;
 270     }
 271
 272     *raddr = new_asce & _ASCE_ORIGIN;
 273
 274     PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __FUNCTION__, new_asce);
 275
 276     return 0;
 277 }
 278
 279 static int mmu_translate_asc(CPUState *env, target_ulong vaddr, uint64_t asc,
 280                              target_ulong *raddr, int *flags, int rw)
 281 {
 282     uint64_t asce = 0;
 283     int level, new_level;
 284     int r;
 285
 286     switch (asc) {
 287     case PSW_ASC_PRIMARY:
 288         PTE_DPRINTF("%s: asc=primary\n", __FUNCTION__);
 289         asce = env->cregs[1];
 290         break;
 291     case PSW_ASC_SECONDARY:
 292         PTE_DPRINTF("%s: asc=secondary\n", __FUNCTION__);
 293         asce = env->cregs[7];
 294         break;
 295     case PSW_ASC_HOME:
 296         PTE_DPRINTF("%s: asc=home\n", __FUNCTION__);
 297         asce = env->cregs[13];
 298         break;
 299     }
 300
 301     switch (asce & _ASCE_TYPE_MASK) {
 302     case _ASCE_TYPE_REGION1:
 303         break;
 304     case _ASCE_TYPE_REGION2:
 305         if (vaddr & 0xffe0000000000000ULL) {
 306             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 307                         " 0xffe0000000000000ULL\n", __FUNCTION__,
 308                         vaddr);
 309             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 310             return -1;
 311         }
 312         break;
 313     case _ASCE_TYPE_REGION3:
 314         if (vaddr & 0xfffffc0000000000ULL) {
 315             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 316                         " 0xfffffc0000000000ULL\n", __FUNCTION__,
 317                         vaddr);
 318             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 319             return -1;
 320         }
 321         break;
 322     case _ASCE_TYPE_SEGMENT:
 323         if (vaddr & 0xffffffff80000000ULL) {
 324             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 325                         " 0xffffffff80000000ULL\n", __FUNCTION__,
 326                         vaddr);
 327             trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
 328             return -1;
 329         }
 330         break;
 331     }
 332
 333     /* fake level above current */
 334     level = asce & _ASCE_TYPE_MASK;
 335     new_level = level + 4;
 336     asce = (asce & ~_ASCE_TYPE_MASK) | (new_level & _ASCE_TYPE_MASK);
 337
 338     r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw);
 339
 340     if ((rw == 1) && !(*flags & PAGE_WRITE)) {
 341         trigger_prot_fault(env, vaddr, asc);
 342         return -1;
 343     }
 344
 345     return r;
 346 }
 347
 348 int mmu_translate(CPUState *env, target_ulong vaddr, int rw, uint64_t asc,
 349                   target_ulong *raddr, int *flags)
 350 {
 351     int r = -1;
 352
 353     *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 354     vaddr &= TARGET_PAGE_MASK;
 355
 356     if (!(env->psw.mask & PSW_MASK_DAT)) {
 357         *raddr = vaddr;
 358         r = 0;
 359         goto out;
 360     }
 361
 362     switch (asc) {
 363     case PSW_ASC_PRIMARY:
 364     case PSW_ASC_HOME:
 365         r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw);
 366         break;
 367     case PSW_ASC_SECONDARY:
 368         /*
 369          * Instruction: Primary
 370          * Data: Secondary
 371          */
 372         if (rw == 2) {
 373             r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
 374                                   rw);
 375             *flags &= ~(PAGE_READ | PAGE_WRITE);
 376         } else {
 377             r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
 378                                   rw);
 379             *flags &= ~(PAGE_EXEC);
 380         }
 381         break;
 382     case PSW_ASC_ACCREG:
 383     default:
 384         hw_error("guest switched to unknown asc mode\n");
 385         break;
 386     }
 387
 388 out:
 389     /* Convert real address -> absolute address */
 390     if (*raddr < 0x2000) {
 391         *raddr = *raddr + env->psa;
 392     }
 393
 394     return r;
 395 }
 396
 397 int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong _vaddr, int rw,
 398                                 int mmu_idx, int is_softmmu)
 399 {
 400     uint64_t asc = env->psw.mask & PSW_MASK_ASC;
 401     target_ulong vaddr, raddr;
 402     int prot;
 403
 404     DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d is_softmmu %d\n",
 405             __FUNCTION__, _vaddr, rw, mmu_idx, is_softmmu);
 406
 407     _vaddr &= TARGET_PAGE_MASK;
 408     vaddr = _vaddr;
 409
 410     /* 31-Bit mode */
 411     if (!(env->psw.mask & PSW_MASK_64)) {
 412         vaddr &= 0x7fffffff;
 413     }
 414
 415     if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot)) {
 416         /* Translation ended in exception */
 417         return 1;
 418     }
 419
 420     /* check out of RAM access */
 421     if (raddr > (ram_size + virtio_size)) {
 422         DPRINTF("%s: aaddr %" PRIx64 " > ram_size %" PRIx64 "\n", __FUNCTION__,
 423                 (uint64_t)aaddr, (uint64_t)ram_size);
 424         trigger_pgm_exception(env, PGM_ADDRESSING, ILC_LATER);
 425         return 1;
 426     }
 427
 428     DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __FUNCTION__,
 429             (uint64_t)vaddr, (uint64_t)raddr, prot);
 430
 431     tlb_set_page(env, _vaddr, raddr, prot,
 432                  mmu_idx, TARGET_PAGE_SIZE);
 433
 434     return 0;
 435 }
 436
 437 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong vaddr)
 438 {
 439     target_ulong raddr;
 440     int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 441     int old_exc = env->exception_index;
 442     uint64_t asc = env->psw.mask & PSW_MASK_ASC;
 443
 444     /* 31-Bit mode */
 445     if (!(env->psw.mask & PSW_MASK_64)) {
 446         vaddr &= 0x7fffffff;
 447     }
 448
 449     mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
 450     env->exception_index = old_exc;
 451
 452     return raddr;
 453 }
 454
 455 void load_psw(CPUState *env, uint64_t mask, uint64_t addr)
 456 {
 457     if (mask & PSW_MASK_WAIT) {
 458         env->halted = 1;
 459         env->exception_index = EXCP_HLT;
 460         if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) {
 461             /* XXX disabled wait state - CPU is dead */
 462         }
 463     }
 464
 465     env->psw.addr = addr;
 466     env->psw.mask = mask;
 467     env->cc_op = (mask >> 13) & 3;
 468 }
 469
 470 static uint64_t get_psw_mask(CPUState *env)
 471 {
 472     uint64_t r = env->psw.mask;
 473
 474     env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
 475
 476     r &= ~(3ULL << 13);
 477     assert(!(env->cc_op & ~3));
 478     r |= env->cc_op << 13;
 479
 480     return r;
 481 }
 482
 483 static void do_svc_interrupt(CPUState *env)
 484 {
 485     uint64_t mask, addr;
 486     LowCore *lowcore;
 487     target_phys_addr_t len = TARGET_PAGE_SIZE;
 488
 489     lowcore = cpu_physical_memory_map(env->psa, &len, 1);
 490
 491     lowcore->svc_code = cpu_to_be16(env->int_svc_code);
 492     lowcore->svc_ilc = cpu_to_be16(env->int_svc_ilc);
 493     lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 494     lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + (env->int_svc_ilc));
 495     mask = be64_to_cpu(lowcore->svc_new_psw.mask);
 496     addr = be64_to_cpu(lowcore->svc_new_psw.addr);
 497
 498     cpu_physical_memory_unmap(lowcore, len, 1, len);
 499
 500     load_psw(env, mask, addr);
 501 }
 502
 503 static void do_program_interrupt(CPUState *env)
 504 {
 505     uint64_t mask, addr;
 506     LowCore *lowcore;
 507     target_phys_addr_t len = TARGET_PAGE_SIZE;
 508     int ilc = env->int_pgm_ilc;
 509
 510     switch (ilc) {
 511     case ILC_LATER:
 512         ilc = get_ilc(ldub_code(env->psw.addr));
 513         break;
 514     case ILC_LATER_INC:
 515         ilc = get_ilc(ldub_code(env->psw.addr));
 516         env->psw.addr += ilc * 2;
 517         break;
 518     case ILC_LATER_INC_2:
 519         ilc = get_ilc(ldub_code(env->psw.addr)) * 2;
 520         env->psw.addr += ilc;
 521         break;
 522     }
 523
 524     qemu_log("%s: code=0x%x ilc=%d\n", __FUNCTION__, env->int_pgm_code, ilc);
 525
 526     lowcore = cpu_physical_memory_map(env->psa, &len, 1);
 527
 528     lowcore->pgm_ilc = cpu_to_be16(ilc);
 529     lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
 530     lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 531     lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
 532     mask = be64_to_cpu(lowcore->program_new_psw.mask);
 533     addr = be64_to_cpu(lowcore->program_new_psw.addr);
 534
 535     cpu_physical_memory_unmap(lowcore, len, 1, len);
 536
 537     DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __FUNCTION__,
 538             env->int_pgm_code, ilc, env->psw.mask,
 539             env->psw.addr);
 540
 541     load_psw(env, mask, addr);
 542 }
 543
 544 #define VIRTIO_SUBCODE_64 0x0D00
 545
 546 static void do_ext_interrupt(CPUState *env)
 547 {
 548     uint64_t mask, addr;
 549     LowCore *lowcore;
 550     target_phys_addr_t len = TARGET_PAGE_SIZE;
 551     ExtQueue *q;
 552
 553     if (!(env->psw.mask & PSW_MASK_EXT)) {
 554         cpu_abort(env, "Ext int w/o ext mask\n");
 555     }
 556
 557     if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) {
 558         cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
 559     }
 560
 561     q = &env->ext_queue[env->ext_index];
 562     lowcore = cpu_physical_memory_map(env->psa, &len, 1);
 563
 564     lowcore->ext_int_code = cpu_to_be16(q->code);
 565     lowcore->ext_params = cpu_to_be32(q->param);
 566     lowcore->ext_params2 = cpu_to_be64(q->param64);
 567     lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 568     lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
 569     lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64);
 570     mask = be64_to_cpu(lowcore->external_new_psw.mask);
 571     addr = be64_to_cpu(lowcore->external_new_psw.addr);
 572
 573     cpu_physical_memory_unmap(lowcore, len, 1, len);
 574
 575     env->ext_index--;
 576     if (env->ext_index == -1) {
 577         env->pending_int &= ~INTERRUPT_EXT;
 578     }
 579
 580     DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __FUNCTION__,
 581             env->psw.mask, env->psw.addr);
 582
 583     load_psw(env, mask, addr);
 584 }
 585
 586 void do_interrupt (CPUState *env)
 587 {
 588     qemu_log("%s: %d at pc=%" PRIx64 "\n", __FUNCTION__, env->exception_index,
 589              env->psw.addr);
 590
 591     /* handle external interrupts */
 592     if ((env->psw.mask & PSW_MASK_EXT) &&
 593         env->exception_index == -1) {
 594         if (env->pending_int & INTERRUPT_EXT) {
 595             /* code is already in env */
 596             env->exception_index = EXCP_EXT;
 597         } else if (env->pending_int & INTERRUPT_TOD) {
 598             cpu_inject_ext(env, 0x1004, 0, 0);
 599             env->exception_index = EXCP_EXT;
 600             env->pending_int &= ~INTERRUPT_EXT;
 601             env->pending_int &= ~INTERRUPT_TOD;
 602         } else if (env->pending_int & INTERRUPT_CPUTIMER) {
 603             cpu_inject_ext(env, 0x1005, 0, 0);
 604             env->exception_index = EXCP_EXT;
 605             env->pending_int &= ~INTERRUPT_EXT;
 606             env->pending_int &= ~INTERRUPT_TOD;
 607         }
 608     }
 609
 610     switch (env->exception_index) {
 611     case EXCP_PGM:
 612         do_program_interrupt(env);
 613         break;
 614     case EXCP_SVC:
 615         do_svc_interrupt(env);
 616         break;
 617     case EXCP_EXT:
 618         do_ext_interrupt(env);
 619         break;
 620     }
 621     env->exception_index = -1;
 622
 623     if (!env->pending_int) {
 624         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 625     }
 626 }
 627
 628 #endif /* CONFIG_USER_ONLY */