hw/mips_r4k.c

   1 /*
   2  * QEMU/MIPS pseudo-board
   3  *
   4  * emulates a simple machine with ISA-like bus.
   5  * ISA IO space mapped to the 0x14000000 (PHYS) and
   6  * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
   7  * All peripherial devices are attached to this "bus" with
   8  * the standard PC ISA addresses.
   9 */
  10 #include "hw.h"
  11 #include "mips.h"
  12 #include "pc.h"
  13 #include "isa.h"
  14 #include "net.h"
  15 #include "sysemu.h"
  16 #include "boards.h"
  17
  18 #ifdef TARGET_WORDS_BIGENDIAN
  19 #define BIOS_FILENAME "mips_bios.bin"
  20 #else
  21 #define BIOS_FILENAME "mipsel_bios.bin"
  22 #endif
  23
  24 #define PHYS_TO_VIRT(x) ((x) | ~(target_ulong)0x7fffffff)
  25
  26 #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
  27
  28 #define MAX_IDE_BUS 2
  29
  30 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  31 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  32 static const int ide_irq[2] = { 14, 15 };
  33
  34 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
  35 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
  36
  37 extern FILE *logfile;
  38
  39 static PITState *pit; /* PIT i8254 */
  40
  41 /* i8254 PIT is attached to the IRQ0 at PIC i8259 */
  42
  43 static struct _loaderparams {
  44     int ram_size;
  45     const char *kernel_filename;
  46     const char *kernel_cmdline;
  47     const char *initrd_filename;
  48 } loaderparams;
  49
  50 static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
  51                               uint32_t val)
  52 {
  53     if ((addr & 0xffff) == 0 && val == 42)
  54         qemu_system_reset_request ();
  55     else if ((addr & 0xffff) == 4 && val == 42)
  56         qemu_system_shutdown_request ();
  57 }
  58
  59 static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
  60 {
  61     return 0;
  62 }
  63
  64 static CPUWriteMemoryFunc *mips_qemu_write[] = {
  65     &mips_qemu_writel,
  66     &mips_qemu_writel,
  67     &mips_qemu_writel,
  68 };
  69
  70 static CPUReadMemoryFunc *mips_qemu_read[] = {
  71     &mips_qemu_readl,
  72     &mips_qemu_readl,
  73     &mips_qemu_readl,
  74 };
  75
  76 static int mips_qemu_iomemtype = 0;
  77
  78 static void load_kernel (CPUState *env)
  79 {
  80     int64_t entry, kernel_low, kernel_high;
  81     long kernel_size, initrd_size;
  82     ram_addr_t initrd_offset;
  83
  84     kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND,
  85                            &entry, &kernel_low, &kernel_high);
  86     if (kernel_size >= 0) {
  87         if ((entry & ~0x7fffffffULL) == 0x80000000)
  88             entry = (int32_t)entry;
  89         env->PC[env->current_tc] = entry;
  90     } else {
  91         fprintf(stderr, "qemu: could not load kernel '%s'\n",
  92                 loaderparams.kernel_filename);
  93         exit(1);
  94     }
  95
  96     /* load initrd */
  97     initrd_size = 0;
  98     initrd_offset = 0;
  99     if (loaderparams.initrd_filename) {
 100         initrd_size = get_image_size (loaderparams.initrd_filename);
 101         if (initrd_size > 0) {
 102             initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
 103             if (initrd_offset + initrd_size > ram_size) {
 104                 fprintf(stderr,
 105                         "qemu: memory too small for initial ram disk '%s'\n",
 106                         loaderparams.initrd_filename);
 107                 exit(1);
 108             }
 109             initrd_size = load_image(loaderparams.initrd_filename,
 110                                      phys_ram_base + initrd_offset);
 111         }
 112         if (initrd_size == (target_ulong) -1) {
 113             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 114                     loaderparams.initrd_filename);
 115             exit(1);
 116         }
 117     }
 118
 119     /* Store command line.  */
 120     if (initrd_size > 0) {
 121         int ret;
 122         ret = sprintf(phys_ram_base + (16 << 20) - 256,
 123                       "rd_start=0x" TARGET_FMT_lx " rd_size=%li ",
 124                       PHYS_TO_VIRT((uint32_t)initrd_offset),
 125                       initrd_size);
 126         strcpy (phys_ram_base + (16 << 20) - 256 + ret,
 127                 loaderparams.kernel_cmdline);
 128     }
 129     else {
 130         strcpy (phys_ram_base + (16 << 20) - 256,
 131                 loaderparams.kernel_cmdline);
 132     }
 133
 134     *(int32_t *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
 135     *(int32_t *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
 136 }
 137
 138 static void main_cpu_reset(void *opaque)
 139 {
 140     CPUState *env = opaque;
 141     cpu_reset(env);
 142
 143     if (loaderparams.kernel_filename)
 144         load_kernel (env);
 145 }
 146
 147 static
 148 void mips_r4k_init (int ram_size, int vga_ram_size,
 149                     const char *boot_device, DisplayState *ds,
 150                     const char *kernel_filename, const char *kernel_cmdline,
 151                     const char *initrd_filename, const char *cpu_model)
 152 {
 153     char buf[1024];
 154     unsigned long bios_offset;
 155     int bios_size;
 156     CPUState *env;
 157     RTCState *rtc_state;
 158     int i;
 159     qemu_irq *i8259;
 160     int index;
 161     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 162
 163     /* init CPUs */
 164     if (cpu_model == NULL) {
 165 #ifdef TARGET_MIPS64
 166         cpu_model = "R4000";
 167 #else
 168         cpu_model = "24Kf";
 169 #endif
 170     }
 171     env = cpu_init(cpu_model);
 172     if (!env) {
 173         fprintf(stderr, "Unable to find CPU definition\n");
 174         exit(1);
 175     }
 176     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 177     qemu_register_reset(main_cpu_reset, env);
 178
 179     /* allocate RAM */
 180     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 181
 182     if (!mips_qemu_iomemtype) {
 183         mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
 184                                                      mips_qemu_write, NULL);
 185     }
 186     cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
 187
 188     /* Try to load a BIOS image. If this fails, we continue regardless,
 189        but initialize the hardware ourselves. When a kernel gets
 190        preloaded we also initialize the hardware, since the BIOS wasn't
 191        run. */
 192     bios_offset = ram_size + vga_ram_size;
 193     if (bios_name == NULL)
 194         bios_name = BIOS_FILENAME;
 195     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 196     bios_size = load_image(buf, phys_ram_base + bios_offset);
 197     if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
 198         cpu_register_physical_memory(0x1fc00000,
 199                                      BIOS_SIZE, bios_offset | IO_MEM_ROM);
 200     } else {
 201         /* not fatal */
 202         fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
 203                 buf);
 204     }
 205
 206     if (kernel_filename) {
 207         loaderparams.ram_size = ram_size;
 208         loaderparams.kernel_filename = kernel_filename;
 209         loaderparams.kernel_cmdline = kernel_cmdline;
 210         loaderparams.initrd_filename = initrd_filename;
 211         load_kernel (env);
 212     }
 213
 214     /* Init CPU internal devices */
 215     cpu_mips_irq_init_cpu(env);
 216     cpu_mips_clock_init(env);
 217     cpu_mips_irqctrl_init();
 218
 219     /* The PIC is attached to the MIPS CPU INT0 pin */
 220     i8259 = i8259_init(env->irq[2]);
 221
 222     rtc_state = rtc_init(0x70, i8259[8]);
 223
 224     /* Register 64 KB of ISA IO space at 0x14000000 */
 225     isa_mmio_init(0x14000000, 0x00010000);
 226     isa_mem_base = 0x10000000;
 227
 228     pit = pit_init(0x40, i8259[0]);
 229
 230     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 231         if (serial_hds[i]) {
 232             serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]);
 233         }
 234     }
 235
 236     isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
 237                  vga_ram_size);
 238
 239     if (nd_table[0].vlan) {
 240         if (nd_table[0].model == NULL
 241             || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
 242             isa_ne2000_init(0x300, i8259[9], &nd_table[0]);
 243         } else if (strcmp(nd_table[0].model, "?") == 0) {
 244             fprintf(stderr, "qemu: Supported NICs: ne2k_isa\n");
 245             exit (1);
 246         } else {
 247             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 248             exit (1);
 249         }
 250     }
 251
 252     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 253         fprintf(stderr, "qemu: too many IDE bus\n");
 254         exit(1);
 255     }
 256
 257     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 258         index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 259         if (index != -1)
 260             hd[i] = drives_table[index].bdrv;
 261         else
 262             hd[i] = NULL;
 263     }
 264
 265     for(i = 0; i < MAX_IDE_BUS; i++)
 266         isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
 267                      hd[MAX_IDE_DEVS * i],
 268                      hd[MAX_IDE_DEVS * i + 1]);
 269
 270     i8042_init(i8259[1], i8259[12], 0x60);
 271 }
 272
 273 QEMUMachine mips_machine = {
 274     "mips",
 275     "mips r4k platform",
 276     mips_r4k_init,
 277 };