hw/wdt_i6300esb.c

   1 /*
   2  * Virtual hardware watchdog.
   3  *
   4  * Copyright (C) 2009 Red Hat Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  * By Richard W.M. Jones (rjones@redhat.com).
  20  */
  21
  22 #include <inttypes.h>
  23
  24 #include "qemu-common.h"
  25 #include "qemu-timer.h"
  26 #include "watchdog.h"
  27 #include "hw.h"
  28 #include "pci.h"
  29
  30 /*#define I6300ESB_DEBUG 1*/
  31
  32 #ifdef I6300ESB_DEBUG
  33 #define i6300esb_debug(fs,...) \
  34     fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
  35 #else
  36 #define i6300esb_debug(fs,...)
  37 #endif
  38
  39 /* PCI configuration registers */
  40 #define ESB_CONFIG_REG  0x60            /* Config register                   */
  41 #define ESB_LOCK_REG    0x68            /* WDT lock register                 */
  42
  43 /* Memory mapped registers (offset from base address) */
  44 #define ESB_TIMER1_REG  0x00            /* Timer1 value after each reset     */
  45 #define ESB_TIMER2_REG  0x04            /* Timer2 value after each reset     */
  46 #define ESB_GINTSR_REG  0x08            /* General Interrupt Status Register */
  47 #define ESB_RELOAD_REG  0x0c            /* Reload register                   */
  48
  49 /* Lock register bits */
  50 #define ESB_WDT_FUNC    (0x01 << 2)   /* Watchdog functionality            */
  51 #define ESB_WDT_ENABLE  (0x01 << 1)   /* Enable WDT                        */
  52 #define ESB_WDT_LOCK    (0x01 << 0)   /* Lock (nowayout)                   */
  53
  54 /* Config register bits */
  55 #define ESB_WDT_REBOOT  (0x01 << 5)   /* Enable reboot on timeout          */
  56 #define ESB_WDT_FREQ    (0x01 << 2)   /* Decrement frequency               */
  57 #define ESB_WDT_INTTYPE (0x11 << 0)   /* Interrupt type on timer1 timeout  */
  58
  59 /* Reload register bits */
  60 #define ESB_WDT_RELOAD  (0x01 << 8)    /* prevent timeout                   */
  61
  62 /* Magic constants */
  63 #define ESB_UNLOCK1     0x80            /* Step 1 to unlock reset registers  */
  64 #define ESB_UNLOCK2     0x86            /* Step 2 to unlock reset registers  */
  65
  66 /* Device state. */
  67 struct I6300State {
  68     PCIDevice dev;
  69
  70     int reboot_enabled;         /* "Reboot" on timer expiry.  The real action
  71                                  * performed depends on the -watchdog-action
  72                                  * param passed on QEMU command line.
  73                                  */
  74     int clock_scale;            /* Clock scale. */
  75 #define CLOCK_SCALE_1KHZ 0
  76 #define CLOCK_SCALE_1MHZ 1
  77
  78     int int_type;               /* Interrupt type generated. */
  79 #define INT_TYPE_IRQ 0          /* APIC 1, INT 10 */
  80 #define INT_TYPE_SMI 2
  81 #define INT_TYPE_DISABLED 3
  82
  83     int free_run;               /* If true, reload timer on expiry. */
  84     int locked;                 /* If true, enabled field cannot be changed. */
  85     int enabled;                /* If true, watchdog is enabled. */
  86
  87     QEMUTimer *timer;           /* The actual watchdog timer. */
  88
  89     uint32_t timer1_preload;    /* Values preloaded into timer1, timer2. */
  90     uint32_t timer2_preload;
  91     int stage;                  /* Stage (1 or 2). */
  92
  93     int unlock_state;           /* Guest writes 0x80, 0x86 to unlock the
  94                                  * registers, and we transition through
  95                                  * states 0 -> 1 -> 2 when this happens.
  96                                  */
  97
  98     int previous_reboot_flag;   /* If the watchdog caused the previous
  99                                  * reboot, this flag will be set.
 100                                  */
 101 };
 102
 103 typedef struct I6300State I6300State;
 104
 105 /* This function is called when the watchdog has either been enabled
 106  * (hence it starts counting down) or has been keep-alived.
 107  */
 108 static void i6300esb_restart_timer(I6300State *d, int stage)
 109 {
 110     int64_t timeout;
 111
 112     if (!d->enabled)
 113         return;
 114
 115     d->stage = stage;
 116
 117     if (d->stage <= 1)
 118         timeout = d->timer1_preload;
 119     else
 120         timeout = d->timer2_preload;
 121
 122     if (d->clock_scale == CLOCK_SCALE_1KHZ)
 123         timeout <<= 15;
 124     else
 125         timeout <<= 5;
 126
 127     /* Get the timeout in units of ticks_per_sec. */
 128     timeout = get_ticks_per_sec() * timeout / 33000000;
 129
 130     i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);
 131
 132     qemu_mod_timer(d->timer, qemu_get_clock(vm_clock) + timeout);
 133 }
 134
 135 /* This is called when the guest disables the watchdog. */
 136 static void i6300esb_disable_timer(I6300State *d)
 137 {
 138     i6300esb_debug("timer disabled\n");
 139
 140     qemu_del_timer(d->timer);
 141 }
 142
 143 static void i6300esb_reset(DeviceState *dev)
 144 {
 145     PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, dev);
 146     I6300State *d = DO_UPCAST(I6300State, dev, pdev);
 147
 148     i6300esb_debug("I6300State = %p\n", d);
 149
 150     i6300esb_disable_timer(d);
 151
 152     /* NB: Don't change d->previous_reboot_flag in this function. */
 153
 154     d->reboot_enabled = 1;
 155     d->clock_scale = CLOCK_SCALE_1KHZ;
 156     d->int_type = INT_TYPE_IRQ;
 157     d->free_run = 0;
 158     d->locked = 0;
 159     d->enabled = 0;
 160     d->timer1_preload = 0xfffff;
 161     d->timer2_preload = 0xfffff;
 162     d->stage = 1;
 163     d->unlock_state = 0;
 164 }
 165
 166 /* This function is called when the watchdog expires.  Note that
 167  * the hardware has two timers, and so expiry happens in two stages.
 168  * If d->stage == 1 then we perform the first stage action (usually,
 169  * sending an interrupt) and then restart the timer again for the
 170  * second stage.  If the second stage expires then the watchdog
 171  * really has run out.
 172  */
 173 static void i6300esb_timer_expired(void *vp)
 174 {
 175     I6300State *d = vp;
 176
 177     i6300esb_debug("stage %d\n", d->stage);
 178
 179     if (d->stage == 1) {
 180         /* What to do at the end of stage 1? */
 181         switch (d->int_type) {
 182         case INT_TYPE_IRQ:
 183             fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
 184             break;
 185         case INT_TYPE_SMI:
 186             fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
 187             break;
 188         }
 189
 190         /* Start the second stage. */
 191         i6300esb_restart_timer(d, 2);
 192     } else {
 193         /* Second stage expired, reboot for real. */
 194         if (d->reboot_enabled) {
 195             d->previous_reboot_flag = 1;
 196             watchdog_perform_action(); /* This reboots, exits, etc */
 197             i6300esb_reset(&d->dev.qdev);
 198         }
 199
 200         /* In "free running mode" we start stage 1 again. */
 201         if (d->free_run)
 202             i6300esb_restart_timer(d, 1);
 203     }
 204 }
 205
 206 static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
 207                                   uint32_t data, int len)
 208 {
 209     I6300State *d = DO_UPCAST(I6300State, dev, dev);
 210     int old;
 211
 212     i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
 213
 214     if (addr == ESB_CONFIG_REG && len == 2) {
 215         d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
 216         d->clock_scale =
 217             (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
 218         d->int_type = (data & ESB_WDT_INTTYPE);
 219     } else if (addr == ESB_LOCK_REG && len == 1) {
 220         if (!d->locked) {
 221             d->locked = (data & ESB_WDT_LOCK) != 0;
 222             d->free_run = (data & ESB_WDT_FUNC) != 0;
 223             old = d->enabled;
 224             d->enabled = (data & ESB_WDT_ENABLE) != 0;
 225             if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
 226                 i6300esb_restart_timer(d, 1);
 227             else if (!d->enabled)
 228                 i6300esb_disable_timer(d);
 229         }
 230     } else {
 231         pci_default_write_config(dev, addr, data, len);
 232     }
 233 }
 234
 235 static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
 236 {
 237     I6300State *d = DO_UPCAST(I6300State, dev, dev);
 238     uint32_t data;
 239
 240     i6300esb_debug ("addr = %x, len = %d\n", addr, len);
 241
 242     if (addr == ESB_CONFIG_REG && len == 2) {
 243         data =
 244             (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) |
 245             (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) |
 246             d->int_type;
 247         return data;
 248     } else if (addr == ESB_LOCK_REG && len == 1) {
 249         data =
 250             (d->free_run ? ESB_WDT_FUNC : 0) |
 251             (d->locked ? ESB_WDT_LOCK : 0) |
 252             (d->enabled ? ESB_WDT_ENABLE : 0);
 253         return data;
 254     } else {
 255         return pci_default_read_config(dev, addr, len);
 256     }
 257 }
 258
 259 static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr)
 260 {
 261     i6300esb_debug ("addr = %x\n", (int) addr);
 262
 263     return 0;
 264 }
 265
 266 static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr)
 267 {
 268     uint32_t data = 0;
 269     I6300State *d = vp;
 270
 271     i6300esb_debug("addr = %x\n", (int) addr);
 272
 273     if (addr == 0xc) {
 274         /* The previous reboot flag is really bit 9, but there is
 275          * a bug in the Linux driver where it thinks it's bit 12.
 276          * Set both.
 277          */
 278         data = d->previous_reboot_flag ? 0x1200 : 0;
 279     }
 280
 281     return data;
 282 }
 283
 284 static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr)
 285 {
 286     i6300esb_debug("addr = %x\n", (int) addr);
 287
 288     return 0;
 289 }
 290
 291 static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val)
 292 {
 293     I6300State *d = vp;
 294
 295     i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
 296
 297     if (addr == 0xc && val == 0x80)
 298         d->unlock_state = 1;
 299     else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
 300         d->unlock_state = 2;
 301 }
 302
 303 static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val)
 304 {
 305     I6300State *d = vp;
 306
 307     i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
 308
 309     if (addr == 0xc && val == 0x80)
 310         d->unlock_state = 1;
 311     else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
 312         d->unlock_state = 2;
 313     else {
 314         if (d->unlock_state == 2) {
 315             if (addr == 0xc) {
 316                 if ((val & 0x100) != 0)
 317                     /* This is the "ping" from the userspace watchdog in
 318                      * the guest ...
 319                      */
 320                     i6300esb_restart_timer(d, 1);
 321
 322                 /* Setting bit 9 resets the previous reboot flag.
 323                  * There's a bug in the Linux driver where it sets
 324                  * bit 12 instead.
 325                  */
 326                 if ((val & 0x200) != 0 || (val & 0x1000) != 0) {
 327                     d->previous_reboot_flag = 0;
 328                 }
 329             }
 330
 331             d->unlock_state = 0;
 332         }
 333     }
 334 }
 335
 336 static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val)
 337 {
 338     I6300State *d = vp;
 339
 340     i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);
 341
 342     if (addr == 0xc && val == 0x80)
 343         d->unlock_state = 1;
 344     else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
 345         d->unlock_state = 2;
 346     else {
 347         if (d->unlock_state == 2) {
 348             if (addr == 0)
 349                 d->timer1_preload = val & 0xfffff;
 350             else if (addr == 4)
 351                 d->timer2_preload = val & 0xfffff;
 352
 353             d->unlock_state = 0;
 354         }
 355     }
 356 }
 357
 358 static void i6300esb_map(PCIDevice *dev, int region_num,
 359                          pcibus_t addr, pcibus_t size, int type)
 360 {
 361     static CPUReadMemoryFunc * const mem_read[3] = {
 362         i6300esb_mem_readb,
 363         i6300esb_mem_readw,
 364         i6300esb_mem_readl,
 365     };
 366     static CPUWriteMemoryFunc * const mem_write[3] = {
 367         i6300esb_mem_writeb,
 368         i6300esb_mem_writew,
 369         i6300esb_mem_writel,
 370     };
 371     I6300State *d = DO_UPCAST(I6300State, dev, dev);
 372     int io_mem;
 373
 374     i6300esb_debug("addr = %"FMT_PCIBUS", size = %"FMT_PCIBUS", type = %d\n",
 375                    addr, size, type);
 376
 377     io_mem = cpu_register_io_memory(mem_read, mem_write, d,
 378                                     DEVICE_NATIVE_ENDIAN);
 379     cpu_register_physical_memory (addr, 0x10, io_mem);
 380     /* qemu_register_coalesced_mmio (addr, 0x10); ? */
 381 }
 382
 383 static const VMStateDescription vmstate_i6300esb = {
 384     .name = "i6300esb_wdt",
 385     .version_id = sizeof(I6300State),
 386     .minimum_version_id = sizeof(I6300State),
 387     .minimum_version_id_old = sizeof(I6300State),
 388     .fields      = (VMStateField []) {
 389         VMSTATE_PCI_DEVICE(dev, I6300State),
 390         VMSTATE_INT32(reboot_enabled, I6300State),
 391         VMSTATE_INT32(clock_scale, I6300State),
 392         VMSTATE_INT32(int_type, I6300State),
 393         VMSTATE_INT32(free_run, I6300State),
 394         VMSTATE_INT32(locked, I6300State),
 395         VMSTATE_INT32(enabled, I6300State),
 396         VMSTATE_TIMER(timer, I6300State),
 397         VMSTATE_UINT32(timer1_preload, I6300State),
 398         VMSTATE_UINT32(timer2_preload, I6300State),
 399         VMSTATE_INT32(stage, I6300State),
 400         VMSTATE_INT32(unlock_state, I6300State),
 401         VMSTATE_INT32(previous_reboot_flag, I6300State),
 402         VMSTATE_END_OF_LIST()
 403     }
 404 };
 405
 406 static int i6300esb_init(PCIDevice *dev)
 407 {
 408     I6300State *d = DO_UPCAST(I6300State, dev, dev);
 409     uint8_t *pci_conf;
 410
 411     i6300esb_debug("I6300State = %p\n", d);
 412
 413     d->timer = qemu_new_timer(vm_clock, i6300esb_timer_expired, d);
 414     d->previous_reboot_flag = 0;
 415
 416     pci_conf = d->dev.config;
 417     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 418     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_ESB_9);
 419     pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER);
 420
 421     pci_register_bar(&d->dev, 0, 0x10,
 422                             PCI_BASE_ADDRESS_SPACE_MEMORY, i6300esb_map);
 423
 424     return 0;
 425 }
 426
 427 static WatchdogTimerModel model = {
 428     .wdt_name = "i6300esb",
 429     .wdt_description = "Intel 6300ESB",
 430 };
 431
 432 static PCIDeviceInfo i6300esb_info = {
 433     .qdev.name    = "i6300esb",
 434     .qdev.size    = sizeof(I6300State),
 435     .qdev.vmsd    = &vmstate_i6300esb,
 436     .qdev.reset   = i6300esb_reset,
 437     .config_read  = i6300esb_config_read,
 438     .config_write = i6300esb_config_write,
 439     .init         = i6300esb_init,
 440 };
 441
 442 static void i6300esb_register_devices(void)
 443 {
 444     watchdog_add_model(&model);
 445     pci_qdev_register(&i6300esb_info);
 446 }
 447
 448 device_init(i6300esb_register_devices);