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ppc: remove video.x
[qemu/lumag.git] / hw / sun4m.c
blob03921092307817d9be42d30121ac62cd77f1af70
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "esp.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
41 #include "loader.h"
42 #include "elf.h"
43 #include "blockdev.h"
44
45 //#define DEBUG_IRQ
46
47 /*
48 * Sun4m architecture was used in the following machines:
49 *
50 * SPARCserver 6xxMP/xx
51 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
52 * SPARCclassic X (4/10)
53 * SPARCstation LX/ZX (4/30)
54 * SPARCstation Voyager
55 * SPARCstation 10/xx, SPARCserver 10/xx
56 * SPARCstation 5, SPARCserver 5
57 * SPARCstation 20/xx, SPARCserver 20
58 * SPARCstation 4
59 *
60 * Sun4d architecture was used in the following machines:
61 *
62 * SPARCcenter 2000
63 * SPARCserver 1000
64 *
65 * Sun4c architecture was used in the following machines:
66 * SPARCstation 1/1+, SPARCserver 1/1+
67 * SPARCstation SLC
68 * SPARCstation IPC
69 * SPARCstation ELC
70 * SPARCstation IPX
71 *
72 * See for example: http://www.sunhelp.org/faq/sunref1.html
73 */
74
75 #ifdef DEBUG_IRQ
76 #define DPRINTF(fmt, ...) \
77 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
78 #else
79 #define DPRINTF(fmt, ...)
80 #endif
81
82 #define KERNEL_LOAD_ADDR 0x00004000
83 #define CMDLINE_ADDR 0x007ff000
84 #define INITRD_LOAD_ADDR 0x00800000
85 #define PROM_SIZE_MAX (1024 * 1024)
86 #define PROM_VADDR 0xffd00000
87 #define PROM_FILENAME "openbios-sparc32"
88 #define CFG_ADDR 0xd00000510ULL
89 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
90
91 #define MAX_CPUS 16
92 #define MAX_PILS 16
93 #define MAX_VSIMMS 4
94
95 #define ESCC_CLOCK 4915200
96
97 struct sun4m_hwdef {
98 target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
99 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
100 target_phys_addr_t serial_base, fd_base;
101 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
102 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
103 target_phys_addr_t bpp_base, dbri_base, sx_base;
104 struct {
105 target_phys_addr_t reg_base, vram_base;
106 } vsimm[MAX_VSIMMS];
107 target_phys_addr_t ecc_base;
108 uint32_t ecc_version;
109 uint8_t nvram_machine_id;
110 uint16_t machine_id;
111 uint32_t iommu_version;
112 uint64_t max_mem;
113 const char * const default_cpu_model;
114 };
115
116 #define MAX_IOUNITS 5
117
118 struct sun4d_hwdef {
119 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
120 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
121 target_phys_addr_t serial_base;
122 target_phys_addr_t espdma_base, esp_base;
123 target_phys_addr_t ledma_base, le_base;
124 target_phys_addr_t tcx_base;
125 target_phys_addr_t sbi_base;
126 uint8_t nvram_machine_id;
127 uint16_t machine_id;
128 uint32_t iounit_version;
129 uint64_t max_mem;
130 const char * const default_cpu_model;
131 };
132
133 struct sun4c_hwdef {
134 target_phys_addr_t iommu_base, slavio_base;
135 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136 target_phys_addr_t serial_base, fd_base;
137 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138 target_phys_addr_t tcx_base, aux1_base;
139 uint8_t nvram_machine_id;
140 uint16_t machine_id;
141 uint32_t iommu_version;
142 uint64_t max_mem;
143 const char * const default_cpu_model;
144 };
145
146 int DMA_get_channel_mode (int nchan)
147 {
148 return 0;
149 }
150 int DMA_read_memory (int nchan, void *buf, int pos, int size)
151 {
152 return 0;
153 }
154 int DMA_write_memory (int nchan, void *buf, int pos, int size)
155 {
156 return 0;
157 }
158 void DMA_hold_DREQ (int nchan) {}
159 void DMA_release_DREQ (int nchan) {}
160 void DMA_schedule(int nchan) {}
161
162 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
163 {
164 }
165
166 void DMA_register_channel (int nchan,
167 DMA_transfer_handler transfer_handler,
168 void *opaque)
169 {
170 }
171
172 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
173 {
174 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
175 return 0;
176 }
177
178 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
179 const char *cmdline, const char *boot_devices,
180 ram_addr_t RAM_size, uint32_t kernel_size,
181 int width, int height, int depth,
182 int nvram_machine_id, const char *arch)
183 {
184 unsigned int i;
185 uint32_t start, end;
186 uint8_t image[0x1ff0];
187 struct OpenBIOS_nvpart_v1 *part_header;
188
189 memset(image, '\0', sizeof(image));
190
191 start = 0;
192
193 // OpenBIOS nvram variables
194 // Variable partition
195 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
196 part_header->signature = OPENBIOS_PART_SYSTEM;
197 pstrcpy(part_header->name, sizeof(part_header->name), "system");
198
199 end = start + sizeof(struct OpenBIOS_nvpart_v1);
200 for (i = 0; i < nb_prom_envs; i++)
201 end = OpenBIOS_set_var(image, end, prom_envs[i]);
202
203 // End marker
204 image[end++] = '\0';
205
206 end = start + ((end - start + 15) & ~15);
207 OpenBIOS_finish_partition(part_header, end - start);
208
209 // free partition
210 start = end;
211 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
212 part_header->signature = OPENBIOS_PART_FREE;
213 pstrcpy(part_header->name, sizeof(part_header->name), "free");
214
215 end = 0x1fd0;
216 OpenBIOS_finish_partition(part_header, end - start);
217
218 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
219 nvram_machine_id);
220
221 for (i = 0; i < sizeof(image); i++)
222 m48t59_write(nvram, i, image[i]);
223 }
224
225 static DeviceState *slavio_intctl;
226
227 void pic_info(Monitor *mon)
228 {
229 if (slavio_intctl)
230 slavio_pic_info(mon, slavio_intctl);
231 }
232
233 void irq_info(Monitor *mon)
234 {
235 if (slavio_intctl)
236 slavio_irq_info(mon, slavio_intctl);
237 }
238
239 void cpu_check_irqs(CPUState *env)
240 {
241 if (env->pil_in && (env->interrupt_index == 0 ||
242 (env->interrupt_index & ~15) == TT_EXTINT)) {
243 unsigned int i;
244
245 for (i = 15; i > 0; i--) {
246 if (env->pil_in & (1 << i)) {
247 int old_interrupt = env->interrupt_index;
248
249 env->interrupt_index = TT_EXTINT | i;
250 if (old_interrupt != env->interrupt_index) {
251 DPRINTF("Set CPU IRQ %d\n", i);
252 cpu_interrupt(env, CPU_INTERRUPT_HARD);
253 }
254 break;
255 }
256 }
257 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
258 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
259 env->interrupt_index = 0;
260 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
261 }
262 }
263
264 static void cpu_set_irq(void *opaque, int irq, int level)
265 {
266 CPUState *env = opaque;
267
268 if (level) {
269 DPRINTF("Raise CPU IRQ %d\n", irq);
270 env->halted = 0;
271 env->pil_in |= 1 << irq;
272 cpu_check_irqs(env);
273 } else {
274 DPRINTF("Lower CPU IRQ %d\n", irq);
275 env->pil_in &= ~(1 << irq);
276 cpu_check_irqs(env);
277 }
278 }
279
280 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
281 {
282 }
283
284 static void main_cpu_reset(void *opaque)
285 {
286 CPUState *env = opaque;
287
288 cpu_reset(env);
289 env->halted = 0;
290 }
291
292 static void secondary_cpu_reset(void *opaque)
293 {
294 CPUState *env = opaque;
295
296 cpu_reset(env);
297 env->halted = 1;
298 }
299
300 static void cpu_halt_signal(void *opaque, int irq, int level)
301 {
302 if (level && cpu_single_env)
303 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
304 }
305
306 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
307 {
308 return addr - 0xf0000000ULL;
309 }
310
311 static unsigned long sun4m_load_kernel(const char *kernel_filename,
312 const char *initrd_filename,
313 ram_addr_t RAM_size)
314 {
315 int linux_boot;
316 unsigned int i;
317 long initrd_size, kernel_size;
318 uint8_t *ptr;
319
320 linux_boot = (kernel_filename != NULL);
321
322 kernel_size = 0;
323 if (linux_boot) {
324 int bswap_needed;
325
326 #ifdef BSWAP_NEEDED
327 bswap_needed = 1;
328 #else
329 bswap_needed = 0;
330 #endif
331 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
332 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
333 if (kernel_size < 0)
334 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
335 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
336 TARGET_PAGE_SIZE);
337 if (kernel_size < 0)
338 kernel_size = load_image_targphys(kernel_filename,
339 KERNEL_LOAD_ADDR,
340 RAM_size - KERNEL_LOAD_ADDR);
341 if (kernel_size < 0) {
342 fprintf(stderr, "qemu: could not load kernel '%s'\n",
343 kernel_filename);
344 exit(1);
345 }
346
347 /* load initrd */
348 initrd_size = 0;
349 if (initrd_filename) {
350 initrd_size = load_image_targphys(initrd_filename,
351 INITRD_LOAD_ADDR,
352 RAM_size - INITRD_LOAD_ADDR);
353 if (initrd_size < 0) {
354 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
355 initrd_filename);
356 exit(1);
357 }
358 }
359 if (initrd_size > 0) {
360 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
361 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
362 if (ldl_p(ptr) == 0x48647253) { // HdrS
363 stl_p(ptr + 16, INITRD_LOAD_ADDR);
364 stl_p(ptr + 20, initrd_size);
365 break;
366 }
367 }
368 }
369 }
370 return kernel_size;
371 }
372
373 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
374 {
375 DeviceState *dev;
376 SysBusDevice *s;
377
378 dev = qdev_create(NULL, "iommu");
379 qdev_prop_set_uint32(dev, "version", version);
380 qdev_init_nofail(dev);
381 s = sysbus_from_qdev(dev);
382 sysbus_connect_irq(s, 0, irq);
383 sysbus_mmio_map(s, 0, addr);
384
385 return s;
386 }
387
388 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
389 void *iommu, qemu_irq *dev_irq)
390 {
391 DeviceState *dev;
392 SysBusDevice *s;
393
394 dev = qdev_create(NULL, "sparc32_dma");
395 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
396 qdev_init_nofail(dev);
397 s = sysbus_from_qdev(dev);
398 sysbus_connect_irq(s, 0, parent_irq);
399 *dev_irq = qdev_get_gpio_in(dev, 0);
400 sysbus_mmio_map(s, 0, daddr);
401
402 return s;
403 }
404
405 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
406 void *dma_opaque, qemu_irq irq)
407 {
408 DeviceState *dev;
409 SysBusDevice *s;
410 qemu_irq reset;
411
412 qemu_check_nic_model(&nd_table[0], "lance");
413
414 dev = qdev_create(NULL, "lance");
415 qdev_set_nic_properties(dev, nd);
416 qdev_prop_set_ptr(dev, "dma", dma_opaque);
417 qdev_init_nofail(dev);
418 s = sysbus_from_qdev(dev);
419 sysbus_mmio_map(s, 0, leaddr);
420 sysbus_connect_irq(s, 0, irq);
421 reset = qdev_get_gpio_in(dev, 0);
422 qdev_connect_gpio_out(dma_opaque, 0, reset);
423 }
424
425 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
426 target_phys_addr_t addrg,
427 qemu_irq **parent_irq)
428 {
429 DeviceState *dev;
430 SysBusDevice *s;
431 unsigned int i, j;
432
433 dev = qdev_create(NULL, "slavio_intctl");
434 qdev_init_nofail(dev);
435
436 s = sysbus_from_qdev(dev);
437
438 for (i = 0; i < MAX_CPUS; i++) {
439 for (j = 0; j < MAX_PILS; j++) {
440 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
441 }
442 }
443 sysbus_mmio_map(s, 0, addrg);
444 for (i = 0; i < MAX_CPUS; i++) {
445 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
446 }
447
448 return dev;
449 }
450
451 #define SYS_TIMER_OFFSET 0x10000ULL
452 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
453
454 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
455 qemu_irq *cpu_irqs, unsigned int num_cpus)
456 {
457 DeviceState *dev;
458 SysBusDevice *s;
459 unsigned int i;
460
461 dev = qdev_create(NULL, "slavio_timer");
462 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
463 qdev_init_nofail(dev);
464 s = sysbus_from_qdev(dev);
465 sysbus_connect_irq(s, 0, master_irq);
466 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
467
468 for (i = 0; i < MAX_CPUS; i++) {
469 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
470 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
471 }
472 }
473
474 #define MISC_LEDS 0x01600000
475 #define MISC_CFG 0x01800000
476 #define MISC_DIAG 0x01a00000
477 #define MISC_MDM 0x01b00000
478 #define MISC_SYS 0x01f00000
479
480 static void slavio_misc_init(target_phys_addr_t base,
481 target_phys_addr_t aux1_base,
482 target_phys_addr_t aux2_base, qemu_irq irq,
483 qemu_irq fdc_tc)
484 {
485 DeviceState *dev;
486 SysBusDevice *s;
487
488 dev = qdev_create(NULL, "slavio_misc");
489 qdev_init_nofail(dev);
490 s = sysbus_from_qdev(dev);
491 if (base) {
492 /* 8 bit registers */
493 /* Slavio control */
494 sysbus_mmio_map(s, 0, base + MISC_CFG);
495 /* Diagnostics */
496 sysbus_mmio_map(s, 1, base + MISC_DIAG);
497 /* Modem control */
498 sysbus_mmio_map(s, 2, base + MISC_MDM);
499 /* 16 bit registers */
500 /* ss600mp diag LEDs */
501 sysbus_mmio_map(s, 3, base + MISC_LEDS);
502 /* 32 bit registers */
503 /* System control */
504 sysbus_mmio_map(s, 4, base + MISC_SYS);
505 }
506 if (aux1_base) {
507 /* AUX 1 (Misc System Functions) */
508 sysbus_mmio_map(s, 5, aux1_base);
509 }
510 if (aux2_base) {
511 /* AUX 2 (Software Powerdown Control) */
512 sysbus_mmio_map(s, 6, aux2_base);
513 }
514 sysbus_connect_irq(s, 0, irq);
515 sysbus_connect_irq(s, 1, fdc_tc);
516 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
517 }
518
519 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
520 {
521 DeviceState *dev;
522 SysBusDevice *s;
523
524 dev = qdev_create(NULL, "eccmemctl");
525 qdev_prop_set_uint32(dev, "version", version);
526 qdev_init_nofail(dev);
527 s = sysbus_from_qdev(dev);
528 sysbus_connect_irq(s, 0, irq);
529 sysbus_mmio_map(s, 0, base);
530 if (version == 0) { // SS-600MP only
531 sysbus_mmio_map(s, 1, base + 0x1000);
532 }
533 }
534
535 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
536 {
537 DeviceState *dev;
538 SysBusDevice *s;
539
540 dev = qdev_create(NULL, "apc");
541 qdev_init_nofail(dev);
542 s = sysbus_from_qdev(dev);
543 /* Power management (APC) XXX: not a Slavio device */
544 sysbus_mmio_map(s, 0, power_base);
545 sysbus_connect_irq(s, 0, cpu_halt);
546 }
547
548 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
549 int height, int depth)
550 {
551 DeviceState *dev;
552 SysBusDevice *s;
553
554 dev = qdev_create(NULL, "SUNW,tcx");
555 qdev_prop_set_taddr(dev, "addr", addr);
556 qdev_prop_set_uint32(dev, "vram_size", vram_size);
557 qdev_prop_set_uint16(dev, "width", width);
558 qdev_prop_set_uint16(dev, "height", height);
559 qdev_prop_set_uint16(dev, "depth", depth);
560 qdev_init_nofail(dev);
561 s = sysbus_from_qdev(dev);
562 /* 8-bit plane */
563 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
564 /* DAC */
565 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
566 /* TEC (dummy) */
567 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
568 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
569 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
570 if (depth == 24) {
571 /* 24-bit plane */
572 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
573 /* Control plane */
574 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
575 } else {
576 /* THC 8 bit (dummy) */
577 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
578 }
579 }
580
581 /* NCR89C100/MACIO Internal ID register */
582 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
583
584 static void idreg_init(target_phys_addr_t addr)
585 {
586 DeviceState *dev;
587 SysBusDevice *s;
588
589 dev = qdev_create(NULL, "macio_idreg");
590 qdev_init_nofail(dev);
591 s = sysbus_from_qdev(dev);
592
593 sysbus_mmio_map(s, 0, addr);
594 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
595 }
596
597 static int idreg_init1(SysBusDevice *dev)
598 {
599 ram_addr_t idreg_offset;
600
601 idreg_offset = qemu_ram_alloc(NULL, "sun4m.idreg", sizeof(idreg_data));
602 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
603 return 0;
604 }
605
606 static SysBusDeviceInfo idreg_info = {
607 .init = idreg_init1,
608 .qdev.name = "macio_idreg",
609 .qdev.size = sizeof(SysBusDevice),
610 };
611
612 static void idreg_register_devices(void)
613 {
614 sysbus_register_withprop(&idreg_info);
615 }
616
617 device_init(idreg_register_devices);
618
619 /* SS-5 TCX AFX register */
620 static void afx_init(target_phys_addr_t addr)
621 {
622 DeviceState *dev;
623 SysBusDevice *s;
624
625 dev = qdev_create(NULL, "tcx_afx");
626 qdev_init_nofail(dev);
627 s = sysbus_from_qdev(dev);
628
629 sysbus_mmio_map(s, 0, addr);
630 }
631
632 static int afx_init1(SysBusDevice *dev)
633 {
634 ram_addr_t afx_offset;
635
636 afx_offset = qemu_ram_alloc(NULL, "sun4m.afx", 4);
637 sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);
638 return 0;
639 }
640
641 static SysBusDeviceInfo afx_info = {
642 .init = afx_init1,
643 .qdev.name = "tcx_afx",
644 .qdev.size = sizeof(SysBusDevice),
645 };
646
647 static void afx_register_devices(void)
648 {
649 sysbus_register_withprop(&afx_info);
650 }
651
652 device_init(afx_register_devices);
653
654 /* Boot PROM (OpenBIOS) */
655 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
656 {
657 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
658 return addr + *base_addr - PROM_VADDR;
659 }
660
661 static void prom_init(target_phys_addr_t addr, const char *bios_name)
662 {
663 DeviceState *dev;
664 SysBusDevice *s;
665 char *filename;
666 int ret;
667
668 dev = qdev_create(NULL, "openprom");
669 qdev_init_nofail(dev);
670 s = sysbus_from_qdev(dev);
671
672 sysbus_mmio_map(s, 0, addr);
673
674 /* load boot prom */
675 if (bios_name == NULL) {
676 bios_name = PROM_FILENAME;
677 }
678 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
679 if (filename) {
680 ret = load_elf(filename, translate_prom_address, &addr, NULL,
681 NULL, NULL, 1, ELF_MACHINE, 0);
682 if (ret < 0 || ret > PROM_SIZE_MAX) {
683 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
684 }
685 qemu_free(filename);
686 } else {
687 ret = -1;
688 }
689 if (ret < 0 || ret > PROM_SIZE_MAX) {
690 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
691 exit(1);
692 }
693 }
694
695 static int prom_init1(SysBusDevice *dev)
696 {
697 ram_addr_t prom_offset;
698
699 prom_offset = qemu_ram_alloc(NULL, "sun4m.prom", PROM_SIZE_MAX);
700 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
701 return 0;
702 }
703
704 static SysBusDeviceInfo prom_info = {
705 .init = prom_init1,
706 .qdev.name = "openprom",
707 .qdev.size = sizeof(SysBusDevice),
708 .qdev.props = (Property[]) {
709 {/* end of property list */}
710 }
711 };
712
713 static void prom_register_devices(void)
714 {
715 sysbus_register_withprop(&prom_info);
716 }
717
718 device_init(prom_register_devices);
719
720 typedef struct RamDevice
721 {
722 SysBusDevice busdev;
723 uint64_t size;
724 } RamDevice;
725
726 /* System RAM */
727 static int ram_init1(SysBusDevice *dev)
728 {
729 ram_addr_t RAM_size, ram_offset;
730 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
731
732 RAM_size = d->size;
733
734 ram_offset = qemu_ram_alloc(NULL, "sun4m.ram", RAM_size);
735 sysbus_init_mmio(dev, RAM_size, ram_offset);
736 return 0;
737 }
738
739 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
740 uint64_t max_mem)
741 {
742 DeviceState *dev;
743 SysBusDevice *s;
744 RamDevice *d;
745
746 /* allocate RAM */
747 if ((uint64_t)RAM_size > max_mem) {
748 fprintf(stderr,
749 "qemu: Too much memory for this machine: %d, maximum %d\n",
750 (unsigned int)(RAM_size / (1024 * 1024)),
751 (unsigned int)(max_mem / (1024 * 1024)));
752 exit(1);
753 }
754 dev = qdev_create(NULL, "memory");
755 s = sysbus_from_qdev(dev);
756
757 d = FROM_SYSBUS(RamDevice, s);
758 d->size = RAM_size;
759 qdev_init_nofail(dev);
760
761 sysbus_mmio_map(s, 0, addr);
762 }
763
764 static SysBusDeviceInfo ram_info = {
765 .init = ram_init1,
766 .qdev.name = "memory",
767 .qdev.size = sizeof(RamDevice),
768 .qdev.props = (Property[]) {
769 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
770 DEFINE_PROP_END_OF_LIST(),
771 }
772 };
773
774 static void ram_register_devices(void)
775 {
776 sysbus_register_withprop(&ram_info);
777 }
778
779 device_init(ram_register_devices);
780
781 static void cpu_devinit(const char *cpu_model, unsigned int id,
782 uint64_t prom_addr, qemu_irq **cpu_irqs)
783 {
784 CPUState *env;
785
786 env = cpu_init(cpu_model);
787 if (!env) {
788 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
789 exit(1);
790 }
791
792 cpu_sparc_set_id(env, id);
793 if (id == 0) {
794 qemu_register_reset(main_cpu_reset, env);
795 } else {
796 qemu_register_reset(secondary_cpu_reset, env);
797 env->halted = 1;
798 }
799 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
800 env->prom_addr = prom_addr;
801 }
802
803 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
804 const char *boot_device,
805 const char *kernel_filename,
806 const char *kernel_cmdline,
807 const char *initrd_filename, const char *cpu_model)
808 {
809 unsigned int i;
810 void *iommu, *espdma, *ledma, *nvram;
811 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
812 espdma_irq, ledma_irq;
813 qemu_irq esp_reset, dma_enable;
814 qemu_irq fdc_tc;
815 qemu_irq *cpu_halt;
816 unsigned long kernel_size;
817 DriveInfo *fd[MAX_FD];
818 void *fw_cfg;
819 unsigned int num_vsimms;
820
821 /* init CPUs */
822 if (!cpu_model)
823 cpu_model = hwdef->default_cpu_model;
824
825 for(i = 0; i < smp_cpus; i++) {
826 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
827 }
828
829 for (i = smp_cpus; i < MAX_CPUS; i++)
830 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
831
832
833 /* set up devices */
834 ram_init(0, RAM_size, hwdef->max_mem);
835 /* models without ECC don't trap when missing ram is accessed */
836 if (!hwdef->ecc_base) {
837 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
838 }
839
840 prom_init(hwdef->slavio_base, bios_name);
841
842 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
843 hwdef->intctl_base + 0x10000ULL,
844 cpu_irqs);
845
846 for (i = 0; i < 32; i++) {
847 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
848 }
849 for (i = 0; i < MAX_CPUS; i++) {
850 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
851 }
852
853 if (hwdef->idreg_base) {
854 idreg_init(hwdef->idreg_base);
855 }
856
857 if (hwdef->afx_base) {
858 afx_init(hwdef->afx_base);
859 }
860
861 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
862 slavio_irq[30]);
863
864 if (hwdef->iommu_pad_base) {
865 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
866 Software shouldn't use aliased addresses, neither should it crash
867 when does. Using empty_slot instead of aliasing can help with
868 debugging such accesses */
869 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
870 }
871
872 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
873 iommu, &espdma_irq);
874
875 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
876 slavio_irq[16], iommu, &ledma_irq);
877
878 if (graphic_depth != 8 && graphic_depth != 24) {
879 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
880 exit (1);
881 }
882 num_vsimms = 0;
883 if (num_vsimms == 0) {
884 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
885 graphic_depth);
886 }
887
888 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
889 /* vsimm registers probed by OBP */
890 if (hwdef->vsimm[i].reg_base) {
891 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
892 }
893 }
894
895 if (hwdef->sx_base) {
896 empty_slot_init(hwdef->sx_base, 0x2000);
897 }
898
899 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
900
901 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
902
903 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
904
905 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
906 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
907 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
908 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
909 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
910 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
911
912 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
913 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
914 slavio_irq[30], fdc_tc);
915
916 if (hwdef->apc_base) {
917 apc_init(hwdef->apc_base, cpu_halt[0]);
918 }
919
920 if (hwdef->fd_base) {
921 /* there is zero or one floppy drive */
922 memset(fd, 0, sizeof(fd));
923 fd[0] = drive_get(IF_FLOPPY, 0, 0);
924 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
925 &fdc_tc);
926 }
927
928 if (drive_get_max_bus(IF_SCSI) > 0) {
929 fprintf(stderr, "qemu: too many SCSI bus\n");
930 exit(1);
931 }
932
933 esp_init(hwdef->esp_base, 2,
934 espdma_memory_read, espdma_memory_write,
935 espdma, espdma_irq, &esp_reset, &dma_enable);
936
937 qdev_connect_gpio_out(espdma, 0, esp_reset);
938 qdev_connect_gpio_out(espdma, 1, dma_enable);
939
940 if (hwdef->cs_base) {
941 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
942 slavio_irq[5]);
943 }
944
945 if (hwdef->dbri_base) {
946 /* ISDN chip with attached CS4215 audio codec */
947 /* prom space */
948 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
949 /* reg space */
950 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
951 }
952
953 if (hwdef->bpp_base) {
954 /* parallel port */
955 empty_slot_init(hwdef->bpp_base, 0x20);
956 }
957
958 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
959 RAM_size);
960
961 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
962 boot_device, RAM_size, kernel_size, graphic_width,
963 graphic_height, graphic_depth, hwdef->nvram_machine_id,
964 "Sun4m");
965
966 if (hwdef->ecc_base)
967 ecc_init(hwdef->ecc_base, slavio_irq[28],
968 hwdef->ecc_version);
969
970 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
971 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
972 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
973 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
974 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
975 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
976 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
977 if (kernel_cmdline) {
978 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
979 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
980 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
981 (uint8_t*)strdup(kernel_cmdline),
982 strlen(kernel_cmdline) + 1);
983 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
984 strlen(kernel_cmdline) + 1);
985 } else {
986 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
987 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
988 }
989 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
990 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
991 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
992 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
993 }
994
995 enum {
996 ss2_id = 0,
997 ss5_id = 32,
998 vger_id,
999 lx_id,
1000 ss4_id,
1001 scls_id,
1002 sbook_id,
1003 ss10_id = 64,
1004 ss20_id,
1005 ss600mp_id,
1006 ss1000_id = 96,
1007 ss2000_id,
1008 };
1009
1010 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1011 /* SS-5 */
1012 {
1013 .iommu_base = 0x10000000,
1014 .iommu_pad_base = 0x10004000,
1015 .iommu_pad_len = 0x0fffb000,
1016 .tcx_base = 0x50000000,
1017 .cs_base = 0x6c000000,
1018 .slavio_base = 0x70000000,
1019 .ms_kb_base = 0x71000000,
1020 .serial_base = 0x71100000,
1021 .nvram_base = 0x71200000,
1022 .fd_base = 0x71400000,
1023 .counter_base = 0x71d00000,
1024 .intctl_base = 0x71e00000,
1025 .idreg_base = 0x78000000,
1026 .dma_base = 0x78400000,
1027 .esp_base = 0x78800000,
1028 .le_base = 0x78c00000,
1029 .apc_base = 0x6a000000,
1030 .afx_base = 0x6e000000,
1031 .aux1_base = 0x71900000,
1032 .aux2_base = 0x71910000,
1033 .nvram_machine_id = 0x80,
1034 .machine_id = ss5_id,
1035 .iommu_version = 0x05000000,
1036 .max_mem = 0x10000000,
1037 .default_cpu_model = "Fujitsu MB86904",
1038 },
1039 /* SS-10 */
1040 {
1041 .iommu_base = 0xfe0000000ULL,
1042 .tcx_base = 0xe20000000ULL,
1043 .slavio_base = 0xff0000000ULL,
1044 .ms_kb_base = 0xff1000000ULL,
1045 .serial_base = 0xff1100000ULL,
1046 .nvram_base = 0xff1200000ULL,
1047 .fd_base = 0xff1700000ULL,
1048 .counter_base = 0xff1300000ULL,
1049 .intctl_base = 0xff1400000ULL,
1050 .idreg_base = 0xef0000000ULL,
1051 .dma_base = 0xef0400000ULL,
1052 .esp_base = 0xef0800000ULL,
1053 .le_base = 0xef0c00000ULL,
1054 .apc_base = 0xefa000000ULL, // XXX should not exist
1055 .aux1_base = 0xff1800000ULL,
1056 .aux2_base = 0xff1a01000ULL,
1057 .ecc_base = 0xf00000000ULL,
1058 .ecc_version = 0x10000000, // version 0, implementation 1
1059 .nvram_machine_id = 0x72,
1060 .machine_id = ss10_id,
1061 .iommu_version = 0x03000000,
1062 .max_mem = 0xf00000000ULL,
1063 .default_cpu_model = "TI SuperSparc II",
1064 },
1065 /* SS-600MP */
1066 {
1067 .iommu_base = 0xfe0000000ULL,
1068 .tcx_base = 0xe20000000ULL,
1069 .slavio_base = 0xff0000000ULL,
1070 .ms_kb_base = 0xff1000000ULL,
1071 .serial_base = 0xff1100000ULL,
1072 .nvram_base = 0xff1200000ULL,
1073 .counter_base = 0xff1300000ULL,
1074 .intctl_base = 0xff1400000ULL,
1075 .dma_base = 0xef0081000ULL,
1076 .esp_base = 0xef0080000ULL,
1077 .le_base = 0xef0060000ULL,
1078 .apc_base = 0xefa000000ULL, // XXX should not exist
1079 .aux1_base = 0xff1800000ULL,
1080 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1081 .ecc_base = 0xf00000000ULL,
1082 .ecc_version = 0x00000000, // version 0, implementation 0
1083 .nvram_machine_id = 0x71,
1084 .machine_id = ss600mp_id,
1085 .iommu_version = 0x01000000,
1086 .max_mem = 0xf00000000ULL,
1087 .default_cpu_model = "TI SuperSparc II",
1088 },
1089 /* SS-20 */
1090 {
1091 .iommu_base = 0xfe0000000ULL,
1092 .tcx_base = 0xe20000000ULL,
1093 .slavio_base = 0xff0000000ULL,
1094 .ms_kb_base = 0xff1000000ULL,
1095 .serial_base = 0xff1100000ULL,
1096 .nvram_base = 0xff1200000ULL,
1097 .fd_base = 0xff1700000ULL,
1098 .counter_base = 0xff1300000ULL,
1099 .intctl_base = 0xff1400000ULL,
1100 .idreg_base = 0xef0000000ULL,
1101 .dma_base = 0xef0400000ULL,
1102 .esp_base = 0xef0800000ULL,
1103 .le_base = 0xef0c00000ULL,
1104 .bpp_base = 0xef4800000ULL,
1105 .apc_base = 0xefa000000ULL, // XXX should not exist
1106 .aux1_base = 0xff1800000ULL,
1107 .aux2_base = 0xff1a01000ULL,
1108 .dbri_base = 0xee0000000ULL,
1109 .sx_base = 0xf80000000ULL,
1110 .vsimm = {
1111 {
1112 .reg_base = 0x9c000000ULL,
1113 .vram_base = 0xfc000000ULL
1114 }, {
1115 .reg_base = 0x90000000ULL,
1116 .vram_base = 0xf0000000ULL
1117 }, {
1118 .reg_base = 0x94000000ULL
1119 }, {
1120 .reg_base = 0x98000000ULL
1121 }
1122 },
1123 .ecc_base = 0xf00000000ULL,
1124 .ecc_version = 0x20000000, // version 0, implementation 2
1125 .nvram_machine_id = 0x72,
1126 .machine_id = ss20_id,
1127 .iommu_version = 0x13000000,
1128 .max_mem = 0xf00000000ULL,
1129 .default_cpu_model = "TI SuperSparc II",
1130 },
1131 /* Voyager */
1132 {
1133 .iommu_base = 0x10000000,
1134 .tcx_base = 0x50000000,
1135 .slavio_base = 0x70000000,
1136 .ms_kb_base = 0x71000000,
1137 .serial_base = 0x71100000,
1138 .nvram_base = 0x71200000,
1139 .fd_base = 0x71400000,
1140 .counter_base = 0x71d00000,
1141 .intctl_base = 0x71e00000,
1142 .idreg_base = 0x78000000,
1143 .dma_base = 0x78400000,
1144 .esp_base = 0x78800000,
1145 .le_base = 0x78c00000,
1146 .apc_base = 0x71300000, // pmc
1147 .aux1_base = 0x71900000,
1148 .aux2_base = 0x71910000,
1149 .nvram_machine_id = 0x80,
1150 .machine_id = vger_id,
1151 .iommu_version = 0x05000000,
1152 .max_mem = 0x10000000,
1153 .default_cpu_model = "Fujitsu MB86904",
1154 },
1155 /* LX */
1156 {
1157 .iommu_base = 0x10000000,
1158 .iommu_pad_base = 0x10004000,
1159 .iommu_pad_len = 0x0fffb000,
1160 .tcx_base = 0x50000000,
1161 .slavio_base = 0x70000000,
1162 .ms_kb_base = 0x71000000,
1163 .serial_base = 0x71100000,
1164 .nvram_base = 0x71200000,
1165 .fd_base = 0x71400000,
1166 .counter_base = 0x71d00000,
1167 .intctl_base = 0x71e00000,
1168 .idreg_base = 0x78000000,
1169 .dma_base = 0x78400000,
1170 .esp_base = 0x78800000,
1171 .le_base = 0x78c00000,
1172 .aux1_base = 0x71900000,
1173 .aux2_base = 0x71910000,
1174 .nvram_machine_id = 0x80,
1175 .machine_id = lx_id,
1176 .iommu_version = 0x04000000,
1177 .max_mem = 0x10000000,
1178 .default_cpu_model = "TI MicroSparc I",
1179 },
1180 /* SS-4 */
1181 {
1182 .iommu_base = 0x10000000,
1183 .tcx_base = 0x50000000,
1184 .cs_base = 0x6c000000,
1185 .slavio_base = 0x70000000,
1186 .ms_kb_base = 0x71000000,
1187 .serial_base = 0x71100000,
1188 .nvram_base = 0x71200000,
1189 .fd_base = 0x71400000,
1190 .counter_base = 0x71d00000,
1191 .intctl_base = 0x71e00000,
1192 .idreg_base = 0x78000000,
1193 .dma_base = 0x78400000,
1194 .esp_base = 0x78800000,
1195 .le_base = 0x78c00000,
1196 .apc_base = 0x6a000000,
1197 .aux1_base = 0x71900000,
1198 .aux2_base = 0x71910000,
1199 .nvram_machine_id = 0x80,
1200 .machine_id = ss4_id,
1201 .iommu_version = 0x05000000,
1202 .max_mem = 0x10000000,
1203 .default_cpu_model = "Fujitsu MB86904",
1204 },
1205 /* SPARCClassic */
1206 {
1207 .iommu_base = 0x10000000,
1208 .tcx_base = 0x50000000,
1209 .slavio_base = 0x70000000,
1210 .ms_kb_base = 0x71000000,
1211 .serial_base = 0x71100000,
1212 .nvram_base = 0x71200000,
1213 .fd_base = 0x71400000,
1214 .counter_base = 0x71d00000,
1215 .intctl_base = 0x71e00000,
1216 .idreg_base = 0x78000000,
1217 .dma_base = 0x78400000,
1218 .esp_base = 0x78800000,
1219 .le_base = 0x78c00000,
1220 .apc_base = 0x6a000000,
1221 .aux1_base = 0x71900000,
1222 .aux2_base = 0x71910000,
1223 .nvram_machine_id = 0x80,
1224 .machine_id = scls_id,
1225 .iommu_version = 0x05000000,
1226 .max_mem = 0x10000000,
1227 .default_cpu_model = "TI MicroSparc I",
1228 },
1229 /* SPARCbook */
1230 {
1231 .iommu_base = 0x10000000,
1232 .tcx_base = 0x50000000, // XXX
1233 .slavio_base = 0x70000000,
1234 .ms_kb_base = 0x71000000,
1235 .serial_base = 0x71100000,
1236 .nvram_base = 0x71200000,
1237 .fd_base = 0x71400000,
1238 .counter_base = 0x71d00000,
1239 .intctl_base = 0x71e00000,
1240 .idreg_base = 0x78000000,
1241 .dma_base = 0x78400000,
1242 .esp_base = 0x78800000,
1243 .le_base = 0x78c00000,
1244 .apc_base = 0x6a000000,
1245 .aux1_base = 0x71900000,
1246 .aux2_base = 0x71910000,
1247 .nvram_machine_id = 0x80,
1248 .machine_id = sbook_id,
1249 .iommu_version = 0x05000000,
1250 .max_mem = 0x10000000,
1251 .default_cpu_model = "TI MicroSparc I",
1252 },
1253 };
1254
1255 /* SPARCstation 5 hardware initialisation */
1256 static void ss5_init(ram_addr_t RAM_size,
1257 const char *boot_device,
1258 const char *kernel_filename, const char *kernel_cmdline,
1259 const char *initrd_filename, const char *cpu_model)
1260 {
1261 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1262 kernel_cmdline, initrd_filename, cpu_model);
1263 }
1264
1265 /* SPARCstation 10 hardware initialisation */
1266 static void ss10_init(ram_addr_t RAM_size,
1267 const char *boot_device,
1268 const char *kernel_filename, const char *kernel_cmdline,
1269 const char *initrd_filename, const char *cpu_model)
1270 {
1271 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1272 kernel_cmdline, initrd_filename, cpu_model);
1273 }
1274
1275 /* SPARCserver 600MP hardware initialisation */
1276 static void ss600mp_init(ram_addr_t RAM_size,
1277 const char *boot_device,
1278 const char *kernel_filename,
1279 const char *kernel_cmdline,
1280 const char *initrd_filename, const char *cpu_model)
1281 {
1282 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1283 kernel_cmdline, initrd_filename, cpu_model);
1284 }
1285
1286 /* SPARCstation 20 hardware initialisation */
1287 static void ss20_init(ram_addr_t RAM_size,
1288 const char *boot_device,
1289 const char *kernel_filename, const char *kernel_cmdline,
1290 const char *initrd_filename, const char *cpu_model)
1291 {
1292 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1293 kernel_cmdline, initrd_filename, cpu_model);
1294 }
1295
1296 /* SPARCstation Voyager hardware initialisation */
1297 static void vger_init(ram_addr_t RAM_size,
1298 const char *boot_device,
1299 const char *kernel_filename, const char *kernel_cmdline,
1300 const char *initrd_filename, const char *cpu_model)
1301 {
1302 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1303 kernel_cmdline, initrd_filename, cpu_model);
1304 }
1305
1306 /* SPARCstation LX hardware initialisation */
1307 static void ss_lx_init(ram_addr_t RAM_size,
1308 const char *boot_device,
1309 const char *kernel_filename, const char *kernel_cmdline,
1310 const char *initrd_filename, const char *cpu_model)
1311 {
1312 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1313 kernel_cmdline, initrd_filename, cpu_model);
1314 }
1315
1316 /* SPARCstation 4 hardware initialisation */
1317 static void ss4_init(ram_addr_t RAM_size,
1318 const char *boot_device,
1319 const char *kernel_filename, const char *kernel_cmdline,
1320 const char *initrd_filename, const char *cpu_model)
1321 {
1322 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1323 kernel_cmdline, initrd_filename, cpu_model);
1324 }
1325
1326 /* SPARCClassic hardware initialisation */
1327 static void scls_init(ram_addr_t RAM_size,
1328 const char *boot_device,
1329 const char *kernel_filename, const char *kernel_cmdline,
1330 const char *initrd_filename, const char *cpu_model)
1331 {
1332 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1333 kernel_cmdline, initrd_filename, cpu_model);
1334 }
1335
1336 /* SPARCbook hardware initialisation */
1337 static void sbook_init(ram_addr_t RAM_size,
1338 const char *boot_device,
1339 const char *kernel_filename, const char *kernel_cmdline,
1340 const char *initrd_filename, const char *cpu_model)
1341 {
1342 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1343 kernel_cmdline, initrd_filename, cpu_model);
1344 }
1345
1346 static QEMUMachine ss5_machine = {
1347 .name = "SS-5",
1348 .desc = "Sun4m platform, SPARCstation 5",
1349 .init = ss5_init,
1350 .use_scsi = 1,
1351 .is_default = 1,
1352 };
1353
1354 static QEMUMachine ss10_machine = {
1355 .name = "SS-10",
1356 .desc = "Sun4m platform, SPARCstation 10",
1357 .init = ss10_init,
1358 .use_scsi = 1,
1359 .max_cpus = 4,
1360 };
1361
1362 static QEMUMachine ss600mp_machine = {
1363 .name = "SS-600MP",
1364 .desc = "Sun4m platform, SPARCserver 600MP",
1365 .init = ss600mp_init,
1366 .use_scsi = 1,
1367 .max_cpus = 4,
1368 };
1369
1370 static QEMUMachine ss20_machine = {
1371 .name = "SS-20",
1372 .desc = "Sun4m platform, SPARCstation 20",
1373 .init = ss20_init,
1374 .use_scsi = 1,
1375 .max_cpus = 4,
1376 };
1377
1378 static QEMUMachine voyager_machine = {
1379 .name = "Voyager",
1380 .desc = "Sun4m platform, SPARCstation Voyager",
1381 .init = vger_init,
1382 .use_scsi = 1,
1383 };
1384
1385 static QEMUMachine ss_lx_machine = {
1386 .name = "LX",
1387 .desc = "Sun4m platform, SPARCstation LX",
1388 .init = ss_lx_init,
1389 .use_scsi = 1,
1390 };
1391
1392 static QEMUMachine ss4_machine = {
1393 .name = "SS-4",
1394 .desc = "Sun4m platform, SPARCstation 4",
1395 .init = ss4_init,
1396 .use_scsi = 1,
1397 };
1398
1399 static QEMUMachine scls_machine = {
1400 .name = "SPARCClassic",
1401 .desc = "Sun4m platform, SPARCClassic",
1402 .init = scls_init,
1403 .use_scsi = 1,
1404 };
1405
1406 static QEMUMachine sbook_machine = {
1407 .name = "SPARCbook",
1408 .desc = "Sun4m platform, SPARCbook",
1409 .init = sbook_init,
1410 .use_scsi = 1,
1411 };
1412
1413 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1414 /* SS-1000 */
1415 {
1416 .iounit_bases = {
1417 0xfe0200000ULL,
1418 0xfe1200000ULL,
1419 0xfe2200000ULL,
1420 0xfe3200000ULL,
1421 -1,
1422 },
1423 .tcx_base = 0x820000000ULL,
1424 .slavio_base = 0xf00000000ULL,
1425 .ms_kb_base = 0xf00240000ULL,
1426 .serial_base = 0xf00200000ULL,
1427 .nvram_base = 0xf00280000ULL,
1428 .counter_base = 0xf00300000ULL,
1429 .espdma_base = 0x800081000ULL,
1430 .esp_base = 0x800080000ULL,
1431 .ledma_base = 0x800040000ULL,
1432 .le_base = 0x800060000ULL,
1433 .sbi_base = 0xf02800000ULL,
1434 .nvram_machine_id = 0x80,
1435 .machine_id = ss1000_id,
1436 .iounit_version = 0x03000000,
1437 .max_mem = 0xf00000000ULL,
1438 .default_cpu_model = "TI SuperSparc II",
1439 },
1440 /* SS-2000 */
1441 {
1442 .iounit_bases = {
1443 0xfe0200000ULL,
1444 0xfe1200000ULL,
1445 0xfe2200000ULL,
1446 0xfe3200000ULL,
1447 0xfe4200000ULL,
1448 },
1449 .tcx_base = 0x820000000ULL,
1450 .slavio_base = 0xf00000000ULL,
1451 .ms_kb_base = 0xf00240000ULL,
1452 .serial_base = 0xf00200000ULL,
1453 .nvram_base = 0xf00280000ULL,
1454 .counter_base = 0xf00300000ULL,
1455 .espdma_base = 0x800081000ULL,
1456 .esp_base = 0x800080000ULL,
1457 .ledma_base = 0x800040000ULL,
1458 .le_base = 0x800060000ULL,
1459 .sbi_base = 0xf02800000ULL,
1460 .nvram_machine_id = 0x80,
1461 .machine_id = ss2000_id,
1462 .iounit_version = 0x03000000,
1463 .max_mem = 0xf00000000ULL,
1464 .default_cpu_model = "TI SuperSparc II",
1465 },
1466 };
1467
1468 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1469 {
1470 DeviceState *dev;
1471 SysBusDevice *s;
1472 unsigned int i;
1473
1474 dev = qdev_create(NULL, "sbi");
1475 qdev_init_nofail(dev);
1476
1477 s = sysbus_from_qdev(dev);
1478
1479 for (i = 0; i < MAX_CPUS; i++) {
1480 sysbus_connect_irq(s, i, *parent_irq[i]);
1481 }
1482
1483 sysbus_mmio_map(s, 0, addr);
1484
1485 return dev;
1486 }
1487
1488 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1489 const char *boot_device,
1490 const char *kernel_filename,
1491 const char *kernel_cmdline,
1492 const char *initrd_filename, const char *cpu_model)
1493 {
1494 unsigned int i;
1495 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1496 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1497 espdma_irq, ledma_irq;
1498 qemu_irq esp_reset, dma_enable;
1499 unsigned long kernel_size;
1500 void *fw_cfg;
1501 DeviceState *dev;
1502
1503 /* init CPUs */
1504 if (!cpu_model)
1505 cpu_model = hwdef->default_cpu_model;
1506
1507 for(i = 0; i < smp_cpus; i++) {
1508 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1509 }
1510
1511 for (i = smp_cpus; i < MAX_CPUS; i++)
1512 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1513
1514 /* set up devices */
1515 ram_init(0, RAM_size, hwdef->max_mem);
1516
1517 prom_init(hwdef->slavio_base, bios_name);
1518
1519 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1520
1521 for (i = 0; i < 32; i++) {
1522 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1523 }
1524 for (i = 0; i < MAX_CPUS; i++) {
1525 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1526 }
1527
1528 for (i = 0; i < MAX_IOUNITS; i++)
1529 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1530 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1531 hwdef->iounit_version,
1532 sbi_irq[0]);
1533
1534 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1535 iounits[0], &espdma_irq);
1536
1537 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1538 iounits[0], &ledma_irq);
1539
1540 if (graphic_depth != 8 && graphic_depth != 24) {
1541 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1542 exit (1);
1543 }
1544 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1545 graphic_depth);
1546
1547 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1548
1549 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1550
1551 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1552
1553 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1554 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1555 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1556 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1557 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1558 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1559
1560 if (drive_get_max_bus(IF_SCSI) > 0) {
1561 fprintf(stderr, "qemu: too many SCSI bus\n");
1562 exit(1);
1563 }
1564
1565 esp_init(hwdef->esp_base, 2,
1566 espdma_memory_read, espdma_memory_write,
1567 espdma, espdma_irq, &esp_reset, &dma_enable);
1568
1569 qdev_connect_gpio_out(espdma, 0, esp_reset);
1570 qdev_connect_gpio_out(espdma, 1, dma_enable);
1571
1572 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1573 RAM_size);
1574
1575 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1576 boot_device, RAM_size, kernel_size, graphic_width,
1577 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1578 "Sun4d");
1579
1580 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1581 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1582 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1583 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1584 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1585 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1586 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1587 if (kernel_cmdline) {
1588 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1589 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1590 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1591 (uint8_t*)strdup(kernel_cmdline),
1592 strlen(kernel_cmdline) + 1);
1593 } else {
1594 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1595 }
1596 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1597 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1598 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1599 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1600 }
1601
1602 /* SPARCserver 1000 hardware initialisation */
1603 static void ss1000_init(ram_addr_t RAM_size,
1604 const char *boot_device,
1605 const char *kernel_filename, const char *kernel_cmdline,
1606 const char *initrd_filename, const char *cpu_model)
1607 {
1608 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1609 kernel_cmdline, initrd_filename, cpu_model);
1610 }
1611
1612 /* SPARCcenter 2000 hardware initialisation */
1613 static void ss2000_init(ram_addr_t RAM_size,
1614 const char *boot_device,
1615 const char *kernel_filename, const char *kernel_cmdline,
1616 const char *initrd_filename, const char *cpu_model)
1617 {
1618 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1619 kernel_cmdline, initrd_filename, cpu_model);
1620 }
1621
1622 static QEMUMachine ss1000_machine = {
1623 .name = "SS-1000",
1624 .desc = "Sun4d platform, SPARCserver 1000",
1625 .init = ss1000_init,
1626 .use_scsi = 1,
1627 .max_cpus = 8,
1628 };
1629
1630 static QEMUMachine ss2000_machine = {
1631 .name = "SS-2000",
1632 .desc = "Sun4d platform, SPARCcenter 2000",
1633 .init = ss2000_init,
1634 .use_scsi = 1,
1635 .max_cpus = 20,
1636 };
1637
1638 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1639 /* SS-2 */
1640 {
1641 .iommu_base = 0xf8000000,
1642 .tcx_base = 0xfe000000,
1643 .slavio_base = 0xf6000000,
1644 .intctl_base = 0xf5000000,
1645 .counter_base = 0xf3000000,
1646 .ms_kb_base = 0xf0000000,
1647 .serial_base = 0xf1000000,
1648 .nvram_base = 0xf2000000,
1649 .fd_base = 0xf7200000,
1650 .dma_base = 0xf8400000,
1651 .esp_base = 0xf8800000,
1652 .le_base = 0xf8c00000,
1653 .aux1_base = 0xf7400003,
1654 .nvram_machine_id = 0x55,
1655 .machine_id = ss2_id,
1656 .max_mem = 0x10000000,
1657 .default_cpu_model = "Cypress CY7C601",
1658 },
1659 };
1660
1661 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1662 qemu_irq *parent_irq)
1663 {
1664 DeviceState *dev;
1665 SysBusDevice *s;
1666 unsigned int i;
1667
1668 dev = qdev_create(NULL, "sun4c_intctl");
1669 qdev_init_nofail(dev);
1670
1671 s = sysbus_from_qdev(dev);
1672
1673 for (i = 0; i < MAX_PILS; i++) {
1674 sysbus_connect_irq(s, i, parent_irq[i]);
1675 }
1676 sysbus_mmio_map(s, 0, addr);
1677
1678 return dev;
1679 }
1680
1681 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1682 const char *boot_device,
1683 const char *kernel_filename,
1684 const char *kernel_cmdline,
1685 const char *initrd_filename, const char *cpu_model)
1686 {
1687 void *iommu, *espdma, *ledma, *nvram;
1688 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1689 qemu_irq esp_reset, dma_enable;
1690 qemu_irq fdc_tc;
1691 unsigned long kernel_size;
1692 DriveInfo *fd[MAX_FD];
1693 void *fw_cfg;
1694 DeviceState *dev;
1695 unsigned int i;
1696
1697 /* init CPU */
1698 if (!cpu_model)
1699 cpu_model = hwdef->default_cpu_model;
1700
1701 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1702
1703 /* set up devices */
1704 ram_init(0, RAM_size, hwdef->max_mem);
1705
1706 prom_init(hwdef->slavio_base, bios_name);
1707
1708 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1709
1710 for (i = 0; i < 8; i++) {
1711 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1712 }
1713
1714 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1715 slavio_irq[1]);
1716
1717 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1718 iommu, &espdma_irq);
1719
1720 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1721 slavio_irq[3], iommu, &ledma_irq);
1722
1723 if (graphic_depth != 8 && graphic_depth != 24) {
1724 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1725 exit (1);
1726 }
1727 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1728 graphic_depth);
1729
1730 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1731
1732 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1733
1734 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1735 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1736 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1737 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1738 escc_init(hwdef->serial_base, slavio_irq[1],
1739 slavio_irq[1], serial_hds[0], serial_hds[1],
1740 ESCC_CLOCK, 1);
1741
1742 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1743
1744 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1745 /* there is zero or one floppy drive */
1746 memset(fd, 0, sizeof(fd));
1747 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1748 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1749 &fdc_tc);
1750 }
1751
1752 if (drive_get_max_bus(IF_SCSI) > 0) {
1753 fprintf(stderr, "qemu: too many SCSI bus\n");
1754 exit(1);
1755 }
1756
1757 esp_init(hwdef->esp_base, 2,
1758 espdma_memory_read, espdma_memory_write,
1759 espdma, espdma_irq, &esp_reset, &dma_enable);
1760
1761 qdev_connect_gpio_out(espdma, 0, esp_reset);
1762 qdev_connect_gpio_out(espdma, 1, dma_enable);
1763
1764 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1765 RAM_size);
1766
1767 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1768 boot_device, RAM_size, kernel_size, graphic_width,
1769 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1770 "Sun4c");
1771
1772 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1773 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1774 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1775 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1776 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1777 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1778 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1779 if (kernel_cmdline) {
1780 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1781 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1782 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1783 (uint8_t*)strdup(kernel_cmdline),
1784 strlen(kernel_cmdline) + 1);
1785 } else {
1786 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1787 }
1788 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1789 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1790 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1791 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1792 }
1793
1794 /* SPARCstation 2 hardware initialisation */
1795 static void ss2_init(ram_addr_t RAM_size,
1796 const char *boot_device,
1797 const char *kernel_filename, const char *kernel_cmdline,
1798 const char *initrd_filename, const char *cpu_model)
1799 {
1800 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1801 kernel_cmdline, initrd_filename, cpu_model);
1802 }
1803
1804 static QEMUMachine ss2_machine = {
1805 .name = "SS-2",
1806 .desc = "Sun4c platform, SPARCstation 2",
1807 .init = ss2_init,
1808 .use_scsi = 1,
1809 };
1810
1811 static void ss2_machine_init(void)
1812 {
1813 qemu_register_machine(&ss5_machine);
1814 qemu_register_machine(&ss10_machine);
1815 qemu_register_machine(&ss600mp_machine);
1816 qemu_register_machine(&ss20_machine);
1817 qemu_register_machine(&voyager_machine);
1818 qemu_register_machine(&ss_lx_machine);
1819 qemu_register_machine(&ss4_machine);
1820 qemu_register_machine(&scls_machine);
1821 qemu_register_machine(&sbook_machine);
1822 qemu_register_machine(&ss1000_machine);
1823 qemu_register_machine(&ss2000_machine);
1824 qemu_register_machine(&ss2_machine);
1825 }
1826
1827 machine_init(ss2_machine_init);
various patches