?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Record which USBDevice USBPort belongs too.
[qemu/lumag.git] / hw / usb-ohci.c
blob240e8409af82ebd1ff43e78756b21e59fabe0ce0
1 /*
2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 *
20 * TODO:
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
24 * all together.
25 * o Handle unrecoverable errors properly
26 * o BIOS work to boot from USB storage
27 */
28
29 #include "hw.h"
30 #include "qemu-timer.h"
31 #include "usb.h"
32 #include "pci.h"
33 #include "usb-ohci.h"
34 #include "sysbus.h"
35 #include "qdev-addr.h"
36
37 //#define DEBUG_OHCI
38 /* Dump packet contents. */
39 //#define DEBUG_PACKET
40 //#define DEBUG_ISOCH
41 /* This causes frames to occur 1000x slower */
42 //#define OHCI_TIME_WARP 1
43
44 #ifdef DEBUG_OHCI
45 #define DPRINTF printf
46 #else
47 #define DPRINTF(...)
48 #endif
49
50 /* Number of Downstream Ports on the root hub. */
51
52 #define OHCI_MAX_PORTS 15
53
54 static int64_t usb_frame_time;
55 static int64_t usb_bit_time;
56
57 typedef struct OHCIPort {
58 USBPort port;
59 uint32_t ctrl;
60 } OHCIPort;
61
62 typedef struct {
63 USBBus bus;
64 qemu_irq irq;
65 int mem;
66 int num_ports;
67 const char *name;
68
69 QEMUTimer *eof_timer;
70 int64_t sof_time;
71
72 /* OHCI state */
73 /* Control partition */
74 uint32_t ctl, status;
75 uint32_t intr_status;
76 uint32_t intr;
77
78 /* memory pointer partition */
79 uint32_t hcca;
80 uint32_t ctrl_head, ctrl_cur;
81 uint32_t bulk_head, bulk_cur;
82 uint32_t per_cur;
83 uint32_t done;
84 int done_count;
85
86 /* Frame counter partition */
87 uint32_t fsmps:15;
88 uint32_t fit:1;
89 uint32_t fi:14;
90 uint32_t frt:1;
91 uint16_t frame_number;
92 uint16_t padding;
93 uint32_t pstart;
94 uint32_t lst;
95
96 /* Root Hub partition */
97 uint32_t rhdesc_a, rhdesc_b;
98 uint32_t rhstatus;
99 OHCIPort rhport[OHCI_MAX_PORTS];
100
101 /* PXA27x Non-OHCI events */
102 uint32_t hstatus;
103 uint32_t hmask;
104 uint32_t hreset;
105 uint32_t htest;
106
107 /* SM501 local memory offset */
108 target_phys_addr_t localmem_base;
109
110 /* Active packets. */
111 uint32_t old_ctl;
112 USBPacket usb_packet;
113 uint8_t usb_buf[8192];
114 uint32_t async_td;
115 int async_complete;
116
117 } OHCIState;
118
119 /* Host Controller Communications Area */
120 struct ohci_hcca {
121 uint32_t intr[32];
122 uint16_t frame, pad;
123 uint32_t done;
124 };
125
126 static void ohci_bus_stop(OHCIState *ohci);
127
128 /* Bitfields for the first word of an Endpoint Desciptor. */
129 #define OHCI_ED_FA_SHIFT 0
130 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
131 #define OHCI_ED_EN_SHIFT 7
132 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
133 #define OHCI_ED_D_SHIFT 11
134 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
135 #define OHCI_ED_S (1<<13)
136 #define OHCI_ED_K (1<<14)
137 #define OHCI_ED_F (1<<15)
138 #define OHCI_ED_MPS_SHIFT 16
139 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
140
141 /* Flags in the head field of an Endpoint Desciptor. */
142 #define OHCI_ED_H 1
143 #define OHCI_ED_C 2
144
145 /* Bitfields for the first word of a Transfer Desciptor. */
146 #define OHCI_TD_R (1<<18)
147 #define OHCI_TD_DP_SHIFT 19
148 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
149 #define OHCI_TD_DI_SHIFT 21
150 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
151 #define OHCI_TD_T0 (1<<24)
152 #define OHCI_TD_T1 (1<<24)
153 #define OHCI_TD_EC_SHIFT 26
154 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
155 #define OHCI_TD_CC_SHIFT 28
156 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
157
158 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
159 /* CC & DI - same as in the General Transfer Desciptor */
160 #define OHCI_TD_SF_SHIFT 0
161 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
162 #define OHCI_TD_FC_SHIFT 24
163 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
164
165 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
166 #define OHCI_TD_PSW_CC_SHIFT 12
167 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
168 #define OHCI_TD_PSW_SIZE_SHIFT 0
169 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
170
171 #define OHCI_PAGE_MASK 0xfffff000
172 #define OHCI_OFFSET_MASK 0xfff
173
174 #define OHCI_DPTR_MASK 0xfffffff0
175
176 #define OHCI_BM(val, field) \
177 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
178
179 #define OHCI_SET_BM(val, field, newval) do { \
180 val &= ~OHCI_##field##_MASK; \
181 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
182 } while(0)
183
184 /* endpoint descriptor */
185 struct ohci_ed {
186 uint32_t flags;
187 uint32_t tail;
188 uint32_t head;
189 uint32_t next;
190 };
191
192 /* General transfer descriptor */
193 struct ohci_td {
194 uint32_t flags;
195 uint32_t cbp;
196 uint32_t next;
197 uint32_t be;
198 };
199
200 /* Isochronous transfer descriptor */
201 struct ohci_iso_td {
202 uint32_t flags;
203 uint32_t bp;
204 uint32_t next;
205 uint32_t be;
206 uint16_t offset[8];
207 };
208
209 #define USB_HZ 12000000
210
211 /* OHCI Local stuff */
212 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
213 #define OHCI_CTL_PLE (1<<2)
214 #define OHCI_CTL_IE (1<<3)
215 #define OHCI_CTL_CLE (1<<4)
216 #define OHCI_CTL_BLE (1<<5)
217 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
218 #define OHCI_USB_RESET 0x00
219 #define OHCI_USB_RESUME 0x40
220 #define OHCI_USB_OPERATIONAL 0x80
221 #define OHCI_USB_SUSPEND 0xc0
222 #define OHCI_CTL_IR (1<<8)
223 #define OHCI_CTL_RWC (1<<9)
224 #define OHCI_CTL_RWE (1<<10)
225
226 #define OHCI_STATUS_HCR (1<<0)
227 #define OHCI_STATUS_CLF (1<<1)
228 #define OHCI_STATUS_BLF (1<<2)
229 #define OHCI_STATUS_OCR (1<<3)
230 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
231
232 #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
233 #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
234 #define OHCI_INTR_SF (1<<2) /* Start of frame */
235 #define OHCI_INTR_RD (1<<3) /* Resume detect */
236 #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
237 #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
238 #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
239 #define OHCI_INTR_OC (1<<30) /* Ownership change */
240 #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
241
242 #define OHCI_HCCA_SIZE 0x100
243 #define OHCI_HCCA_MASK 0xffffff00
244
245 #define OHCI_EDPTR_MASK 0xfffffff0
246
247 #define OHCI_FMI_FI 0x00003fff
248 #define OHCI_FMI_FSMPS 0xffff0000
249 #define OHCI_FMI_FIT 0x80000000
250
251 #define OHCI_FR_RT (1<<31)
252
253 #define OHCI_LS_THRESH 0x628
254
255 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
256 #define OHCI_RHA_PSM (1<<8)
257 #define OHCI_RHA_NPS (1<<9)
258 #define OHCI_RHA_DT (1<<10)
259 #define OHCI_RHA_OCPM (1<<11)
260 #define OHCI_RHA_NOCP (1<<12)
261 #define OHCI_RHA_POTPGT_MASK 0xff000000
262
263 #define OHCI_RHS_LPS (1<<0)
264 #define OHCI_RHS_OCI (1<<1)
265 #define OHCI_RHS_DRWE (1<<15)
266 #define OHCI_RHS_LPSC (1<<16)
267 #define OHCI_RHS_OCIC (1<<17)
268 #define OHCI_RHS_CRWE (1<<31)
269
270 #define OHCI_PORT_CCS (1<<0)
271 #define OHCI_PORT_PES (1<<1)
272 #define OHCI_PORT_PSS (1<<2)
273 #define OHCI_PORT_POCI (1<<3)
274 #define OHCI_PORT_PRS (1<<4)
275 #define OHCI_PORT_PPS (1<<8)
276 #define OHCI_PORT_LSDA (1<<9)
277 #define OHCI_PORT_CSC (1<<16)
278 #define OHCI_PORT_PESC (1<<17)
279 #define OHCI_PORT_PSSC (1<<18)
280 #define OHCI_PORT_OCIC (1<<19)
281 #define OHCI_PORT_PRSC (1<<20)
282 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
283 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
284
285 #define OHCI_TD_DIR_SETUP 0x0
286 #define OHCI_TD_DIR_OUT 0x1
287 #define OHCI_TD_DIR_IN 0x2
288 #define OHCI_TD_DIR_RESERVED 0x3
289
290 #define OHCI_CC_NOERROR 0x0
291 #define OHCI_CC_CRC 0x1
292 #define OHCI_CC_BITSTUFFING 0x2
293 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
294 #define OHCI_CC_STALL 0x4
295 #define OHCI_CC_DEVICENOTRESPONDING 0x5
296 #define OHCI_CC_PIDCHECKFAILURE 0x6
297 #define OHCI_CC_UNDEXPETEDPID 0x7
298 #define OHCI_CC_DATAOVERRUN 0x8
299 #define OHCI_CC_DATAUNDERRUN 0x9
300 #define OHCI_CC_BUFFEROVERRUN 0xc
301 #define OHCI_CC_BUFFERUNDERRUN 0xd
302
303 #define OHCI_HRESET_FSBIR (1 << 0)
304
305 /* Update IRQ levels */
306 static inline void ohci_intr_update(OHCIState *ohci)
307 {
308 int level = 0;
309
310 if ((ohci->intr & OHCI_INTR_MIE) &&
311 (ohci->intr_status & ohci->intr))
312 level = 1;
313
314 qemu_set_irq(ohci->irq, level);
315 }
316
317 /* Set an interrupt */
318 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
319 {
320 ohci->intr_status |= intr;
321 ohci_intr_update(ohci);
322 }
323
324 /* Attach or detach a device on a root hub port. */
325 static void ohci_attach(USBPort *port1, USBDevice *dev)
326 {
327 OHCIState *s = port1->opaque;
328 OHCIPort *port = &s->rhport[port1->index];
329 uint32_t old_state = port->ctrl;
330
331 if (dev) {
332 if (port->port.dev) {
333 usb_attach(port1, NULL);
334 }
335 /* set connect status */
336 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
337
338 /* update speed */
339 if (dev->speed == USB_SPEED_LOW)
340 port->ctrl |= OHCI_PORT_LSDA;
341 else
342 port->ctrl &= ~OHCI_PORT_LSDA;
343 port->port.dev = dev;
344
345 /* notify of remote-wakeup */
346 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND)
347 ohci_set_interrupt(s, OHCI_INTR_RD);
348
349 /* send the attach message */
350 usb_send_msg(dev, USB_MSG_ATTACH);
351 DPRINTF("usb-ohci: Attached port %d\n", port1->index);
352 } else {
353 /* set connect status */
354 if (port->ctrl & OHCI_PORT_CCS) {
355 port->ctrl &= ~OHCI_PORT_CCS;
356 port->ctrl |= OHCI_PORT_CSC;
357 }
358 /* disable port */
359 if (port->ctrl & OHCI_PORT_PES) {
360 port->ctrl &= ~OHCI_PORT_PES;
361 port->ctrl |= OHCI_PORT_PESC;
362 }
363 dev = port->port.dev;
364 if (dev) {
365 /* send the detach message */
366 usb_send_msg(dev, USB_MSG_DETACH);
367 }
368 port->port.dev = NULL;
369 DPRINTF("usb-ohci: Detached port %d\n", port1->index);
370 }
371
372 if (old_state != port->ctrl)
373 ohci_set_interrupt(s, OHCI_INTR_RHSC);
374 }
375
376 /* Reset the controller */
377 static void ohci_reset(void *opaque)
378 {
379 OHCIState *ohci = opaque;
380 OHCIPort *port;
381 int i;
382
383 ohci_bus_stop(ohci);
384 ohci->ctl = 0;
385 ohci->old_ctl = 0;
386 ohci->status = 0;
387 ohci->intr_status = 0;
388 ohci->intr = OHCI_INTR_MIE;
389
390 ohci->hcca = 0;
391 ohci->ctrl_head = ohci->ctrl_cur = 0;
392 ohci->bulk_head = ohci->bulk_cur = 0;
393 ohci->per_cur = 0;
394 ohci->done = 0;
395 ohci->done_count = 7;
396
397 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
398 * I took the value linux sets ...
399 */
400 ohci->fsmps = 0x2778;
401 ohci->fi = 0x2edf;
402 ohci->fit = 0;
403 ohci->frt = 0;
404 ohci->frame_number = 0;
405 ohci->pstart = 0;
406 ohci->lst = OHCI_LS_THRESH;
407
408 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
409 ohci->rhdesc_b = 0x0; /* Impl. specific */
410 ohci->rhstatus = 0;
411
412 for (i = 0; i < ohci->num_ports; i++)
413 {
414 port = &ohci->rhport[i];
415 port->ctrl = 0;
416 if (port->port.dev)
417 ohci_attach(&port->port, port->port.dev);
418 }
419 if (ohci->async_td) {
420 usb_cancel_packet(&ohci->usb_packet);
421 ohci->async_td = 0;
422 }
423 DPRINTF("usb-ohci: Reset %s\n", ohci->name);
424 }
425
426 /* Get an array of dwords from main memory */
427 static inline int get_dwords(OHCIState *ohci,
428 uint32_t addr, uint32_t *buf, int num)
429 {
430 int i;
431
432 addr += ohci->localmem_base;
433
434 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
435 cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0);
436 *buf = le32_to_cpu(*buf);
437 }
438
439 return 1;
440 }
441
442 /* Put an array of dwords in to main memory */
443 static inline int put_dwords(OHCIState *ohci,
444 uint32_t addr, uint32_t *buf, int num)
445 {
446 int i;
447
448 addr += ohci->localmem_base;
449
450 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
451 uint32_t tmp = cpu_to_le32(*buf);
452 cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1);
453 }
454
455 return 1;
456 }
457
458 /* Get an array of words from main memory */
459 static inline int get_words(OHCIState *ohci,
460 uint32_t addr, uint16_t *buf, int num)
461 {
462 int i;
463
464 addr += ohci->localmem_base;
465
466 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
467 cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0);
468 *buf = le16_to_cpu(*buf);
469 }
470
471 return 1;
472 }
473
474 /* Put an array of words in to main memory */
475 static inline int put_words(OHCIState *ohci,
476 uint32_t addr, uint16_t *buf, int num)
477 {
478 int i;
479
480 addr += ohci->localmem_base;
481
482 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
483 uint16_t tmp = cpu_to_le16(*buf);
484 cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1);
485 }
486
487 return 1;
488 }
489
490 static inline int ohci_read_ed(OHCIState *ohci,
491 uint32_t addr, struct ohci_ed *ed)
492 {
493 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
494 }
495
496 static inline int ohci_read_td(OHCIState *ohci,
497 uint32_t addr, struct ohci_td *td)
498 {
499 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
500 }
501
502 static inline int ohci_read_iso_td(OHCIState *ohci,
503 uint32_t addr, struct ohci_iso_td *td)
504 {
505 return (get_dwords(ohci, addr, (uint32_t *)td, 4) &&
506 get_words(ohci, addr + 16, td->offset, 8));
507 }
508
509 static inline int ohci_read_hcca(OHCIState *ohci,
510 uint32_t addr, struct ohci_hcca *hcca)
511 {
512 cpu_physical_memory_rw(addr + ohci->localmem_base,
513 (uint8_t *)hcca, sizeof(*hcca), 0);
514 return 1;
515 }
516
517 static inline int ohci_put_ed(OHCIState *ohci,
518 uint32_t addr, struct ohci_ed *ed)
519 {
520 return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
521 }
522
523 static inline int ohci_put_td(OHCIState *ohci,
524 uint32_t addr, struct ohci_td *td)
525 {
526 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
527 }
528
529 static inline int ohci_put_iso_td(OHCIState *ohci,
530 uint32_t addr, struct ohci_iso_td *td)
531 {
532 return (put_dwords(ohci, addr, (uint32_t *)td, 4) &&
533 put_words(ohci, addr + 16, td->offset, 8));
534 }
535
536 static inline int ohci_put_hcca(OHCIState *ohci,
537 uint32_t addr, struct ohci_hcca *hcca)
538 {
539 cpu_physical_memory_rw(addr + ohci->localmem_base,
540 (uint8_t *)hcca, sizeof(*hcca), 1);
541 return 1;
542 }
543
544 /* Read/Write the contents of a TD from/to main memory. */
545 static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
546 uint8_t *buf, int len, int write)
547 {
548 uint32_t ptr;
549 uint32_t n;
550
551 ptr = td->cbp;
552 n = 0x1000 - (ptr & 0xfff);
553 if (n > len)
554 n = len;
555 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
556 if (n == len)
557 return;
558 ptr = td->be & ~0xfffu;
559 buf += n;
560 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
561 }
562
563 /* Read/Write the contents of an ISO TD from/to main memory. */
564 static void ohci_copy_iso_td(OHCIState *ohci,
565 uint32_t start_addr, uint32_t end_addr,
566 uint8_t *buf, int len, int write)
567 {
568 uint32_t ptr;
569 uint32_t n;
570
571 ptr = start_addr;
572 n = 0x1000 - (ptr & 0xfff);
573 if (n > len)
574 n = len;
575 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
576 if (n == len)
577 return;
578 ptr = end_addr & ~0xfffu;
579 buf += n;
580 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
581 }
582
583 static void ohci_process_lists(OHCIState *ohci, int completion);
584
585 static void ohci_async_complete_packet(USBPacket *packet, void *opaque)
586 {
587 OHCIState *ohci = opaque;
588 #ifdef DEBUG_PACKET
589 DPRINTF("Async packet complete\n");
590 #endif
591 ohci->async_complete = 1;
592 ohci_process_lists(ohci, 1);
593 }
594
595 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
596
597 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
598 int completion)
599 {
600 int dir;
601 size_t len = 0;
602 #ifdef DEBUG_ISOCH
603 const char *str = NULL;
604 #endif
605 int pid;
606 int ret;
607 int i;
608 USBDevice *dev;
609 struct ohci_iso_td iso_td;
610 uint32_t addr;
611 uint16_t starting_frame;
612 int16_t relative_frame_number;
613 int frame_count;
614 uint32_t start_offset, next_offset, end_offset = 0;
615 uint32_t start_addr, end_addr;
616
617 addr = ed->head & OHCI_DPTR_MASK;
618
619 if (!ohci_read_iso_td(ohci, addr, &iso_td)) {
620 printf("usb-ohci: ISO_TD read error at %x\n", addr);
621 return 0;
622 }
623
624 starting_frame = OHCI_BM(iso_td.flags, TD_SF);
625 frame_count = OHCI_BM(iso_td.flags, TD_FC);
626 relative_frame_number = USUB(ohci->frame_number, starting_frame);
627
628 #ifdef DEBUG_ISOCH
629 printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
630 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
631 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
632 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
633 "frame_number 0x%.8x starting_frame 0x%.8x\n"
634 "frame_count 0x%.8x relative %d\n"
635 "di 0x%.8x cc 0x%.8x\n",
636 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
637 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
638 iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3],
639 iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7],
640 ohci->frame_number, starting_frame,
641 frame_count, relative_frame_number,
642 OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC));
643 #endif
644
645 if (relative_frame_number < 0) {
646 DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
647 return 1;
648 } else if (relative_frame_number > frame_count) {
649 /* ISO TD expired - retire the TD to the Done Queue and continue with
650 the next ISO TD of the same ED */
651 DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
652 frame_count);
653 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
654 ed->head &= ~OHCI_DPTR_MASK;
655 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
656 iso_td.next = ohci->done;
657 ohci->done = addr;
658 i = OHCI_BM(iso_td.flags, TD_DI);
659 if (i < ohci->done_count)
660 ohci->done_count = i;
661 ohci_put_iso_td(ohci, addr, &iso_td);
662 return 0;
663 }
664
665 dir = OHCI_BM(ed->flags, ED_D);
666 switch (dir) {
667 case OHCI_TD_DIR_IN:
668 #ifdef DEBUG_ISOCH
669 str = "in";
670 #endif
671 pid = USB_TOKEN_IN;
672 break;
673 case OHCI_TD_DIR_OUT:
674 #ifdef DEBUG_ISOCH
675 str = "out";
676 #endif
677 pid = USB_TOKEN_OUT;
678 break;
679 case OHCI_TD_DIR_SETUP:
680 #ifdef DEBUG_ISOCH
681 str = "setup";
682 #endif
683 pid = USB_TOKEN_SETUP;
684 break;
685 default:
686 printf("usb-ohci: Bad direction %d\n", dir);
687 return 1;
688 }
689
690 if (!iso_td.bp || !iso_td.be) {
691 printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
692 return 1;
693 }
694
695 start_offset = iso_td.offset[relative_frame_number];
696 next_offset = iso_td.offset[relative_frame_number + 1];
697
698 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
699 ((relative_frame_number < frame_count) &&
700 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
701 printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
702 start_offset, next_offset);
703 return 1;
704 }
705
706 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
707 printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
708 start_offset, next_offset);
709 return 1;
710 }
711
712 if ((start_offset & 0x1000) == 0) {
713 start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
714 (start_offset & OHCI_OFFSET_MASK);
715 } else {
716 start_addr = (iso_td.be & OHCI_PAGE_MASK) |
717 (start_offset & OHCI_OFFSET_MASK);
718 }
719
720 if (relative_frame_number < frame_count) {
721 end_offset = next_offset - 1;
722 if ((end_offset & 0x1000) == 0) {
723 end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
724 (end_offset & OHCI_OFFSET_MASK);
725 } else {
726 end_addr = (iso_td.be & OHCI_PAGE_MASK) |
727 (end_offset & OHCI_OFFSET_MASK);
728 }
729 } else {
730 /* Last packet in the ISO TD */
731 end_addr = iso_td.be;
732 }
733
734 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
735 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
736 - (start_addr & OHCI_OFFSET_MASK);
737 } else {
738 len = end_addr - start_addr + 1;
739 }
740
741 if (len && dir != OHCI_TD_DIR_IN) {
742 ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 0);
743 }
744
745 if (completion) {
746 ret = ohci->usb_packet.len;
747 } else {
748 ret = USB_RET_NODEV;
749 for (i = 0; i < ohci->num_ports; i++) {
750 dev = ohci->rhport[i].port.dev;
751 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
752 continue;
753 ohci->usb_packet.pid = pid;
754 ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
755 ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
756 ohci->usb_packet.data = ohci->usb_buf;
757 ohci->usb_packet.len = len;
758 ohci->usb_packet.complete_cb = ohci_async_complete_packet;
759 ohci->usb_packet.complete_opaque = ohci;
760 ret = dev->info->handle_packet(dev, &ohci->usb_packet);
761 if (ret != USB_RET_NODEV)
762 break;
763 }
764
765 if (ret == USB_RET_ASYNC) {
766 return 1;
767 }
768 }
769
770 #ifdef DEBUG_ISOCH
771 printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
772 start_offset, end_offset, start_addr, end_addr, str, len, ret);
773 #endif
774
775 /* Writeback */
776 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
777 /* IN transfer succeeded */
778 ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 1);
779 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
780 OHCI_CC_NOERROR);
781 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
782 } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
783 /* OUT transfer succeeded */
784 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
785 OHCI_CC_NOERROR);
786 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
787 } else {
788 if (ret > (ssize_t) len) {
789 printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
790 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
791 OHCI_CC_DATAOVERRUN);
792 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
793 len);
794 } else if (ret >= 0) {
795 printf("usb-ohci: DataUnderrun %d\n", ret);
796 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
797 OHCI_CC_DATAUNDERRUN);
798 } else {
799 switch (ret) {
800 case USB_RET_NODEV:
801 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
802 OHCI_CC_DEVICENOTRESPONDING);
803 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
804 0);
805 break;
806 case USB_RET_NAK:
807 case USB_RET_STALL:
808 printf("usb-ohci: got NAK/STALL %d\n", ret);
809 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
810 OHCI_CC_STALL);
811 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
812 0);
813 break;
814 default:
815 printf("usb-ohci: Bad device response %d\n", ret);
816 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
817 OHCI_CC_UNDEXPETEDPID);
818 break;
819 }
820 }
821 }
822
823 if (relative_frame_number == frame_count) {
824 /* Last data packet of ISO TD - retire the TD to the Done Queue */
825 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
826 ed->head &= ~OHCI_DPTR_MASK;
827 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
828 iso_td.next = ohci->done;
829 ohci->done = addr;
830 i = OHCI_BM(iso_td.flags, TD_DI);
831 if (i < ohci->done_count)
832 ohci->done_count = i;
833 }
834 ohci_put_iso_td(ohci, addr, &iso_td);
835 return 1;
836 }
837
838 /* Service a transport descriptor.
839 Returns nonzero to terminate processing of this endpoint. */
840
841 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
842 {
843 int dir;
844 size_t len = 0;
845 #ifdef DEBUG_PACKET
846 const char *str = NULL;
847 #endif
848 int pid;
849 int ret;
850 int i;
851 USBDevice *dev;
852 struct ohci_td td;
853 uint32_t addr;
854 int flag_r;
855 int completion;
856
857 addr = ed->head & OHCI_DPTR_MASK;
858 /* See if this TD has already been submitted to the device. */
859 completion = (addr == ohci->async_td);
860 if (completion && !ohci->async_complete) {
861 #ifdef DEBUG_PACKET
862 DPRINTF("Skipping async TD\n");
863 #endif
864 return 1;
865 }
866 if (!ohci_read_td(ohci, addr, &td)) {
867 fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
868 return 0;
869 }
870
871 dir = OHCI_BM(ed->flags, ED_D);
872 switch (dir) {
873 case OHCI_TD_DIR_OUT:
874 case OHCI_TD_DIR_IN:
875 /* Same value. */
876 break;
877 default:
878 dir = OHCI_BM(td.flags, TD_DP);
879 break;
880 }
881
882 switch (dir) {
883 case OHCI_TD_DIR_IN:
884 #ifdef DEBUG_PACKET
885 str = "in";
886 #endif
887 pid = USB_TOKEN_IN;
888 break;
889 case OHCI_TD_DIR_OUT:
890 #ifdef DEBUG_PACKET
891 str = "out";
892 #endif
893 pid = USB_TOKEN_OUT;
894 break;
895 case OHCI_TD_DIR_SETUP:
896 #ifdef DEBUG_PACKET
897 str = "setup";
898 #endif
899 pid = USB_TOKEN_SETUP;
900 break;
901 default:
902 fprintf(stderr, "usb-ohci: Bad direction\n");
903 return 1;
904 }
905 if (td.cbp && td.be) {
906 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
907 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
908 } else {
909 len = (td.be - td.cbp) + 1;
910 }
911
912 if (len && dir != OHCI_TD_DIR_IN && !completion) {
913 ohci_copy_td(ohci, &td, ohci->usb_buf, len, 0);
914 }
915 }
916
917 flag_r = (td.flags & OHCI_TD_R) != 0;
918 #ifdef DEBUG_PACKET
919 DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
920 addr, (int64_t)len, str, flag_r, td.cbp, td.be);
921
922 if (len > 0 && dir != OHCI_TD_DIR_IN) {
923 DPRINTF(" data:");
924 for (i = 0; i < len; i++)
925 printf(" %.2x", ohci->usb_buf[i]);
926 DPRINTF("\n");
927 }
928 #endif
929 if (completion) {
930 ret = ohci->usb_packet.len;
931 ohci->async_td = 0;
932 ohci->async_complete = 0;
933 } else {
934 ret = USB_RET_NODEV;
935 for (i = 0; i < ohci->num_ports; i++) {
936 dev = ohci->rhport[i].port.dev;
937 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
938 continue;
939
940 if (ohci->async_td) {
941 /* ??? The hardware should allow one active packet per
942 endpoint. We only allow one active packet per controller.
943 This should be sufficient as long as devices respond in a
944 timely manner.
945 */
946 #ifdef DEBUG_PACKET
947 DPRINTF("Too many pending packets\n");
948 #endif
949 return 1;
950 }
951 ohci->usb_packet.pid = pid;
952 ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
953 ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
954 ohci->usb_packet.data = ohci->usb_buf;
955 ohci->usb_packet.len = len;
956 ohci->usb_packet.complete_cb = ohci_async_complete_packet;
957 ohci->usb_packet.complete_opaque = ohci;
958 ret = dev->info->handle_packet(dev, &ohci->usb_packet);
959 if (ret != USB_RET_NODEV)
960 break;
961 }
962 #ifdef DEBUG_PACKET
963 DPRINTF("ret=%d\n", ret);
964 #endif
965 if (ret == USB_RET_ASYNC) {
966 ohci->async_td = addr;
967 return 1;
968 }
969 }
970 if (ret >= 0) {
971 if (dir == OHCI_TD_DIR_IN) {
972 ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
973 #ifdef DEBUG_PACKET
974 DPRINTF(" data:");
975 for (i = 0; i < ret; i++)
976 printf(" %.2x", ohci->usb_buf[i]);
977 DPRINTF("\n");
978 #endif
979 } else {
980 ret = len;
981 }
982 }
983
984 /* Writeback */
985 if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
986 /* Transmission succeeded. */
987 if (ret == len) {
988 td.cbp = 0;
989 } else {
990 td.cbp += ret;
991 if ((td.cbp & 0xfff) + ret > 0xfff) {
992 td.cbp &= 0xfff;
993 td.cbp |= td.be & ~0xfff;
994 }
995 }
996 td.flags |= OHCI_TD_T1;
997 td.flags ^= OHCI_TD_T0;
998 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
999 OHCI_SET_BM(td.flags, TD_EC, 0);
1000
1001 ed->head &= ~OHCI_ED_C;
1002 if (td.flags & OHCI_TD_T0)
1003 ed->head |= OHCI_ED_C;
1004 } else {
1005 if (ret >= 0) {
1006 DPRINTF("usb-ohci: Underrun\n");
1007 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
1008 } else {
1009 switch (ret) {
1010 case USB_RET_NODEV:
1011 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
1012 case USB_RET_NAK:
1013 DPRINTF("usb-ohci: got NAK\n");
1014 return 1;
1015 case USB_RET_STALL:
1016 DPRINTF("usb-ohci: got STALL\n");
1017 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
1018 break;
1019 case USB_RET_BABBLE:
1020 DPRINTF("usb-ohci: got BABBLE\n");
1021 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
1022 break;
1023 default:
1024 fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
1025 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
1026 OHCI_SET_BM(td.flags, TD_EC, 3);
1027 break;
1028 }
1029 }
1030 ed->head |= OHCI_ED_H;
1031 }
1032
1033 /* Retire this TD */
1034 ed->head &= ~OHCI_DPTR_MASK;
1035 ed->head |= td.next & OHCI_DPTR_MASK;
1036 td.next = ohci->done;
1037 ohci->done = addr;
1038 i = OHCI_BM(td.flags, TD_DI);
1039 if (i < ohci->done_count)
1040 ohci->done_count = i;
1041 ohci_put_td(ohci, addr, &td);
1042 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
1043 }
1044
1045 /* Service an endpoint list. Returns nonzero if active TD were found. */
1046 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
1047 {
1048 struct ohci_ed ed;
1049 uint32_t next_ed;
1050 uint32_t cur;
1051 int active;
1052
1053 active = 0;
1054
1055 if (head == 0)
1056 return 0;
1057
1058 for (cur = head; cur; cur = next_ed) {
1059 if (!ohci_read_ed(ohci, cur, &ed)) {
1060 fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
1061 return 0;
1062 }
1063
1064 next_ed = ed.next & OHCI_DPTR_MASK;
1065
1066 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1067 uint32_t addr;
1068 /* Cancel pending packets for ED that have been paused. */
1069 addr = ed.head & OHCI_DPTR_MASK;
1070 if (ohci->async_td && addr == ohci->async_td) {
1071 usb_cancel_packet(&ohci->usb_packet);
1072 ohci->async_td = 0;
1073 }
1074 continue;
1075 }
1076
1077 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1078 #ifdef DEBUG_PACKET
1079 DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
1080 "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
1081 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1082 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1083 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1084 OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
1085 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1086 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1087 #endif
1088 active = 1;
1089
1090 if ((ed.flags & OHCI_ED_F) == 0) {
1091 if (ohci_service_td(ohci, &ed))
1092 break;
1093 } else {
1094 /* Handle isochronous endpoints */
1095 if (ohci_service_iso_td(ohci, &ed, completion))
1096 break;
1097 }
1098 }
1099
1100 ohci_put_ed(ohci, cur, &ed);
1101 }
1102
1103 return active;
1104 }
1105
1106 /* Generate a SOF event, and set a timer for EOF */
1107 static void ohci_sof(OHCIState *ohci)
1108 {
1109 ohci->sof_time = qemu_get_clock(vm_clock);
1110 qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1111 ohci_set_interrupt(ohci, OHCI_INTR_SF);
1112 }
1113
1114 /* Process Control and Bulk lists. */
1115 static void ohci_process_lists(OHCIState *ohci, int completion)
1116 {
1117 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1118 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
1119 DPRINTF("usb-ohci: head %x, cur %x\n",
1120 ohci->ctrl_head, ohci->ctrl_cur);
1121 }
1122 if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
1123 ohci->ctrl_cur = 0;
1124 ohci->status &= ~OHCI_STATUS_CLF;
1125 }
1126 }
1127
1128 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1129 if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
1130 ohci->bulk_cur = 0;
1131 ohci->status &= ~OHCI_STATUS_BLF;
1132 }
1133 }
1134 }
1135
1136 /* Do frame processing on frame boundary */
1137 static void ohci_frame_boundary(void *opaque)
1138 {
1139 OHCIState *ohci = opaque;
1140 struct ohci_hcca hcca;
1141
1142 ohci_read_hcca(ohci, ohci->hcca, &hcca);
1143
1144 /* Process all the lists at the end of the frame */
1145 if (ohci->ctl & OHCI_CTL_PLE) {
1146 int n;
1147
1148 n = ohci->frame_number & 0x1f;
1149 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
1150 }
1151
1152 /* Cancel all pending packets if either of the lists has been disabled. */
1153 if (ohci->async_td &&
1154 ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1155 usb_cancel_packet(&ohci->usb_packet);
1156 ohci->async_td = 0;
1157 }
1158 ohci->old_ctl = ohci->ctl;
1159 ohci_process_lists(ohci, 0);
1160
1161 /* Frame boundary, so do EOF stuf here */
1162 ohci->frt = ohci->fit;
1163
1164 /* Increment frame number and take care of endianness. */
1165 ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1166 hcca.frame = cpu_to_le16(ohci->frame_number);
1167
1168 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1169 if (!ohci->done)
1170 abort();
1171 if (ohci->intr & ohci->intr_status)
1172 ohci->done |= 1;
1173 hcca.done = cpu_to_le32(ohci->done);
1174 ohci->done = 0;
1175 ohci->done_count = 7;
1176 ohci_set_interrupt(ohci, OHCI_INTR_WD);
1177 }
1178
1179 if (ohci->done_count != 7 && ohci->done_count != 0)
1180 ohci->done_count--;
1181
1182 /* Do SOF stuff here */
1183 ohci_sof(ohci);
1184
1185 /* Writeback HCCA */
1186 ohci_put_hcca(ohci, ohci->hcca, &hcca);
1187 }
1188
1189 /* Start sending SOF tokens across the USB bus, lists are processed in
1190 * next frame
1191 */
1192 static int ohci_bus_start(OHCIState *ohci)
1193 {
1194 ohci->eof_timer = qemu_new_timer(vm_clock,
1195 ohci_frame_boundary,
1196 ohci);
1197
1198 if (ohci->eof_timer == NULL) {
1199 fprintf(stderr, "usb-ohci: %s: qemu_new_timer failed\n", ohci->name);
1200 /* TODO: Signal unrecoverable error */
1201 return 0;
1202 }
1203
1204 DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
1205
1206 ohci_sof(ohci);
1207
1208 return 1;
1209 }
1210
1211 /* Stop sending SOF tokens on the bus */
1212 static void ohci_bus_stop(OHCIState *ohci)
1213 {
1214 if (ohci->eof_timer)
1215 qemu_del_timer(ohci->eof_timer);
1216 ohci->eof_timer = NULL;
1217 }
1218
1219 /* Sets a flag in a port status register but only set it if the port is
1220 * connected, if not set ConnectStatusChange flag. If flag is enabled
1221 * return 1.
1222 */
1223 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1224 {
1225 int ret = 1;
1226
1227 /* writing a 0 has no effect */
1228 if (val == 0)
1229 return 0;
1230
1231 /* If CurrentConnectStatus is cleared we set
1232 * ConnectStatusChange
1233 */
1234 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1235 ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1236 if (ohci->rhstatus & OHCI_RHS_DRWE) {
1237 /* TODO: CSC is a wakeup event */
1238 }
1239 return 0;
1240 }
1241
1242 if (ohci->rhport[i].ctrl & val)
1243 ret = 0;
1244
1245 /* set the bit */
1246 ohci->rhport[i].ctrl |= val;
1247
1248 return ret;
1249 }
1250
1251 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1252 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1253 {
1254 val &= OHCI_FMI_FI;
1255
1256 if (val != ohci->fi) {
1257 DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
1258 ohci->name, ohci->fi, ohci->fi);
1259 }
1260
1261 ohci->fi = val;
1262 }
1263
1264 static void ohci_port_power(OHCIState *ohci, int i, int p)
1265 {
1266 if (p) {
1267 ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1268 } else {
1269 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1270 OHCI_PORT_CCS|
1271 OHCI_PORT_PSS|
1272 OHCI_PORT_PRS);
1273 }
1274 }
1275
1276 /* Set HcControlRegister */
1277 static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1278 {
1279 uint32_t old_state;
1280 uint32_t new_state;
1281
1282 old_state = ohci->ctl & OHCI_CTL_HCFS;
1283 ohci->ctl = val;
1284 new_state = ohci->ctl & OHCI_CTL_HCFS;
1285
1286 /* no state change */
1287 if (old_state == new_state)
1288 return;
1289
1290 switch (new_state) {
1291 case OHCI_USB_OPERATIONAL:
1292 ohci_bus_start(ohci);
1293 break;
1294 case OHCI_USB_SUSPEND:
1295 ohci_bus_stop(ohci);
1296 DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
1297 break;
1298 case OHCI_USB_RESUME:
1299 DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
1300 break;
1301 case OHCI_USB_RESET:
1302 ohci_reset(ohci);
1303 DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
1304 break;
1305 }
1306 }
1307
1308 static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1309 {
1310 uint16_t fr;
1311 int64_t tks;
1312
1313 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1314 return (ohci->frt << 31);
1315
1316 /* Being in USB operational state guarnatees sof_time was
1317 * set already.
1318 */
1319 tks = qemu_get_clock(vm_clock) - ohci->sof_time;
1320
1321 /* avoid muldiv if possible */
1322 if (tks >= usb_frame_time)
1323 return (ohci->frt << 31);
1324
1325 tks = muldiv64(1, tks, usb_bit_time);
1326 fr = (uint16_t)(ohci->fi - tks);
1327
1328 return (ohci->frt << 31) | fr;
1329 }
1330
1331
1332 /* Set root hub status */
1333 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1334 {
1335 uint32_t old_state;
1336
1337 old_state = ohci->rhstatus;
1338
1339 /* write 1 to clear OCIC */
1340 if (val & OHCI_RHS_OCIC)
1341 ohci->rhstatus &= ~OHCI_RHS_OCIC;
1342
1343 if (val & OHCI_RHS_LPS) {
1344 int i;
1345
1346 for (i = 0; i < ohci->num_ports; i++)
1347 ohci_port_power(ohci, i, 0);
1348 DPRINTF("usb-ohci: powered down all ports\n");
1349 }
1350
1351 if (val & OHCI_RHS_LPSC) {
1352 int i;
1353
1354 for (i = 0; i < ohci->num_ports; i++)
1355 ohci_port_power(ohci, i, 1);
1356 DPRINTF("usb-ohci: powered up all ports\n");
1357 }
1358
1359 if (val & OHCI_RHS_DRWE)
1360 ohci->rhstatus |= OHCI_RHS_DRWE;
1361
1362 if (val & OHCI_RHS_CRWE)
1363 ohci->rhstatus &= ~OHCI_RHS_DRWE;
1364
1365 if (old_state != ohci->rhstatus)
1366 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1367 }
1368
1369 /* Set root hub port status */
1370 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1371 {
1372 uint32_t old_state;
1373 OHCIPort *port;
1374
1375 port = &ohci->rhport[portnum];
1376 old_state = port->ctrl;
1377
1378 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1379 if (val & OHCI_PORT_WTC)
1380 port->ctrl &= ~(val & OHCI_PORT_WTC);
1381
1382 if (val & OHCI_PORT_CCS)
1383 port->ctrl &= ~OHCI_PORT_PES;
1384
1385 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1386
1387 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
1388 DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
1389 }
1390
1391 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1392 DPRINTF("usb-ohci: port %d: RESET\n", portnum);
1393 usb_send_msg(port->port.dev, USB_MSG_RESET);
1394 port->ctrl &= ~OHCI_PORT_PRS;
1395 /* ??? Should this also set OHCI_PORT_PESC. */
1396 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1397 }
1398
1399 /* Invert order here to ensure in ambiguous case, device is
1400 * powered up...
1401 */
1402 if (val & OHCI_PORT_LSDA)
1403 ohci_port_power(ohci, portnum, 0);
1404 if (val & OHCI_PORT_PPS)
1405 ohci_port_power(ohci, portnum, 1);
1406
1407 if (old_state != port->ctrl)
1408 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1409
1410 return;
1411 }
1412
1413 static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
1414 {
1415 OHCIState *ohci = ptr;
1416 uint32_t retval;
1417
1418 addr &= 0xff;
1419
1420 /* Only aligned reads are allowed on OHCI */
1421 if (addr & 3) {
1422 fprintf(stderr, "usb-ohci: Mis-aligned read\n");
1423 return 0xffffffff;
1424 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1425 /* HcRhPortStatus */
1426 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1427 } else {
1428 switch (addr >> 2) {
1429 case 0: /* HcRevision */
1430 retval = 0x10;
1431 break;
1432
1433 case 1: /* HcControl */
1434 retval = ohci->ctl;
1435 break;
1436
1437 case 2: /* HcCommandStatus */
1438 retval = ohci->status;
1439 break;
1440
1441 case 3: /* HcInterruptStatus */
1442 retval = ohci->intr_status;
1443 break;
1444
1445 case 4: /* HcInterruptEnable */
1446 case 5: /* HcInterruptDisable */
1447 retval = ohci->intr;
1448 break;
1449
1450 case 6: /* HcHCCA */
1451 retval = ohci->hcca;
1452 break;
1453
1454 case 7: /* HcPeriodCurrentED */
1455 retval = ohci->per_cur;
1456 break;
1457
1458 case 8: /* HcControlHeadED */
1459 retval = ohci->ctrl_head;
1460 break;
1461
1462 case 9: /* HcControlCurrentED */
1463 retval = ohci->ctrl_cur;
1464 break;
1465
1466 case 10: /* HcBulkHeadED */
1467 retval = ohci->bulk_head;
1468 break;
1469
1470 case 11: /* HcBulkCurrentED */
1471 retval = ohci->bulk_cur;
1472 break;
1473
1474 case 12: /* HcDoneHead */
1475 retval = ohci->done;
1476 break;
1477
1478 case 13: /* HcFmInterretval */
1479 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1480 break;
1481
1482 case 14: /* HcFmRemaining */
1483 retval = ohci_get_frame_remaining(ohci);
1484 break;
1485
1486 case 15: /* HcFmNumber */
1487 retval = ohci->frame_number;
1488 break;
1489
1490 case 16: /* HcPeriodicStart */
1491 retval = ohci->pstart;
1492 break;
1493
1494 case 17: /* HcLSThreshold */
1495 retval = ohci->lst;
1496 break;
1497
1498 case 18: /* HcRhDescriptorA */
1499 retval = ohci->rhdesc_a;
1500 break;
1501
1502 case 19: /* HcRhDescriptorB */
1503 retval = ohci->rhdesc_b;
1504 break;
1505
1506 case 20: /* HcRhStatus */
1507 retval = ohci->rhstatus;
1508 break;
1509
1510 /* PXA27x specific registers */
1511 case 24: /* HcStatus */
1512 retval = ohci->hstatus & ohci->hmask;
1513 break;
1514
1515 case 25: /* HcHReset */
1516 retval = ohci->hreset;
1517 break;
1518
1519 case 26: /* HcHInterruptEnable */
1520 retval = ohci->hmask;
1521 break;
1522
1523 case 27: /* HcHInterruptTest */
1524 retval = ohci->htest;
1525 break;
1526
1527 default:
1528 fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
1529 retval = 0xffffffff;
1530 }
1531 }
1532
1533 return retval;
1534 }
1535
1536 static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
1537 {
1538 OHCIState *ohci = ptr;
1539
1540 addr &= 0xff;
1541
1542 /* Only aligned reads are allowed on OHCI */
1543 if (addr & 3) {
1544 fprintf(stderr, "usb-ohci: Mis-aligned write\n");
1545 return;
1546 }
1547
1548 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1549 /* HcRhPortStatus */
1550 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1551 return;
1552 }
1553
1554 switch (addr >> 2) {
1555 case 1: /* HcControl */
1556 ohci_set_ctl(ohci, val);
1557 break;
1558
1559 case 2: /* HcCommandStatus */
1560 /* SOC is read-only */
1561 val = (val & ~OHCI_STATUS_SOC);
1562
1563 /* Bits written as '0' remain unchanged in the register */
1564 ohci->status |= val;
1565
1566 if (ohci->status & OHCI_STATUS_HCR)
1567 ohci_reset(ohci);
1568 break;
1569
1570 case 3: /* HcInterruptStatus */
1571 ohci->intr_status &= ~val;
1572 ohci_intr_update(ohci);
1573 break;
1574
1575 case 4: /* HcInterruptEnable */
1576 ohci->intr |= val;
1577 ohci_intr_update(ohci);
1578 break;
1579
1580 case 5: /* HcInterruptDisable */
1581 ohci->intr &= ~val;
1582 ohci_intr_update(ohci);
1583 break;
1584
1585 case 6: /* HcHCCA */
1586 ohci->hcca = val & OHCI_HCCA_MASK;
1587 break;
1588
1589 case 8: /* HcControlHeadED */
1590 ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1591 break;
1592
1593 case 9: /* HcControlCurrentED */
1594 ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1595 break;
1596
1597 case 10: /* HcBulkHeadED */
1598 ohci->bulk_head = val & OHCI_EDPTR_MASK;
1599 break;
1600
1601 case 11: /* HcBulkCurrentED */
1602 ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1603 break;
1604
1605 case 13: /* HcFmInterval */
1606 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1607 ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1608 ohci_set_frame_interval(ohci, val);
1609 break;
1610
1611 case 15: /* HcFmNumber */
1612 break;
1613
1614 case 16: /* HcPeriodicStart */
1615 ohci->pstart = val & 0xffff;
1616 break;
1617
1618 case 17: /* HcLSThreshold */
1619 ohci->lst = val & 0xffff;
1620 break;
1621
1622 case 18: /* HcRhDescriptorA */
1623 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1624 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1625 break;
1626
1627 case 19: /* HcRhDescriptorB */
1628 break;
1629
1630 case 20: /* HcRhStatus */
1631 ohci_set_hub_status(ohci, val);
1632 break;
1633
1634 /* PXA27x specific registers */
1635 case 24: /* HcStatus */
1636 ohci->hstatus &= ~(val & ohci->hmask);
1637
1638 case 25: /* HcHReset */
1639 ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1640 if (val & OHCI_HRESET_FSBIR)
1641 ohci_reset(ohci);
1642 break;
1643
1644 case 26: /* HcHInterruptEnable */
1645 ohci->hmask = val;
1646 break;
1647
1648 case 27: /* HcHInterruptTest */
1649 ohci->htest = val;
1650 break;
1651
1652 default:
1653 fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
1654 break;
1655 }
1656 }
1657
1658 /* Only dword reads are defined on OHCI register space */
1659 static CPUReadMemoryFunc * const ohci_readfn[3]={
1660 ohci_mem_read,
1661 ohci_mem_read,
1662 ohci_mem_read
1663 };
1664
1665 /* Only dword writes are defined on OHCI register space */
1666 static CPUWriteMemoryFunc * const ohci_writefn[3]={
1667 ohci_mem_write,
1668 ohci_mem_write,
1669 ohci_mem_write
1670 };
1671
1672 static void usb_ohci_init(OHCIState *ohci, DeviceState *dev,
1673 int num_ports, uint32_t localmem_base)
1674 {
1675 int i;
1676
1677 if (usb_frame_time == 0) {
1678 #ifdef OHCI_TIME_WARP
1679 usb_frame_time = get_ticks_per_sec();
1680 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000);
1681 #else
1682 usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000);
1683 if (get_ticks_per_sec() >= USB_HZ) {
1684 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ);
1685 } else {
1686 usb_bit_time = 1;
1687 }
1688 #endif
1689 DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
1690 usb_frame_time, usb_bit_time);
1691 }
1692
1693 ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci,
1694 DEVICE_LITTLE_ENDIAN);
1695 ohci->localmem_base = localmem_base;
1696
1697 ohci->name = dev->info->name;
1698
1699 usb_bus_new(&ohci->bus, dev);
1700 ohci->num_ports = num_ports;
1701 for (i = 0; i < num_ports; i++) {
1702 usb_register_port(&ohci->bus, &ohci->rhport[i].port, ohci, i, NULL, ohci_attach);
1703 }
1704
1705 ohci->async_td = 0;
1706 qemu_register_reset(ohci_reset, ohci);
1707 }
1708
1709 typedef struct {
1710 PCIDevice pci_dev;
1711 OHCIState state;
1712 } OHCIPCIState;
1713
1714 static void ohci_mapfunc(PCIDevice *pci_dev, int i,
1715 pcibus_t addr, pcibus_t size, int type)
1716 {
1717 OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, pci_dev);
1718 cpu_register_physical_memory(addr, size, ohci->state.mem);
1719 }
1720
1721 static int usb_ohci_initfn_pci(struct PCIDevice *dev)
1722 {
1723 OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
1724 int num_ports = 3;
1725
1726 pci_config_set_vendor_id(ohci->pci_dev.config, PCI_VENDOR_ID_APPLE);
1727 pci_config_set_device_id(ohci->pci_dev.config,
1728 PCI_DEVICE_ID_APPLE_IPID_USB);
1729 ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
1730 pci_config_set_class(ohci->pci_dev.config, PCI_CLASS_SERIAL_USB);
1731 /* TODO: RST# value should be 0. */
1732 ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
1733
1734 usb_ohci_init(&ohci->state, &dev->qdev, num_ports, 0);
1735 ohci->state.irq = ohci->pci_dev.irq[0];
1736
1737 /* TODO: avoid cast below by using dev */
1738 pci_register_bar(&ohci->pci_dev, 0, 256,
1739 PCI_BASE_ADDRESS_SPACE_MEMORY, ohci_mapfunc);
1740 return 0;
1741 }
1742
1743 void usb_ohci_init_pci(struct PCIBus *bus, int devfn)
1744 {
1745 pci_create_simple(bus, devfn, "pci-ohci");
1746 }
1747
1748 typedef struct {
1749 SysBusDevice busdev;
1750 OHCIState ohci;
1751 uint32_t num_ports;
1752 target_phys_addr_t dma_offset;
1753 } OHCISysBusState;
1754
1755 static int ohci_init_pxa(SysBusDevice *dev)
1756 {
1757 OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev);
1758
1759 usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset);
1760 sysbus_init_irq(dev, &s->ohci.irq);
1761 sysbus_init_mmio(dev, 0x1000, s->ohci.mem);
1762
1763 return 0;
1764 }
1765
1766 static PCIDeviceInfo ohci_pci_info = {
1767 .qdev.name = "pci-ohci",
1768 .qdev.desc = "Apple USB Controller",
1769 .qdev.size = sizeof(OHCIPCIState),
1770 .init = usb_ohci_initfn_pci,
1771 };
1772
1773 static SysBusDeviceInfo ohci_sysbus_info = {
1774 .init = ohci_init_pxa,
1775 .qdev.name = "sysbus-ohci",
1776 .qdev.desc = "OHCI USB Controller",
1777 .qdev.size = sizeof(OHCISysBusState),
1778 .qdev.props = (Property[]) {
1779 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
1780 DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3),
1781 DEFINE_PROP_END_OF_LIST(),
1782 }
1783 };
1784
1785 static void ohci_register(void)
1786 {
1787 pci_qdev_register(&ohci_pci_info);
1788 sysbus_register_withprop(&ohci_sysbus_info);
1789 }
1790 device_init(ohci_register);
various patches