hw/stellaris.c

   1 /*
   2  * Luminary Micro Stellaris peripherals
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "ssi.h"
  12 #include "arm-misc.h"
  13 #include "devices.h"
  14 #include "qemu-timer.h"
  15 #include "i2c.h"
  16 #include "net.h"
  17 #include "boards.h"
  18
  19 #define GPIO_A 0
  20 #define GPIO_B 1
  21 #define GPIO_C 2
  22 #define GPIO_D 3
  23 #define GPIO_E 4
  24 #define GPIO_F 5
  25 #define GPIO_G 6
  26
  27 #define BP_OLED_I2C  0x01
  28 #define BP_OLED_SSI  0x02
  29 #define BP_GAMEPAD   0x04
  30
  31 typedef const struct {
  32     const char *name;
  33     uint32_t did0;
  34     uint32_t did1;
  35     uint32_t dc0;
  36     uint32_t dc1;
  37     uint32_t dc2;
  38     uint32_t dc3;
  39     uint32_t dc4;
  40     uint32_t peripherals;
  41 } stellaris_board_info;
  42
  43 /* General purpose timer module.  */
  44
  45 typedef struct gptm_state {
  46     SysBusDevice busdev;
  47     uint32_t config;
  48     uint32_t mode[2];
  49     uint32_t control;
  50     uint32_t state;
  51     uint32_t mask;
  52     uint32_t load[2];
  53     uint32_t match[2];
  54     uint32_t prescale[2];
  55     uint32_t match_prescale[2];
  56     uint32_t rtc;
  57     int64_t tick[2];
  58     struct gptm_state *opaque[2];
  59     QEMUTimer *timer[2];
  60     /* The timers have an alternate output used to trigger the ADC.  */
  61     qemu_irq trigger;
  62     qemu_irq irq;
  63 } gptm_state;
  64
  65 static void gptm_update_irq(gptm_state *s)
  66 {
  67     int level;
  68     level = (s->state & s->mask) != 0;
  69     qemu_set_irq(s->irq, level);
  70 }
  71
  72 static void gptm_stop(gptm_state *s, int n)
  73 {
  74     qemu_del_timer(s->timer[n]);
  75 }
  76
  77 static void gptm_reload(gptm_state *s, int n, int reset)
  78 {
  79     int64_t tick;
  80     if (reset)
  81         tick = qemu_get_clock_ns(vm_clock);
  82     else
  83         tick = s->tick[n];
  84
  85     if (s->config == 0) {
  86         /* 32-bit CountDown.  */
  87         uint32_t count;
  88         count = s->load[0] | (s->load[1] << 16);
  89         tick += (int64_t)count * system_clock_scale;
  90     } else if (s->config == 1) {
  91         /* 32-bit RTC.  1Hz tick.  */
  92         tick += get_ticks_per_sec();
  93     } else if (s->mode[n] == 0xa) {
  94         /* PWM mode.  Not implemented.  */
  95     } else {
  96         hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
  97     }
  98     s->tick[n] = tick;
  99     qemu_mod_timer(s->timer[n], tick);
 100 }
 101
 102 static void gptm_tick(void *opaque)
 103 {
 104     gptm_state **p = (gptm_state **)opaque;
 105     gptm_state *s;
 106     int n;
 107
 108     s = *p;
 109     n = p - s->opaque;
 110     if (s->config == 0) {
 111         s->state |= 1;
 112         if ((s->control & 0x20)) {
 113             /* Output trigger.  */
 114             qemu_irq_pulse(s->trigger);
 115         }
 116         if (s->mode[0] & 1) {
 117             /* One-shot.  */
 118             s->control &= ~1;
 119         } else {
 120             /* Periodic.  */
 121             gptm_reload(s, 0, 0);
 122         }
 123     } else if (s->config == 1) {
 124         /* RTC.  */
 125         uint32_t match;
 126         s->rtc++;
 127         match = s->match[0] | (s->match[1] << 16);
 128         if (s->rtc > match)
 129             s->rtc = 0;
 130         if (s->rtc == 0) {
 131             s->state |= 8;
 132         }
 133         gptm_reload(s, 0, 0);
 134     } else if (s->mode[n] == 0xa) {
 135         /* PWM mode.  Not implemented.  */
 136     } else {
 137         hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
 138     }
 139     gptm_update_irq(s);
 140 }
 141
 142 static uint32_t gptm_read(void *opaque, target_phys_addr_t offset)
 143 {
 144     gptm_state *s = (gptm_state *)opaque;
 145
 146     switch (offset) {
 147     case 0x00: /* CFG */
 148         return s->config;
 149     case 0x04: /* TAMR */
 150         return s->mode[0];
 151     case 0x08: /* TBMR */
 152         return s->mode[1];
 153     case 0x0c: /* CTL */
 154         return s->control;
 155     case 0x18: /* IMR */
 156         return s->mask;
 157     case 0x1c: /* RIS */
 158         return s->state;
 159     case 0x20: /* MIS */
 160         return s->state & s->mask;
 161     case 0x24: /* CR */
 162         return 0;
 163     case 0x28: /* TAILR */
 164         return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
 165     case 0x2c: /* TBILR */
 166         return s->load[1];
 167     case 0x30: /* TAMARCHR */
 168         return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
 169     case 0x34: /* TBMATCHR */
 170         return s->match[1];
 171     case 0x38: /* TAPR */
 172         return s->prescale[0];
 173     case 0x3c: /* TBPR */
 174         return s->prescale[1];
 175     case 0x40: /* TAPMR */
 176         return s->match_prescale[0];
 177     case 0x44: /* TBPMR */
 178         return s->match_prescale[1];
 179     case 0x48: /* TAR */
 180         if (s->control == 1)
 181             return s->rtc;
 182     case 0x4c: /* TBR */
 183         hw_error("TODO: Timer value read\n");
 184     default:
 185         hw_error("gptm_read: Bad offset 0x%x\n", (int)offset);
 186         return 0;
 187     }
 188 }
 189
 190 static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value)
 191 {
 192     gptm_state *s = (gptm_state *)opaque;
 193     uint32_t oldval;
 194
 195     /* The timers should be disabled before changing the configuration.
 196        We take advantage of this and defer everything until the timer
 197        is enabled.  */
 198     switch (offset) {
 199     case 0x00: /* CFG */
 200         s->config = value;
 201         break;
 202     case 0x04: /* TAMR */
 203         s->mode[0] = value;
 204         break;
 205     case 0x08: /* TBMR */
 206         s->mode[1] = value;
 207         break;
 208     case 0x0c: /* CTL */
 209         oldval = s->control;
 210         s->control = value;
 211         /* TODO: Implement pause.  */
 212         if ((oldval ^ value) & 1) {
 213             if (value & 1) {
 214                 gptm_reload(s, 0, 1);
 215             } else {
 216                 gptm_stop(s, 0);
 217             }
 218         }
 219         if (((oldval ^ value) & 0x100) && s->config >= 4) {
 220             if (value & 0x100) {
 221                 gptm_reload(s, 1, 1);
 222             } else {
 223                 gptm_stop(s, 1);
 224             }
 225         }
 226         break;
 227     case 0x18: /* IMR */
 228         s->mask = value & 0x77;
 229         gptm_update_irq(s);
 230         break;
 231     case 0x24: /* CR */
 232         s->state &= ~value;
 233         break;
 234     case 0x28: /* TAILR */
 235         s->load[0] = value & 0xffff;
 236         if (s->config < 4) {
 237             s->load[1] = value >> 16;
 238         }
 239         break;
 240     case 0x2c: /* TBILR */
 241         s->load[1] = value & 0xffff;
 242         break;
 243     case 0x30: /* TAMARCHR */
 244         s->match[0] = value & 0xffff;
 245         if (s->config < 4) {
 246             s->match[1] = value >> 16;
 247         }
 248         break;
 249     case 0x34: /* TBMATCHR */
 250         s->match[1] = value >> 16;
 251         break;
 252     case 0x38: /* TAPR */
 253         s->prescale[0] = value;
 254         break;
 255     case 0x3c: /* TBPR */
 256         s->prescale[1] = value;
 257         break;
 258     case 0x40: /* TAPMR */
 259         s->match_prescale[0] = value;
 260         break;
 261     case 0x44: /* TBPMR */
 262         s->match_prescale[0] = value;
 263         break;
 264     default:
 265         hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
 266     }
 267     gptm_update_irq(s);
 268 }
 269
 270 static CPUReadMemoryFunc * const gptm_readfn[] = {
 271    gptm_read,
 272    gptm_read,
 273    gptm_read
 274 };
 275
 276 static CPUWriteMemoryFunc * const gptm_writefn[] = {
 277    gptm_write,
 278    gptm_write,
 279    gptm_write
 280 };
 281
 282 static void gptm_save(QEMUFile *f, void *opaque)
 283 {
 284     gptm_state *s = (gptm_state *)opaque;
 285
 286     qemu_put_be32(f, s->config);
 287     qemu_put_be32(f, s->mode[0]);
 288     qemu_put_be32(f, s->mode[1]);
 289     qemu_put_be32(f, s->control);
 290     qemu_put_be32(f, s->state);
 291     qemu_put_be32(f, s->mask);
 292     qemu_put_be32(f, s->mode[0]);
 293     qemu_put_be32(f, s->mode[0]);
 294     qemu_put_be32(f, s->load[0]);
 295     qemu_put_be32(f, s->load[1]);
 296     qemu_put_be32(f, s->match[0]);
 297     qemu_put_be32(f, s->match[1]);
 298     qemu_put_be32(f, s->prescale[0]);
 299     qemu_put_be32(f, s->prescale[1]);
 300     qemu_put_be32(f, s->match_prescale[0]);
 301     qemu_put_be32(f, s->match_prescale[1]);
 302     qemu_put_be32(f, s->rtc);
 303     qemu_put_be64(f, s->tick[0]);
 304     qemu_put_be64(f, s->tick[1]);
 305     qemu_put_timer(f, s->timer[0]);
 306     qemu_put_timer(f, s->timer[1]);
 307 }
 308
 309 static int gptm_load(QEMUFile *f, void *opaque, int version_id)
 310 {
 311     gptm_state *s = (gptm_state *)opaque;
 312
 313     if (version_id != 1)
 314         return -EINVAL;
 315
 316     s->config = qemu_get_be32(f);
 317     s->mode[0] = qemu_get_be32(f);
 318     s->mode[1] = qemu_get_be32(f);
 319     s->control = qemu_get_be32(f);
 320     s->state = qemu_get_be32(f);
 321     s->mask = qemu_get_be32(f);
 322     s->mode[0] = qemu_get_be32(f);
 323     s->mode[0] = qemu_get_be32(f);
 324     s->load[0] = qemu_get_be32(f);
 325     s->load[1] = qemu_get_be32(f);
 326     s->match[0] = qemu_get_be32(f);
 327     s->match[1] = qemu_get_be32(f);
 328     s->prescale[0] = qemu_get_be32(f);
 329     s->prescale[1] = qemu_get_be32(f);
 330     s->match_prescale[0] = qemu_get_be32(f);
 331     s->match_prescale[1] = qemu_get_be32(f);
 332     s->rtc = qemu_get_be32(f);
 333     s->tick[0] = qemu_get_be64(f);
 334     s->tick[1] = qemu_get_be64(f);
 335     qemu_get_timer(f, s->timer[0]);
 336     qemu_get_timer(f, s->timer[1]);
 337
 338     return 0;
 339 }
 340
 341 static int stellaris_gptm_init(SysBusDevice *dev)
 342 {
 343     int iomemtype;
 344     gptm_state *s = FROM_SYSBUS(gptm_state, dev);
 345
 346     sysbus_init_irq(dev, &s->irq);
 347     qdev_init_gpio_out(&dev->qdev, &s->trigger, 1);
 348
 349     iomemtype = cpu_register_io_memory(gptm_readfn,
 350                                        gptm_writefn, s,
 351                                        DEVICE_NATIVE_ENDIAN);
 352     sysbus_init_mmio(dev, 0x1000, iomemtype);
 353
 354     s->opaque[0] = s->opaque[1] = s;
 355     s->timer[0] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[0]);
 356     s->timer[1] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[1]);
 357     register_savevm(&dev->qdev, "stellaris_gptm", -1, 1,
 358                     gptm_save, gptm_load, s);
 359     return 0;
 360 }
 361
 362
 363 /* System controller.  */
 364
 365 typedef struct {
 366     uint32_t pborctl;
 367     uint32_t ldopctl;
 368     uint32_t int_status;
 369     uint32_t int_mask;
 370     uint32_t resc;
 371     uint32_t rcc;
 372     uint32_t rcgc[3];
 373     uint32_t scgc[3];
 374     uint32_t dcgc[3];
 375     uint32_t clkvclr;
 376     uint32_t ldoarst;
 377     uint32_t user0;
 378     uint32_t user1;
 379     qemu_irq irq;
 380     stellaris_board_info *board;
 381 } ssys_state;
 382
 383 static void ssys_update(ssys_state *s)
 384 {
 385   qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
 386 }
 387
 388 static uint32_t pllcfg_sandstorm[16] = {
 389     0x31c0, /* 1 Mhz */
 390     0x1ae0, /* 1.8432 Mhz */
 391     0x18c0, /* 2 Mhz */
 392     0xd573, /* 2.4576 Mhz */
 393     0x37a6, /* 3.57954 Mhz */
 394     0x1ae2, /* 3.6864 Mhz */
 395     0x0c40, /* 4 Mhz */
 396     0x98bc, /* 4.906 Mhz */
 397     0x935b, /* 4.9152 Mhz */
 398     0x09c0, /* 5 Mhz */
 399     0x4dee, /* 5.12 Mhz */
 400     0x0c41, /* 6 Mhz */
 401     0x75db, /* 6.144 Mhz */
 402     0x1ae6, /* 7.3728 Mhz */
 403     0x0600, /* 8 Mhz */
 404     0x585b /* 8.192 Mhz */
 405 };
 406
 407 static uint32_t pllcfg_fury[16] = {
 408     0x3200, /* 1 Mhz */
 409     0x1b20, /* 1.8432 Mhz */
 410     0x1900, /* 2 Mhz */
 411     0xf42b, /* 2.4576 Mhz */
 412     0x37e3, /* 3.57954 Mhz */
 413     0x1b21, /* 3.6864 Mhz */
 414     0x0c80, /* 4 Mhz */
 415     0x98ee, /* 4.906 Mhz */
 416     0xd5b4, /* 4.9152 Mhz */
 417     0x0a00, /* 5 Mhz */
 418     0x4e27, /* 5.12 Mhz */
 419     0x1902, /* 6 Mhz */
 420     0xec1c, /* 6.144 Mhz */
 421     0x1b23, /* 7.3728 Mhz */
 422     0x0640, /* 8 Mhz */
 423     0xb11c /* 8.192 Mhz */
 424 };
 425
 426 static uint32_t ssys_read(void *opaque, target_phys_addr_t offset)
 427 {
 428     ssys_state *s = (ssys_state *)opaque;
 429
 430     switch (offset) {
 431     case 0x000: /* DID0 */
 432         return s->board->did0;
 433     case 0x004: /* DID1 */
 434         return s->board->did1;
 435     case 0x008: /* DC0 */
 436         return s->board->dc0;
 437     case 0x010: /* DC1 */
 438         return s->board->dc1;
 439     case 0x014: /* DC2 */
 440         return s->board->dc2;
 441     case 0x018: /* DC3 */
 442         return s->board->dc3;
 443     case 0x01c: /* DC4 */
 444         return s->board->dc4;
 445     case 0x030: /* PBORCTL */
 446         return s->pborctl;
 447     case 0x034: /* LDOPCTL */
 448         return s->ldopctl;
 449     case 0x040: /* SRCR0 */
 450         return 0;
 451     case 0x044: /* SRCR1 */
 452         return 0;
 453     case 0x048: /* SRCR2 */
 454         return 0;
 455     case 0x050: /* RIS */
 456         return s->int_status;
 457     case 0x054: /* IMC */
 458         return s->int_mask;
 459     case 0x058: /* MISC */
 460         return s->int_status & s->int_mask;
 461     case 0x05c: /* RESC */
 462         return s->resc;
 463     case 0x060: /* RCC */
 464         return s->rcc;
 465     case 0x064: /* PLLCFG */
 466         {
 467             int xtal;
 468             xtal = (s->rcc >> 6) & 0xf;
 469             if (s->board->did0 & (1 << 16)) {
 470                 return pllcfg_fury[xtal];
 471             } else {
 472                 return pllcfg_sandstorm[xtal];
 473             }
 474         }
 475     case 0x100: /* RCGC0 */
 476         return s->rcgc[0];
 477     case 0x104: /* RCGC1 */
 478         return s->rcgc[1];
 479     case 0x108: /* RCGC2 */
 480         return s->rcgc[2];
 481     case 0x110: /* SCGC0 */
 482         return s->scgc[0];
 483     case 0x114: /* SCGC1 */
 484         return s->scgc[1];
 485     case 0x118: /* SCGC2 */
 486         return s->scgc[2];
 487     case 0x120: /* DCGC0 */
 488         return s->dcgc[0];
 489     case 0x124: /* DCGC1 */
 490         return s->dcgc[1];
 491     case 0x128: /* DCGC2 */
 492         return s->dcgc[2];
 493     case 0x150: /* CLKVCLR */
 494         return s->clkvclr;
 495     case 0x160: /* LDOARST */
 496         return s->ldoarst;
 497     case 0x1e0: /* USER0 */
 498         return s->user0;
 499     case 0x1e4: /* USER1 */
 500         return s->user1;
 501     default:
 502         hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
 503         return 0;
 504     }
 505 }
 506
 507 static void ssys_calculate_system_clock(ssys_state *s)
 508 {
 509     system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
 510 }
 511
 512 static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value)
 513 {
 514     ssys_state *s = (ssys_state *)opaque;
 515
 516     switch (offset) {
 517     case 0x030: /* PBORCTL */
 518         s->pborctl = value & 0xffff;
 519         break;
 520     case 0x034: /* LDOPCTL */
 521         s->ldopctl = value & 0x1f;
 522         break;
 523     case 0x040: /* SRCR0 */
 524     case 0x044: /* SRCR1 */
 525     case 0x048: /* SRCR2 */
 526         fprintf(stderr, "Peripheral reset not implemented\n");
 527         break;
 528     case 0x054: /* IMC */
 529         s->int_mask = value & 0x7f;
 530         break;
 531     case 0x058: /* MISC */
 532         s->int_status &= ~value;
 533         break;
 534     case 0x05c: /* RESC */
 535         s->resc = value & 0x3f;
 536         break;
 537     case 0x060: /* RCC */
 538         if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 539             /* PLL enable.  */
 540             s->int_status |= (1 << 6);
 541         }
 542         s->rcc = value;
 543         ssys_calculate_system_clock(s);
 544         break;
 545     case 0x100: /* RCGC0 */
 546         s->rcgc[0] = value;
 547         break;
 548     case 0x104: /* RCGC1 */
 549         s->rcgc[1] = value;
 550         break;
 551     case 0x108: /* RCGC2 */
 552         s->rcgc[2] = value;
 553         break;
 554     case 0x110: /* SCGC0 */
 555         s->scgc[0] = value;
 556         break;
 557     case 0x114: /* SCGC1 */
 558         s->scgc[1] = value;
 559         break;
 560     case 0x118: /* SCGC2 */
 561         s->scgc[2] = value;
 562         break;
 563     case 0x120: /* DCGC0 */
 564         s->dcgc[0] = value;
 565         break;
 566     case 0x124: /* DCGC1 */
 567         s->dcgc[1] = value;
 568         break;
 569     case 0x128: /* DCGC2 */
 570         s->dcgc[2] = value;
 571         break;
 572     case 0x150: /* CLKVCLR */
 573         s->clkvclr = value;
 574         break;
 575     case 0x160: /* LDOARST */
 576         s->ldoarst = value;
 577         break;
 578     default:
 579         hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
 580     }
 581     ssys_update(s);
 582 }
 583
 584 static CPUReadMemoryFunc * const ssys_readfn[] = {
 585    ssys_read,
 586    ssys_read,
 587    ssys_read
 588 };
 589
 590 static CPUWriteMemoryFunc * const ssys_writefn[] = {
 591    ssys_write,
 592    ssys_write,
 593    ssys_write
 594 };
 595
 596 static void ssys_reset(void *opaque)
 597 {
 598     ssys_state *s = (ssys_state *)opaque;
 599
 600     s->pborctl = 0x7ffd;
 601     s->rcc = 0x078e3ac0;
 602     s->rcgc[0] = 1;
 603     s->scgc[0] = 1;
 604     s->dcgc[0] = 1;
 605 }
 606
 607 static void ssys_save(QEMUFile *f, void *opaque)
 608 {
 609     ssys_state *s = (ssys_state *)opaque;
 610
 611     qemu_put_be32(f, s->pborctl);
 612     qemu_put_be32(f, s->ldopctl);
 613     qemu_put_be32(f, s->int_mask);
 614     qemu_put_be32(f, s->int_status);
 615     qemu_put_be32(f, s->resc);
 616     qemu_put_be32(f, s->rcc);
 617     qemu_put_be32(f, s->rcgc[0]);
 618     qemu_put_be32(f, s->rcgc[1]);
 619     qemu_put_be32(f, s->rcgc[2]);
 620     qemu_put_be32(f, s->scgc[0]);
 621     qemu_put_be32(f, s->scgc[1]);
 622     qemu_put_be32(f, s->scgc[2]);
 623     qemu_put_be32(f, s->dcgc[0]);
 624     qemu_put_be32(f, s->dcgc[1]);
 625     qemu_put_be32(f, s->dcgc[2]);
 626     qemu_put_be32(f, s->clkvclr);
 627     qemu_put_be32(f, s->ldoarst);
 628 }
 629
 630 static int ssys_load(QEMUFile *f, void *opaque, int version_id)
 631 {
 632     ssys_state *s = (ssys_state *)opaque;
 633
 634     if (version_id != 1)
 635         return -EINVAL;
 636
 637     s->pborctl = qemu_get_be32(f);
 638     s->ldopctl = qemu_get_be32(f);
 639     s->int_mask = qemu_get_be32(f);
 640     s->int_status = qemu_get_be32(f);
 641     s->resc = qemu_get_be32(f);
 642     s->rcc = qemu_get_be32(f);
 643     s->rcgc[0] = qemu_get_be32(f);
 644     s->rcgc[1] = qemu_get_be32(f);
 645     s->rcgc[2] = qemu_get_be32(f);
 646     s->scgc[0] = qemu_get_be32(f);
 647     s->scgc[1] = qemu_get_be32(f);
 648     s->scgc[2] = qemu_get_be32(f);
 649     s->dcgc[0] = qemu_get_be32(f);
 650     s->dcgc[1] = qemu_get_be32(f);
 651     s->dcgc[2] = qemu_get_be32(f);
 652     s->clkvclr = qemu_get_be32(f);
 653     s->ldoarst = qemu_get_be32(f);
 654     ssys_calculate_system_clock(s);
 655
 656     return 0;
 657 }
 658
 659 static int stellaris_sys_init(uint32_t base, qemu_irq irq,
 660                               stellaris_board_info * board,
 661                               uint8_t *macaddr)
 662 {
 663     int iomemtype;
 664     ssys_state *s;
 665
 666     s = (ssys_state *)qemu_mallocz(sizeof(ssys_state));
 667     s->irq = irq;
 668     s->board = board;
 669     /* Most devices come preprogrammed with a MAC address in the user data. */
 670     s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
 671     s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
 672
 673     iomemtype = cpu_register_io_memory(ssys_readfn,
 674                                        ssys_writefn, s,
 675                                        DEVICE_NATIVE_ENDIAN);
 676     cpu_register_physical_memory(base, 0x00001000, iomemtype);
 677     ssys_reset(s);
 678     register_savevm(NULL, "stellaris_sys", -1, 1, ssys_save, ssys_load, s);
 679     return 0;
 680 }
 681
 682
 683 /* I2C controller.  */
 684
 685 typedef struct {
 686     SysBusDevice busdev;
 687     i2c_bus *bus;
 688     qemu_irq irq;
 689     uint32_t msa;
 690     uint32_t mcs;
 691     uint32_t mdr;
 692     uint32_t mtpr;
 693     uint32_t mimr;
 694     uint32_t mris;
 695     uint32_t mcr;
 696 } stellaris_i2c_state;
 697
 698 #define STELLARIS_I2C_MCS_BUSY    0x01
 699 #define STELLARIS_I2C_MCS_ERROR   0x02
 700 #define STELLARIS_I2C_MCS_ADRACK  0x04
 701 #define STELLARIS_I2C_MCS_DATACK  0x08
 702 #define STELLARIS_I2C_MCS_ARBLST  0x10
 703 #define STELLARIS_I2C_MCS_IDLE    0x20
 704 #define STELLARIS_I2C_MCS_BUSBSY  0x40
 705
 706 static uint32_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset)
 707 {
 708     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 709
 710     switch (offset) {
 711     case 0x00: /* MSA */
 712         return s->msa;
 713     case 0x04: /* MCS */
 714         /* We don't emulate timing, so the controller is never busy.  */
 715         return s->mcs | STELLARIS_I2C_MCS_IDLE;
 716     case 0x08: /* MDR */
 717         return s->mdr;
 718     case 0x0c: /* MTPR */
 719         return s->mtpr;
 720     case 0x10: /* MIMR */
 721         return s->mimr;
 722     case 0x14: /* MRIS */
 723         return s->mris;
 724     case 0x18: /* MMIS */
 725         return s->mris & s->mimr;
 726     case 0x20: /* MCR */
 727         return s->mcr;
 728     default:
 729         hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
 730         return 0;
 731     }
 732 }
 733
 734 static void stellaris_i2c_update(stellaris_i2c_state *s)
 735 {
 736     int level;
 737
 738     level = (s->mris & s->mimr) != 0;
 739     qemu_set_irq(s->irq, level);
 740 }
 741
 742 static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset,
 743                                 uint32_t value)
 744 {
 745     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 746
 747     switch (offset) {
 748     case 0x00: /* MSA */
 749         s->msa = value & 0xff;
 750         break;
 751     case 0x04: /* MCS */
 752         if ((s->mcr & 0x10) == 0) {
 753             /* Disabled.  Do nothing.  */
 754             break;
 755         }
 756         /* Grab the bus if this is starting a transfer.  */
 757         if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 758             if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
 759                 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
 760             } else {
 761                 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
 762                 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
 763             }
 764         }
 765         /* If we don't have the bus then indicate an error.  */
 766         if (!i2c_bus_busy(s->bus)
 767                 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 768             s->mcs |= STELLARIS_I2C_MCS_ERROR;
 769             break;
 770         }
 771         s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
 772         if (value & 1) {
 773             /* Transfer a byte.  */
 774             /* TODO: Handle errors.  */
 775             if (s->msa & 1) {
 776                 /* Recv */
 777                 s->mdr = i2c_recv(s->bus) & 0xff;
 778             } else {
 779                 /* Send */
 780                 i2c_send(s->bus, s->mdr);
 781             }
 782             /* Raise an interrupt.  */
 783             s->mris |= 1;
 784         }
 785         if (value & 4) {
 786             /* Finish transfer.  */
 787             i2c_end_transfer(s->bus);
 788             s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
 789         }
 790         break;
 791     case 0x08: /* MDR */
 792         s->mdr = value & 0xff;
 793         break;
 794     case 0x0c: /* MTPR */
 795         s->mtpr = value & 0xff;
 796         break;
 797     case 0x10: /* MIMR */
 798         s->mimr = 1;
 799         break;
 800     case 0x1c: /* MICR */
 801         s->mris &= ~value;
 802         break;
 803     case 0x20: /* MCR */
 804         if (value & 1)
 805             hw_error(
 806                       "stellaris_i2c_write: Loopback not implemented\n");
 807         if (value & 0x20)
 808             hw_error(
 809                       "stellaris_i2c_write: Slave mode not implemented\n");
 810         s->mcr = value & 0x31;
 811         break;
 812     default:
 813         hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
 814                   (int)offset);
 815     }
 816     stellaris_i2c_update(s);
 817 }
 818
 819 static void stellaris_i2c_reset(stellaris_i2c_state *s)
 820 {
 821     if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
 822         i2c_end_transfer(s->bus);
 823
 824     s->msa = 0;
 825     s->mcs = 0;
 826     s->mdr = 0;
 827     s->mtpr = 1;
 828     s->mimr = 0;
 829     s->mris = 0;
 830     s->mcr = 0;
 831     stellaris_i2c_update(s);
 832 }
 833
 834 static CPUReadMemoryFunc * const stellaris_i2c_readfn[] = {
 835    stellaris_i2c_read,
 836    stellaris_i2c_read,
 837    stellaris_i2c_read
 838 };
 839
 840 static CPUWriteMemoryFunc * const stellaris_i2c_writefn[] = {
 841    stellaris_i2c_write,
 842    stellaris_i2c_write,
 843    stellaris_i2c_write
 844 };
 845
 846 static void stellaris_i2c_save(QEMUFile *f, void *opaque)
 847 {
 848     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 849
 850     qemu_put_be32(f, s->msa);
 851     qemu_put_be32(f, s->mcs);
 852     qemu_put_be32(f, s->mdr);
 853     qemu_put_be32(f, s->mtpr);
 854     qemu_put_be32(f, s->mimr);
 855     qemu_put_be32(f, s->mris);
 856     qemu_put_be32(f, s->mcr);
 857 }
 858
 859 static int stellaris_i2c_load(QEMUFile *f, void *opaque, int version_id)
 860 {
 861     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 862
 863     if (version_id != 1)
 864         return -EINVAL;
 865
 866     s->msa = qemu_get_be32(f);
 867     s->mcs = qemu_get_be32(f);
 868     s->mdr = qemu_get_be32(f);
 869     s->mtpr = qemu_get_be32(f);
 870     s->mimr = qemu_get_be32(f);
 871     s->mris = qemu_get_be32(f);
 872     s->mcr = qemu_get_be32(f);
 873
 874     return 0;
 875 }
 876
 877 static int stellaris_i2c_init(SysBusDevice * dev)
 878 {
 879     stellaris_i2c_state *s = FROM_SYSBUS(stellaris_i2c_state, dev);
 880     i2c_bus *bus;
 881     int iomemtype;
 882
 883     sysbus_init_irq(dev, &s->irq);
 884     bus = i2c_init_bus(&dev->qdev, "i2c");
 885     s->bus = bus;
 886
 887     iomemtype = cpu_register_io_memory(stellaris_i2c_readfn,
 888                                        stellaris_i2c_writefn, s,
 889                                        DEVICE_NATIVE_ENDIAN);
 890     sysbus_init_mmio(dev, 0x1000, iomemtype);
 891     /* ??? For now we only implement the master interface.  */
 892     stellaris_i2c_reset(s);
 893     register_savevm(&dev->qdev, "stellaris_i2c", -1, 1,
 894                     stellaris_i2c_save, stellaris_i2c_load, s);
 895     return 0;
 896 }
 897
 898 /* Analogue to Digital Converter.  This is only partially implemented,
 899    enough for applications that use a combined ADC and timer tick.  */
 900
 901 #define STELLARIS_ADC_EM_CONTROLLER 0
 902 #define STELLARIS_ADC_EM_COMP       1
 903 #define STELLARIS_ADC_EM_EXTERNAL   4
 904 #define STELLARIS_ADC_EM_TIMER      5
 905 #define STELLARIS_ADC_EM_PWM0       6
 906 #define STELLARIS_ADC_EM_PWM1       7
 907 #define STELLARIS_ADC_EM_PWM2       8
 908
 909 #define STELLARIS_ADC_FIFO_EMPTY    0x0100
 910 #define STELLARIS_ADC_FIFO_FULL     0x1000
 911
 912 typedef struct
 913 {
 914     SysBusDevice busdev;
 915     uint32_t actss;
 916     uint32_t ris;
 917     uint32_t im;
 918     uint32_t emux;
 919     uint32_t ostat;
 920     uint32_t ustat;
 921     uint32_t sspri;
 922     uint32_t sac;
 923     struct {
 924         uint32_t state;
 925         uint32_t data[16];
 926     } fifo[4];
 927     uint32_t ssmux[4];
 928     uint32_t ssctl[4];
 929     uint32_t noise;
 930     qemu_irq irq[4];
 931 } stellaris_adc_state;
 932
 933 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
 934 {
 935     int tail;
 936
 937     tail = s->fifo[n].state & 0xf;
 938     if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
 939         s->ustat |= 1 << n;
 940     } else {
 941         s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
 942         s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
 943         if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
 944             s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
 945     }
 946     return s->fifo[n].data[tail];
 947 }
 948
 949 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
 950                                      uint32_t value)
 951 {
 952     int head;
 953
 954     /* TODO: Real hardware has limited size FIFOs.  We have a full 16 entry
 955        FIFO fir each sequencer.  */
 956     head = (s->fifo[n].state >> 4) & 0xf;
 957     if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
 958         s->ostat |= 1 << n;
 959         return;
 960     }
 961     s->fifo[n].data[head] = value;
 962     head = (head + 1) & 0xf;
 963     s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
 964     s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
 965     if ((s->fifo[n].state & 0xf) == head)
 966         s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
 967 }
 968
 969 static void stellaris_adc_update(stellaris_adc_state *s)
 970 {
 971     int level;
 972     int n;
 973
 974     for (n = 0; n < 4; n++) {
 975         level = (s->ris & s->im & (1 << n)) != 0;
 976         qemu_set_irq(s->irq[n], level);
 977     }
 978 }
 979
 980 static void stellaris_adc_trigger(void *opaque, int irq, int level)
 981 {
 982     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
 983     int n;
 984
 985     for (n = 0; n < 4; n++) {
 986         if ((s->actss & (1 << n)) == 0) {
 987             continue;
 988         }
 989
 990         if (((s->emux >> (n * 4)) & 0xff) != 5) {
 991             continue;
 992         }
 993
 994         /* Some applications use the ADC as a random number source, so introduce
 995            some variation into the signal.  */
 996         s->noise = s->noise * 314159 + 1;
 997         /* ??? actual inputs not implemented.  Return an arbitrary value.  */
 998         stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
 999         s->ris |= (1 << n);
1000         stellaris_adc_update(s);
1001     }
1002 }
1003
1004 static void stellaris_adc_reset(stellaris_adc_state *s)
1005 {
1006     int n;
1007
1008     for (n = 0; n < 4; n++) {
1009         s->ssmux[n] = 0;
1010         s->ssctl[n] = 0;
1011         s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
1012     }
1013 }
1014
1015 static uint32_t stellaris_adc_read(void *opaque, target_phys_addr_t offset)
1016 {
1017     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1018
1019     /* TODO: Implement this.  */
1020     if (offset >= 0x40 && offset < 0xc0) {
1021         int n;
1022         n = (offset - 0x40) >> 5;
1023         switch (offset & 0x1f) {
1024         case 0x00: /* SSMUX */
1025             return s->ssmux[n];
1026         case 0x04: /* SSCTL */
1027             return s->ssctl[n];
1028         case 0x08: /* SSFIFO */
1029             return stellaris_adc_fifo_read(s, n);
1030         case 0x0c: /* SSFSTAT */
1031             return s->fifo[n].state;
1032         default:
1033             break;
1034         }
1035     }
1036     switch (offset) {
1037     case 0x00: /* ACTSS */
1038         return s->actss;
1039     case 0x04: /* RIS */
1040         return s->ris;
1041     case 0x08: /* IM */
1042         return s->im;
1043     case 0x0c: /* ISC */
1044         return s->ris & s->im;
1045     case 0x10: /* OSTAT */
1046         return s->ostat;
1047     case 0x14: /* EMUX */
1048         return s->emux;
1049     case 0x18: /* USTAT */
1050         return s->ustat;
1051     case 0x20: /* SSPRI */
1052         return s->sspri;
1053     case 0x30: /* SAC */
1054         return s->sac;
1055     default:
1056         hw_error("strllaris_adc_read: Bad offset 0x%x\n",
1057                   (int)offset);
1058         return 0;
1059     }
1060 }
1061
1062 static void stellaris_adc_write(void *opaque, target_phys_addr_t offset,
1063                                 uint32_t value)
1064 {
1065     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1066
1067     /* TODO: Implement this.  */
1068     if (offset >= 0x40 && offset < 0xc0) {
1069         int n;
1070         n = (offset - 0x40) >> 5;
1071         switch (offset & 0x1f) {
1072         case 0x00: /* SSMUX */
1073             s->ssmux[n] = value & 0x33333333;
1074             return;
1075         case 0x04: /* SSCTL */
1076             if (value != 6) {
1077                 hw_error("ADC: Unimplemented sequence %x\n",
1078                           value);
1079             }
1080             s->ssctl[n] = value;
1081             return;
1082         default:
1083             break;
1084         }
1085     }
1086     switch (offset) {
1087     case 0x00: /* ACTSS */
1088         s->actss = value & 0xf;
1089         break;
1090     case 0x08: /* IM */
1091         s->im = value;
1092         break;
1093     case 0x0c: /* ISC */
1094         s->ris &= ~value;
1095         break;
1096     case 0x10: /* OSTAT */
1097         s->ostat &= ~value;
1098         break;
1099     case 0x14: /* EMUX */
1100         s->emux = value;
1101         break;
1102     case 0x18: /* USTAT */
1103         s->ustat &= ~value;
1104         break;
1105     case 0x20: /* SSPRI */
1106         s->sspri = value;
1107         break;
1108     case 0x28: /* PSSI */
1109         hw_error("Not implemented:  ADC sample initiate\n");
1110         break;
1111     case 0x30: /* SAC */
1112         s->sac = value;
1113         break;
1114     default:
1115         hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
1116     }
1117     stellaris_adc_update(s);
1118 }
1119
1120 static CPUReadMemoryFunc * const stellaris_adc_readfn[] = {
1121    stellaris_adc_read,
1122    stellaris_adc_read,
1123    stellaris_adc_read
1124 };
1125
1126 static CPUWriteMemoryFunc * const stellaris_adc_writefn[] = {
1127    stellaris_adc_write,
1128    stellaris_adc_write,
1129    stellaris_adc_write
1130 };
1131
1132 static void stellaris_adc_save(QEMUFile *f, void *opaque)
1133 {
1134     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1135     int i;
1136     int j;
1137
1138     qemu_put_be32(f, s->actss);
1139     qemu_put_be32(f, s->ris);
1140     qemu_put_be32(f, s->im);
1141     qemu_put_be32(f, s->emux);
1142     qemu_put_be32(f, s->ostat);
1143     qemu_put_be32(f, s->ustat);
1144     qemu_put_be32(f, s->sspri);
1145     qemu_put_be32(f, s->sac);
1146     for (i = 0; i < 4; i++) {
1147         qemu_put_be32(f, s->fifo[i].state);
1148         for (j = 0; j < 16; j++) {
1149             qemu_put_be32(f, s->fifo[i].data[j]);
1150         }
1151         qemu_put_be32(f, s->ssmux[i]);
1152         qemu_put_be32(f, s->ssctl[i]);
1153     }
1154     qemu_put_be32(f, s->noise);
1155 }
1156
1157 static int stellaris_adc_load(QEMUFile *f, void *opaque, int version_id)
1158 {
1159     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1160     int i;
1161     int j;
1162
1163     if (version_id != 1)
1164         return -EINVAL;
1165
1166     s->actss = qemu_get_be32(f);
1167     s->ris = qemu_get_be32(f);
1168     s->im = qemu_get_be32(f);
1169     s->emux = qemu_get_be32(f);
1170     s->ostat = qemu_get_be32(f);
1171     s->ustat = qemu_get_be32(f);
1172     s->sspri = qemu_get_be32(f);
1173     s->sac = qemu_get_be32(f);
1174     for (i = 0; i < 4; i++) {
1175         s->fifo[i].state = qemu_get_be32(f);
1176         for (j = 0; j < 16; j++) {
1177             s->fifo[i].data[j] = qemu_get_be32(f);
1178         }
1179         s->ssmux[i] = qemu_get_be32(f);
1180         s->ssctl[i] = qemu_get_be32(f);
1181     }
1182     s->noise = qemu_get_be32(f);
1183
1184     return 0;
1185 }
1186
1187 static int stellaris_adc_init(SysBusDevice *dev)
1188 {
1189     stellaris_adc_state *s = FROM_SYSBUS(stellaris_adc_state, dev);
1190     int iomemtype;
1191     int n;
1192
1193     for (n = 0; n < 4; n++) {
1194         sysbus_init_irq(dev, &s->irq[n]);
1195     }
1196
1197     iomemtype = cpu_register_io_memory(stellaris_adc_readfn,
1198                                        stellaris_adc_writefn, s,
1199                                        DEVICE_NATIVE_ENDIAN);
1200     sysbus_init_mmio(dev, 0x1000, iomemtype);
1201     stellaris_adc_reset(s);
1202     qdev_init_gpio_in(&dev->qdev, stellaris_adc_trigger, 1);
1203     register_savevm(&dev->qdev, "stellaris_adc", -1, 1,
1204                     stellaris_adc_save, stellaris_adc_load, s);
1205     return 0;
1206 }
1207
1208 /* Some boards have both an OLED controller and SD card connected to
1209    the same SSI port, with the SD card chip select connected to a
1210    GPIO pin.  Technically the OLED chip select is connected to the SSI
1211    Fss pin.  We do not bother emulating that as both devices should
1212    never be selected simultaneously, and our OLED controller ignores stray
1213    0xff commands that occur when deselecting the SD card.  */
1214
1215 typedef struct {
1216     SSISlave ssidev;
1217     qemu_irq irq;
1218     int current_dev;
1219     SSIBus *bus[2];
1220 } stellaris_ssi_bus_state;
1221
1222 static void stellaris_ssi_bus_select(void *opaque, int irq, int level)
1223 {
1224     stellaris_ssi_bus_state *s = (stellaris_ssi_bus_state *)opaque;
1225
1226     s->current_dev = level;
1227 }
1228
1229 static uint32_t stellaris_ssi_bus_transfer(SSISlave *dev, uint32_t val)
1230 {
1231     stellaris_ssi_bus_state *s = FROM_SSI_SLAVE(stellaris_ssi_bus_state, dev);
1232
1233     return ssi_transfer(s->bus[s->current_dev], val);
1234 }
1235
1236 static void stellaris_ssi_bus_save(QEMUFile *f, void *opaque)
1237 {
1238     stellaris_ssi_bus_state *s = (stellaris_ssi_bus_state *)opaque;
1239
1240     qemu_put_be32(f, s->current_dev);
1241 }
1242
1243 static int stellaris_ssi_bus_load(QEMUFile *f, void *opaque, int version_id)
1244 {
1245     stellaris_ssi_bus_state *s = (stellaris_ssi_bus_state *)opaque;
1246
1247     if (version_id != 1)
1248         return -EINVAL;
1249
1250     s->current_dev = qemu_get_be32(f);
1251
1252     return 0;
1253 }
1254
1255 static int stellaris_ssi_bus_init(SSISlave *dev)
1256 {
1257     stellaris_ssi_bus_state *s = FROM_SSI_SLAVE(stellaris_ssi_bus_state, dev);
1258
1259     s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0");
1260     s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
1261     qdev_init_gpio_in(&dev->qdev, stellaris_ssi_bus_select, 1);
1262
1263     register_savevm(&dev->qdev, "stellaris_ssi_bus", -1, 1,
1264                     stellaris_ssi_bus_save, stellaris_ssi_bus_load, s);
1265     return 0;
1266 }
1267
1268 /* Board init.  */
1269 static stellaris_board_info stellaris_boards[] = {
1270   { "LM3S811EVB",
1271     0,
1272     0x0032000e,
1273     0x001f001f, /* dc0 */
1274     0x001132bf,
1275     0x01071013,
1276     0x3f0f01ff,
1277     0x0000001f,
1278     BP_OLED_I2C
1279   },
1280   { "LM3S6965EVB",
1281     0x10010002,
1282     0x1073402e,
1283     0x00ff007f, /* dc0 */
1284     0x001133ff,
1285     0x030f5317,
1286     0x0f0f87ff,
1287     0x5000007f,
1288     BP_OLED_SSI | BP_GAMEPAD
1289   }
1290 };
1291
1292 static void stellaris_init(const char *kernel_filename, const char *cpu_model,
1293                            stellaris_board_info *board)
1294 {
1295     static const int uart_irq[] = {5, 6, 33, 34};
1296     static const int timer_irq[] = {19, 21, 23, 35};
1297     static const uint32_t gpio_addr[7] =
1298       { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1299         0x40024000, 0x40025000, 0x40026000};
1300     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1301
1302     qemu_irq *pic;
1303     DeviceState *gpio_dev[7];
1304     qemu_irq gpio_in[7][8];
1305     qemu_irq gpio_out[7][8];
1306     qemu_irq adc;
1307     int sram_size;
1308     int flash_size;
1309     i2c_bus *i2c;
1310     DeviceState *dev;
1311     int i;
1312     int j;
1313
1314     flash_size = ((board->dc0 & 0xffff) + 1) << 1;
1315     sram_size = (board->dc0 >> 18) + 1;
1316     pic = armv7m_init(flash_size, sram_size, kernel_filename, cpu_model);
1317
1318     if (board->dc1 & (1 << 16)) {
1319         dev = sysbus_create_varargs("stellaris-adc", 0x40038000,
1320                                     pic[14], pic[15], pic[16], pic[17], NULL);
1321         adc = qdev_get_gpio_in(dev, 0);
1322     } else {
1323         adc = NULL;
1324     }
1325     for (i = 0; i < 4; i++) {
1326         if (board->dc2 & (0x10000 << i)) {
1327             dev = sysbus_create_simple("stellaris-gptm",
1328                                        0x40030000 + i * 0x1000,
1329                                        pic[timer_irq[i]]);
1330             /* TODO: This is incorrect, but we get away with it because
1331                the ADC output is only ever pulsed.  */
1332             qdev_connect_gpio_out(dev, 0, adc);
1333         }
1334     }
1335
1336     stellaris_sys_init(0x400fe000, pic[28], board, nd_table[0].macaddr);
1337
1338     for (i = 0; i < 7; i++) {
1339         if (board->dc4 & (1 << i)) {
1340             gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1341                                                pic[gpio_irq[i]]);
1342             for (j = 0; j < 8; j++) {
1343                 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1344                 gpio_out[i][j] = NULL;
1345             }
1346         }
1347     }
1348
1349     if (board->dc2 & (1 << 12)) {
1350         dev = sysbus_create_simple("stellaris-i2c", 0x40020000, pic[8]);
1351         i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
1352         if (board->peripherals & BP_OLED_I2C) {
1353             i2c_create_slave(i2c, "ssd0303", 0x3d);
1354         }
1355     }
1356
1357     for (i = 0; i < 4; i++) {
1358         if (board->dc2 & (1 << i)) {
1359             sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000,
1360                                  pic[uart_irq[i]]);
1361         }
1362     }
1363     if (board->dc2 & (1 << 4)) {
1364         dev = sysbus_create_simple("pl022", 0x40008000, pic[7]);
1365         if (board->peripherals & BP_OLED_SSI) {
1366             DeviceState *mux;
1367             void *bus;
1368
1369             bus = qdev_get_child_bus(dev, "ssi");
1370             mux = ssi_create_slave(bus, "evb6965-ssi");
1371             gpio_out[GPIO_D][0] = qdev_get_gpio_in(mux, 0);
1372
1373             bus = qdev_get_child_bus(mux, "ssi0");
1374             ssi_create_slave(bus, "ssi-sd");
1375
1376             bus = qdev_get_child_bus(mux, "ssi1");
1377             dev = ssi_create_slave(bus, "ssd0323");
1378             gpio_out[GPIO_C][7] = qdev_get_gpio_in(dev, 0);
1379
1380             /* Make sure the select pin is high.  */
1381             qemu_irq_raise(gpio_out[GPIO_D][0]);
1382         }
1383     }
1384     if (board->dc4 & (1 << 28)) {
1385         DeviceState *enet;
1386
1387         qemu_check_nic_model(&nd_table[0], "stellaris");
1388
1389         enet = qdev_create(NULL, "stellaris_enet");
1390         qdev_set_nic_properties(enet, &nd_table[0]);
1391         qdev_init_nofail(enet);
1392         sysbus_mmio_map(sysbus_from_qdev(enet), 0, 0x40048000);
1393         sysbus_connect_irq(sysbus_from_qdev(enet), 0, pic[42]);
1394     }
1395     if (board->peripherals & BP_GAMEPAD) {
1396         qemu_irq gpad_irq[5];
1397         static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1398
1399         gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1400         gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1401         gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1402         gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1403         gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1404
1405         stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1406     }
1407     for (i = 0; i < 7; i++) {
1408         if (board->dc4 & (1 << i)) {
1409             for (j = 0; j < 8; j++) {
1410                 if (gpio_out[i][j]) {
1411                     qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1412                 }
1413             }
1414         }
1415     }
1416 }
1417
1418 /* FIXME: Figure out how to generate these from stellaris_boards.  */
1419 static void lm3s811evb_init(ram_addr_t ram_size,
1420                      const char *boot_device,
1421                      const char *kernel_filename, const char *kernel_cmdline,
1422                      const char *initrd_filename, const char *cpu_model)
1423 {
1424     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
1425 }
1426
1427 static void lm3s6965evb_init(ram_addr_t ram_size,
1428                      const char *boot_device,
1429                      const char *kernel_filename, const char *kernel_cmdline,
1430                      const char *initrd_filename, const char *cpu_model)
1431 {
1432     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
1433 }
1434
1435 static QEMUMachine lm3s811evb_machine = {
1436     .name = "lm3s811evb",
1437     .desc = "Stellaris LM3S811EVB",
1438     .init = lm3s811evb_init,
1439 };
1440
1441 static QEMUMachine lm3s6965evb_machine = {
1442     .name = "lm3s6965evb",
1443     .desc = "Stellaris LM3S6965EVB",
1444     .init = lm3s6965evb_init,
1445 };
1446
1447 static void stellaris_machine_init(void)
1448 {
1449     qemu_register_machine(&lm3s811evb_machine);
1450     qemu_register_machine(&lm3s6965evb_machine);
1451 }
1452
1453 machine_init(stellaris_machine_init);
1454
1455 static SSISlaveInfo stellaris_ssi_bus_info = {
1456     .qdev.name = "evb6965-ssi",
1457     .qdev.size = sizeof(stellaris_ssi_bus_state),
1458     .init = stellaris_ssi_bus_init,
1459     .transfer = stellaris_ssi_bus_transfer
1460 };
1461
1462 static void stellaris_register_devices(void)
1463 {
1464     sysbus_register_dev("stellaris-i2c", sizeof(stellaris_i2c_state),
1465                         stellaris_i2c_init);
1466     sysbus_register_dev("stellaris-gptm", sizeof(gptm_state),
1467                         stellaris_gptm_init);
1468     sysbus_register_dev("stellaris-adc", sizeof(stellaris_adc_state),
1469                         stellaris_adc_init);
1470     ssi_register_slave(&stellaris_ssi_bus_info);
1471 }
1472
1473 device_init(stellaris_register_devices)