target-ppc/translate_init.c

   1 /*
   2  *  PowerPC CPU initialization for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /* A lot of PowerPC definition have been included here.
  21  * Most of them are not usable for now but have been kept
  22  * inside "#if defined(TODO) ... #endif" statements to make tests easier.
  23  */
  24
  25 #include "dis-asm.h"
  26 #include "gdbstub.h"
  27
  28 //#define PPC_DUMP_CPU
  29 //#define PPC_DEBUG_SPR
  30 //#define PPC_DUMP_SPR_ACCESSES
  31 #if defined(CONFIG_USER_ONLY)
  32 #define TODO_USER_ONLY 1
  33 #endif
  34
  35 struct ppc_def_t {
  36     const char *name;
  37     uint32_t pvr;
  38     uint32_t svr;
  39     uint64_t insns_flags;
  40     uint64_t msr_mask;
  41     powerpc_mmu_t   mmu_model;
  42     powerpc_excp_t  excp_model;
  43     powerpc_input_t bus_model;
  44     uint32_t flags;
  45     int bfd_mach;
  46     void (*init_proc)(CPUPPCState *env);
  47     int  (*check_pow)(CPUPPCState *env);
  48 };
  49
  50 /* For user-mode emulation, we don't emulate any IRQ controller */
  51 #if defined(CONFIG_USER_ONLY)
  52 #define PPC_IRQ_INIT_FN(name)                                                 \
  53 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
  54 {                                                                             \
  55 }
  56 #else
  57 #define PPC_IRQ_INIT_FN(name)                                                 \
  58 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
  59 #endif
  60
  61 PPC_IRQ_INIT_FN(40x);
  62 PPC_IRQ_INIT_FN(6xx);
  63 PPC_IRQ_INIT_FN(970);
  64 PPC_IRQ_INIT_FN(e500);
  65
  66 /* Generic callbacks:
  67  * do nothing but store/retrieve spr value
  68  */
  69 static void spr_read_generic (void *opaque, int gprn, int sprn)
  70 {
  71     gen_load_spr(cpu_gpr[gprn], sprn);
  72 #ifdef PPC_DUMP_SPR_ACCESSES
  73     {
  74         TCGv t0 = tcg_const_i32(sprn);
  75         gen_helper_load_dump_spr(t0);
  76         tcg_temp_free_i32(t0);
  77     }
  78 #endif
  79 }
  80
  81 static void spr_write_generic (void *opaque, int sprn, int gprn)
  82 {
  83     gen_store_spr(sprn, cpu_gpr[gprn]);
  84 #ifdef PPC_DUMP_SPR_ACCESSES
  85     {
  86         TCGv t0 = tcg_const_i32(sprn);
  87         gen_helper_store_dump_spr(t0);
  88         tcg_temp_free_i32(t0);
  89     }
  90 #endif
  91 }
  92
  93 #if !defined(CONFIG_USER_ONLY)
  94 static void spr_write_clear (void *opaque, int sprn, int gprn)
  95 {
  96     TCGv t0 = tcg_temp_new();
  97     TCGv t1 = tcg_temp_new();
  98     gen_load_spr(t0, sprn);
  99     tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
 100     tcg_gen_and_tl(t0, t0, t1);
 101     gen_store_spr(sprn, t0);
 102     tcg_temp_free(t0);
 103     tcg_temp_free(t1);
 104 }
 105 #endif
 106
 107 /* SPR common to all PowerPC */
 108 /* XER */
 109 static void spr_read_xer (void *opaque, int gprn, int sprn)
 110 {
 111     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
 112 }
 113
 114 static void spr_write_xer (void *opaque, int sprn, int gprn)
 115 {
 116     tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
 117 }
 118
 119 /* LR */
 120 static void spr_read_lr (void *opaque, int gprn, int sprn)
 121 {
 122     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
 123 }
 124
 125 static void spr_write_lr (void *opaque, int sprn, int gprn)
 126 {
 127     tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
 128 }
 129
 130 /* CTR */
 131 static void spr_read_ctr (void *opaque, int gprn, int sprn)
 132 {
 133     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
 134 }
 135
 136 static void spr_write_ctr (void *opaque, int sprn, int gprn)
 137 {
 138     tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
 139 }
 140
 141 /* User read access to SPR */
 142 /* USPRx */
 143 /* UMMCRx */
 144 /* UPMCx */
 145 /* USIA */
 146 /* UDECR */
 147 static void spr_read_ureg (void *opaque, int gprn, int sprn)
 148 {
 149     gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
 150 }
 151
 152 /* SPR common to all non-embedded PowerPC */
 153 /* DECR */
 154 #if !defined(CONFIG_USER_ONLY)
 155 static void spr_read_decr (void *opaque, int gprn, int sprn)
 156 {
 157     if (use_icount) {
 158         gen_io_start();
 159     }
 160     gen_helper_load_decr(cpu_gpr[gprn]);
 161     if (use_icount) {
 162         gen_io_end();
 163         gen_stop_exception(opaque);
 164     }
 165 }
 166
 167 static void spr_write_decr (void *opaque, int sprn, int gprn)
 168 {
 169     if (use_icount) {
 170         gen_io_start();
 171     }
 172     gen_helper_store_decr(cpu_gpr[gprn]);
 173     if (use_icount) {
 174         gen_io_end();
 175         gen_stop_exception(opaque);
 176     }
 177 }
 178 #endif
 179
 180 /* SPR common to all non-embedded PowerPC, except 601 */
 181 /* Time base */
 182 static void spr_read_tbl (void *opaque, int gprn, int sprn)
 183 {
 184     if (use_icount) {
 185         gen_io_start();
 186     }
 187     gen_helper_load_tbl(cpu_gpr[gprn]);
 188     if (use_icount) {
 189         gen_io_end();
 190         gen_stop_exception(opaque);
 191     }
 192 }
 193
 194 static void spr_read_tbu (void *opaque, int gprn, int sprn)
 195 {
 196     if (use_icount) {
 197         gen_io_start();
 198     }
 199     gen_helper_load_tbu(cpu_gpr[gprn]);
 200     if (use_icount) {
 201         gen_io_end();
 202         gen_stop_exception(opaque);
 203     }
 204 }
 205
 206 __attribute__ (( unused ))
 207 static void spr_read_atbl (void *opaque, int gprn, int sprn)
 208 {
 209     gen_helper_load_atbl(cpu_gpr[gprn]);
 210 }
 211
 212 __attribute__ (( unused ))
 213 static void spr_read_atbu (void *opaque, int gprn, int sprn)
 214 {
 215     gen_helper_load_atbu(cpu_gpr[gprn]);
 216 }
 217
 218 #if !defined(CONFIG_USER_ONLY)
 219 static void spr_write_tbl (void *opaque, int sprn, int gprn)
 220 {
 221     if (use_icount) {
 222         gen_io_start();
 223     }
 224     gen_helper_store_tbl(cpu_gpr[gprn]);
 225     if (use_icount) {
 226         gen_io_end();
 227         gen_stop_exception(opaque);
 228     }
 229 }
 230
 231 static void spr_write_tbu (void *opaque, int sprn, int gprn)
 232 {
 233     if (use_icount) {
 234         gen_io_start();
 235     }
 236     gen_helper_store_tbu(cpu_gpr[gprn]);
 237     if (use_icount) {
 238         gen_io_end();
 239         gen_stop_exception(opaque);
 240     }
 241 }
 242
 243 __attribute__ (( unused ))
 244 static void spr_write_atbl (void *opaque, int sprn, int gprn)
 245 {
 246     gen_helper_store_atbl(cpu_gpr[gprn]);
 247 }
 248
 249 __attribute__ (( unused ))
 250 static void spr_write_atbu (void *opaque, int sprn, int gprn)
 251 {
 252     gen_helper_store_atbu(cpu_gpr[gprn]);
 253 }
 254 #endif
 255
 256 #if !defined(CONFIG_USER_ONLY)
 257 /* IBAT0U...IBAT0U */
 258 /* IBAT0L...IBAT7L */
 259 static void spr_read_ibat (void *opaque, int gprn, int sprn)
 260 {
 261     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 262 }
 263
 264 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
 265 {
 266     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
 267 }
 268
 269 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
 270 {
 271     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 272     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
 273     tcg_temp_free_i32(t0);
 274 }
 275
 276 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
 277 {
 278     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
 279     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
 280     tcg_temp_free_i32(t0);
 281 }
 282
 283 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
 284 {
 285     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
 286     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
 287     tcg_temp_free_i32(t0);
 288 }
 289
 290 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
 291 {
 292     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
 293     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
 294     tcg_temp_free_i32(t0);
 295 }
 296
 297 /* DBAT0U...DBAT7U */
 298 /* DBAT0L...DBAT7L */
 299 static void spr_read_dbat (void *opaque, int gprn, int sprn)
 300 {
 301     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
 302 }
 303
 304 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
 305 {
 306     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
 307 }
 308
 309 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
 310 {
 311     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
 312     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
 313     tcg_temp_free_i32(t0);
 314 }
 315
 316 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
 317 {
 318     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
 319     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
 320     tcg_temp_free_i32(t0);
 321 }
 322
 323 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
 324 {
 325     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
 326     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
 327     tcg_temp_free_i32(t0);
 328 }
 329
 330 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
 331 {
 332     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
 333     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
 334     tcg_temp_free_i32(t0);
 335 }
 336
 337 /* SDR1 */
 338 static void spr_read_sdr1 (void *opaque, int gprn, int sprn)
 339 {
 340     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));
 341 }
 342
 343 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
 344 {
 345     gen_helper_store_sdr1(cpu_gpr[gprn]);
 346 }
 347
 348 /* 64 bits PowerPC specific SPRs */
 349 /* ASR */
 350 #if defined(TARGET_PPC64)
 351 static void spr_read_hior (void *opaque, int gprn, int sprn)
 352 {
 353     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
 354 }
 355
 356 static void spr_write_hior (void *opaque, int sprn, int gprn)
 357 {
 358     TCGv t0 = tcg_temp_new();
 359     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
 360     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
 361     tcg_temp_free(t0);
 362 }
 363
 364 static void spr_read_asr (void *opaque, int gprn, int sprn)
 365 {
 366     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
 367 }
 368
 369 static void spr_write_asr (void *opaque, int sprn, int gprn)
 370 {
 371     gen_helper_store_asr(cpu_gpr[gprn]);
 372 }
 373 #endif
 374 #endif
 375
 376 /* PowerPC 601 specific registers */
 377 /* RTC */
 378 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
 379 {
 380     gen_helper_load_601_rtcl(cpu_gpr[gprn]);
 381 }
 382
 383 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
 384 {
 385     gen_helper_load_601_rtcu(cpu_gpr[gprn]);
 386 }
 387
 388 #if !defined(CONFIG_USER_ONLY)
 389 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
 390 {
 391     gen_helper_store_601_rtcu(cpu_gpr[gprn]);
 392 }
 393
 394 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
 395 {
 396     gen_helper_store_601_rtcl(cpu_gpr[gprn]);
 397 }
 398
 399 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
 400 {
 401     DisasContext *ctx = opaque;
 402
 403     gen_helper_store_hid0_601(cpu_gpr[gprn]);
 404     /* Must stop the translation as endianness may have changed */
 405     gen_stop_exception(ctx);
 406 }
 407 #endif
 408
 409 /* Unified bats */
 410 #if !defined(CONFIG_USER_ONLY)
 411 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
 412 {
 413     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 414 }
 415
 416 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
 417 {
 418     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 419     gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
 420     tcg_temp_free_i32(t0);
 421 }
 422
 423 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
 424 {
 425     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 426     gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
 427     tcg_temp_free_i32(t0);
 428 }
 429 #endif
 430
 431 /* PowerPC 40x specific registers */
 432 #if !defined(CONFIG_USER_ONLY)
 433 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
 434 {
 435     gen_helper_load_40x_pit(cpu_gpr[gprn]);
 436 }
 437
 438 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
 439 {
 440     gen_helper_store_40x_pit(cpu_gpr[gprn]);
 441 }
 442
 443 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
 444 {
 445     DisasContext *ctx = opaque;
 446
 447     gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
 448     /* We must stop translation as we may have rebooted */
 449     gen_stop_exception(ctx);
 450 }
 451
 452 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
 453 {
 454     gen_helper_store_40x_sler(cpu_gpr[gprn]);
 455 }
 456
 457 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
 458 {
 459     gen_helper_store_booke_tcr(cpu_gpr[gprn]);
 460 }
 461
 462 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
 463 {
 464     gen_helper_store_booke_tsr(cpu_gpr[gprn]);
 465 }
 466 #endif
 467
 468 /* PowerPC 403 specific registers */
 469 /* PBL1 / PBU1 / PBL2 / PBU2 */
 470 #if !defined(CONFIG_USER_ONLY)
 471 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
 472 {
 473     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
 474 }
 475
 476 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
 477 {
 478     TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
 479     gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
 480     tcg_temp_free_i32(t0);
 481 }
 482
 483 static void spr_write_pir (void *opaque, int sprn, int gprn)
 484 {
 485     TCGv t0 = tcg_temp_new();
 486     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
 487     gen_store_spr(SPR_PIR, t0);
 488     tcg_temp_free(t0);
 489 }
 490 #endif
 491
 492 /* SPE specific registers */
 493 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
 494 {
 495     TCGv_i32 t0 = tcg_temp_new_i32();
 496     tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
 497     tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
 498     tcg_temp_free_i32(t0);
 499 }
 500
 501 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
 502 {
 503     TCGv_i32 t0 = tcg_temp_new_i32();
 504     tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
 505     tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
 506     tcg_temp_free_i32(t0);
 507 }
 508
 509 #if !defined(CONFIG_USER_ONLY)
 510 /* Callback used to write the exception vector base */
 511 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
 512 {
 513     TCGv t0 = tcg_temp_new();
 514     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
 515     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 516     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
 517     gen_store_spr(sprn, t0);
 518     tcg_temp_free(t0);
 519 }
 520
 521 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
 522 {
 523     DisasContext *ctx = opaque;
 524
 525     if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
 526         TCGv t0 = tcg_temp_new();
 527         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
 528         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 529         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
 530         gen_store_spr(sprn, t0);
 531         tcg_temp_free(t0);
 532     } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
 533         TCGv t0 = tcg_temp_new();
 534         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
 535         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 536         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
 537         gen_store_spr(sprn, t0);
 538         tcg_temp_free(t0);
 539     } else {
 540         printf("Trying to write an unknown exception vector %d %03x\n",
 541                sprn, sprn);
 542         gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
 543     }
 544 }
 545 #endif
 546
 547 static inline void vscr_init (CPUPPCState *env, uint32_t val)
 548 {
 549     env->vscr = val;
 550     /* Altivec always uses round-to-nearest */
 551     set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
 552     set_flush_to_zero(vscr_nj, &env->vec_status);
 553 }
 554
 555 #if defined(CONFIG_USER_ONLY)
 556 #define spr_register(env, num, name, uea_read, uea_write,                     \
 557                      oea_read, oea_write, initial_value)                      \
 558 do {                                                                          \
 559      _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
 560 } while (0)
 561 static inline void _spr_register (CPUPPCState *env, int num,
 562                                   const char *name,
 563                                   void (*uea_read)(void *opaque, int gprn, int sprn),
 564                                   void (*uea_write)(void *opaque, int sprn, int gprn),
 565                                   target_ulong initial_value)
 566 #else
 567 static inline void spr_register (CPUPPCState *env, int num,
 568                                  const char *name,
 569                                  void (*uea_read)(void *opaque, int gprn, int sprn),
 570                                  void (*uea_write)(void *opaque, int sprn, int gprn),
 571                                  void (*oea_read)(void *opaque, int gprn, int sprn),
 572                                  void (*oea_write)(void *opaque, int sprn, int gprn),
 573                                  target_ulong initial_value)
 574 #endif
 575 {
 576     ppc_spr_t *spr;
 577
 578     spr = &env->spr_cb[num];
 579     if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
 580 #if !defined(CONFIG_USER_ONLY)
 581         spr->oea_read != NULL || spr->oea_write != NULL ||
 582 #endif
 583         spr->uea_read != NULL || spr->uea_write != NULL) {
 584         printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
 585         exit(1);
 586     }
 587 #if defined(PPC_DEBUG_SPR)
 588     printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
 589            name, initial_value);
 590 #endif
 591     spr->name = name;
 592     spr->uea_read = uea_read;
 593     spr->uea_write = uea_write;
 594 #if !defined(CONFIG_USER_ONLY)
 595     spr->oea_read = oea_read;
 596     spr->oea_write = oea_write;
 597 #endif
 598     env->spr[num] = initial_value;
 599 }
 600
 601 /* Generic PowerPC SPRs */
 602 static void gen_spr_generic (CPUPPCState *env)
 603 {
 604     /* Integer processing */
 605     spr_register(env, SPR_XER, "XER",
 606                  &spr_read_xer, &spr_write_xer,
 607                  &spr_read_xer, &spr_write_xer,
 608                  0x00000000);
 609     /* Branch contol */
 610     spr_register(env, SPR_LR, "LR",
 611                  &spr_read_lr, &spr_write_lr,
 612                  &spr_read_lr, &spr_write_lr,
 613                  0x00000000);
 614     spr_register(env, SPR_CTR, "CTR",
 615                  &spr_read_ctr, &spr_write_ctr,
 616                  &spr_read_ctr, &spr_write_ctr,
 617                  0x00000000);
 618     /* Interrupt processing */
 619     spr_register(env, SPR_SRR0, "SRR0",
 620                  SPR_NOACCESS, SPR_NOACCESS,
 621                  &spr_read_generic, &spr_write_generic,
 622                  0x00000000);
 623     spr_register(env, SPR_SRR1, "SRR1",
 624                  SPR_NOACCESS, SPR_NOACCESS,
 625                  &spr_read_generic, &spr_write_generic,
 626                  0x00000000);
 627     /* Processor control */
 628     spr_register(env, SPR_SPRG0, "SPRG0",
 629                  SPR_NOACCESS, SPR_NOACCESS,
 630                  &spr_read_generic, &spr_write_generic,
 631                  0x00000000);
 632     spr_register(env, SPR_SPRG1, "SPRG1",
 633                  SPR_NOACCESS, SPR_NOACCESS,
 634                  &spr_read_generic, &spr_write_generic,
 635                  0x00000000);
 636     spr_register(env, SPR_SPRG2, "SPRG2",
 637                  SPR_NOACCESS, SPR_NOACCESS,
 638                  &spr_read_generic, &spr_write_generic,
 639                  0x00000000);
 640     spr_register(env, SPR_SPRG3, "SPRG3",
 641                  SPR_NOACCESS, SPR_NOACCESS,
 642                  &spr_read_generic, &spr_write_generic,
 643                  0x00000000);
 644 }
 645
 646 /* SPR common to all non-embedded PowerPC, including 601 */
 647 static void gen_spr_ne_601 (CPUPPCState *env)
 648 {
 649     /* Exception processing */
 650     spr_register(env, SPR_DSISR, "DSISR",
 651                  SPR_NOACCESS, SPR_NOACCESS,
 652                  &spr_read_generic, &spr_write_generic,
 653                  0x00000000);
 654     spr_register(env, SPR_DAR, "DAR",
 655                  SPR_NOACCESS, SPR_NOACCESS,
 656                  &spr_read_generic, &spr_write_generic,
 657                  0x00000000);
 658     /* Timer */
 659     spr_register(env, SPR_DECR, "DECR",
 660                  SPR_NOACCESS, SPR_NOACCESS,
 661                  &spr_read_decr, &spr_write_decr,
 662                  0x00000000);
 663     /* Memory management */
 664     spr_register(env, SPR_SDR1, "SDR1",
 665                  SPR_NOACCESS, SPR_NOACCESS,
 666                  &spr_read_sdr1, &spr_write_sdr1,
 667                  0x00000000);
 668 }
 669
 670 /* BATs 0-3 */
 671 static void gen_low_BATs (CPUPPCState *env)
 672 {
 673 #if !defined(CONFIG_USER_ONLY)
 674     spr_register(env, SPR_IBAT0U, "IBAT0U",
 675                  SPR_NOACCESS, SPR_NOACCESS,
 676                  &spr_read_ibat, &spr_write_ibatu,
 677                  0x00000000);
 678     spr_register(env, SPR_IBAT0L, "IBAT0L",
 679                  SPR_NOACCESS, SPR_NOACCESS,
 680                  &spr_read_ibat, &spr_write_ibatl,
 681                  0x00000000);
 682     spr_register(env, SPR_IBAT1U, "IBAT1U",
 683                  SPR_NOACCESS, SPR_NOACCESS,
 684                  &spr_read_ibat, &spr_write_ibatu,
 685                  0x00000000);
 686     spr_register(env, SPR_IBAT1L, "IBAT1L",
 687                  SPR_NOACCESS, SPR_NOACCESS,
 688                  &spr_read_ibat, &spr_write_ibatl,
 689                  0x00000000);
 690     spr_register(env, SPR_IBAT2U, "IBAT2U",
 691                  SPR_NOACCESS, SPR_NOACCESS,
 692                  &spr_read_ibat, &spr_write_ibatu,
 693                  0x00000000);
 694     spr_register(env, SPR_IBAT2L, "IBAT2L",
 695                  SPR_NOACCESS, SPR_NOACCESS,
 696                  &spr_read_ibat, &spr_write_ibatl,
 697                  0x00000000);
 698     spr_register(env, SPR_IBAT3U, "IBAT3U",
 699                  SPR_NOACCESS, SPR_NOACCESS,
 700                  &spr_read_ibat, &spr_write_ibatu,
 701                  0x00000000);
 702     spr_register(env, SPR_IBAT3L, "IBAT3L",
 703                  SPR_NOACCESS, SPR_NOACCESS,
 704                  &spr_read_ibat, &spr_write_ibatl,
 705                  0x00000000);
 706     spr_register(env, SPR_DBAT0U, "DBAT0U",
 707                  SPR_NOACCESS, SPR_NOACCESS,
 708                  &spr_read_dbat, &spr_write_dbatu,
 709                  0x00000000);
 710     spr_register(env, SPR_DBAT0L, "DBAT0L",
 711                  SPR_NOACCESS, SPR_NOACCESS,
 712                  &spr_read_dbat, &spr_write_dbatl,
 713                  0x00000000);
 714     spr_register(env, SPR_DBAT1U, "DBAT1U",
 715                  SPR_NOACCESS, SPR_NOACCESS,
 716                  &spr_read_dbat, &spr_write_dbatu,
 717                  0x00000000);
 718     spr_register(env, SPR_DBAT1L, "DBAT1L",
 719                  SPR_NOACCESS, SPR_NOACCESS,
 720                  &spr_read_dbat, &spr_write_dbatl,
 721                  0x00000000);
 722     spr_register(env, SPR_DBAT2U, "DBAT2U",
 723                  SPR_NOACCESS, SPR_NOACCESS,
 724                  &spr_read_dbat, &spr_write_dbatu,
 725                  0x00000000);
 726     spr_register(env, SPR_DBAT2L, "DBAT2L",
 727                  SPR_NOACCESS, SPR_NOACCESS,
 728                  &spr_read_dbat, &spr_write_dbatl,
 729                  0x00000000);
 730     spr_register(env, SPR_DBAT3U, "DBAT3U",
 731                  SPR_NOACCESS, SPR_NOACCESS,
 732                  &spr_read_dbat, &spr_write_dbatu,
 733                  0x00000000);
 734     spr_register(env, SPR_DBAT3L, "DBAT3L",
 735                  SPR_NOACCESS, SPR_NOACCESS,
 736                  &spr_read_dbat, &spr_write_dbatl,
 737                  0x00000000);
 738     env->nb_BATs += 4;
 739 #endif
 740 }
 741
 742 /* BATs 4-7 */
 743 static void gen_high_BATs (CPUPPCState *env)
 744 {
 745 #if !defined(CONFIG_USER_ONLY)
 746     spr_register(env, SPR_IBAT4U, "IBAT4U",
 747                  SPR_NOACCESS, SPR_NOACCESS,
 748                  &spr_read_ibat_h, &spr_write_ibatu_h,
 749                  0x00000000);
 750     spr_register(env, SPR_IBAT4L, "IBAT4L",
 751                  SPR_NOACCESS, SPR_NOACCESS,
 752                  &spr_read_ibat_h, &spr_write_ibatl_h,
 753                  0x00000000);
 754     spr_register(env, SPR_IBAT5U, "IBAT5U",
 755                  SPR_NOACCESS, SPR_NOACCESS,
 756                  &spr_read_ibat_h, &spr_write_ibatu_h,
 757                  0x00000000);
 758     spr_register(env, SPR_IBAT5L, "IBAT5L",
 759                  SPR_NOACCESS, SPR_NOACCESS,
 760                  &spr_read_ibat_h, &spr_write_ibatl_h,
 761                  0x00000000);
 762     spr_register(env, SPR_IBAT6U, "IBAT6U",
 763                  SPR_NOACCESS, SPR_NOACCESS,
 764                  &spr_read_ibat_h, &spr_write_ibatu_h,
 765                  0x00000000);
 766     spr_register(env, SPR_IBAT6L, "IBAT6L",
 767                  SPR_NOACCESS, SPR_NOACCESS,
 768                  &spr_read_ibat_h, &spr_write_ibatl_h,
 769                  0x00000000);
 770     spr_register(env, SPR_IBAT7U, "IBAT7U",
 771                  SPR_NOACCESS, SPR_NOACCESS,
 772                  &spr_read_ibat_h, &spr_write_ibatu_h,
 773                  0x00000000);
 774     spr_register(env, SPR_IBAT7L, "IBAT7L",
 775                  SPR_NOACCESS, SPR_NOACCESS,
 776                  &spr_read_ibat_h, &spr_write_ibatl_h,
 777                  0x00000000);
 778     spr_register(env, SPR_DBAT4U, "DBAT4U",
 779                  SPR_NOACCESS, SPR_NOACCESS,
 780                  &spr_read_dbat_h, &spr_write_dbatu_h,
 781                  0x00000000);
 782     spr_register(env, SPR_DBAT4L, "DBAT4L",
 783                  SPR_NOACCESS, SPR_NOACCESS,
 784                  &spr_read_dbat_h, &spr_write_dbatl_h,
 785                  0x00000000);
 786     spr_register(env, SPR_DBAT5U, "DBAT5U",
 787                  SPR_NOACCESS, SPR_NOACCESS,
 788                  &spr_read_dbat_h, &spr_write_dbatu_h,
 789                  0x00000000);
 790     spr_register(env, SPR_DBAT5L, "DBAT5L",
 791                  SPR_NOACCESS, SPR_NOACCESS,
 792                  &spr_read_dbat_h, &spr_write_dbatl_h,
 793                  0x00000000);
 794     spr_register(env, SPR_DBAT6U, "DBAT6U",
 795                  SPR_NOACCESS, SPR_NOACCESS,
 796                  &spr_read_dbat_h, &spr_write_dbatu_h,
 797                  0x00000000);
 798     spr_register(env, SPR_DBAT6L, "DBAT6L",
 799                  SPR_NOACCESS, SPR_NOACCESS,
 800                  &spr_read_dbat_h, &spr_write_dbatl_h,
 801                  0x00000000);
 802     spr_register(env, SPR_DBAT7U, "DBAT7U",
 803                  SPR_NOACCESS, SPR_NOACCESS,
 804                  &spr_read_dbat_h, &spr_write_dbatu_h,
 805                  0x00000000);
 806     spr_register(env, SPR_DBAT7L, "DBAT7L",
 807                  SPR_NOACCESS, SPR_NOACCESS,
 808                  &spr_read_dbat_h, &spr_write_dbatl_h,
 809                  0x00000000);
 810     env->nb_BATs += 4;
 811 #endif
 812 }
 813
 814 /* Generic PowerPC time base */
 815 static void gen_tbl (CPUPPCState *env)
 816 {
 817     spr_register(env, SPR_VTBL,  "TBL",
 818                  &spr_read_tbl, SPR_NOACCESS,
 819                  &spr_read_tbl, SPR_NOACCESS,
 820                  0x00000000);
 821     spr_register(env, SPR_TBL,   "TBL",
 822                  &spr_read_tbl, SPR_NOACCESS,
 823                  &spr_read_tbl, &spr_write_tbl,
 824                  0x00000000);
 825     spr_register(env, SPR_VTBU,  "TBU",
 826                  &spr_read_tbu, SPR_NOACCESS,
 827                  &spr_read_tbu, SPR_NOACCESS,
 828                  0x00000000);
 829     spr_register(env, SPR_TBU,   "TBU",
 830                  &spr_read_tbu, SPR_NOACCESS,
 831                  &spr_read_tbu, &spr_write_tbu,
 832                  0x00000000);
 833 }
 834
 835 /* Softare table search registers */
 836 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
 837 {
 838 #if !defined(CONFIG_USER_ONLY)
 839     env->nb_tlb = nb_tlbs;
 840     env->nb_ways = nb_ways;
 841     env->id_tlbs = 1;
 842     spr_register(env, SPR_DMISS, "DMISS",
 843                  SPR_NOACCESS, SPR_NOACCESS,
 844                  &spr_read_generic, SPR_NOACCESS,
 845                  0x00000000);
 846     spr_register(env, SPR_DCMP, "DCMP",
 847                  SPR_NOACCESS, SPR_NOACCESS,
 848                  &spr_read_generic, SPR_NOACCESS,
 849                  0x00000000);
 850     spr_register(env, SPR_HASH1, "HASH1",
 851                  SPR_NOACCESS, SPR_NOACCESS,
 852                  &spr_read_generic, SPR_NOACCESS,
 853                  0x00000000);
 854     spr_register(env, SPR_HASH2, "HASH2",
 855                  SPR_NOACCESS, SPR_NOACCESS,
 856                  &spr_read_generic, SPR_NOACCESS,
 857                  0x00000000);
 858     spr_register(env, SPR_IMISS, "IMISS",
 859                  SPR_NOACCESS, SPR_NOACCESS,
 860                  &spr_read_generic, SPR_NOACCESS,
 861                  0x00000000);
 862     spr_register(env, SPR_ICMP, "ICMP",
 863                  SPR_NOACCESS, SPR_NOACCESS,
 864                  &spr_read_generic, SPR_NOACCESS,
 865                  0x00000000);
 866     spr_register(env, SPR_RPA, "RPA",
 867                  SPR_NOACCESS, SPR_NOACCESS,
 868                  &spr_read_generic, &spr_write_generic,
 869                  0x00000000);
 870 #endif
 871 }
 872
 873 /* SPR common to MPC755 and G2 */
 874 static void gen_spr_G2_755 (CPUPPCState *env)
 875 {
 876     /* SGPRs */
 877     spr_register(env, SPR_SPRG4, "SPRG4",
 878                  SPR_NOACCESS, SPR_NOACCESS,
 879                  &spr_read_generic, &spr_write_generic,
 880                  0x00000000);
 881     spr_register(env, SPR_SPRG5, "SPRG5",
 882                  SPR_NOACCESS, SPR_NOACCESS,
 883                  &spr_read_generic, &spr_write_generic,
 884                  0x00000000);
 885     spr_register(env, SPR_SPRG6, "SPRG6",
 886                  SPR_NOACCESS, SPR_NOACCESS,
 887                  &spr_read_generic, &spr_write_generic,
 888                  0x00000000);
 889     spr_register(env, SPR_SPRG7, "SPRG7",
 890                  SPR_NOACCESS, SPR_NOACCESS,
 891                  &spr_read_generic, &spr_write_generic,
 892                  0x00000000);
 893 }
 894
 895 /* SPR common to all 7xx PowerPC implementations */
 896 static void gen_spr_7xx (CPUPPCState *env)
 897 {
 898     /* Breakpoints */
 899     /* XXX : not implemented */
 900     spr_register(env, SPR_DABR, "DABR",
 901                  SPR_NOACCESS, SPR_NOACCESS,
 902                  &spr_read_generic, &spr_write_generic,
 903                  0x00000000);
 904     /* XXX : not implemented */
 905     spr_register(env, SPR_IABR, "IABR",
 906                  SPR_NOACCESS, SPR_NOACCESS,
 907                  &spr_read_generic, &spr_write_generic,
 908                  0x00000000);
 909     /* Cache management */
 910     /* XXX : not implemented */
 911     spr_register(env, SPR_ICTC, "ICTC",
 912                  SPR_NOACCESS, SPR_NOACCESS,
 913                  &spr_read_generic, &spr_write_generic,
 914                  0x00000000);
 915     /* Performance monitors */
 916     /* XXX : not implemented */
 917     spr_register(env, SPR_MMCR0, "MMCR0",
 918                  SPR_NOACCESS, SPR_NOACCESS,
 919                  &spr_read_generic, &spr_write_generic,
 920                  0x00000000);
 921     /* XXX : not implemented */
 922     spr_register(env, SPR_MMCR1, "MMCR1",
 923                  SPR_NOACCESS, SPR_NOACCESS,
 924                  &spr_read_generic, &spr_write_generic,
 925                  0x00000000);
 926     /* XXX : not implemented */
 927     spr_register(env, SPR_PMC1, "PMC1",
 928                  SPR_NOACCESS, SPR_NOACCESS,
 929                  &spr_read_generic, &spr_write_generic,
 930                  0x00000000);
 931     /* XXX : not implemented */
 932     spr_register(env, SPR_PMC2, "PMC2",
 933                  SPR_NOACCESS, SPR_NOACCESS,
 934                  &spr_read_generic, &spr_write_generic,
 935                  0x00000000);
 936     /* XXX : not implemented */
 937     spr_register(env, SPR_PMC3, "PMC3",
 938                  SPR_NOACCESS, SPR_NOACCESS,
 939                  &spr_read_generic, &spr_write_generic,
 940                  0x00000000);
 941     /* XXX : not implemented */
 942     spr_register(env, SPR_PMC4, "PMC4",
 943                  SPR_NOACCESS, SPR_NOACCESS,
 944                  &spr_read_generic, &spr_write_generic,
 945                  0x00000000);
 946     /* XXX : not implemented */
 947     spr_register(env, SPR_SIAR, "SIAR",
 948                  SPR_NOACCESS, SPR_NOACCESS,
 949                  &spr_read_generic, SPR_NOACCESS,
 950                  0x00000000);
 951     /* XXX : not implemented */
 952     spr_register(env, SPR_UMMCR0, "UMMCR0",
 953                  &spr_read_ureg, SPR_NOACCESS,
 954                  &spr_read_ureg, SPR_NOACCESS,
 955                  0x00000000);
 956     /* XXX : not implemented */
 957     spr_register(env, SPR_UMMCR1, "UMMCR1",
 958                  &spr_read_ureg, SPR_NOACCESS,
 959                  &spr_read_ureg, SPR_NOACCESS,
 960                  0x00000000);
 961     /* XXX : not implemented */
 962     spr_register(env, SPR_UPMC1, "UPMC1",
 963                  &spr_read_ureg, SPR_NOACCESS,
 964                  &spr_read_ureg, SPR_NOACCESS,
 965                  0x00000000);
 966     /* XXX : not implemented */
 967     spr_register(env, SPR_UPMC2, "UPMC2",
 968                  &spr_read_ureg, SPR_NOACCESS,
 969                  &spr_read_ureg, SPR_NOACCESS,
 970                  0x00000000);
 971     /* XXX : not implemented */
 972     spr_register(env, SPR_UPMC3, "UPMC3",
 973                  &spr_read_ureg, SPR_NOACCESS,
 974                  &spr_read_ureg, SPR_NOACCESS,
 975                  0x00000000);
 976     /* XXX : not implemented */
 977     spr_register(env, SPR_UPMC4, "UPMC4",
 978                  &spr_read_ureg, SPR_NOACCESS,
 979                  &spr_read_ureg, SPR_NOACCESS,
 980                  0x00000000);
 981     /* XXX : not implemented */
 982     spr_register(env, SPR_USIAR, "USIAR",
 983                  &spr_read_ureg, SPR_NOACCESS,
 984                  &spr_read_ureg, SPR_NOACCESS,
 985                  0x00000000);
 986     /* External access control */
 987     /* XXX : not implemented */
 988     spr_register(env, SPR_EAR, "EAR",
 989                  SPR_NOACCESS, SPR_NOACCESS,
 990                  &spr_read_generic, &spr_write_generic,
 991                  0x00000000);
 992 }
 993
 994 static void gen_spr_thrm (CPUPPCState *env)
 995 {
 996     /* Thermal management */
 997     /* XXX : not implemented */
 998     spr_register(env, SPR_THRM1, "THRM1",
 999                  SPR_NOACCESS, SPR_NOACCESS,
1000                  &spr_read_generic, &spr_write_generic,
1001                  0x00000000);
1002     /* XXX : not implemented */
1003     spr_register(env, SPR_THRM2, "THRM2",
1004                  SPR_NOACCESS, SPR_NOACCESS,
1005                  &spr_read_generic, &spr_write_generic,
1006                  0x00000000);
1007     /* XXX : not implemented */
1008     spr_register(env, SPR_THRM3, "THRM3",
1009                  SPR_NOACCESS, SPR_NOACCESS,
1010                  &spr_read_generic, &spr_write_generic,
1011                  0x00000000);
1012 }
1013
1014 /* SPR specific to PowerPC 604 implementation */
1015 static void gen_spr_604 (CPUPPCState *env)
1016 {
1017     /* Processor identification */
1018     spr_register(env, SPR_PIR, "PIR",
1019                  SPR_NOACCESS, SPR_NOACCESS,
1020                  &spr_read_generic, &spr_write_pir,
1021                  0x00000000);
1022     /* Breakpoints */
1023     /* XXX : not implemented */
1024     spr_register(env, SPR_IABR, "IABR",
1025                  SPR_NOACCESS, SPR_NOACCESS,
1026                  &spr_read_generic, &spr_write_generic,
1027                  0x00000000);
1028     /* XXX : not implemented */
1029     spr_register(env, SPR_DABR, "DABR",
1030                  SPR_NOACCESS, SPR_NOACCESS,
1031                  &spr_read_generic, &spr_write_generic,
1032                  0x00000000);
1033     /* Performance counters */
1034     /* XXX : not implemented */
1035     spr_register(env, SPR_MMCR0, "MMCR0",
1036                  SPR_NOACCESS, SPR_NOACCESS,
1037                  &spr_read_generic, &spr_write_generic,
1038                  0x00000000);
1039     /* XXX : not implemented */
1040     spr_register(env, SPR_PMC1, "PMC1",
1041                  SPR_NOACCESS, SPR_NOACCESS,
1042                  &spr_read_generic, &spr_write_generic,
1043                  0x00000000);
1044     /* XXX : not implemented */
1045     spr_register(env, SPR_PMC2, "PMC2",
1046                  SPR_NOACCESS, SPR_NOACCESS,
1047                  &spr_read_generic, &spr_write_generic,
1048                  0x00000000);
1049     /* XXX : not implemented */
1050     spr_register(env, SPR_SIAR, "SIAR",
1051                  SPR_NOACCESS, SPR_NOACCESS,
1052                  &spr_read_generic, SPR_NOACCESS,
1053                  0x00000000);
1054     /* XXX : not implemented */
1055     spr_register(env, SPR_SDA, "SDA",
1056                  SPR_NOACCESS, SPR_NOACCESS,
1057                  &spr_read_generic, SPR_NOACCESS,
1058                  0x00000000);
1059     /* External access control */
1060     /* XXX : not implemented */
1061     spr_register(env, SPR_EAR, "EAR",
1062                  SPR_NOACCESS, SPR_NOACCESS,
1063                  &spr_read_generic, &spr_write_generic,
1064                  0x00000000);
1065 }
1066
1067 /* SPR specific to PowerPC 603 implementation */
1068 static void gen_spr_603 (CPUPPCState *env)
1069 {
1070     /* External access control */
1071     /* XXX : not implemented */
1072     spr_register(env, SPR_EAR, "EAR",
1073                  SPR_NOACCESS, SPR_NOACCESS,
1074                  &spr_read_generic, &spr_write_generic,
1075                  0x00000000);
1076 }
1077
1078 /* SPR specific to PowerPC G2 implementation */
1079 static void gen_spr_G2 (CPUPPCState *env)
1080 {
1081     /* Memory base address */
1082     /* MBAR */
1083     /* XXX : not implemented */
1084     spr_register(env, SPR_MBAR, "MBAR",
1085                  SPR_NOACCESS, SPR_NOACCESS,
1086                  &spr_read_generic, &spr_write_generic,
1087                  0x00000000);
1088     /* Exception processing */
1089     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1090                  SPR_NOACCESS, SPR_NOACCESS,
1091                  &spr_read_generic, &spr_write_generic,
1092                  0x00000000);
1093     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1094                  SPR_NOACCESS, SPR_NOACCESS,
1095                  &spr_read_generic, &spr_write_generic,
1096                  0x00000000);
1097     /* Breakpoints */
1098     /* XXX : not implemented */
1099     spr_register(env, SPR_DABR, "DABR",
1100                  SPR_NOACCESS, SPR_NOACCESS,
1101                  &spr_read_generic, &spr_write_generic,
1102                  0x00000000);
1103     /* XXX : not implemented */
1104     spr_register(env, SPR_DABR2, "DABR2",
1105                  SPR_NOACCESS, SPR_NOACCESS,
1106                  &spr_read_generic, &spr_write_generic,
1107                  0x00000000);
1108     /* XXX : not implemented */
1109     spr_register(env, SPR_IABR, "IABR",
1110                  SPR_NOACCESS, SPR_NOACCESS,
1111                  &spr_read_generic, &spr_write_generic,
1112                  0x00000000);
1113     /* XXX : not implemented */
1114     spr_register(env, SPR_IABR2, "IABR2",
1115                  SPR_NOACCESS, SPR_NOACCESS,
1116                  &spr_read_generic, &spr_write_generic,
1117                  0x00000000);
1118     /* XXX : not implemented */
1119     spr_register(env, SPR_IBCR, "IBCR",
1120                  SPR_NOACCESS, SPR_NOACCESS,
1121                  &spr_read_generic, &spr_write_generic,
1122                  0x00000000);
1123     /* XXX : not implemented */
1124     spr_register(env, SPR_DBCR, "DBCR",
1125                  SPR_NOACCESS, SPR_NOACCESS,
1126                  &spr_read_generic, &spr_write_generic,
1127                  0x00000000);
1128 }
1129
1130 /* SPR specific to PowerPC 602 implementation */
1131 static void gen_spr_602 (CPUPPCState *env)
1132 {
1133     /* ESA registers */
1134     /* XXX : not implemented */
1135     spr_register(env, SPR_SER, "SER",
1136                  SPR_NOACCESS, SPR_NOACCESS,
1137                  &spr_read_generic, &spr_write_generic,
1138                  0x00000000);
1139     /* XXX : not implemented */
1140     spr_register(env, SPR_SEBR, "SEBR",
1141                  SPR_NOACCESS, SPR_NOACCESS,
1142                  &spr_read_generic, &spr_write_generic,
1143                  0x00000000);
1144     /* XXX : not implemented */
1145     spr_register(env, SPR_ESASRR, "ESASRR",
1146                  SPR_NOACCESS, SPR_NOACCESS,
1147                  &spr_read_generic, &spr_write_generic,
1148                  0x00000000);
1149     /* Floating point status */
1150     /* XXX : not implemented */
1151     spr_register(env, SPR_SP, "SP",
1152                  SPR_NOACCESS, SPR_NOACCESS,
1153                  &spr_read_generic, &spr_write_generic,
1154                  0x00000000);
1155     /* XXX : not implemented */
1156     spr_register(env, SPR_LT, "LT",
1157                  SPR_NOACCESS, SPR_NOACCESS,
1158                  &spr_read_generic, &spr_write_generic,
1159                  0x00000000);
1160     /* Watchdog timer */
1161     /* XXX : not implemented */
1162     spr_register(env, SPR_TCR, "TCR",
1163                  SPR_NOACCESS, SPR_NOACCESS,
1164                  &spr_read_generic, &spr_write_generic,
1165                  0x00000000);
1166     /* Interrupt base */
1167     spr_register(env, SPR_IBR, "IBR",
1168                  SPR_NOACCESS, SPR_NOACCESS,
1169                  &spr_read_generic, &spr_write_generic,
1170                  0x00000000);
1171     /* XXX : not implemented */
1172     spr_register(env, SPR_IABR, "IABR",
1173                  SPR_NOACCESS, SPR_NOACCESS,
1174                  &spr_read_generic, &spr_write_generic,
1175                  0x00000000);
1176 }
1177
1178 /* SPR specific to PowerPC 601 implementation */
1179 static void gen_spr_601 (CPUPPCState *env)
1180 {
1181     /* Multiplication/division register */
1182     /* MQ */
1183     spr_register(env, SPR_MQ, "MQ",
1184                  &spr_read_generic, &spr_write_generic,
1185                  &spr_read_generic, &spr_write_generic,
1186                  0x00000000);
1187     /* RTC registers */
1188     spr_register(env, SPR_601_RTCU, "RTCU",
1189                  SPR_NOACCESS, SPR_NOACCESS,
1190                  SPR_NOACCESS, &spr_write_601_rtcu,
1191                  0x00000000);
1192     spr_register(env, SPR_601_VRTCU, "RTCU",
1193                  &spr_read_601_rtcu, SPR_NOACCESS,
1194                  &spr_read_601_rtcu, SPR_NOACCESS,
1195                  0x00000000);
1196     spr_register(env, SPR_601_RTCL, "RTCL",
1197                  SPR_NOACCESS, SPR_NOACCESS,
1198                  SPR_NOACCESS, &spr_write_601_rtcl,
1199                  0x00000000);
1200     spr_register(env, SPR_601_VRTCL, "RTCL",
1201                  &spr_read_601_rtcl, SPR_NOACCESS,
1202                  &spr_read_601_rtcl, SPR_NOACCESS,
1203                  0x00000000);
1204     /* Timer */
1205 #if 0 /* ? */
1206     spr_register(env, SPR_601_UDECR, "UDECR",
1207                  &spr_read_decr, SPR_NOACCESS,
1208                  &spr_read_decr, SPR_NOACCESS,
1209                  0x00000000);
1210 #endif
1211     /* External access control */
1212     /* XXX : not implemented */
1213     spr_register(env, SPR_EAR, "EAR",
1214                  SPR_NOACCESS, SPR_NOACCESS,
1215                  &spr_read_generic, &spr_write_generic,
1216                  0x00000000);
1217     /* Memory management */
1218 #if !defined(CONFIG_USER_ONLY)
1219     spr_register(env, SPR_IBAT0U, "IBAT0U",
1220                  SPR_NOACCESS, SPR_NOACCESS,
1221                  &spr_read_601_ubat, &spr_write_601_ubatu,
1222                  0x00000000);
1223     spr_register(env, SPR_IBAT0L, "IBAT0L",
1224                  SPR_NOACCESS, SPR_NOACCESS,
1225                  &spr_read_601_ubat, &spr_write_601_ubatl,
1226                  0x00000000);
1227     spr_register(env, SPR_IBAT1U, "IBAT1U",
1228                  SPR_NOACCESS, SPR_NOACCESS,
1229                  &spr_read_601_ubat, &spr_write_601_ubatu,
1230                  0x00000000);
1231     spr_register(env, SPR_IBAT1L, "IBAT1L",
1232                  SPR_NOACCESS, SPR_NOACCESS,
1233                  &spr_read_601_ubat, &spr_write_601_ubatl,
1234                  0x00000000);
1235     spr_register(env, SPR_IBAT2U, "IBAT2U",
1236                  SPR_NOACCESS, SPR_NOACCESS,
1237                  &spr_read_601_ubat, &spr_write_601_ubatu,
1238                  0x00000000);
1239     spr_register(env, SPR_IBAT2L, "IBAT2L",
1240                  SPR_NOACCESS, SPR_NOACCESS,
1241                  &spr_read_601_ubat, &spr_write_601_ubatl,
1242                  0x00000000);
1243     spr_register(env, SPR_IBAT3U, "IBAT3U",
1244                  SPR_NOACCESS, SPR_NOACCESS,
1245                  &spr_read_601_ubat, &spr_write_601_ubatu,
1246                  0x00000000);
1247     spr_register(env, SPR_IBAT3L, "IBAT3L",
1248                  SPR_NOACCESS, SPR_NOACCESS,
1249                  &spr_read_601_ubat, &spr_write_601_ubatl,
1250                  0x00000000);
1251     env->nb_BATs = 4;
1252 #endif
1253 }
1254
1255 static void gen_spr_74xx (CPUPPCState *env)
1256 {
1257     /* Processor identification */
1258     spr_register(env, SPR_PIR, "PIR",
1259                  SPR_NOACCESS, SPR_NOACCESS,
1260                  &spr_read_generic, &spr_write_pir,
1261                  0x00000000);
1262     /* XXX : not implemented */
1263     spr_register(env, SPR_MMCR2, "MMCR2",
1264                  SPR_NOACCESS, SPR_NOACCESS,
1265                  &spr_read_generic, &spr_write_generic,
1266                  0x00000000);
1267     /* XXX : not implemented */
1268     spr_register(env, SPR_UMMCR2, "UMMCR2",
1269                  &spr_read_ureg, SPR_NOACCESS,
1270                  &spr_read_ureg, SPR_NOACCESS,
1271                  0x00000000);
1272     /* XXX: not implemented */
1273     spr_register(env, SPR_BAMR, "BAMR",
1274                  SPR_NOACCESS, SPR_NOACCESS,
1275                  &spr_read_generic, &spr_write_generic,
1276                  0x00000000);
1277     /* XXX : not implemented */
1278     spr_register(env, SPR_MSSCR0, "MSSCR0",
1279                  SPR_NOACCESS, SPR_NOACCESS,
1280                  &spr_read_generic, &spr_write_generic,
1281                  0x00000000);
1282     /* Hardware implementation registers */
1283     /* XXX : not implemented */
1284     spr_register(env, SPR_HID0, "HID0",
1285                  SPR_NOACCESS, SPR_NOACCESS,
1286                  &spr_read_generic, &spr_write_generic,
1287                  0x00000000);
1288     /* XXX : not implemented */
1289     spr_register(env, SPR_HID1, "HID1",
1290                  SPR_NOACCESS, SPR_NOACCESS,
1291                  &spr_read_generic, &spr_write_generic,
1292                  0x00000000);
1293     /* Altivec */
1294     spr_register(env, SPR_VRSAVE, "VRSAVE",
1295                  &spr_read_generic, &spr_write_generic,
1296                  &spr_read_generic, &spr_write_generic,
1297                  0x00000000);
1298     /* XXX : not implemented */
1299     spr_register(env, SPR_L2CR, "L2CR",
1300                  SPR_NOACCESS, SPR_NOACCESS,
1301                  &spr_read_generic, &spr_write_generic,
1302                  0x00000000);
1303     /* Not strictly an SPR */
1304     vscr_init(env, 0x00010000);
1305 }
1306
1307 static void gen_l3_ctrl (CPUPPCState *env)
1308 {
1309     /* L3CR */
1310     /* XXX : not implemented */
1311     spr_register(env, SPR_L3CR, "L3CR",
1312                  SPR_NOACCESS, SPR_NOACCESS,
1313                  &spr_read_generic, &spr_write_generic,
1314                  0x00000000);
1315     /* L3ITCR0 */
1316     /* XXX : not implemented */
1317     spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1318                  SPR_NOACCESS, SPR_NOACCESS,
1319                  &spr_read_generic, &spr_write_generic,
1320                  0x00000000);
1321     /* L3PM */
1322     /* XXX : not implemented */
1323     spr_register(env, SPR_L3PM, "L3PM",
1324                  SPR_NOACCESS, SPR_NOACCESS,
1325                  &spr_read_generic, &spr_write_generic,
1326                  0x00000000);
1327 }
1328
1329 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1330 {
1331 #if !defined(CONFIG_USER_ONLY)
1332     env->nb_tlb = nb_tlbs;
1333     env->nb_ways = nb_ways;
1334     env->id_tlbs = 1;
1335     /* XXX : not implemented */
1336     spr_register(env, SPR_PTEHI, "PTEHI",
1337                  SPR_NOACCESS, SPR_NOACCESS,
1338                  &spr_read_generic, &spr_write_generic,
1339                  0x00000000);
1340     /* XXX : not implemented */
1341     spr_register(env, SPR_PTELO, "PTELO",
1342                  SPR_NOACCESS, SPR_NOACCESS,
1343                  &spr_read_generic, &spr_write_generic,
1344                  0x00000000);
1345     /* XXX : not implemented */
1346     spr_register(env, SPR_TLBMISS, "TLBMISS",
1347                  SPR_NOACCESS, SPR_NOACCESS,
1348                  &spr_read_generic, &spr_write_generic,
1349                  0x00000000);
1350 #endif
1351 }
1352
1353 static void gen_spr_usprgh (CPUPPCState *env)
1354 {
1355     spr_register(env, SPR_USPRG4, "USPRG4",
1356                  &spr_read_ureg, SPR_NOACCESS,
1357                  &spr_read_ureg, SPR_NOACCESS,
1358                  0x00000000);
1359     spr_register(env, SPR_USPRG5, "USPRG5",
1360                  &spr_read_ureg, SPR_NOACCESS,
1361                  &spr_read_ureg, SPR_NOACCESS,
1362                  0x00000000);
1363     spr_register(env, SPR_USPRG6, "USPRG6",
1364                  &spr_read_ureg, SPR_NOACCESS,
1365                  &spr_read_ureg, SPR_NOACCESS,
1366                  0x00000000);
1367     spr_register(env, SPR_USPRG7, "USPRG7",
1368                  &spr_read_ureg, SPR_NOACCESS,
1369                  &spr_read_ureg, SPR_NOACCESS,
1370                  0x00000000);
1371 }
1372
1373 /* PowerPC BookE SPR */
1374 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1375 {
1376     const char *ivor_names[64] = {
1377         "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1378         "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1379         "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1380         "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1381         "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1382         "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1383         "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1384         "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1385         "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1386         "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1387         "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1388         "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1389         "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1390         "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1391         "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1392         "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1393     };
1394 #define SPR_BOOKE_IVORxx (-1)
1395     int ivor_sprn[64] = {
1396         SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1397         SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1398         SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1399         SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1400         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1401         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1402         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1403         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1404         SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1405         SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1406         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1407         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1408         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1409         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1410         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1411         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1412     };
1413     int i;
1414
1415     /* Interrupt processing */
1416     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1417                  SPR_NOACCESS, SPR_NOACCESS,
1418                  &spr_read_generic, &spr_write_generic,
1419                  0x00000000);
1420     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1421                  SPR_NOACCESS, SPR_NOACCESS,
1422                  &spr_read_generic, &spr_write_generic,
1423                  0x00000000);
1424     /* Debug */
1425     /* XXX : not implemented */
1426     spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1427                  SPR_NOACCESS, SPR_NOACCESS,
1428                  &spr_read_generic, &spr_write_generic,
1429                  0x00000000);
1430     /* XXX : not implemented */
1431     spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1432                  SPR_NOACCESS, SPR_NOACCESS,
1433                  &spr_read_generic, &spr_write_generic,
1434                  0x00000000);
1435     /* XXX : not implemented */
1436     spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1437                  SPR_NOACCESS, SPR_NOACCESS,
1438                  &spr_read_generic, &spr_write_generic,
1439                  0x00000000);
1440     /* XXX : not implemented */
1441     spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1442                  SPR_NOACCESS, SPR_NOACCESS,
1443                  &spr_read_generic, &spr_write_generic,
1444                  0x00000000);
1445     /* XXX : not implemented */
1446     spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1447                  SPR_NOACCESS, SPR_NOACCESS,
1448                  &spr_read_generic, &spr_write_generic,
1449                  0x00000000);
1450     /* XXX : not implemented */
1451     spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1452                  SPR_NOACCESS, SPR_NOACCESS,
1453                  &spr_read_generic, &spr_write_generic,
1454                  0x00000000);
1455     /* XXX : not implemented */
1456     spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1457                  SPR_NOACCESS, SPR_NOACCESS,
1458                  &spr_read_generic, &spr_write_generic,
1459                  0x00000000);
1460     /* XXX : not implemented */
1461     spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1462                  SPR_NOACCESS, SPR_NOACCESS,
1463                  &spr_read_generic, &spr_write_clear,
1464                  0x00000000);
1465     spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1466                  SPR_NOACCESS, SPR_NOACCESS,
1467                  &spr_read_generic, &spr_write_generic,
1468                  0x00000000);
1469     spr_register(env, SPR_BOOKE_ESR, "ESR",
1470                  SPR_NOACCESS, SPR_NOACCESS,
1471                  &spr_read_generic, &spr_write_generic,
1472                  0x00000000);
1473     spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1474                  SPR_NOACCESS, SPR_NOACCESS,
1475                  &spr_read_generic, &spr_write_excp_prefix,
1476                  0x00000000);
1477     /* Exception vectors */
1478     for (i = 0; i < 64; i++) {
1479         if (ivor_mask & (1ULL << i)) {
1480             if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1481                 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1482                 exit(1);
1483             }
1484             spr_register(env, ivor_sprn[i], ivor_names[i],
1485                          SPR_NOACCESS, SPR_NOACCESS,
1486                          &spr_read_generic, &spr_write_excp_vector,
1487                          0x00000000);
1488         }
1489     }
1490     spr_register(env, SPR_BOOKE_PID, "PID",
1491                  SPR_NOACCESS, SPR_NOACCESS,
1492                  &spr_read_generic, &spr_write_generic,
1493                  0x00000000);
1494     spr_register(env, SPR_BOOKE_TCR, "TCR",
1495                  SPR_NOACCESS, SPR_NOACCESS,
1496                  &spr_read_generic, &spr_write_booke_tcr,
1497                  0x00000000);
1498     spr_register(env, SPR_BOOKE_TSR, "TSR",
1499                  SPR_NOACCESS, SPR_NOACCESS,
1500                  &spr_read_generic, &spr_write_booke_tsr,
1501                  0x00000000);
1502     /* Timer */
1503     spr_register(env, SPR_DECR, "DECR",
1504                  SPR_NOACCESS, SPR_NOACCESS,
1505                  &spr_read_decr, &spr_write_decr,
1506                  0x00000000);
1507     spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1508                  SPR_NOACCESS, SPR_NOACCESS,
1509                  SPR_NOACCESS, &spr_write_generic,
1510                  0x00000000);
1511     /* SPRGs */
1512     spr_register(env, SPR_USPRG0, "USPRG0",
1513                  &spr_read_generic, &spr_write_generic,
1514                  &spr_read_generic, &spr_write_generic,
1515                  0x00000000);
1516     spr_register(env, SPR_SPRG4, "SPRG4",
1517                  SPR_NOACCESS, SPR_NOACCESS,
1518                  &spr_read_generic, &spr_write_generic,
1519                  0x00000000);
1520     spr_register(env, SPR_SPRG5, "SPRG5",
1521                  SPR_NOACCESS, SPR_NOACCESS,
1522                  &spr_read_generic, &spr_write_generic,
1523                  0x00000000);
1524     spr_register(env, SPR_SPRG6, "SPRG6",
1525                  SPR_NOACCESS, SPR_NOACCESS,
1526                  &spr_read_generic, &spr_write_generic,
1527                  0x00000000);
1528     spr_register(env, SPR_SPRG7, "SPRG7",
1529                  SPR_NOACCESS, SPR_NOACCESS,
1530                  &spr_read_generic, &spr_write_generic,
1531                  0x00000000);
1532 }
1533
1534 /* FSL storage control registers */
1535 static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
1536 {
1537 #if !defined(CONFIG_USER_ONLY)
1538     const char *mas_names[8] = {
1539         "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1540     };
1541     int mas_sprn[8] = {
1542         SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1543         SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1544     };
1545     int i;
1546
1547     /* TLB assist registers */
1548     /* XXX : not implemented */
1549     for (i = 0; i < 8; i++) {
1550         if (mas_mask & (1 << i)) {
1551             spr_register(env, mas_sprn[i], mas_names[i],
1552                          SPR_NOACCESS, SPR_NOACCESS,
1553                          &spr_read_generic, &spr_write_generic,
1554                          0x00000000);
1555         }
1556     }
1557     if (env->nb_pids > 1) {
1558         /* XXX : not implemented */
1559         spr_register(env, SPR_BOOKE_PID1, "PID1",
1560                      SPR_NOACCESS, SPR_NOACCESS,
1561                      &spr_read_generic, &spr_write_generic,
1562                      0x00000000);
1563     }
1564     if (env->nb_pids > 2) {
1565         /* XXX : not implemented */
1566         spr_register(env, SPR_BOOKE_PID2, "PID2",
1567                      SPR_NOACCESS, SPR_NOACCESS,
1568                      &spr_read_generic, &spr_write_generic,
1569                      0x00000000);
1570     }
1571     /* XXX : not implemented */
1572     spr_register(env, SPR_MMUCFG, "MMUCFG",
1573                  SPR_NOACCESS, SPR_NOACCESS,
1574                  &spr_read_generic, SPR_NOACCESS,
1575                  0x00000000); /* TOFIX */
1576     /* XXX : not implemented */
1577     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1578                  SPR_NOACCESS, SPR_NOACCESS,
1579                  &spr_read_generic, &spr_write_generic,
1580                  0x00000000); /* TOFIX */
1581     switch (env->nb_ways) {
1582     case 4:
1583         /* XXX : not implemented */
1584         spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1585                      SPR_NOACCESS, SPR_NOACCESS,
1586                      &spr_read_generic, SPR_NOACCESS,
1587                      0x00000000); /* TOFIX */
1588         /* Fallthru */
1589     case 3:
1590         /* XXX : not implemented */
1591         spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1592                      SPR_NOACCESS, SPR_NOACCESS,
1593                      &spr_read_generic, SPR_NOACCESS,
1594                      0x00000000); /* TOFIX */
1595         /* Fallthru */
1596     case 2:
1597         /* XXX : not implemented */
1598         spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1599                      SPR_NOACCESS, SPR_NOACCESS,
1600                      &spr_read_generic, SPR_NOACCESS,
1601                      0x00000000); /* TOFIX */
1602         /* Fallthru */
1603     case 1:
1604         /* XXX : not implemented */
1605         spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1606                      SPR_NOACCESS, SPR_NOACCESS,
1607                      &spr_read_generic, SPR_NOACCESS,
1608                      0x00000000); /* TOFIX */
1609         /* Fallthru */
1610     case 0:
1611     default:
1612         break;
1613     }
1614 #endif
1615 }
1616
1617 /* SPR specific to PowerPC 440 implementation */
1618 static void gen_spr_440 (CPUPPCState *env)
1619 {
1620     /* Cache control */
1621     /* XXX : not implemented */
1622     spr_register(env, SPR_440_DNV0, "DNV0",
1623                  SPR_NOACCESS, SPR_NOACCESS,
1624                  &spr_read_generic, &spr_write_generic,
1625                  0x00000000);
1626     /* XXX : not implemented */
1627     spr_register(env, SPR_440_DNV1, "DNV1",
1628                  SPR_NOACCESS, SPR_NOACCESS,
1629                  &spr_read_generic, &spr_write_generic,
1630                  0x00000000);
1631     /* XXX : not implemented */
1632     spr_register(env, SPR_440_DNV2, "DNV2",
1633                  SPR_NOACCESS, SPR_NOACCESS,
1634                  &spr_read_generic, &spr_write_generic,
1635                  0x00000000);
1636     /* XXX : not implemented */
1637     spr_register(env, SPR_440_DNV3, "DNV3",
1638                  SPR_NOACCESS, SPR_NOACCESS,
1639                  &spr_read_generic, &spr_write_generic,
1640                  0x00000000);
1641     /* XXX : not implemented */
1642     spr_register(env, SPR_440_DTV0, "DTV0",
1643                  SPR_NOACCESS, SPR_NOACCESS,
1644                  &spr_read_generic, &spr_write_generic,
1645                  0x00000000);
1646     /* XXX : not implemented */
1647     spr_register(env, SPR_440_DTV1, "DTV1",
1648                  SPR_NOACCESS, SPR_NOACCESS,
1649                  &spr_read_generic, &spr_write_generic,
1650                  0x00000000);
1651     /* XXX : not implemented */
1652     spr_register(env, SPR_440_DTV2, "DTV2",
1653                  SPR_NOACCESS, SPR_NOACCESS,
1654                  &spr_read_generic, &spr_write_generic,
1655                  0x00000000);
1656     /* XXX : not implemented */
1657     spr_register(env, SPR_440_DTV3, "DTV3",
1658                  SPR_NOACCESS, SPR_NOACCESS,
1659                  &spr_read_generic, &spr_write_generic,
1660                  0x00000000);
1661     /* XXX : not implemented */
1662     spr_register(env, SPR_440_DVLIM, "DVLIM",
1663                  SPR_NOACCESS, SPR_NOACCESS,
1664                  &spr_read_generic, &spr_write_generic,
1665                  0x00000000);
1666     /* XXX : not implemented */
1667     spr_register(env, SPR_440_INV0, "INV0",
1668                  SPR_NOACCESS, SPR_NOACCESS,
1669                  &spr_read_generic, &spr_write_generic,
1670                  0x00000000);
1671     /* XXX : not implemented */
1672     spr_register(env, SPR_440_INV1, "INV1",
1673                  SPR_NOACCESS, SPR_NOACCESS,
1674                  &spr_read_generic, &spr_write_generic,
1675                  0x00000000);
1676     /* XXX : not implemented */
1677     spr_register(env, SPR_440_INV2, "INV2",
1678                  SPR_NOACCESS, SPR_NOACCESS,
1679                  &spr_read_generic, &spr_write_generic,
1680                  0x00000000);
1681     /* XXX : not implemented */
1682     spr_register(env, SPR_440_INV3, "INV3",
1683                  SPR_NOACCESS, SPR_NOACCESS,
1684                  &spr_read_generic, &spr_write_generic,
1685                  0x00000000);
1686     /* XXX : not implemented */
1687     spr_register(env, SPR_440_ITV0, "ITV0",
1688                  SPR_NOACCESS, SPR_NOACCESS,
1689                  &spr_read_generic, &spr_write_generic,
1690                  0x00000000);
1691     /* XXX : not implemented */
1692     spr_register(env, SPR_440_ITV1, "ITV1",
1693                  SPR_NOACCESS, SPR_NOACCESS,
1694                  &spr_read_generic, &spr_write_generic,
1695                  0x00000000);
1696     /* XXX : not implemented */
1697     spr_register(env, SPR_440_ITV2, "ITV2",
1698                  SPR_NOACCESS, SPR_NOACCESS,
1699                  &spr_read_generic, &spr_write_generic,
1700                  0x00000000);
1701     /* XXX : not implemented */
1702     spr_register(env, SPR_440_ITV3, "ITV3",
1703                  SPR_NOACCESS, SPR_NOACCESS,
1704                  &spr_read_generic, &spr_write_generic,
1705                  0x00000000);
1706     /* XXX : not implemented */
1707     spr_register(env, SPR_440_IVLIM, "IVLIM",
1708                  SPR_NOACCESS, SPR_NOACCESS,
1709                  &spr_read_generic, &spr_write_generic,
1710                  0x00000000);
1711     /* Cache debug */
1712     /* XXX : not implemented */
1713     spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1714                  SPR_NOACCESS, SPR_NOACCESS,
1715                  &spr_read_generic, SPR_NOACCESS,
1716                  0x00000000);
1717     /* XXX : not implemented */
1718     spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1719                  SPR_NOACCESS, SPR_NOACCESS,
1720                  &spr_read_generic, SPR_NOACCESS,
1721                  0x00000000);
1722     /* XXX : not implemented */
1723     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1724                  SPR_NOACCESS, SPR_NOACCESS,
1725                  &spr_read_generic, SPR_NOACCESS,
1726                  0x00000000);
1727     /* XXX : not implemented */
1728     spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1729                  SPR_NOACCESS, SPR_NOACCESS,
1730                  &spr_read_generic, SPR_NOACCESS,
1731                  0x00000000);
1732     /* XXX : not implemented */
1733     spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1734                  SPR_NOACCESS, SPR_NOACCESS,
1735                  &spr_read_generic, SPR_NOACCESS,
1736                  0x00000000);
1737     /* XXX : not implemented */
1738     spr_register(env, SPR_440_DBDR, "DBDR",
1739                  SPR_NOACCESS, SPR_NOACCESS,
1740                  &spr_read_generic, &spr_write_generic,
1741                  0x00000000);
1742     /* Processor control */
1743     spr_register(env, SPR_4xx_CCR0, "CCR0",
1744                  SPR_NOACCESS, SPR_NOACCESS,
1745                  &spr_read_generic, &spr_write_generic,
1746                  0x00000000);
1747     spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1748                  SPR_NOACCESS, SPR_NOACCESS,
1749                  &spr_read_generic, SPR_NOACCESS,
1750                  0x00000000);
1751     /* Storage control */
1752     spr_register(env, SPR_440_MMUCR, "MMUCR",
1753                  SPR_NOACCESS, SPR_NOACCESS,
1754                  &spr_read_generic, &spr_write_generic,
1755                  0x00000000);
1756 }
1757
1758 /* SPR shared between PowerPC 40x implementations */
1759 static void gen_spr_40x (CPUPPCState *env)
1760 {
1761     /* Cache */
1762     /* not emulated, as Qemu do not emulate caches */
1763     spr_register(env, SPR_40x_DCCR, "DCCR",
1764                  SPR_NOACCESS, SPR_NOACCESS,
1765                  &spr_read_generic, &spr_write_generic,
1766                  0x00000000);
1767     /* not emulated, as Qemu do not emulate caches */
1768     spr_register(env, SPR_40x_ICCR, "ICCR",
1769                  SPR_NOACCESS, SPR_NOACCESS,
1770                  &spr_read_generic, &spr_write_generic,
1771                  0x00000000);
1772     /* not emulated, as Qemu do not emulate caches */
1773     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1774                  SPR_NOACCESS, SPR_NOACCESS,
1775                  &spr_read_generic, SPR_NOACCESS,
1776                  0x00000000);
1777     /* Exception */
1778     spr_register(env, SPR_40x_DEAR, "DEAR",
1779                  SPR_NOACCESS, SPR_NOACCESS,
1780                  &spr_read_generic, &spr_write_generic,
1781                  0x00000000);
1782     spr_register(env, SPR_40x_ESR, "ESR",
1783                  SPR_NOACCESS, SPR_NOACCESS,
1784                  &spr_read_generic, &spr_write_generic,
1785                  0x00000000);
1786     spr_register(env, SPR_40x_EVPR, "EVPR",
1787                  SPR_NOACCESS, SPR_NOACCESS,
1788                  &spr_read_generic, &spr_write_excp_prefix,
1789                  0x00000000);
1790     spr_register(env, SPR_40x_SRR2, "SRR2",
1791                  &spr_read_generic, &spr_write_generic,
1792                  &spr_read_generic, &spr_write_generic,
1793                  0x00000000);
1794     spr_register(env, SPR_40x_SRR3, "SRR3",
1795                  &spr_read_generic, &spr_write_generic,
1796                  &spr_read_generic, &spr_write_generic,
1797                  0x00000000);
1798     /* Timers */
1799     spr_register(env, SPR_40x_PIT, "PIT",
1800                  SPR_NOACCESS, SPR_NOACCESS,
1801                  &spr_read_40x_pit, &spr_write_40x_pit,
1802                  0x00000000);
1803     spr_register(env, SPR_40x_TCR, "TCR",
1804                  SPR_NOACCESS, SPR_NOACCESS,
1805                  &spr_read_generic, &spr_write_booke_tcr,
1806                  0x00000000);
1807     spr_register(env, SPR_40x_TSR, "TSR",
1808                  SPR_NOACCESS, SPR_NOACCESS,
1809                  &spr_read_generic, &spr_write_booke_tsr,
1810                  0x00000000);
1811 }
1812
1813 /* SPR specific to PowerPC 405 implementation */
1814 static void gen_spr_405 (CPUPPCState *env)
1815 {
1816     /* MMU */
1817     spr_register(env, SPR_40x_PID, "PID",
1818                  SPR_NOACCESS, SPR_NOACCESS,
1819                  &spr_read_generic, &spr_write_generic,
1820                  0x00000000);
1821     spr_register(env, SPR_4xx_CCR0, "CCR0",
1822                  SPR_NOACCESS, SPR_NOACCESS,
1823                  &spr_read_generic, &spr_write_generic,
1824                  0x00700000);
1825     /* Debug interface */
1826     /* XXX : not implemented */
1827     spr_register(env, SPR_40x_DBCR0, "DBCR0",
1828                  SPR_NOACCESS, SPR_NOACCESS,
1829                  &spr_read_generic, &spr_write_40x_dbcr0,
1830                  0x00000000);
1831     /* XXX : not implemented */
1832     spr_register(env, SPR_405_DBCR1, "DBCR1",
1833                  SPR_NOACCESS, SPR_NOACCESS,
1834                  &spr_read_generic, &spr_write_generic,
1835                  0x00000000);
1836     /* XXX : not implemented */
1837     spr_register(env, SPR_40x_DBSR, "DBSR",
1838                  SPR_NOACCESS, SPR_NOACCESS,
1839                  &spr_read_generic, &spr_write_clear,
1840                  /* Last reset was system reset */
1841                  0x00000300);
1842     /* XXX : not implemented */
1843     spr_register(env, SPR_40x_DAC1, "DAC1",
1844                  SPR_NOACCESS, SPR_NOACCESS,
1845                  &spr_read_generic, &spr_write_generic,
1846                  0x00000000);
1847     spr_register(env, SPR_40x_DAC2, "DAC2",
1848                  SPR_NOACCESS, SPR_NOACCESS,
1849                  &spr_read_generic, &spr_write_generic,
1850                  0x00000000);
1851     /* XXX : not implemented */
1852     spr_register(env, SPR_405_DVC1, "DVC1",
1853                  SPR_NOACCESS, SPR_NOACCESS,
1854                  &spr_read_generic, &spr_write_generic,
1855                  0x00000000);
1856     /* XXX : not implemented */
1857     spr_register(env, SPR_405_DVC2, "DVC2",
1858                  SPR_NOACCESS, SPR_NOACCESS,
1859                  &spr_read_generic, &spr_write_generic,
1860                  0x00000000);
1861     /* XXX : not implemented */
1862     spr_register(env, SPR_40x_IAC1, "IAC1",
1863                  SPR_NOACCESS, SPR_NOACCESS,
1864                  &spr_read_generic, &spr_write_generic,
1865                  0x00000000);
1866     spr_register(env, SPR_40x_IAC2, "IAC2",
1867                  SPR_NOACCESS, SPR_NOACCESS,
1868                  &spr_read_generic, &spr_write_generic,
1869                  0x00000000);
1870     /* XXX : not implemented */
1871     spr_register(env, SPR_405_IAC3, "IAC3",
1872                  SPR_NOACCESS, SPR_NOACCESS,
1873                  &spr_read_generic, &spr_write_generic,
1874                  0x00000000);
1875     /* XXX : not implemented */
1876     spr_register(env, SPR_405_IAC4, "IAC4",
1877                  SPR_NOACCESS, SPR_NOACCESS,
1878                  &spr_read_generic, &spr_write_generic,
1879                  0x00000000);
1880     /* Storage control */
1881     /* XXX: TODO: not implemented */
1882     spr_register(env, SPR_405_SLER, "SLER",
1883                  SPR_NOACCESS, SPR_NOACCESS,
1884                  &spr_read_generic, &spr_write_40x_sler,
1885                  0x00000000);
1886     spr_register(env, SPR_40x_ZPR, "ZPR",
1887                  SPR_NOACCESS, SPR_NOACCESS,
1888                  &spr_read_generic, &spr_write_generic,
1889                  0x00000000);
1890     /* XXX : not implemented */
1891     spr_register(env, SPR_405_SU0R, "SU0R",
1892                  SPR_NOACCESS, SPR_NOACCESS,
1893                  &spr_read_generic, &spr_write_generic,
1894                  0x00000000);
1895     /* SPRG */
1896     spr_register(env, SPR_USPRG0, "USPRG0",
1897                  &spr_read_ureg, SPR_NOACCESS,
1898                  &spr_read_ureg, SPR_NOACCESS,
1899                  0x00000000);
1900     spr_register(env, SPR_SPRG4, "SPRG4",
1901                  SPR_NOACCESS, SPR_NOACCESS,
1902                  &spr_read_generic, &spr_write_generic,
1903                  0x00000000);
1904     spr_register(env, SPR_SPRG5, "SPRG5",
1905                  SPR_NOACCESS, SPR_NOACCESS,
1906                  spr_read_generic, &spr_write_generic,
1907                  0x00000000);
1908     spr_register(env, SPR_SPRG6, "SPRG6",
1909                  SPR_NOACCESS, SPR_NOACCESS,
1910                  spr_read_generic, &spr_write_generic,
1911                  0x00000000);
1912     spr_register(env, SPR_SPRG7, "SPRG7",
1913                  SPR_NOACCESS, SPR_NOACCESS,
1914                  spr_read_generic, &spr_write_generic,
1915                  0x00000000);
1916     gen_spr_usprgh(env);
1917 }
1918
1919 /* SPR shared between PowerPC 401 & 403 implementations */
1920 static void gen_spr_401_403 (CPUPPCState *env)
1921 {
1922     /* Time base */
1923     spr_register(env, SPR_403_VTBL,  "TBL",
1924                  &spr_read_tbl, SPR_NOACCESS,
1925                  &spr_read_tbl, SPR_NOACCESS,
1926                  0x00000000);
1927     spr_register(env, SPR_403_TBL,   "TBL",
1928                  SPR_NOACCESS, SPR_NOACCESS,
1929                  SPR_NOACCESS, &spr_write_tbl,
1930                  0x00000000);
1931     spr_register(env, SPR_403_VTBU,  "TBU",
1932                  &spr_read_tbu, SPR_NOACCESS,
1933                  &spr_read_tbu, SPR_NOACCESS,
1934                  0x00000000);
1935     spr_register(env, SPR_403_TBU,   "TBU",
1936                  SPR_NOACCESS, SPR_NOACCESS,
1937                  SPR_NOACCESS, &spr_write_tbu,
1938                  0x00000000);
1939     /* Debug */
1940     /* not emulated, as Qemu do not emulate caches */
1941     spr_register(env, SPR_403_CDBCR, "CDBCR",
1942                  SPR_NOACCESS, SPR_NOACCESS,
1943                  &spr_read_generic, &spr_write_generic,
1944                  0x00000000);
1945 }
1946
1947 /* SPR specific to PowerPC 401 implementation */
1948 static void gen_spr_401 (CPUPPCState *env)
1949 {
1950     /* Debug interface */
1951     /* XXX : not implemented */
1952     spr_register(env, SPR_40x_DBCR0, "DBCR",
1953                  SPR_NOACCESS, SPR_NOACCESS,
1954                  &spr_read_generic, &spr_write_40x_dbcr0,
1955                  0x00000000);
1956     /* XXX : not implemented */
1957     spr_register(env, SPR_40x_DBSR, "DBSR",
1958                  SPR_NOACCESS, SPR_NOACCESS,
1959                  &spr_read_generic, &spr_write_clear,
1960                  /* Last reset was system reset */
1961                  0x00000300);
1962     /* XXX : not implemented */
1963     spr_register(env, SPR_40x_DAC1, "DAC",
1964                  SPR_NOACCESS, SPR_NOACCESS,
1965                  &spr_read_generic, &spr_write_generic,
1966                  0x00000000);
1967     /* XXX : not implemented */
1968     spr_register(env, SPR_40x_IAC1, "IAC",
1969                  SPR_NOACCESS, SPR_NOACCESS,
1970                  &spr_read_generic, &spr_write_generic,
1971                  0x00000000);
1972     /* Storage control */
1973     /* XXX: TODO: not implemented */
1974     spr_register(env, SPR_405_SLER, "SLER",
1975                  SPR_NOACCESS, SPR_NOACCESS,
1976                  &spr_read_generic, &spr_write_40x_sler,
1977                  0x00000000);
1978     /* not emulated, as Qemu never does speculative access */
1979     spr_register(env, SPR_40x_SGR, "SGR",
1980                  SPR_NOACCESS, SPR_NOACCESS,
1981                  &spr_read_generic, &spr_write_generic,
1982                  0xFFFFFFFF);
1983     /* not emulated, as Qemu do not emulate caches */
1984     spr_register(env, SPR_40x_DCWR, "DCWR",
1985                  SPR_NOACCESS, SPR_NOACCESS,
1986                  &spr_read_generic, &spr_write_generic,
1987                  0x00000000);
1988 }
1989
1990 static void gen_spr_401x2 (CPUPPCState *env)
1991 {
1992     gen_spr_401(env);
1993     spr_register(env, SPR_40x_PID, "PID",
1994                  SPR_NOACCESS, SPR_NOACCESS,
1995                  &spr_read_generic, &spr_write_generic,
1996                  0x00000000);
1997     spr_register(env, SPR_40x_ZPR, "ZPR",
1998                  SPR_NOACCESS, SPR_NOACCESS,
1999                  &spr_read_generic, &spr_write_generic,
2000                  0x00000000);
2001 }
2002
2003 /* SPR specific to PowerPC 403 implementation */
2004 static void gen_spr_403 (CPUPPCState *env)
2005 {
2006     /* Debug interface */
2007     /* XXX : not implemented */
2008     spr_register(env, SPR_40x_DBCR0, "DBCR0",
2009                  SPR_NOACCESS, SPR_NOACCESS,
2010                  &spr_read_generic, &spr_write_40x_dbcr0,
2011                  0x00000000);
2012     /* XXX : not implemented */
2013     spr_register(env, SPR_40x_DBSR, "DBSR",
2014                  SPR_NOACCESS, SPR_NOACCESS,
2015                  &spr_read_generic, &spr_write_clear,
2016                  /* Last reset was system reset */
2017                  0x00000300);
2018     /* XXX : not implemented */
2019     spr_register(env, SPR_40x_DAC1, "DAC1",
2020                  SPR_NOACCESS, SPR_NOACCESS,
2021                  &spr_read_generic, &spr_write_generic,
2022                  0x00000000);
2023     /* XXX : not implemented */
2024     spr_register(env, SPR_40x_DAC2, "DAC2",
2025                  SPR_NOACCESS, SPR_NOACCESS,
2026                  &spr_read_generic, &spr_write_generic,
2027                  0x00000000);
2028     /* XXX : not implemented */
2029     spr_register(env, SPR_40x_IAC1, "IAC1",
2030                  SPR_NOACCESS, SPR_NOACCESS,
2031                  &spr_read_generic, &spr_write_generic,
2032                  0x00000000);
2033     /* XXX : not implemented */
2034     spr_register(env, SPR_40x_IAC2, "IAC2",
2035                  SPR_NOACCESS, SPR_NOACCESS,
2036                  &spr_read_generic, &spr_write_generic,
2037                  0x00000000);
2038 }
2039
2040 static void gen_spr_403_real (CPUPPCState *env)
2041 {
2042     spr_register(env, SPR_403_PBL1,  "PBL1",
2043                  SPR_NOACCESS, SPR_NOACCESS,
2044                  &spr_read_403_pbr, &spr_write_403_pbr,
2045                  0x00000000);
2046     spr_register(env, SPR_403_PBU1,  "PBU1",
2047                  SPR_NOACCESS, SPR_NOACCESS,
2048                  &spr_read_403_pbr, &spr_write_403_pbr,
2049                  0x00000000);
2050     spr_register(env, SPR_403_PBL2,  "PBL2",
2051                  SPR_NOACCESS, SPR_NOACCESS,
2052                  &spr_read_403_pbr, &spr_write_403_pbr,
2053                  0x00000000);
2054     spr_register(env, SPR_403_PBU2,  "PBU2",
2055                  SPR_NOACCESS, SPR_NOACCESS,
2056                  &spr_read_403_pbr, &spr_write_403_pbr,
2057                  0x00000000);
2058 }
2059
2060 static void gen_spr_403_mmu (CPUPPCState *env)
2061 {
2062     /* MMU */
2063     spr_register(env, SPR_40x_PID, "PID",
2064                  SPR_NOACCESS, SPR_NOACCESS,
2065                  &spr_read_generic, &spr_write_generic,
2066                  0x00000000);
2067     spr_register(env, SPR_40x_ZPR, "ZPR",
2068                  SPR_NOACCESS, SPR_NOACCESS,
2069                  &spr_read_generic, &spr_write_generic,
2070                  0x00000000);
2071 }
2072
2073 /* SPR specific to PowerPC compression coprocessor extension */
2074 static void gen_spr_compress (CPUPPCState *env)
2075 {
2076     /* XXX : not implemented */
2077     spr_register(env, SPR_401_SKR, "SKR",
2078                  SPR_NOACCESS, SPR_NOACCESS,
2079                  &spr_read_generic, &spr_write_generic,
2080                  0x00000000);
2081 }
2082
2083 #if defined (TARGET_PPC64)
2084 /* SPR specific to PowerPC 620 */
2085 static void gen_spr_620 (CPUPPCState *env)
2086 {
2087     /* Processor identification */
2088     spr_register(env, SPR_PIR, "PIR",
2089                  SPR_NOACCESS, SPR_NOACCESS,
2090                  &spr_read_generic, &spr_write_pir,
2091                  0x00000000);
2092     spr_register(env, SPR_ASR, "ASR",
2093                  SPR_NOACCESS, SPR_NOACCESS,
2094                  &spr_read_asr, &spr_write_asr,
2095                  0x00000000);
2096     /* Breakpoints */
2097     /* XXX : not implemented */
2098     spr_register(env, SPR_IABR, "IABR",
2099                  SPR_NOACCESS, SPR_NOACCESS,
2100                  &spr_read_generic, &spr_write_generic,
2101                  0x00000000);
2102     /* XXX : not implemented */
2103     spr_register(env, SPR_DABR, "DABR",
2104                  SPR_NOACCESS, SPR_NOACCESS,
2105                  &spr_read_generic, &spr_write_generic,
2106                  0x00000000);
2107     /* XXX : not implemented */
2108     spr_register(env, SPR_SIAR, "SIAR",
2109                  SPR_NOACCESS, SPR_NOACCESS,
2110                  &spr_read_generic, SPR_NOACCESS,
2111                  0x00000000);
2112     /* XXX : not implemented */
2113     spr_register(env, SPR_SDA, "SDA",
2114                  SPR_NOACCESS, SPR_NOACCESS,
2115                  &spr_read_generic, SPR_NOACCESS,
2116                  0x00000000);
2117     /* XXX : not implemented */
2118     spr_register(env, SPR_620_PMC1R, "PMC1",
2119                  SPR_NOACCESS, SPR_NOACCESS,
2120                  &spr_read_generic, SPR_NOACCESS,
2121                  0x00000000);
2122     spr_register(env, SPR_620_PMC1W, "PMC1",
2123                  SPR_NOACCESS, SPR_NOACCESS,
2124                   SPR_NOACCESS, &spr_write_generic,
2125                  0x00000000);
2126     /* XXX : not implemented */
2127     spr_register(env, SPR_620_PMC2R, "PMC2",
2128                  SPR_NOACCESS, SPR_NOACCESS,
2129                  &spr_read_generic, SPR_NOACCESS,
2130                  0x00000000);
2131     spr_register(env, SPR_620_PMC2W, "PMC2",
2132                  SPR_NOACCESS, SPR_NOACCESS,
2133                   SPR_NOACCESS, &spr_write_generic,
2134                  0x00000000);
2135     /* XXX : not implemented */
2136     spr_register(env, SPR_620_MMCR0R, "MMCR0",
2137                  SPR_NOACCESS, SPR_NOACCESS,
2138                  &spr_read_generic, SPR_NOACCESS,
2139                  0x00000000);
2140     spr_register(env, SPR_620_MMCR0W, "MMCR0",
2141                  SPR_NOACCESS, SPR_NOACCESS,
2142                   SPR_NOACCESS, &spr_write_generic,
2143                  0x00000000);
2144     /* External access control */
2145     /* XXX : not implemented */
2146     spr_register(env, SPR_EAR, "EAR",
2147                  SPR_NOACCESS, SPR_NOACCESS,
2148                  &spr_read_generic, &spr_write_generic,
2149                  0x00000000);
2150 #if 0 // XXX: check this
2151     /* XXX : not implemented */
2152     spr_register(env, SPR_620_PMR0, "PMR0",
2153                  SPR_NOACCESS, SPR_NOACCESS,
2154                  &spr_read_generic, &spr_write_generic,
2155                  0x00000000);
2156     /* XXX : not implemented */
2157     spr_register(env, SPR_620_PMR1, "PMR1",
2158                  SPR_NOACCESS, SPR_NOACCESS,
2159                  &spr_read_generic, &spr_write_generic,
2160                  0x00000000);
2161     /* XXX : not implemented */
2162     spr_register(env, SPR_620_PMR2, "PMR2",
2163                  SPR_NOACCESS, SPR_NOACCESS,
2164                  &spr_read_generic, &spr_write_generic,
2165                  0x00000000);
2166     /* XXX : not implemented */
2167     spr_register(env, SPR_620_PMR3, "PMR3",
2168                  SPR_NOACCESS, SPR_NOACCESS,
2169                  &spr_read_generic, &spr_write_generic,
2170                  0x00000000);
2171     /* XXX : not implemented */
2172     spr_register(env, SPR_620_PMR4, "PMR4",
2173                  SPR_NOACCESS, SPR_NOACCESS,
2174                  &spr_read_generic, &spr_write_generic,
2175                  0x00000000);
2176     /* XXX : not implemented */
2177     spr_register(env, SPR_620_PMR5, "PMR5",
2178                  SPR_NOACCESS, SPR_NOACCESS,
2179                  &spr_read_generic, &spr_write_generic,
2180                  0x00000000);
2181     /* XXX : not implemented */
2182     spr_register(env, SPR_620_PMR6, "PMR6",
2183                  SPR_NOACCESS, SPR_NOACCESS,
2184                  &spr_read_generic, &spr_write_generic,
2185                  0x00000000);
2186     /* XXX : not implemented */
2187     spr_register(env, SPR_620_PMR7, "PMR7",
2188                  SPR_NOACCESS, SPR_NOACCESS,
2189                  &spr_read_generic, &spr_write_generic,
2190                  0x00000000);
2191     /* XXX : not implemented */
2192     spr_register(env, SPR_620_PMR8, "PMR8",
2193                  SPR_NOACCESS, SPR_NOACCESS,
2194                  &spr_read_generic, &spr_write_generic,
2195                  0x00000000);
2196     /* XXX : not implemented */
2197     spr_register(env, SPR_620_PMR9, "PMR9",
2198                  SPR_NOACCESS, SPR_NOACCESS,
2199                  &spr_read_generic, &spr_write_generic,
2200                  0x00000000);
2201     /* XXX : not implemented */
2202     spr_register(env, SPR_620_PMRA, "PMR10",
2203                  SPR_NOACCESS, SPR_NOACCESS,
2204                  &spr_read_generic, &spr_write_generic,
2205                  0x00000000);
2206     /* XXX : not implemented */
2207     spr_register(env, SPR_620_PMRB, "PMR11",
2208                  SPR_NOACCESS, SPR_NOACCESS,
2209                  &spr_read_generic, &spr_write_generic,
2210                  0x00000000);
2211     /* XXX : not implemented */
2212     spr_register(env, SPR_620_PMRC, "PMR12",
2213                  SPR_NOACCESS, SPR_NOACCESS,
2214                  &spr_read_generic, &spr_write_generic,
2215                  0x00000000);
2216     /* XXX : not implemented */
2217     spr_register(env, SPR_620_PMRD, "PMR13",
2218                  SPR_NOACCESS, SPR_NOACCESS,
2219                  &spr_read_generic, &spr_write_generic,
2220                  0x00000000);
2221     /* XXX : not implemented */
2222     spr_register(env, SPR_620_PMRE, "PMR14",
2223                  SPR_NOACCESS, SPR_NOACCESS,
2224                  &spr_read_generic, &spr_write_generic,
2225                  0x00000000);
2226     /* XXX : not implemented */
2227     spr_register(env, SPR_620_PMRF, "PMR15",
2228                  SPR_NOACCESS, SPR_NOACCESS,
2229                  &spr_read_generic, &spr_write_generic,
2230                  0x00000000);
2231 #endif
2232     /* XXX : not implemented */
2233     spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2234                  SPR_NOACCESS, SPR_NOACCESS,
2235                  &spr_read_generic, &spr_write_generic,
2236                  0x00000000);
2237     /* XXX : not implemented */
2238     spr_register(env, SPR_620_L2CR, "L2CR",
2239                  SPR_NOACCESS, SPR_NOACCESS,
2240                  &spr_read_generic, &spr_write_generic,
2241                  0x00000000);
2242     /* XXX : not implemented */
2243     spr_register(env, SPR_620_L2SR, "L2SR",
2244                  SPR_NOACCESS, SPR_NOACCESS,
2245                  &spr_read_generic, &spr_write_generic,
2246                  0x00000000);
2247 }
2248 #endif /* defined (TARGET_PPC64) */
2249
2250 static void gen_spr_5xx_8xx (CPUPPCState *env)
2251 {
2252     /* Exception processing */
2253     spr_register(env, SPR_DSISR, "DSISR",
2254                  SPR_NOACCESS, SPR_NOACCESS,
2255                  &spr_read_generic, &spr_write_generic,
2256                  0x00000000);
2257     spr_register(env, SPR_DAR, "DAR",
2258                  SPR_NOACCESS, SPR_NOACCESS,
2259                  &spr_read_generic, &spr_write_generic,
2260                  0x00000000);
2261     /* Timer */
2262     spr_register(env, SPR_DECR, "DECR",
2263                  SPR_NOACCESS, SPR_NOACCESS,
2264                  &spr_read_decr, &spr_write_decr,
2265                  0x00000000);
2266     /* XXX : not implemented */
2267     spr_register(env, SPR_MPC_EIE, "EIE",
2268                  SPR_NOACCESS, SPR_NOACCESS,
2269                  &spr_read_generic, &spr_write_generic,
2270                  0x00000000);
2271     /* XXX : not implemented */
2272     spr_register(env, SPR_MPC_EID, "EID",
2273                  SPR_NOACCESS, SPR_NOACCESS,
2274                  &spr_read_generic, &spr_write_generic,
2275                  0x00000000);
2276     /* XXX : not implemented */
2277     spr_register(env, SPR_MPC_NRI, "NRI",
2278                  SPR_NOACCESS, SPR_NOACCESS,
2279                  &spr_read_generic, &spr_write_generic,
2280                  0x00000000);
2281     /* XXX : not implemented */
2282     spr_register(env, SPR_MPC_CMPA, "CMPA",
2283                  SPR_NOACCESS, SPR_NOACCESS,
2284                  &spr_read_generic, &spr_write_generic,
2285                  0x00000000);
2286     /* XXX : not implemented */
2287     spr_register(env, SPR_MPC_CMPB, "CMPB",
2288                  SPR_NOACCESS, SPR_NOACCESS,
2289                  &spr_read_generic, &spr_write_generic,
2290                  0x00000000);
2291     /* XXX : not implemented */
2292     spr_register(env, SPR_MPC_CMPC, "CMPC",
2293                  SPR_NOACCESS, SPR_NOACCESS,
2294                  &spr_read_generic, &spr_write_generic,
2295                  0x00000000);
2296     /* XXX : not implemented */
2297     spr_register(env, SPR_MPC_CMPD, "CMPD",
2298                  SPR_NOACCESS, SPR_NOACCESS,
2299                  &spr_read_generic, &spr_write_generic,
2300                  0x00000000);
2301     /* XXX : not implemented */
2302     spr_register(env, SPR_MPC_ECR, "ECR",
2303                  SPR_NOACCESS, SPR_NOACCESS,
2304                  &spr_read_generic, &spr_write_generic,
2305                  0x00000000);
2306     /* XXX : not implemented */
2307     spr_register(env, SPR_MPC_DER, "DER",
2308                  SPR_NOACCESS, SPR_NOACCESS,
2309                  &spr_read_generic, &spr_write_generic,
2310                  0x00000000);
2311     /* XXX : not implemented */
2312     spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2313                  SPR_NOACCESS, SPR_NOACCESS,
2314                  &spr_read_generic, &spr_write_generic,
2315                  0x00000000);
2316     /* XXX : not implemented */
2317     spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2318                  SPR_NOACCESS, SPR_NOACCESS,
2319                  &spr_read_generic, &spr_write_generic,
2320                  0x00000000);
2321     /* XXX : not implemented */
2322     spr_register(env, SPR_MPC_CMPE, "CMPE",
2323                  SPR_NOACCESS, SPR_NOACCESS,
2324                  &spr_read_generic, &spr_write_generic,
2325                  0x00000000);
2326     /* XXX : not implemented */
2327     spr_register(env, SPR_MPC_CMPF, "CMPF",
2328                  SPR_NOACCESS, SPR_NOACCESS,
2329                  &spr_read_generic, &spr_write_generic,
2330                  0x00000000);
2331     /* XXX : not implemented */
2332     spr_register(env, SPR_MPC_CMPG, "CMPG",
2333                  SPR_NOACCESS, SPR_NOACCESS,
2334                  &spr_read_generic, &spr_write_generic,
2335                  0x00000000);
2336     /* XXX : not implemented */
2337     spr_register(env, SPR_MPC_CMPH, "CMPH",
2338                  SPR_NOACCESS, SPR_NOACCESS,
2339                  &spr_read_generic, &spr_write_generic,
2340                  0x00000000);
2341     /* XXX : not implemented */
2342     spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2343                  SPR_NOACCESS, SPR_NOACCESS,
2344                  &spr_read_generic, &spr_write_generic,
2345                  0x00000000);
2346     /* XXX : not implemented */
2347     spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2348                  SPR_NOACCESS, SPR_NOACCESS,
2349                  &spr_read_generic, &spr_write_generic,
2350                  0x00000000);
2351     /* XXX : not implemented */
2352     spr_register(env, SPR_MPC_BAR, "BAR",
2353                  SPR_NOACCESS, SPR_NOACCESS,
2354                  &spr_read_generic, &spr_write_generic,
2355                  0x00000000);
2356     /* XXX : not implemented */
2357     spr_register(env, SPR_MPC_DPDR, "DPDR",
2358                  SPR_NOACCESS, SPR_NOACCESS,
2359                  &spr_read_generic, &spr_write_generic,
2360                  0x00000000);
2361     /* XXX : not implemented */
2362     spr_register(env, SPR_MPC_IMMR, "IMMR",
2363                  SPR_NOACCESS, SPR_NOACCESS,
2364                  &spr_read_generic, &spr_write_generic,
2365                  0x00000000);
2366 }
2367
2368 static void gen_spr_5xx (CPUPPCState *env)
2369 {
2370     /* XXX : not implemented */
2371     spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2372                  SPR_NOACCESS, SPR_NOACCESS,
2373                  &spr_read_generic, &spr_write_generic,
2374                  0x00000000);
2375     /* XXX : not implemented */
2376     spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2377                  SPR_NOACCESS, SPR_NOACCESS,
2378                  &spr_read_generic, &spr_write_generic,
2379                  0x00000000);
2380     /* XXX : not implemented */
2381     spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2382                  SPR_NOACCESS, SPR_NOACCESS,
2383                  &spr_read_generic, &spr_write_generic,
2384                  0x00000000);
2385     /* XXX : not implemented */
2386     spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2387                  SPR_NOACCESS, SPR_NOACCESS,
2388                  &spr_read_generic, &spr_write_generic,
2389                  0x00000000);
2390     /* XXX : not implemented */
2391     spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2392                  SPR_NOACCESS, SPR_NOACCESS,
2393                  &spr_read_generic, &spr_write_generic,
2394                  0x00000000);
2395     /* XXX : not implemented */
2396     spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2397                  SPR_NOACCESS, SPR_NOACCESS,
2398                  &spr_read_generic, &spr_write_generic,
2399                  0x00000000);
2400     /* XXX : not implemented */
2401     spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2402                  SPR_NOACCESS, SPR_NOACCESS,
2403                  &spr_read_generic, &spr_write_generic,
2404                  0x00000000);
2405     /* XXX : not implemented */
2406     spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2407                  SPR_NOACCESS, SPR_NOACCESS,
2408                  &spr_read_generic, &spr_write_generic,
2409                  0x00000000);
2410     /* XXX : not implemented */
2411     spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2412                  SPR_NOACCESS, SPR_NOACCESS,
2413                  &spr_read_generic, &spr_write_generic,
2414                  0x00000000);
2415     /* XXX : not implemented */
2416     spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2417                  SPR_NOACCESS, SPR_NOACCESS,
2418                  &spr_read_generic, &spr_write_generic,
2419                  0x00000000);
2420     /* XXX : not implemented */
2421     spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2422                  SPR_NOACCESS, SPR_NOACCESS,
2423                  &spr_read_generic, &spr_write_generic,
2424                  0x00000000);
2425     /* XXX : not implemented */
2426     spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2427                  SPR_NOACCESS, SPR_NOACCESS,
2428                  &spr_read_generic, &spr_write_generic,
2429                  0x00000000);
2430     /* XXX : not implemented */
2431     spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2432                  SPR_NOACCESS, SPR_NOACCESS,
2433                  &spr_read_generic, &spr_write_generic,
2434                  0x00000000);
2435     /* XXX : not implemented */
2436     spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2437                  SPR_NOACCESS, SPR_NOACCESS,
2438                  &spr_read_generic, &spr_write_generic,
2439                  0x00000000);
2440     /* XXX : not implemented */
2441     spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2442                  SPR_NOACCESS, SPR_NOACCESS,
2443                  &spr_read_generic, &spr_write_generic,
2444                  0x00000000);
2445     /* XXX : not implemented */
2446     spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2447                  SPR_NOACCESS, SPR_NOACCESS,
2448                  &spr_read_generic, &spr_write_generic,
2449                  0x00000000);
2450     /* XXX : not implemented */
2451     spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2452                  SPR_NOACCESS, SPR_NOACCESS,
2453                  &spr_read_generic, &spr_write_generic,
2454                  0x00000000);
2455     /* XXX : not implemented */
2456     spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2457                  SPR_NOACCESS, SPR_NOACCESS,
2458                  &spr_read_generic, &spr_write_generic,
2459                  0x00000000);
2460     /* XXX : not implemented */
2461     spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2462                  SPR_NOACCESS, SPR_NOACCESS,
2463                  &spr_read_generic, &spr_write_generic,
2464                  0x00000000);
2465     /* XXX : not implemented */
2466     spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2467                  SPR_NOACCESS, SPR_NOACCESS,
2468                  &spr_read_generic, &spr_write_generic,
2469                  0x00000000);
2470     /* XXX : not implemented */
2471     spr_register(env, SPR_RCPU_FPECR, "FPECR",
2472                  SPR_NOACCESS, SPR_NOACCESS,
2473                  &spr_read_generic, &spr_write_generic,
2474                  0x00000000);
2475 }
2476
2477 static void gen_spr_8xx (CPUPPCState *env)
2478 {
2479     /* XXX : not implemented */
2480     spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2481                  SPR_NOACCESS, SPR_NOACCESS,
2482                  &spr_read_generic, &spr_write_generic,
2483                  0x00000000);
2484     /* XXX : not implemented */
2485     spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2486                  SPR_NOACCESS, SPR_NOACCESS,
2487                  &spr_read_generic, &spr_write_generic,
2488                  0x00000000);
2489     /* XXX : not implemented */
2490     spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2491                  SPR_NOACCESS, SPR_NOACCESS,
2492                  &spr_read_generic, &spr_write_generic,
2493                  0x00000000);
2494     /* XXX : not implemented */
2495     spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2496                  SPR_NOACCESS, SPR_NOACCESS,
2497                  &spr_read_generic, &spr_write_generic,
2498                  0x00000000);
2499     /* XXX : not implemented */
2500     spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2501                  SPR_NOACCESS, SPR_NOACCESS,
2502                  &spr_read_generic, &spr_write_generic,
2503                  0x00000000);
2504     /* XXX : not implemented */
2505     spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2506                  SPR_NOACCESS, SPR_NOACCESS,
2507                  &spr_read_generic, &spr_write_generic,
2508                  0x00000000);
2509     /* XXX : not implemented */
2510     spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2511                  SPR_NOACCESS, SPR_NOACCESS,
2512                  &spr_read_generic, &spr_write_generic,
2513                  0x00000000);
2514     /* XXX : not implemented */
2515     spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2516                  SPR_NOACCESS, SPR_NOACCESS,
2517                  &spr_read_generic, &spr_write_generic,
2518                  0x00000000);
2519     /* XXX : not implemented */
2520     spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2521                  SPR_NOACCESS, SPR_NOACCESS,
2522                  &spr_read_generic, &spr_write_generic,
2523                  0x00000000);
2524     /* XXX : not implemented */
2525     spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2526                  SPR_NOACCESS, SPR_NOACCESS,
2527                  &spr_read_generic, &spr_write_generic,
2528                  0x00000000);
2529     /* XXX : not implemented */
2530     spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2531                  SPR_NOACCESS, SPR_NOACCESS,
2532                  &spr_read_generic, &spr_write_generic,
2533                  0x00000000);
2534     /* XXX : not implemented */
2535     spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2536                  SPR_NOACCESS, SPR_NOACCESS,
2537                  &spr_read_generic, &spr_write_generic,
2538                  0x00000000);
2539     /* XXX : not implemented */
2540     spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2541                  SPR_NOACCESS, SPR_NOACCESS,
2542                  &spr_read_generic, &spr_write_generic,
2543                  0x00000000);
2544     /* XXX : not implemented */
2545     spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2546                  SPR_NOACCESS, SPR_NOACCESS,
2547                  &spr_read_generic, &spr_write_generic,
2548                  0x00000000);
2549     /* XXX : not implemented */
2550     spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2551                  SPR_NOACCESS, SPR_NOACCESS,
2552                  &spr_read_generic, &spr_write_generic,
2553                  0x00000000);
2554     /* XXX : not implemented */
2555     spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2556                  SPR_NOACCESS, SPR_NOACCESS,
2557                  &spr_read_generic, &spr_write_generic,
2558                  0x00000000);
2559     /* XXX : not implemented */
2560     spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2561                  SPR_NOACCESS, SPR_NOACCESS,
2562                  &spr_read_generic, &spr_write_generic,
2563                  0x00000000);
2564     /* XXX : not implemented */
2565     spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2566                  SPR_NOACCESS, SPR_NOACCESS,
2567                  &spr_read_generic, &spr_write_generic,
2568                  0x00000000);
2569     /* XXX : not implemented */
2570     spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2571                  SPR_NOACCESS, SPR_NOACCESS,
2572                  &spr_read_generic, &spr_write_generic,
2573                  0x00000000);
2574     /* XXX : not implemented */
2575     spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2576                  SPR_NOACCESS, SPR_NOACCESS,
2577                  &spr_read_generic, &spr_write_generic,
2578                  0x00000000);
2579     /* XXX : not implemented */
2580     spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2581                  SPR_NOACCESS, SPR_NOACCESS,
2582                  &spr_read_generic, &spr_write_generic,
2583                  0x00000000);
2584     /* XXX : not implemented */
2585     spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2586                  SPR_NOACCESS, SPR_NOACCESS,
2587                  &spr_read_generic, &spr_write_generic,
2588                  0x00000000);
2589     /* XXX : not implemented */
2590     spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2591                  SPR_NOACCESS, SPR_NOACCESS,
2592                  &spr_read_generic, &spr_write_generic,
2593                  0x00000000);
2594     /* XXX : not implemented */
2595     spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2596                  SPR_NOACCESS, SPR_NOACCESS,
2597                  &spr_read_generic, &spr_write_generic,
2598                  0x00000000);
2599     /* XXX : not implemented */
2600     spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2601                  SPR_NOACCESS, SPR_NOACCESS,
2602                  &spr_read_generic, &spr_write_generic,
2603                  0x00000000);
2604 }
2605
2606 // XXX: TODO
2607 /*
2608  * AMR     => SPR 29 (Power 2.04)
2609  * CTRL    => SPR 136 (Power 2.04)
2610  * CTRL    => SPR 152 (Power 2.04)
2611  * SCOMC   => SPR 276 (64 bits ?)
2612  * SCOMD   => SPR 277 (64 bits ?)
2613  * TBU40   => SPR 286 (Power 2.04 hypv)
2614  * HSPRG0  => SPR 304 (Power 2.04 hypv)
2615  * HSPRG1  => SPR 305 (Power 2.04 hypv)
2616  * HDSISR  => SPR 306 (Power 2.04 hypv)
2617  * HDAR    => SPR 307 (Power 2.04 hypv)
2618  * PURR    => SPR 309 (Power 2.04 hypv)
2619  * HDEC    => SPR 310 (Power 2.04 hypv)
2620  * HIOR    => SPR 311 (hypv)
2621  * RMOR    => SPR 312 (970)
2622  * HRMOR   => SPR 313 (Power 2.04 hypv)
2623  * HSRR0   => SPR 314 (Power 2.04 hypv)
2624  * HSRR1   => SPR 315 (Power 2.04 hypv)
2625  * LPCR    => SPR 316 (970)
2626  * LPIDR   => SPR 317 (970)
2627  * EPR     => SPR 702 (Power 2.04 emb)
2628  * perf    => 768-783 (Power 2.04)
2629  * perf    => 784-799 (Power 2.04)
2630  * PPR     => SPR 896 (Power 2.04)
2631  * EPLC    => SPR 947 (Power 2.04 emb)
2632  * EPSC    => SPR 948 (Power 2.04 emb)
2633  * DABRX   => 1015    (Power 2.04 hypv)
2634  * FPECR   => SPR 1022 (?)
2635  * ... and more (thermal management, performance counters, ...)
2636  */
2637
2638 /*****************************************************************************/
2639 /* Exception vectors models                                                  */
2640 static void init_excp_4xx_real (CPUPPCState *env)
2641 {
2642 #if !defined(CONFIG_USER_ONLY)
2643     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2644     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2645     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2646     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2647     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2648     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2649     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2650     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2651     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2652     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2653     env->hreset_excp_prefix = 0x00000000UL;
2654     env->ivor_mask = 0x0000FFF0UL;
2655     env->ivpr_mask = 0xFFFF0000UL;
2656     /* Hardware reset vector */
2657     env->hreset_vector = 0xFFFFFFFCUL;
2658 #endif
2659 }
2660
2661 static void init_excp_4xx_softmmu (CPUPPCState *env)
2662 {
2663 #if !defined(CONFIG_USER_ONLY)
2664     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2665     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2666     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2667     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2668     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2669     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2670     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2671     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2672     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2673     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2674     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2675     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2676     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2677     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2678     env->hreset_excp_prefix = 0x00000000UL;
2679     env->ivor_mask = 0x0000FFF0UL;
2680     env->ivpr_mask = 0xFFFF0000UL;
2681     /* Hardware reset vector */
2682     env->hreset_vector = 0xFFFFFFFCUL;
2683 #endif
2684 }
2685
2686 static void init_excp_MPC5xx (CPUPPCState *env)
2687 {
2688 #if !defined(CONFIG_USER_ONLY)
2689     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2690     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2691     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2692     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2693     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2694     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2695     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2696     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2697     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2698     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2699     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2700     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2701     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2702     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2703     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2704     env->hreset_excp_prefix = 0x00000000UL;
2705     env->ivor_mask = 0x0000FFF0UL;
2706     env->ivpr_mask = 0xFFFF0000UL;
2707     /* Hardware reset vector */
2708     env->hreset_vector = 0xFFFFFFFCUL;
2709 #endif
2710 }
2711
2712 static void init_excp_MPC8xx (CPUPPCState *env)
2713 {
2714 #if !defined(CONFIG_USER_ONLY)
2715     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2716     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2717     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2718     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2719     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2720     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2721     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2722     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2723     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2724     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2725     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2726     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2727     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2728     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2729     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2730     env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2731     env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2732     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2733     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2734     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2735     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2736     env->hreset_excp_prefix = 0x00000000UL;
2737     env->ivor_mask = 0x0000FFF0UL;
2738     env->ivpr_mask = 0xFFFF0000UL;
2739     /* Hardware reset vector */
2740     env->hreset_vector = 0xFFFFFFFCUL;
2741 #endif
2742 }
2743
2744 static void init_excp_G2 (CPUPPCState *env)
2745 {
2746 #if !defined(CONFIG_USER_ONLY)
2747     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2748     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2749     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2750     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2751     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2752     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2753     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2754     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2755     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2756     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2757     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2758     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2759     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2760     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2761     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2762     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2763     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2764     env->hreset_excp_prefix = 0x00000000UL;
2765     /* Hardware reset vector */
2766     env->hreset_vector = 0xFFFFFFFCUL;
2767 #endif
2768 }
2769
2770 static void init_excp_e200 (CPUPPCState *env)
2771 {
2772 #if !defined(CONFIG_USER_ONLY)
2773     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2774     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2775     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2776     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2777     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2778     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2779     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2780     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2781     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2782     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2783     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2784     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2785     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2786     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2787     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2788     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2789     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2790     env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
2791     env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
2792     env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
2793     env->hreset_excp_prefix = 0x00000000UL;
2794     env->ivor_mask = 0x0000FFF7UL;
2795     env->ivpr_mask = 0xFFFF0000UL;
2796     /* Hardware reset vector */
2797     env->hreset_vector = 0xFFFFFFFCUL;
2798 #endif
2799 }
2800
2801 static void init_excp_BookE (CPUPPCState *env)
2802 {
2803 #if !defined(CONFIG_USER_ONLY)
2804     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2805     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2806     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2807     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2808     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2809     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2810     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2811     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2812     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2813     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2814     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2815     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2816     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2817     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2818     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2819     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2820     env->hreset_excp_prefix = 0x00000000UL;
2821     env->ivor_mask = 0x0000FFE0UL;
2822     env->ivpr_mask = 0xFFFF0000UL;
2823     /* Hardware reset vector */
2824     env->hreset_vector = 0xFFFFFFFCUL;
2825 #endif
2826 }
2827
2828 static void init_excp_601 (CPUPPCState *env)
2829 {
2830 #if !defined(CONFIG_USER_ONLY)
2831     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2832     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2833     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2834     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2835     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2836     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2837     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2838     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2839     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2840     env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2841     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2842     env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2843     env->hreset_excp_prefix = 0xFFF00000UL;
2844     /* Hardware reset vector */
2845     env->hreset_vector = 0x00000100UL;
2846 #endif
2847 }
2848
2849 static void init_excp_602 (CPUPPCState *env)
2850 {
2851 #if !defined(CONFIG_USER_ONLY)
2852     /* XXX: exception prefix has a special behavior on 602 */
2853     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2854     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2855     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2856     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2857     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2858     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2859     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2860     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2861     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2862     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2863     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2864     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2865     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2866     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2867     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2868     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2869     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2870     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2871     env->hreset_excp_prefix = 0xFFF00000UL;
2872     /* Hardware reset vector */
2873     env->hreset_vector = 0xFFFFFFFCUL;
2874 #endif
2875 }
2876
2877 static void init_excp_603 (CPUPPCState *env)
2878 {
2879 #if !defined(CONFIG_USER_ONLY)
2880     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2881     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2882     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2883     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2884     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2885     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2886     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2887     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2888     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2889     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2890     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2891     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2892     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2893     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2894     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2895     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2896     env->hreset_excp_prefix = 0x00000000UL;
2897     /* Hardware reset vector */
2898     env->hreset_vector = 0xFFFFFFFCUL;
2899 #endif
2900 }
2901
2902 static void init_excp_604 (CPUPPCState *env)
2903 {
2904 #if !defined(CONFIG_USER_ONLY)
2905     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2906     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2907     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2908     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2909     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2910     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2911     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2912     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2913     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2914     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2915     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2916     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2917     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2918     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2919     env->hreset_excp_prefix = 0xFFF00000UL;
2920     /* Hardware reset vector */
2921     env->hreset_vector = 0x00000100UL;
2922 #endif
2923 }
2924
2925 #if defined(TARGET_PPC64)
2926 static void init_excp_620 (CPUPPCState *env)
2927 {
2928 #if !defined(CONFIG_USER_ONLY)
2929     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2930     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2931     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2932     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2933     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2934     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2935     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2936     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2937     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2938     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2939     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2940     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2941     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2942     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2943     env->hreset_excp_prefix = 0xFFF00000UL;
2944     /* Hardware reset vector */
2945     env->hreset_vector = 0x0000000000000100ULL;
2946 #endif
2947 }
2948 #endif /* defined(TARGET_PPC64) */
2949
2950 static void init_excp_7x0 (CPUPPCState *env)
2951 {
2952 #if !defined(CONFIG_USER_ONLY)
2953     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2954     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2955     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2956     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2957     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2958     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2959     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2960     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2961     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2962     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2963     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2964     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2965     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2966     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2967     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2968     env->hreset_excp_prefix = 0x00000000UL;
2969     /* Hardware reset vector */
2970     env->hreset_vector = 0xFFFFFFFCUL;
2971 #endif
2972 }
2973
2974 static void init_excp_750cl (CPUPPCState *env)
2975 {
2976 #if !defined(CONFIG_USER_ONLY)
2977     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2978     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2979     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2980     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2981     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2982     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2983     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2984     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2985     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2986     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2987     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2988     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2989     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2990     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2991     env->hreset_excp_prefix = 0x00000000UL;
2992     /* Hardware reset vector */
2993     env->hreset_vector = 0xFFFFFFFCUL;
2994 #endif
2995 }
2996
2997 static void init_excp_750cx (CPUPPCState *env)
2998 {
2999 #if !defined(CONFIG_USER_ONLY)
3000     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3001     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3002     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3003     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3004     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3005     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3006     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3007     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3008     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3009     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3010     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3011     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3012     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3013     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3014     env->hreset_excp_prefix = 0x00000000UL;
3015     /* Hardware reset vector */
3016     env->hreset_vector = 0xFFFFFFFCUL;
3017 #endif
3018 }
3019
3020 /* XXX: Check if this is correct */
3021 static void init_excp_7x5 (CPUPPCState *env)
3022 {
3023 #if !defined(CONFIG_USER_ONLY)
3024     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3025     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3026     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3027     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3028     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3029     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3030     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3031     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3032     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3033     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3034     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3035     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3036     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3037     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3038     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3039     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3040     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3041     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3042     env->hreset_excp_prefix = 0x00000000UL;
3043     /* Hardware reset vector */
3044     env->hreset_vector = 0xFFFFFFFCUL;
3045 #endif
3046 }
3047
3048 static void init_excp_7400 (CPUPPCState *env)
3049 {
3050 #if !defined(CONFIG_USER_ONLY)
3051     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3052     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3053     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3054     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3055     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3056     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3057     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3058     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3059     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3060     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3061     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3062     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3063     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3064     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3065     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3066     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3067     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3068     env->hreset_excp_prefix = 0x00000000UL;
3069     /* Hardware reset vector */
3070     env->hreset_vector = 0xFFFFFFFCUL;
3071 #endif
3072 }
3073
3074 static void init_excp_7450 (CPUPPCState *env)
3075 {
3076 #if !defined(CONFIG_USER_ONLY)
3077     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3078     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3079     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3080     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3081     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3082     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3083     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3084     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3085     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3086     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3087     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3088     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3089     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3090     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3091     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3092     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3093     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3094     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3095     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3096     env->hreset_excp_prefix = 0x00000000UL;
3097     /* Hardware reset vector */
3098     env->hreset_vector = 0xFFFFFFFCUL;
3099 #endif
3100 }
3101
3102 #if defined (TARGET_PPC64)
3103 static void init_excp_970 (CPUPPCState *env)
3104 {
3105 #if !defined(CONFIG_USER_ONLY)
3106     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3107     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3108     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3109     env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3110     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3111     env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3112     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3113     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3114     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3115     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3116     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3117     env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3118     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3119     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3120     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3121     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3122     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3123     env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3124     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3125     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3126     env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3127     /* Hardware reset vector */
3128     env->hreset_vector = 0x0000000000000100ULL;
3129 #endif
3130 }
3131 #endif
3132
3133 /*****************************************************************************/
3134 /* Power management enable checks                                            */
3135 static int check_pow_none (CPUPPCState *env)
3136 {
3137     return 0;
3138 }
3139
3140 static int check_pow_nocheck (CPUPPCState *env)
3141 {
3142     return 1;
3143 }
3144
3145 static int check_pow_hid0 (CPUPPCState *env)
3146 {
3147     if (env->spr[SPR_HID0] & 0x00E00000)
3148         return 1;
3149
3150     return 0;
3151 }
3152
3153 static int check_pow_hid0_74xx (CPUPPCState *env)
3154 {
3155     if (env->spr[SPR_HID0] & 0x00600000)
3156         return 1;
3157
3158     return 0;
3159 }
3160
3161 /*****************************************************************************/
3162 /* PowerPC implementations definitions                                       */
3163
3164 /* PowerPC 401                                                               */
3165 #define POWERPC_INSNS_401    (PPC_INSNS_BASE | PPC_STRING |                   \
3166                               PPC_WRTEE | PPC_DCR |                           \
3167                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3168                               PPC_CACHE_DCBZ |                                \
3169                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3170                               PPC_4xx_COMMON | PPC_40x_EXCP)
3171 #define POWERPC_MSRM_401     (0x00000000000FD201ULL)
3172 #define POWERPC_MMU_401      (POWERPC_MMU_REAL)
3173 #define POWERPC_EXCP_401     (POWERPC_EXCP_40x)
3174 #define POWERPC_INPUT_401    (PPC_FLAGS_INPUT_401)
3175 #define POWERPC_BFDM_401     (bfd_mach_ppc_403)
3176 #define POWERPC_FLAG_401     (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3177                               POWERPC_FLAG_BUS_CLK)
3178 #define check_pow_401        check_pow_nocheck
3179
3180 static void init_proc_401 (CPUPPCState *env)
3181 {
3182     gen_spr_40x(env);
3183     gen_spr_401_403(env);
3184     gen_spr_401(env);
3185     init_excp_4xx_real(env);
3186     env->dcache_line_size = 32;
3187     env->icache_line_size = 32;
3188     /* Allocate hardware IRQ controller */
3189     ppc40x_irq_init(env);
3190 }
3191
3192 /* PowerPC 401x2                                                             */
3193 #define POWERPC_INSNS_401x2  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3194                               PPC_DCR | PPC_WRTEE |                           \
3195                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3196                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3197                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3198                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3199                               PPC_4xx_COMMON | PPC_40x_EXCP)
3200 #define POWERPC_MSRM_401x2   (0x00000000001FD231ULL)
3201 #define POWERPC_MMU_401x2    (POWERPC_MMU_SOFT_4xx_Z)
3202 #define POWERPC_EXCP_401x2   (POWERPC_EXCP_40x)
3203 #define POWERPC_INPUT_401x2  (PPC_FLAGS_INPUT_401)
3204 #define POWERPC_BFDM_401x2   (bfd_mach_ppc_403)
3205 #define POWERPC_FLAG_401x2   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3206                               POWERPC_FLAG_BUS_CLK)
3207 #define check_pow_401x2      check_pow_nocheck
3208
3209 static void init_proc_401x2 (CPUPPCState *env)
3210 {
3211     gen_spr_40x(env);
3212     gen_spr_401_403(env);
3213     gen_spr_401x2(env);
3214     gen_spr_compress(env);
3215     /* Memory management */
3216 #if !defined(CONFIG_USER_ONLY)
3217     env->nb_tlb = 64;
3218     env->nb_ways = 1;
3219     env->id_tlbs = 0;
3220 #endif
3221     init_excp_4xx_softmmu(env);
3222     env->dcache_line_size = 32;
3223     env->icache_line_size = 32;
3224     /* Allocate hardware IRQ controller */
3225     ppc40x_irq_init(env);
3226 }
3227
3228 /* PowerPC 401x3                                                             */
3229 #define POWERPC_INSNS_401x3  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3230                               PPC_DCR | PPC_WRTEE |                           \
3231                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3232                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3233                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3234                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3235                               PPC_4xx_COMMON | PPC_40x_EXCP)
3236 #define POWERPC_MSRM_401x3   (0x00000000001FD631ULL)
3237 #define POWERPC_MMU_401x3    (POWERPC_MMU_SOFT_4xx_Z)
3238 #define POWERPC_EXCP_401x3   (POWERPC_EXCP_40x)
3239 #define POWERPC_INPUT_401x3  (PPC_FLAGS_INPUT_401)
3240 #define POWERPC_BFDM_401x3   (bfd_mach_ppc_403)
3241 #define POWERPC_FLAG_401x3   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3242                               POWERPC_FLAG_BUS_CLK)
3243 #define check_pow_401x3      check_pow_nocheck
3244
3245 __attribute__ (( unused ))
3246 static void init_proc_401x3 (CPUPPCState *env)
3247 {
3248     gen_spr_40x(env);
3249     gen_spr_401_403(env);
3250     gen_spr_401(env);
3251     gen_spr_401x2(env);
3252     gen_spr_compress(env);
3253     init_excp_4xx_softmmu(env);
3254     env->dcache_line_size = 32;
3255     env->icache_line_size = 32;
3256     /* Allocate hardware IRQ controller */
3257     ppc40x_irq_init(env);
3258 }
3259
3260 /* IOP480                                                                    */
3261 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING |                   \
3262                               PPC_DCR | PPC_WRTEE |                           \
3263                               PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |    \
3264                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3265                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3266                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3267                               PPC_4xx_COMMON | PPC_40x_EXCP)
3268 #define POWERPC_MSRM_IOP480  (0x00000000001FD231ULL)
3269 #define POWERPC_MMU_IOP480   (POWERPC_MMU_SOFT_4xx_Z)
3270 #define POWERPC_EXCP_IOP480  (POWERPC_EXCP_40x)
3271 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3272 #define POWERPC_BFDM_IOP480  (bfd_mach_ppc_403)
3273 #define POWERPC_FLAG_IOP480  (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3274                               POWERPC_FLAG_BUS_CLK)
3275 #define check_pow_IOP480     check_pow_nocheck
3276
3277 static void init_proc_IOP480 (CPUPPCState *env)
3278 {
3279     gen_spr_40x(env);
3280     gen_spr_401_403(env);
3281     gen_spr_401x2(env);
3282     gen_spr_compress(env);
3283     /* Memory management */
3284 #if !defined(CONFIG_USER_ONLY)
3285     env->nb_tlb = 64;
3286     env->nb_ways = 1;
3287     env->id_tlbs = 0;
3288 #endif
3289     init_excp_4xx_softmmu(env);
3290     env->dcache_line_size = 32;
3291     env->icache_line_size = 32;
3292     /* Allocate hardware IRQ controller */
3293     ppc40x_irq_init(env);
3294 }
3295
3296 /* PowerPC 403                                                               */
3297 #define POWERPC_INSNS_403    (PPC_INSNS_BASE | PPC_STRING |                   \
3298                               PPC_DCR | PPC_WRTEE |                           \
3299                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3300                               PPC_CACHE_DCBZ |                                \
3301                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3302                               PPC_4xx_COMMON | PPC_40x_EXCP)
3303 #define POWERPC_MSRM_403     (0x000000000007D00DULL)
3304 #define POWERPC_MMU_403      (POWERPC_MMU_REAL)
3305 #define POWERPC_EXCP_403     (POWERPC_EXCP_40x)
3306 #define POWERPC_INPUT_403    (PPC_FLAGS_INPUT_401)
3307 #define POWERPC_BFDM_403     (bfd_mach_ppc_403)
3308 #define POWERPC_FLAG_403     (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
3309                               POWERPC_FLAG_BUS_CLK)
3310 #define check_pow_403        check_pow_nocheck
3311
3312 static void init_proc_403 (CPUPPCState *env)
3313 {
3314     gen_spr_40x(env);
3315     gen_spr_401_403(env);
3316     gen_spr_403(env);
3317     gen_spr_403_real(env);
3318     init_excp_4xx_real(env);
3319     env->dcache_line_size = 32;
3320     env->icache_line_size = 32;
3321     /* Allocate hardware IRQ controller */
3322     ppc40x_irq_init(env);
3323 }
3324
3325 /* PowerPC 403 GCX                                                           */
3326 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING |                   \
3327                               PPC_DCR | PPC_WRTEE |                           \
3328                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3329                               PPC_CACHE_DCBZ |                                \
3330                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3331                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3332                               PPC_4xx_COMMON | PPC_40x_EXCP)
3333 #define POWERPC_MSRM_403GCX  (0x000000000007D00DULL)
3334 #define POWERPC_MMU_403GCX   (POWERPC_MMU_SOFT_4xx_Z)
3335 #define POWERPC_EXCP_403GCX  (POWERPC_EXCP_40x)
3336 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3337 #define POWERPC_BFDM_403GCX  (bfd_mach_ppc_403)
3338 #define POWERPC_FLAG_403GCX  (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
3339                               POWERPC_FLAG_BUS_CLK)
3340 #define check_pow_403GCX     check_pow_nocheck
3341
3342 static void init_proc_403GCX (CPUPPCState *env)
3343 {
3344     gen_spr_40x(env);
3345     gen_spr_401_403(env);
3346     gen_spr_403(env);
3347     gen_spr_403_real(env);
3348     gen_spr_403_mmu(env);
3349     /* Bus access control */
3350     /* not emulated, as Qemu never does speculative access */
3351     spr_register(env, SPR_40x_SGR, "SGR",
3352                  SPR_NOACCESS, SPR_NOACCESS,
3353                  &spr_read_generic, &spr_write_generic,
3354                  0xFFFFFFFF);
3355     /* not emulated, as Qemu do not emulate caches */
3356     spr_register(env, SPR_40x_DCWR, "DCWR",
3357                  SPR_NOACCESS, SPR_NOACCESS,
3358                  &spr_read_generic, &spr_write_generic,
3359                  0x00000000);
3360     /* Memory management */
3361 #if !defined(CONFIG_USER_ONLY)
3362     env->nb_tlb = 64;
3363     env->nb_ways = 1;
3364     env->id_tlbs = 0;
3365 #endif
3366     init_excp_4xx_softmmu(env);
3367     env->dcache_line_size = 32;
3368     env->icache_line_size = 32;
3369     /* Allocate hardware IRQ controller */
3370     ppc40x_irq_init(env);
3371 }
3372
3373 /* PowerPC 405                                                               */
3374 #define POWERPC_INSNS_405    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3375                               PPC_DCR | PPC_WRTEE |                           \
3376                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3377                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3378                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3379                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3380                               PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3381 #define POWERPC_MSRM_405     (0x000000000006E630ULL)
3382 #define POWERPC_MMU_405      (POWERPC_MMU_SOFT_4xx)
3383 #define POWERPC_EXCP_405     (POWERPC_EXCP_40x)
3384 #define POWERPC_INPUT_405    (PPC_FLAGS_INPUT_405)
3385 #define POWERPC_BFDM_405     (bfd_mach_ppc_403)
3386 #define POWERPC_FLAG_405     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3387                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3388 #define check_pow_405        check_pow_nocheck
3389
3390 static void init_proc_405 (CPUPPCState *env)
3391 {
3392     /* Time base */
3393     gen_tbl(env);
3394     gen_spr_40x(env);
3395     gen_spr_405(env);
3396     /* Bus access control */
3397     /* not emulated, as Qemu never does speculative access */
3398     spr_register(env, SPR_40x_SGR, "SGR",
3399                  SPR_NOACCESS, SPR_NOACCESS,
3400                  &spr_read_generic, &spr_write_generic,
3401                  0xFFFFFFFF);
3402     /* not emulated, as Qemu do not emulate caches */
3403     spr_register(env, SPR_40x_DCWR, "DCWR",
3404                  SPR_NOACCESS, SPR_NOACCESS,
3405                  &spr_read_generic, &spr_write_generic,
3406                  0x00000000);
3407     /* Memory management */
3408 #if !defined(CONFIG_USER_ONLY)
3409     env->nb_tlb = 64;
3410     env->nb_ways = 1;
3411     env->id_tlbs = 0;
3412 #endif
3413     init_excp_4xx_softmmu(env);
3414     env->dcache_line_size = 32;
3415     env->icache_line_size = 32;
3416     /* Allocate hardware IRQ controller */
3417     ppc40x_irq_init(env);
3418 }
3419
3420 /* PowerPC 440 EP                                                            */
3421 #define POWERPC_INSNS_440EP  (PPC_INSNS_BASE | PPC_STRING |                   \
3422                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
3423                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3424                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3425                               PPC_MEM_TLBSYNC | PPC_MFTB |                    \
3426                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3427                               PPC_440_SPEC)
3428 #define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
3429 #define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
3430 #define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
3431 #define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
3432 #define POWERPC_BFDM_440EP   (bfd_mach_ppc_403)
3433 #define POWERPC_FLAG_440EP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3434                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3435 #define check_pow_440EP      check_pow_nocheck
3436
3437 __attribute__ (( unused ))
3438 static void init_proc_440EP (CPUPPCState *env)
3439 {
3440     /* Time base */
3441     gen_tbl(env);
3442     gen_spr_BookE(env, 0x000000000000FFFFULL);
3443     gen_spr_440(env);
3444     gen_spr_usprgh(env);
3445     /* Processor identification */
3446     spr_register(env, SPR_BOOKE_PIR, "PIR",
3447                  SPR_NOACCESS, SPR_NOACCESS,
3448                  &spr_read_generic, &spr_write_pir,
3449                  0x00000000);
3450     /* XXX : not implemented */
3451     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3452                  SPR_NOACCESS, SPR_NOACCESS,
3453                  &spr_read_generic, &spr_write_generic,
3454                  0x00000000);
3455     /* XXX : not implemented */
3456     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3457                  SPR_NOACCESS, SPR_NOACCESS,
3458                  &spr_read_generic, &spr_write_generic,
3459                  0x00000000);
3460     /* XXX : not implemented */
3461     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3462                  SPR_NOACCESS, SPR_NOACCESS,
3463                  &spr_read_generic, &spr_write_generic,
3464                  0x00000000);
3465     /* XXX : not implemented */
3466     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3467                  SPR_NOACCESS, SPR_NOACCESS,
3468                  &spr_read_generic, &spr_write_generic,
3469                  0x00000000);
3470     /* XXX : not implemented */
3471     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3472                  SPR_NOACCESS, SPR_NOACCESS,
3473                  &spr_read_generic, &spr_write_generic,
3474                  0x00000000);
3475     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3476                  SPR_NOACCESS, SPR_NOACCESS,
3477                  &spr_read_generic, &spr_write_generic,
3478                  0x00000000);
3479     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3480                  SPR_NOACCESS, SPR_NOACCESS,
3481                  &spr_read_generic, &spr_write_generic,
3482                  0x00000000);
3483     /* XXX : not implemented */
3484     spr_register(env, SPR_440_CCR1, "CCR1",
3485                  SPR_NOACCESS, SPR_NOACCESS,
3486                  &spr_read_generic, &spr_write_generic,
3487                  0x00000000);
3488     /* Memory management */
3489 #if !defined(CONFIG_USER_ONLY)
3490     env->nb_tlb = 64;
3491     env->nb_ways = 1;
3492     env->id_tlbs = 0;
3493 #endif
3494     init_excp_BookE(env);
3495     env->dcache_line_size = 32;
3496     env->icache_line_size = 32;
3497     /* XXX: TODO: allocate internal IRQ controller */
3498 }
3499
3500 /* PowerPC 440 GP                                                            */
3501 #define POWERPC_INSNS_440GP  (PPC_INSNS_BASE | PPC_STRING |                   \
3502                               PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |  \
3503                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3504                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3505                               PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |       \
3506                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3507                               PPC_440_SPEC)
3508 #define POWERPC_MSRM_440GP   (0x000000000006FF30ULL)
3509 #define POWERPC_MMU_440GP    (POWERPC_MMU_BOOKE)
3510 #define POWERPC_EXCP_440GP   (POWERPC_EXCP_BOOKE)
3511 #define POWERPC_INPUT_440GP  (PPC_FLAGS_INPUT_BookE)
3512 #define POWERPC_BFDM_440GP   (bfd_mach_ppc_403)
3513 #define POWERPC_FLAG_440GP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3514                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3515 #define check_pow_440GP      check_pow_nocheck
3516
3517 __attribute__ (( unused ))
3518 static void init_proc_440GP (CPUPPCState *env)
3519 {
3520     /* Time base */
3521     gen_tbl(env);
3522     gen_spr_BookE(env, 0x000000000000FFFFULL);
3523     gen_spr_440(env);
3524     gen_spr_usprgh(env);
3525     /* Processor identification */
3526     spr_register(env, SPR_BOOKE_PIR, "PIR",
3527                  SPR_NOACCESS, SPR_NOACCESS,
3528                  &spr_read_generic, &spr_write_pir,
3529                  0x00000000);
3530     /* XXX : not implemented */
3531     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3532                  SPR_NOACCESS, SPR_NOACCESS,
3533                  &spr_read_generic, &spr_write_generic,
3534                  0x00000000);
3535     /* XXX : not implemented */
3536     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3537                  SPR_NOACCESS, SPR_NOACCESS,
3538                  &spr_read_generic, &spr_write_generic,
3539                  0x00000000);
3540     /* XXX : not implemented */
3541     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3542                  SPR_NOACCESS, SPR_NOACCESS,
3543                  &spr_read_generic, &spr_write_generic,
3544                  0x00000000);
3545     /* XXX : not implemented */
3546     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3547                  SPR_NOACCESS, SPR_NOACCESS,
3548                  &spr_read_generic, &spr_write_generic,
3549                  0x00000000);
3550     /* Memory management */
3551 #if !defined(CONFIG_USER_ONLY)
3552     env->nb_tlb = 64;
3553     env->nb_ways = 1;
3554     env->id_tlbs = 0;
3555 #endif
3556     init_excp_BookE(env);
3557     env->dcache_line_size = 32;
3558     env->icache_line_size = 32;
3559     /* XXX: TODO: allocate internal IRQ controller */
3560 }
3561
3562 /* PowerPC 440x4                                                             */
3563 #define POWERPC_INSNS_440x4  (PPC_INSNS_BASE | PPC_STRING |                   \
3564                               PPC_DCR | PPC_WRTEE |                           \
3565                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3566                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3567                               PPC_MEM_TLBSYNC | PPC_MFTB |                    \
3568                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3569                               PPC_440_SPEC)
3570 #define POWERPC_MSRM_440x4   (0x000000000006FF30ULL)
3571 #define POWERPC_MMU_440x4    (POWERPC_MMU_BOOKE)
3572 #define POWERPC_EXCP_440x4   (POWERPC_EXCP_BOOKE)
3573 #define POWERPC_INPUT_440x4  (PPC_FLAGS_INPUT_BookE)
3574 #define POWERPC_BFDM_440x4   (bfd_mach_ppc_403)
3575 #define POWERPC_FLAG_440x4   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3576                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3577 #define check_pow_440x4      check_pow_nocheck
3578
3579 __attribute__ (( unused ))
3580 static void init_proc_440x4 (CPUPPCState *env)
3581 {
3582     /* Time base */
3583     gen_tbl(env);
3584     gen_spr_BookE(env, 0x000000000000FFFFULL);
3585     gen_spr_440(env);
3586     gen_spr_usprgh(env);
3587     /* Processor identification */
3588     spr_register(env, SPR_BOOKE_PIR, "PIR",
3589                  SPR_NOACCESS, SPR_NOACCESS,
3590                  &spr_read_generic, &spr_write_pir,
3591                  0x00000000);
3592     /* XXX : not implemented */
3593     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3594                  SPR_NOACCESS, SPR_NOACCESS,
3595                  &spr_read_generic, &spr_write_generic,
3596                  0x00000000);
3597     /* XXX : not implemented */
3598     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3599                  SPR_NOACCESS, SPR_NOACCESS,
3600                  &spr_read_generic, &spr_write_generic,
3601                  0x00000000);
3602     /* XXX : not implemented */
3603     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3604                  SPR_NOACCESS, SPR_NOACCESS,
3605                  &spr_read_generic, &spr_write_generic,
3606                  0x00000000);
3607     /* XXX : not implemented */
3608     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3609                  SPR_NOACCESS, SPR_NOACCESS,
3610                  &spr_read_generic, &spr_write_generic,
3611                  0x00000000);
3612     /* Memory management */
3613 #if !defined(CONFIG_USER_ONLY)
3614     env->nb_tlb = 64;
3615     env->nb_ways = 1;
3616     env->id_tlbs = 0;
3617 #endif
3618     init_excp_BookE(env);
3619     env->dcache_line_size = 32;
3620     env->icache_line_size = 32;
3621     /* XXX: TODO: allocate internal IRQ controller */
3622 }
3623
3624 /* PowerPC 440x5                                                             */
3625 #define POWERPC_INSNS_440x5  (PPC_INSNS_BASE | PPC_STRING |                   \
3626                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
3627                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3628                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3629                               PPC_MEM_TLBSYNC | PPC_MFTB |                    \
3630                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3631                               PPC_440_SPEC)
3632 #define POWERPC_MSRM_440x5   (0x000000000006FF30ULL)
3633 #define POWERPC_MMU_440x5    (POWERPC_MMU_BOOKE)
3634 #define POWERPC_EXCP_440x5   (POWERPC_EXCP_BOOKE)
3635 #define POWERPC_INPUT_440x5  (PPC_FLAGS_INPUT_BookE)
3636 #define POWERPC_BFDM_440x5   (bfd_mach_ppc_403)
3637 #define POWERPC_FLAG_440x5   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |           \
3638                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3639 #define check_pow_440x5      check_pow_nocheck
3640
3641 static void init_proc_440x5 (CPUPPCState *env)
3642 {
3643     /* Time base */
3644     gen_tbl(env);
3645     gen_spr_BookE(env, 0x000000000000FFFFULL);
3646     gen_spr_440(env);
3647     gen_spr_usprgh(env);
3648     /* Processor identification */
3649     spr_register(env, SPR_BOOKE_PIR, "PIR",
3650                  SPR_NOACCESS, SPR_NOACCESS,
3651                  &spr_read_generic, &spr_write_pir,
3652                  0x00000000);
3653     /* XXX : not implemented */
3654     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3655                  SPR_NOACCESS, SPR_NOACCESS,
3656                  &spr_read_generic, &spr_write_generic,
3657                  0x00000000);
3658     /* XXX : not implemented */
3659     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3660                  SPR_NOACCESS, SPR_NOACCESS,
3661                  &spr_read_generic, &spr_write_generic,
3662                  0x00000000);
3663     /* XXX : not implemented */
3664     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3665                  SPR_NOACCESS, SPR_NOACCESS,
3666                  &spr_read_generic, &spr_write_generic,
3667                  0x00000000);
3668     /* XXX : not implemented */
3669     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3670                  SPR_NOACCESS, SPR_NOACCESS,
3671                  &spr_read_generic, &spr_write_generic,
3672                  0x00000000);
3673     /* XXX : not implemented */
3674     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3675                  SPR_NOACCESS, SPR_NOACCESS,
3676                  &spr_read_generic, &spr_write_generic,
3677                  0x00000000);
3678     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3679                  SPR_NOACCESS, SPR_NOACCESS,
3680                  &spr_read_generic, &spr_write_generic,
3681                  0x00000000);
3682     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3683                  SPR_NOACCESS, SPR_NOACCESS,
3684                  &spr_read_generic, &spr_write_generic,
3685                  0x00000000);
3686     /* XXX : not implemented */
3687     spr_register(env, SPR_440_CCR1, "CCR1",
3688                  SPR_NOACCESS, SPR_NOACCESS,
3689                  &spr_read_generic, &spr_write_generic,
3690                  0x00000000);
3691     /* Memory management */
3692 #if !defined(CONFIG_USER_ONLY)
3693     env->nb_tlb = 64;
3694     env->nb_ways = 1;
3695     env->id_tlbs = 0;
3696 #endif
3697     init_excp_BookE(env);
3698     env->dcache_line_size = 32;
3699     env->icache_line_size = 32;
3700     ppc40x_irq_init(env);
3701 }
3702
3703 /* PowerPC 460 (guessed)                                                     */
3704 #define POWERPC_INSNS_460    (PPC_INSNS_BASE | PPC_STRING |                   \
3705                               PPC_DCR | PPC_DCRX  | PPC_DCRUX |               \
3706                               PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |            \
3707                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3708                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3709                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3710                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3711                               PPC_440_SPEC)
3712 #define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3713 #define POWERPC_MMU_460      (POWERPC_MMU_BOOKE)
3714 #define POWERPC_EXCP_460     (POWERPC_EXCP_BOOKE)
3715 #define POWERPC_INPUT_460    (PPC_FLAGS_INPUT_BookE)
3716 #define POWERPC_BFDM_460     (bfd_mach_ppc_403)
3717 #define POWERPC_FLAG_460     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3718                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3719 #define check_pow_460        check_pow_nocheck
3720
3721 __attribute__ (( unused ))
3722 static void init_proc_460 (CPUPPCState *env)
3723 {
3724     /* Time base */
3725     gen_tbl(env);
3726     gen_spr_BookE(env, 0x000000000000FFFFULL);
3727     gen_spr_440(env);
3728     gen_spr_usprgh(env);
3729     /* Processor identification */
3730     spr_register(env, SPR_BOOKE_PIR, "PIR",
3731                  SPR_NOACCESS, SPR_NOACCESS,
3732                  &spr_read_generic, &spr_write_pir,
3733                  0x00000000);
3734     /* XXX : not implemented */
3735     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3736                  SPR_NOACCESS, SPR_NOACCESS,
3737                  &spr_read_generic, &spr_write_generic,
3738                  0x00000000);
3739     /* XXX : not implemented */
3740     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3741                  SPR_NOACCESS, SPR_NOACCESS,
3742                  &spr_read_generic, &spr_write_generic,
3743                  0x00000000);
3744     /* XXX : not implemented */
3745     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3746                  SPR_NOACCESS, SPR_NOACCESS,
3747                  &spr_read_generic, &spr_write_generic,
3748                  0x00000000);
3749     /* XXX : not implemented */
3750     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3751                  SPR_NOACCESS, SPR_NOACCESS,
3752                  &spr_read_generic, &spr_write_generic,
3753                  0x00000000);
3754     /* XXX : not implemented */
3755     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3756                  SPR_NOACCESS, SPR_NOACCESS,
3757                  &spr_read_generic, &spr_write_generic,
3758                  0x00000000);
3759     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3760                  SPR_NOACCESS, SPR_NOACCESS,
3761                  &spr_read_generic, &spr_write_generic,
3762                  0x00000000);
3763     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3764                  SPR_NOACCESS, SPR_NOACCESS,
3765                  &spr_read_generic, &spr_write_generic,
3766                  0x00000000);
3767     /* XXX : not implemented */
3768     spr_register(env, SPR_440_CCR1, "CCR1",
3769                  SPR_NOACCESS, SPR_NOACCESS,
3770                  &spr_read_generic, &spr_write_generic,
3771                  0x00000000);
3772     /* XXX : not implemented */
3773     spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3774                  &spr_read_generic, &spr_write_generic,
3775                  &spr_read_generic, &spr_write_generic,
3776                  0x00000000);
3777     /* Memory management */
3778 #if !defined(CONFIG_USER_ONLY)
3779     env->nb_tlb = 64;
3780     env->nb_ways = 1;
3781     env->id_tlbs = 0;
3782 #endif
3783     init_excp_BookE(env);
3784     env->dcache_line_size = 32;
3785     env->icache_line_size = 32;
3786     /* XXX: TODO: allocate internal IRQ controller */
3787 }
3788
3789 /* PowerPC 460F (guessed)                                                    */
3790 #define POWERPC_INSNS_460F   (PPC_INSNS_BASE | PPC_STRING |                   \
3791                               PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |   \
3792                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
3793                               PPC_FLOAT_STFIWX | PPC_MFTB |                   \
3794                               PPC_DCR | PPC_DCRX | PPC_DCRUX |                \
3795                               PPC_WRTEE | PPC_MFAPIDI |                       \
3796                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3797                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3798                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3799                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3800                               PPC_440_SPEC)
3801 #define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3802 #define POWERPC_MMU_460F     (POWERPC_MMU_BOOKE)
3803 #define POWERPC_EXCP_460F    (POWERPC_EXCP_BOOKE)
3804 #define POWERPC_INPUT_460F   (PPC_FLAGS_INPUT_BookE)
3805 #define POWERPC_BFDM_460F    (bfd_mach_ppc_403)
3806 #define POWERPC_FLAG_460F    (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3807                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3808 #define check_pow_460F       check_pow_nocheck
3809
3810 __attribute__ (( unused ))
3811 static void init_proc_460F (CPUPPCState *env)
3812 {
3813     /* Time base */
3814     gen_tbl(env);
3815     gen_spr_BookE(env, 0x000000000000FFFFULL);
3816     gen_spr_440(env);
3817     gen_spr_usprgh(env);
3818     /* Processor identification */
3819     spr_register(env, SPR_BOOKE_PIR, "PIR",
3820                  SPR_NOACCESS, SPR_NOACCESS,
3821                  &spr_read_generic, &spr_write_pir,
3822                  0x00000000);
3823     /* XXX : not implemented */
3824     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3825                  SPR_NOACCESS, SPR_NOACCESS,
3826                  &spr_read_generic, &spr_write_generic,
3827                  0x00000000);
3828     /* XXX : not implemented */
3829     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3830                  SPR_NOACCESS, SPR_NOACCESS,
3831                  &spr_read_generic, &spr_write_generic,
3832                  0x00000000);
3833     /* XXX : not implemented */
3834     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3835                  SPR_NOACCESS, SPR_NOACCESS,
3836                  &spr_read_generic, &spr_write_generic,
3837                  0x00000000);
3838     /* XXX : not implemented */
3839     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3840                  SPR_NOACCESS, SPR_NOACCESS,
3841                  &spr_read_generic, &spr_write_generic,
3842                  0x00000000);
3843     /* XXX : not implemented */
3844     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3845                  SPR_NOACCESS, SPR_NOACCESS,
3846                  &spr_read_generic, &spr_write_generic,
3847                  0x00000000);
3848     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3849                  SPR_NOACCESS, SPR_NOACCESS,
3850                  &spr_read_generic, &spr_write_generic,
3851                  0x00000000);
3852     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3853                  SPR_NOACCESS, SPR_NOACCESS,
3854                  &spr_read_generic, &spr_write_generic,
3855                  0x00000000);
3856     /* XXX : not implemented */
3857     spr_register(env, SPR_440_CCR1, "CCR1",
3858                  SPR_NOACCESS, SPR_NOACCESS,
3859                  &spr_read_generic, &spr_write_generic,
3860                  0x00000000);
3861     /* XXX : not implemented */
3862     spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3863                  &spr_read_generic, &spr_write_generic,
3864                  &spr_read_generic, &spr_write_generic,
3865                  0x00000000);
3866     /* Memory management */
3867 #if !defined(CONFIG_USER_ONLY)
3868     env->nb_tlb = 64;
3869     env->nb_ways = 1;
3870     env->id_tlbs = 0;
3871 #endif
3872     init_excp_BookE(env);
3873     env->dcache_line_size = 32;
3874     env->icache_line_size = 32;
3875     /* XXX: TODO: allocate internal IRQ controller */
3876 }
3877
3878 /* Freescale 5xx cores (aka RCPU) */
3879 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING |                   \
3880                               PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
3881                               PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3882                               PPC_MFTB)
3883 #define POWERPC_MSRM_MPC5xx  (0x000000000001FF43ULL)
3884 #define POWERPC_MMU_MPC5xx   (POWERPC_MMU_REAL)
3885 #define POWERPC_EXCP_MPC5xx  (POWERPC_EXCP_603)
3886 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3887 #define POWERPC_BFDM_MPC5xx  (bfd_mach_ppc_505)
3888 #define POWERPC_FLAG_MPC5xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3889                               POWERPC_FLAG_BUS_CLK)
3890 #define check_pow_MPC5xx     check_pow_none
3891
3892 __attribute__ (( unused ))
3893 static void init_proc_MPC5xx (CPUPPCState *env)
3894 {
3895     /* Time base */
3896     gen_tbl(env);
3897     gen_spr_5xx_8xx(env);
3898     gen_spr_5xx(env);
3899     init_excp_MPC5xx(env);
3900     env->dcache_line_size = 32;
3901     env->icache_line_size = 32;
3902     /* XXX: TODO: allocate internal IRQ controller */
3903 }
3904
3905 /* Freescale 8xx cores (aka PowerQUICC) */
3906 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING  |                  \
3907                               PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
3908                               PPC_CACHE_ICBI | PPC_MFTB)
3909 #define POWERPC_MSRM_MPC8xx  (0x000000000001F673ULL)
3910 #define POWERPC_MMU_MPC8xx   (POWERPC_MMU_MPC8xx)
3911 #define POWERPC_EXCP_MPC8xx  (POWERPC_EXCP_603)
3912 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3913 #define POWERPC_BFDM_MPC8xx  (bfd_mach_ppc_860)
3914 #define POWERPC_FLAG_MPC8xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3915                               POWERPC_FLAG_BUS_CLK)
3916 #define check_pow_MPC8xx     check_pow_none
3917
3918 __attribute__ (( unused ))
3919 static void init_proc_MPC8xx (CPUPPCState *env)
3920 {
3921     /* Time base */
3922     gen_tbl(env);
3923     gen_spr_5xx_8xx(env);
3924     gen_spr_8xx(env);
3925     init_excp_MPC8xx(env);
3926     env->dcache_line_size = 32;
3927     env->icache_line_size = 32;
3928     /* XXX: TODO: allocate internal IRQ controller */
3929 }
3930
3931 /* Freescale 82xx cores (aka PowerQUICC-II)                                  */
3932 /* PowerPC G2                                                                */
3933 #define POWERPC_INSNS_G2     (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3934                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
3935                               PPC_FLOAT_STFIWX |                              \
3936                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
3937                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3938                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3939                               PPC_SEGMENT | PPC_EXTERN)
3940 #define POWERPC_MSRM_G2      (0x000000000006FFF2ULL)
3941 #define POWERPC_MMU_G2       (POWERPC_MMU_SOFT_6xx)
3942 //#define POWERPC_EXCP_G2      (POWERPC_EXCP_G2)
3943 #define POWERPC_INPUT_G2     (PPC_FLAGS_INPUT_6xx)
3944 #define POWERPC_BFDM_G2      (bfd_mach_ppc_ec603e)
3945 #define POWERPC_FLAG_G2      (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3946                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3947 #define check_pow_G2         check_pow_hid0
3948
3949 static void init_proc_G2 (CPUPPCState *env)
3950 {
3951     gen_spr_ne_601(env);
3952     gen_spr_G2_755(env);
3953     gen_spr_G2(env);
3954     /* Time base */
3955     gen_tbl(env);
3956     /* External access control */
3957     /* XXX : not implemented */
3958     spr_register(env, SPR_EAR, "EAR",
3959                  SPR_NOACCESS, SPR_NOACCESS,
3960                  &spr_read_generic, &spr_write_generic,
3961                  0x00000000);
3962     /* Hardware implementation register */
3963     /* XXX : not implemented */
3964     spr_register(env, SPR_HID0, "HID0",
3965                  SPR_NOACCESS, SPR_NOACCESS,
3966                  &spr_read_generic, &spr_write_generic,
3967                  0x00000000);
3968     /* XXX : not implemented */
3969     spr_register(env, SPR_HID1, "HID1",
3970                  SPR_NOACCESS, SPR_NOACCESS,
3971                  &spr_read_generic, &spr_write_generic,
3972                  0x00000000);
3973     /* XXX : not implemented */
3974     spr_register(env, SPR_HID2, "HID2",
3975                  SPR_NOACCESS, SPR_NOACCESS,
3976                  &spr_read_generic, &spr_write_generic,
3977                  0x00000000);
3978     /* Memory management */
3979     gen_low_BATs(env);
3980     gen_high_BATs(env);
3981     gen_6xx_7xx_soft_tlb(env, 64, 2);
3982     init_excp_G2(env);
3983     env->dcache_line_size = 32;
3984     env->icache_line_size = 32;
3985     /* Allocate hardware IRQ controller */
3986     ppc6xx_irq_init(env);
3987 }
3988
3989 /* PowerPC G2LE                                                              */
3990 #define POWERPC_INSNS_G2LE   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3991                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
3992                               PPC_FLOAT_STFIWX |                              \
3993                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
3994                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3995                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3996                               PPC_SEGMENT | PPC_EXTERN)
3997 #define POWERPC_MSRM_G2LE    (0x000000000007FFF3ULL)
3998 #define POWERPC_MMU_G2LE     (POWERPC_MMU_SOFT_6xx)
3999 #define POWERPC_EXCP_G2LE    (POWERPC_EXCP_G2)
4000 #define POWERPC_INPUT_G2LE   (PPC_FLAGS_INPUT_6xx)
4001 #define POWERPC_BFDM_G2LE    (bfd_mach_ppc_ec603e)
4002 #define POWERPC_FLAG_G2LE    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4003                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4004 #define check_pow_G2LE       check_pow_hid0
4005
4006 static void init_proc_G2LE (CPUPPCState *env)
4007 {
4008     gen_spr_ne_601(env);
4009     gen_spr_G2_755(env);
4010     gen_spr_G2(env);
4011     /* Time base */
4012     gen_tbl(env);
4013     /* External access control */
4014     /* XXX : not implemented */
4015     spr_register(env, SPR_EAR, "EAR",
4016                  SPR_NOACCESS, SPR_NOACCESS,
4017                  &spr_read_generic, &spr_write_generic,
4018                  0x00000000);
4019     /* Hardware implementation register */
4020     /* XXX : not implemented */
4021     spr_register(env, SPR_HID0, "HID0",
4022                  SPR_NOACCESS, SPR_NOACCESS,
4023                  &spr_read_generic, &spr_write_generic,
4024                  0x00000000);
4025     /* XXX : not implemented */
4026     spr_register(env, SPR_HID1, "HID1",
4027                  SPR_NOACCESS, SPR_NOACCESS,
4028                  &spr_read_generic, &spr_write_generic,
4029                  0x00000000);
4030     /* XXX : not implemented */
4031     spr_register(env, SPR_HID2, "HID2",
4032                  SPR_NOACCESS, SPR_NOACCESS,
4033                  &spr_read_generic, &spr_write_generic,
4034                  0x00000000);
4035     /* Memory management */
4036     gen_low_BATs(env);
4037     gen_high_BATs(env);
4038     gen_6xx_7xx_soft_tlb(env, 64, 2);
4039     init_excp_G2(env);
4040     env->dcache_line_size = 32;
4041     env->icache_line_size = 32;
4042     /* Allocate hardware IRQ controller */
4043     ppc6xx_irq_init(env);
4044 }
4045
4046 /* e200 core                                                                 */
4047 /* XXX: unimplemented instructions:
4048  * dcblc
4049  * dcbtlst
4050  * dcbtstls
4051  * icblc
4052  * icbtls
4053  * tlbivax
4054  * all SPE multiply-accumulate instructions
4055  */
4056 #define POWERPC_INSNS_e200   (PPC_INSNS_BASE | PPC_ISEL |                     \
4057                               PPC_SPE | PPC_SPE_SINGLE |                      \
4058                               PPC_WRTEE | PPC_RFDI |                          \
4059                               PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |   \
4060                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
4061                               PPC_MEM_TLBSYNC | PPC_TLBIVAX |                 \
4062                               PPC_BOOKE)
4063 #define POWERPC_MSRM_e200    (0x000000000606FF30ULL)
4064 #define POWERPC_MMU_e200     (POWERPC_MMU_BOOKE_FSL)
4065 #define POWERPC_EXCP_e200    (POWERPC_EXCP_BOOKE)
4066 #define POWERPC_INPUT_e200   (PPC_FLAGS_INPUT_BookE)
4067 #define POWERPC_BFDM_e200    (bfd_mach_ppc_860)
4068 #define POWERPC_FLAG_e200    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |            \
4069                               POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |           \
4070                               POWERPC_FLAG_BUS_CLK)
4071 #define check_pow_e200       check_pow_hid0
4072
4073 __attribute__ (( unused ))
4074 static void init_proc_e200 (CPUPPCState *env)
4075 {
4076     /* Time base */
4077     gen_tbl(env);
4078     gen_spr_BookE(env, 0x000000070000FFFFULL);
4079     /* XXX : not implemented */
4080     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4081                  &spr_read_spefscr, &spr_write_spefscr,
4082                  &spr_read_spefscr, &spr_write_spefscr,
4083                  0x00000000);
4084     /* Memory management */
4085     gen_spr_BookE_FSL(env, 0x0000005D);
4086     /* XXX : not implemented */
4087     spr_register(env, SPR_HID0, "HID0",
4088                  SPR_NOACCESS, SPR_NOACCESS,
4089                  &spr_read_generic, &spr_write_generic,
4090                  0x00000000);
4091     /* XXX : not implemented */
4092     spr_register(env, SPR_HID1, "HID1",
4093                  SPR_NOACCESS, SPR_NOACCESS,
4094                  &spr_read_generic, &spr_write_generic,
4095                  0x00000000);
4096     /* XXX : not implemented */
4097     spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4098                  SPR_NOACCESS, SPR_NOACCESS,
4099                  &spr_read_generic, &spr_write_generic,
4100                  0x00000000);
4101     /* XXX : not implemented */
4102     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4103                  SPR_NOACCESS, SPR_NOACCESS,
4104                  &spr_read_generic, &spr_write_generic,
4105                  0x00000000);
4106     /* XXX : not implemented */
4107     spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4108                  SPR_NOACCESS, SPR_NOACCESS,
4109                  &spr_read_generic, &spr_write_generic,
4110                  0x00000000);
4111     /* XXX : not implemented */
4112     spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4113                  SPR_NOACCESS, SPR_NOACCESS,
4114                  &spr_read_generic, &spr_write_generic,
4115                  0x00000000);
4116     /* XXX : not implemented */
4117     spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4118                  SPR_NOACCESS, SPR_NOACCESS,
4119                  &spr_read_generic, &spr_write_generic,
4120                  0x00000000);
4121     /* XXX : not implemented */
4122     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4123                  SPR_NOACCESS, SPR_NOACCESS,
4124                  &spr_read_generic, &spr_write_generic,
4125                  0x00000000);
4126     /* XXX : not implemented */
4127     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4128                  SPR_NOACCESS, SPR_NOACCESS,
4129                  &spr_read_generic, &spr_write_generic,
4130                  0x00000000);
4131     /* XXX : not implemented */
4132     spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4133                  SPR_NOACCESS, SPR_NOACCESS,
4134                  &spr_read_generic, &spr_write_generic,
4135                  0x00000000);
4136     /* XXX : not implemented */
4137     spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4138                  SPR_NOACCESS, SPR_NOACCESS,
4139                  &spr_read_generic, &spr_write_generic,
4140                  0x00000000);
4141     /* XXX : not implemented */
4142     spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4143                  SPR_NOACCESS, SPR_NOACCESS,
4144                  &spr_read_generic, &spr_write_generic,
4145                  0x00000000);
4146     /* XXX : not implemented */
4147     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4148                  SPR_NOACCESS, SPR_NOACCESS,
4149                  &spr_read_generic, &spr_write_generic,
4150                  0x00000000);
4151     /* XXX : not implemented */
4152     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4153                  SPR_NOACCESS, SPR_NOACCESS,
4154                  &spr_read_generic, &spr_write_generic,
4155                  0x00000000);
4156     spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4157                  SPR_NOACCESS, SPR_NOACCESS,
4158                  &spr_read_generic, &spr_write_generic,
4159                  0x00000000);
4160     spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4161                  SPR_NOACCESS, SPR_NOACCESS,
4162                  &spr_read_generic, &spr_write_generic,
4163                  0x00000000);
4164 #if !defined(CONFIG_USER_ONLY)
4165     env->nb_tlb = 64;
4166     env->nb_ways = 1;
4167     env->id_tlbs = 0;
4168 #endif
4169     init_excp_e200(env);
4170     env->dcache_line_size = 32;
4171     env->icache_line_size = 32;
4172     /* XXX: TODO: allocate internal IRQ controller */
4173 }
4174
4175 /* e300 core                                                                 */
4176 #define POWERPC_INSNS_e300   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4177                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4178                               PPC_FLOAT_STFIWX |                              \
4179                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4180                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4181                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4182                               PPC_SEGMENT | PPC_EXTERN)
4183 #define POWERPC_MSRM_e300    (0x000000000007FFF3ULL)
4184 #define POWERPC_MMU_e300     (POWERPC_MMU_SOFT_6xx)
4185 #define POWERPC_EXCP_e300    (POWERPC_EXCP_603)
4186 #define POWERPC_INPUT_e300   (PPC_FLAGS_INPUT_6xx)
4187 #define POWERPC_BFDM_e300    (bfd_mach_ppc_603)
4188 #define POWERPC_FLAG_e300    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4189                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4190 #define check_pow_e300       check_pow_hid0
4191
4192 __attribute__ (( unused ))
4193 static void init_proc_e300 (CPUPPCState *env)
4194 {
4195     gen_spr_ne_601(env);
4196     gen_spr_603(env);
4197     /* Time base */
4198     gen_tbl(env);
4199     /* hardware implementation registers */
4200     /* XXX : not implemented */
4201     spr_register(env, SPR_HID0, "HID0",
4202                  SPR_NOACCESS, SPR_NOACCESS,
4203                  &spr_read_generic, &spr_write_generic,
4204                  0x00000000);
4205     /* XXX : not implemented */
4206     spr_register(env, SPR_HID1, "HID1",
4207                  SPR_NOACCESS, SPR_NOACCESS,
4208                  &spr_read_generic, &spr_write_generic,
4209                  0x00000000);
4210     /* XXX : not implemented */
4211     spr_register(env, SPR_HID2, "HID2",
4212                  SPR_NOACCESS, SPR_NOACCESS,
4213                  &spr_read_generic, &spr_write_generic,
4214                  0x00000000);
4215     /* Memory management */
4216     gen_low_BATs(env);
4217     gen_high_BATs(env);
4218     gen_6xx_7xx_soft_tlb(env, 64, 2);
4219     init_excp_603(env);
4220     env->dcache_line_size = 32;
4221     env->icache_line_size = 32;
4222     /* Allocate hardware IRQ controller */
4223     ppc6xx_irq_init(env);
4224 }
4225
4226 /* e500v1 core                                                               */
4227 #define POWERPC_INSNS_e500v1   (PPC_INSNS_BASE | PPC_ISEL |             \
4228                                 PPC_SPE | PPC_SPE_SINGLE |              \
4229                                 PPC_WRTEE | PPC_RFDI |                  \
4230                                 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4231                                 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |       \
4232                                 PPC_MEM_TLBSYNC | PPC_TLBIVAX |         \
4233                                 PPC_BOOKE)
4234 #define POWERPC_MSRM_e500v1    (0x000000000606FF30ULL)
4235 #define POWERPC_MMU_e500v1     (POWERPC_MMU_BOOKE_FSL)
4236 #define POWERPC_EXCP_e500v1    (POWERPC_EXCP_BOOKE)
4237 #define POWERPC_INPUT_e500v1   (PPC_FLAGS_INPUT_BookE)
4238 #define POWERPC_BFDM_e500v1    (bfd_mach_ppc_860)
4239 #define POWERPC_FLAG_e500v1    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |    \
4240                                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |   \
4241                                 POWERPC_FLAG_BUS_CLK)
4242 #define check_pow_e500v1       check_pow_hid0
4243 #define init_proc_e500v1       init_proc_e500
4244
4245 /* e500v2 core                                                               */
4246 #define POWERPC_INSNS_e500v2   (PPC_INSNS_BASE | PPC_ISEL |             \
4247                                 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |   \
4248                                 PPC_WRTEE | PPC_RFDI |                  \
4249                                 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4250                                 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |       \
4251                                 PPC_MEM_TLBSYNC | PPC_TLBIVAX |         \
4252                                 PPC_BOOKE)
4253 #define POWERPC_MSRM_e500v2    (0x000000000606FF30ULL)
4254 #define POWERPC_MMU_e500v2     (POWERPC_MMU_BOOKE_FSL)
4255 #define POWERPC_EXCP_e500v2    (POWERPC_EXCP_BOOKE)
4256 #define POWERPC_INPUT_e500v2   (PPC_FLAGS_INPUT_BookE)
4257 #define POWERPC_BFDM_e500v2    (bfd_mach_ppc_860)
4258 #define POWERPC_FLAG_e500v2    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |    \
4259                                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |   \
4260                                 POWERPC_FLAG_BUS_CLK)
4261 #define check_pow_e500v2       check_pow_hid0
4262 #define init_proc_e500v2       init_proc_e500
4263
4264 static void init_proc_e500 (CPUPPCState *env)
4265 {
4266     /* Time base */
4267     gen_tbl(env);
4268     gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4269     /* Processor identification */
4270     spr_register(env, SPR_BOOKE_PIR, "PIR",
4271                  SPR_NOACCESS, SPR_NOACCESS,
4272                  &spr_read_generic, &spr_write_pir,
4273                  0x00000000);
4274     /* XXX : not implemented */
4275     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4276                  &spr_read_spefscr, &spr_write_spefscr,
4277                  &spr_read_spefscr, &spr_write_spefscr,
4278                  0x00000000);
4279     /* Memory management */
4280 #if !defined(CONFIG_USER_ONLY)
4281     env->nb_pids = 3;
4282 #endif
4283     gen_spr_BookE_FSL(env, 0x0000005F);
4284     /* XXX : not implemented */
4285     spr_register(env, SPR_HID0, "HID0",
4286                  SPR_NOACCESS, SPR_NOACCESS,
4287                  &spr_read_generic, &spr_write_generic,
4288                  0x00000000);
4289     /* XXX : not implemented */
4290     spr_register(env, SPR_HID1, "HID1",
4291                  SPR_NOACCESS, SPR_NOACCESS,
4292                  &spr_read_generic, &spr_write_generic,
4293                  0x00000000);
4294     /* XXX : not implemented */
4295     spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4296                  SPR_NOACCESS, SPR_NOACCESS,
4297                  &spr_read_generic, &spr_write_generic,
4298                  0x00000000);
4299     /* XXX : not implemented */
4300     spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4301                  SPR_NOACCESS, SPR_NOACCESS,
4302                  &spr_read_generic, &spr_write_generic,
4303                  0x00000000);
4304     /* XXX : not implemented */
4305     spr_register(env, SPR_Exxx_MCAR, "MCAR",
4306                  SPR_NOACCESS, SPR_NOACCESS,
4307                  &spr_read_generic, &spr_write_generic,
4308                  0x00000000);
4309     /* XXX : not implemented */
4310     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4311                  SPR_NOACCESS, SPR_NOACCESS,
4312                  &spr_read_generic, &spr_write_generic,
4313                  0x00000000);
4314     /* XXX : not implemented */
4315     spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4316                  SPR_NOACCESS, SPR_NOACCESS,
4317                  &spr_read_generic, &spr_write_generic,
4318                  0x00000000);
4319     /* XXX : not implemented */
4320     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4321                  SPR_NOACCESS, SPR_NOACCESS,
4322                  &spr_read_generic, &spr_write_generic,
4323                  0x00000000);
4324     /* XXX : not implemented */
4325     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4326                  SPR_NOACCESS, SPR_NOACCESS,
4327                  &spr_read_generic, &spr_write_generic,
4328                  0x00000000);
4329     /* XXX : not implemented */
4330     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4331                  SPR_NOACCESS, SPR_NOACCESS,
4332                  &spr_read_generic, &spr_write_generic,
4333                  0x00000000);
4334     /* XXX : not implemented */
4335     spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4336                  SPR_NOACCESS, SPR_NOACCESS,
4337                  &spr_read_generic, &spr_write_generic,
4338                  0x00000000);
4339     /* XXX : not implemented */
4340     spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4341                  SPR_NOACCESS, SPR_NOACCESS,
4342                  &spr_read_generic, &spr_write_generic,
4343                  0x00000000);
4344     /* XXX : not implemented */
4345     spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4346                  SPR_NOACCESS, SPR_NOACCESS,
4347                  &spr_read_generic, &spr_write_generic,
4348                  0x00000000);
4349     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4350                  SPR_NOACCESS, SPR_NOACCESS,
4351                  &spr_read_generic, &spr_write_generic,
4352                  0x00000000);
4353     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4354                  SPR_NOACCESS, SPR_NOACCESS,
4355                  &spr_read_generic, &spr_write_generic,
4356                  0x00000000);
4357 #if !defined(CONFIG_USER_ONLY)
4358     env->nb_tlb = 64;
4359     env->nb_ways = 1;
4360     env->id_tlbs = 0;
4361 #endif
4362     init_excp_e200(env);
4363     env->dcache_line_size = 32;
4364     env->icache_line_size = 32;
4365     /* Allocate hardware IRQ controller */
4366     ppce500_irq_init(env);
4367 }
4368
4369 /* Non-embedded PowerPC                                                      */
4370
4371 /* POWER : same as 601, without mfmsr, mfsr                                  */
4372 #if defined(TODO)
4373 #define POWERPC_INSNS_POWER  (XXX_TODO)
4374 /* POWER RSC (from RAD6000) */
4375 #define POWERPC_MSRM_POWER   (0x00000000FEF0ULL)
4376 #endif /* TODO */
4377
4378 /* PowerPC 601                                                               */
4379 #define POWERPC_INSNS_601    (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
4380                               PPC_FLOAT |                                     \
4381                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4382                               PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
4383                               PPC_SEGMENT | PPC_EXTERN)
4384 #define POWERPC_MSRM_601     (0x000000000000FD70ULL)
4385 #define POWERPC_MSRR_601     (0x0000000000001040ULL)
4386 //#define POWERPC_MMU_601      (POWERPC_MMU_601)
4387 //#define POWERPC_EXCP_601     (POWERPC_EXCP_601)
4388 #define POWERPC_INPUT_601    (PPC_FLAGS_INPUT_6xx)
4389 #define POWERPC_BFDM_601     (bfd_mach_ppc_601)
4390 #define POWERPC_FLAG_601     (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4391 #define check_pow_601        check_pow_none
4392
4393 static void init_proc_601 (CPUPPCState *env)
4394 {
4395     gen_spr_ne_601(env);
4396     gen_spr_601(env);
4397     /* Hardware implementation registers */
4398     /* XXX : not implemented */
4399     spr_register(env, SPR_HID0, "HID0",
4400                  SPR_NOACCESS, SPR_NOACCESS,
4401                  &spr_read_generic, &spr_write_hid0_601,
4402                  0x80010080);
4403     /* XXX : not implemented */
4404     spr_register(env, SPR_HID1, "HID1",
4405                  SPR_NOACCESS, SPR_NOACCESS,
4406                  &spr_read_generic, &spr_write_generic,
4407                  0x00000000);
4408     /* XXX : not implemented */
4409     spr_register(env, SPR_601_HID2, "HID2",
4410                  SPR_NOACCESS, SPR_NOACCESS,
4411                  &spr_read_generic, &spr_write_generic,
4412                  0x00000000);
4413     /* XXX : not implemented */
4414     spr_register(env, SPR_601_HID5, "HID5",
4415                  SPR_NOACCESS, SPR_NOACCESS,
4416                  &spr_read_generic, &spr_write_generic,
4417                  0x00000000);
4418     /* Memory management */
4419     init_excp_601(env);
4420     /* XXX: beware that dcache line size is 64
4421      *      but dcbz uses 32 bytes "sectors"
4422      * XXX: this breaks clcs instruction !
4423      */
4424     env->dcache_line_size = 32;
4425     env->icache_line_size = 64;
4426     /* Allocate hardware IRQ controller */
4427     ppc6xx_irq_init(env);
4428 }
4429
4430 /* PowerPC 601v                                                              */
4431 #define POWERPC_INSNS_601v   (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
4432                               PPC_FLOAT |                                     \
4433                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4434                               PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
4435                               PPC_SEGMENT | PPC_EXTERN)
4436 #define POWERPC_MSRM_601v    (0x000000000000FD70ULL)
4437 #define POWERPC_MSRR_601v    (0x0000000000001040ULL)
4438 #define POWERPC_MMU_601v     (POWERPC_MMU_601)
4439 #define POWERPC_EXCP_601v    (POWERPC_EXCP_601)
4440 #define POWERPC_INPUT_601v   (PPC_FLAGS_INPUT_6xx)
4441 #define POWERPC_BFDM_601v    (bfd_mach_ppc_601)
4442 #define POWERPC_FLAG_601v    (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4443 #define check_pow_601v       check_pow_none
4444
4445 static void init_proc_601v (CPUPPCState *env)
4446 {
4447     init_proc_601(env);
4448     /* XXX : not implemented */
4449     spr_register(env, SPR_601_HID15, "HID15",
4450                  SPR_NOACCESS, SPR_NOACCESS,
4451                  &spr_read_generic, &spr_write_generic,
4452                  0x00000000);
4453 }
4454
4455 /* PowerPC 602                                                               */
4456 #define POWERPC_INSNS_602    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4457                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4458                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4459                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4460                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4461                               PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4462                               PPC_SEGMENT | PPC_602_SPEC)
4463 #define POWERPC_MSRM_602     (0x0000000000C7FF73ULL)
4464 /* XXX: 602 MMU is quite specific. Should add a special case */
4465 #define POWERPC_MMU_602      (POWERPC_MMU_SOFT_6xx)
4466 //#define POWERPC_EXCP_602     (POWERPC_EXCP_602)
4467 #define POWERPC_INPUT_602    (PPC_FLAGS_INPUT_6xx)
4468 #define POWERPC_BFDM_602     (bfd_mach_ppc_602)
4469 #define POWERPC_FLAG_602     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4470                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4471 #define check_pow_602        check_pow_hid0
4472
4473 static void init_proc_602 (CPUPPCState *env)
4474 {
4475     gen_spr_ne_601(env);
4476     gen_spr_602(env);
4477     /* Time base */
4478     gen_tbl(env);
4479     /* hardware implementation registers */
4480     /* XXX : not implemented */
4481     spr_register(env, SPR_HID0, "HID0",
4482                  SPR_NOACCESS, SPR_NOACCESS,
4483                  &spr_read_generic, &spr_write_generic,
4484                  0x00000000);
4485     /* XXX : not implemented */
4486     spr_register(env, SPR_HID1, "HID1",
4487                  SPR_NOACCESS, SPR_NOACCESS,
4488                  &spr_read_generic, &spr_write_generic,
4489                  0x00000000);
4490     /* Memory management */
4491     gen_low_BATs(env);
4492     gen_6xx_7xx_soft_tlb(env, 64, 2);
4493     init_excp_602(env);
4494     env->dcache_line_size = 32;
4495     env->icache_line_size = 32;
4496     /* Allocate hardware IRQ controller */
4497     ppc6xx_irq_init(env);
4498 }
4499
4500 /* PowerPC 603                                                               */
4501 #define POWERPC_INSNS_603    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4502                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4503                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4504                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4505                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4506                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4507                               PPC_SEGMENT | PPC_EXTERN)
4508 #define POWERPC_MSRM_603     (0x000000000007FF73ULL)
4509 #define POWERPC_MMU_603      (POWERPC_MMU_SOFT_6xx)
4510 //#define POWERPC_EXCP_603     (POWERPC_EXCP_603)
4511 #define POWERPC_INPUT_603    (PPC_FLAGS_INPUT_6xx)
4512 #define POWERPC_BFDM_603     (bfd_mach_ppc_603)
4513 #define POWERPC_FLAG_603     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4514                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4515 #define check_pow_603        check_pow_hid0
4516
4517 static void init_proc_603 (CPUPPCState *env)
4518 {
4519     gen_spr_ne_601(env);
4520     gen_spr_603(env);
4521     /* Time base */
4522     gen_tbl(env);
4523     /* hardware implementation registers */
4524     /* XXX : not implemented */
4525     spr_register(env, SPR_HID0, "HID0",
4526                  SPR_NOACCESS, SPR_NOACCESS,
4527                  &spr_read_generic, &spr_write_generic,
4528                  0x00000000);
4529     /* XXX : not implemented */
4530     spr_register(env, SPR_HID1, "HID1",
4531                  SPR_NOACCESS, SPR_NOACCESS,
4532                  &spr_read_generic, &spr_write_generic,
4533                  0x00000000);
4534     /* Memory management */
4535     gen_low_BATs(env);
4536     gen_6xx_7xx_soft_tlb(env, 64, 2);
4537     init_excp_603(env);
4538     env->dcache_line_size = 32;
4539     env->icache_line_size = 32;
4540     /* Allocate hardware IRQ controller */
4541     ppc6xx_irq_init(env);
4542 }
4543
4544 /* PowerPC 603e                                                              */
4545 #define POWERPC_INSNS_603E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4546                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4547                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4548                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4549                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4550                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4551                               PPC_SEGMENT | PPC_EXTERN)
4552 #define POWERPC_MSRM_603E    (0x000000000007FF73ULL)
4553 #define POWERPC_MMU_603E     (POWERPC_MMU_SOFT_6xx)
4554 //#define POWERPC_EXCP_603E    (POWERPC_EXCP_603E)
4555 #define POWERPC_INPUT_603E   (PPC_FLAGS_INPUT_6xx)
4556 #define POWERPC_BFDM_603E    (bfd_mach_ppc_ec603e)
4557 #define POWERPC_FLAG_603E    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4558                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4559 #define check_pow_603E       check_pow_hid0
4560
4561 static void init_proc_603E (CPUPPCState *env)
4562 {
4563     gen_spr_ne_601(env);
4564     gen_spr_603(env);
4565     /* Time base */
4566     gen_tbl(env);
4567     /* hardware implementation registers */
4568     /* XXX : not implemented */
4569     spr_register(env, SPR_HID0, "HID0",
4570                  SPR_NOACCESS, SPR_NOACCESS,
4571                  &spr_read_generic, &spr_write_generic,
4572                  0x00000000);
4573     /* XXX : not implemented */
4574     spr_register(env, SPR_HID1, "HID1",
4575                  SPR_NOACCESS, SPR_NOACCESS,
4576                  &spr_read_generic, &spr_write_generic,
4577                  0x00000000);
4578     /* XXX : not implemented */
4579     spr_register(env, SPR_IABR, "IABR",
4580                  SPR_NOACCESS, SPR_NOACCESS,
4581                  &spr_read_generic, &spr_write_generic,
4582                  0x00000000);
4583     /* Memory management */
4584     gen_low_BATs(env);
4585     gen_6xx_7xx_soft_tlb(env, 64, 2);
4586     init_excp_603(env);
4587     env->dcache_line_size = 32;
4588     env->icache_line_size = 32;
4589     /* Allocate hardware IRQ controller */
4590     ppc6xx_irq_init(env);
4591 }
4592
4593 /* PowerPC 604                                                               */
4594 #define POWERPC_INSNS_604    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4595                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4596                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4597                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4598                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4599                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4600                               PPC_SEGMENT | PPC_EXTERN)
4601 #define POWERPC_MSRM_604     (0x000000000005FF77ULL)
4602 #define POWERPC_MMU_604      (POWERPC_MMU_32B)
4603 //#define POWERPC_EXCP_604     (POWERPC_EXCP_604)
4604 #define POWERPC_INPUT_604    (PPC_FLAGS_INPUT_6xx)
4605 #define POWERPC_BFDM_604     (bfd_mach_ppc_604)
4606 #define POWERPC_FLAG_604     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4607                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4608 #define check_pow_604        check_pow_nocheck
4609
4610 static void init_proc_604 (CPUPPCState *env)
4611 {
4612     gen_spr_ne_601(env);
4613     gen_spr_604(env);
4614     /* Time base */
4615     gen_tbl(env);
4616     /* Hardware implementation registers */
4617     /* XXX : not implemented */
4618     spr_register(env, SPR_HID0, "HID0",
4619                  SPR_NOACCESS, SPR_NOACCESS,
4620                  &spr_read_generic, &spr_write_generic,
4621                  0x00000000);
4622     /* Memory management */
4623     gen_low_BATs(env);
4624     init_excp_604(env);
4625     env->dcache_line_size = 32;
4626     env->icache_line_size = 32;
4627     /* Allocate hardware IRQ controller */
4628     ppc6xx_irq_init(env);
4629 }
4630
4631 /* PowerPC 604E                                                              */
4632 #define POWERPC_INSNS_604E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4633                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4634                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4635                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4636                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4637                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4638                               PPC_SEGMENT | PPC_EXTERN)
4639 #define POWERPC_MSRM_604E    (0x000000000005FF77ULL)
4640 #define POWERPC_MMU_604E     (POWERPC_MMU_32B)
4641 #define POWERPC_EXCP_604E    (POWERPC_EXCP_604)
4642 #define POWERPC_INPUT_604E   (PPC_FLAGS_INPUT_6xx)
4643 #define POWERPC_BFDM_604E    (bfd_mach_ppc_604)
4644 #define POWERPC_FLAG_604E    (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4645                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4646 #define check_pow_604E       check_pow_nocheck
4647
4648 static void init_proc_604E (CPUPPCState *env)
4649 {
4650     gen_spr_ne_601(env);
4651     gen_spr_604(env);
4652     /* XXX : not implemented */
4653     spr_register(env, SPR_MMCR1, "MMCR1",
4654                  SPR_NOACCESS, SPR_NOACCESS,
4655                  &spr_read_generic, &spr_write_generic,
4656                  0x00000000);
4657     /* XXX : not implemented */
4658     spr_register(env, SPR_PMC3, "PMC3",
4659                  SPR_NOACCESS, SPR_NOACCESS,
4660                  &spr_read_generic, &spr_write_generic,
4661                  0x00000000);
4662     /* XXX : not implemented */
4663     spr_register(env, SPR_PMC4, "PMC4",
4664                  SPR_NOACCESS, SPR_NOACCESS,
4665                  &spr_read_generic, &spr_write_generic,
4666                  0x00000000);
4667     /* Time base */
4668     gen_tbl(env);
4669     /* Hardware implementation registers */
4670     /* XXX : not implemented */
4671     spr_register(env, SPR_HID0, "HID0",
4672                  SPR_NOACCESS, SPR_NOACCESS,
4673                  &spr_read_generic, &spr_write_generic,
4674                  0x00000000);
4675     /* XXX : not implemented */
4676     spr_register(env, SPR_HID1, "HID1",
4677                  SPR_NOACCESS, SPR_NOACCESS,
4678                  &spr_read_generic, &spr_write_generic,
4679                  0x00000000);
4680     /* Memory management */
4681     gen_low_BATs(env);
4682     init_excp_604(env);
4683     env->dcache_line_size = 32;
4684     env->icache_line_size = 32;
4685     /* Allocate hardware IRQ controller */
4686     ppc6xx_irq_init(env);
4687 }
4688
4689 /* PowerPC 740                                                               */
4690 #define POWERPC_INSNS_740    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4691                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4692                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4693                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4694                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4695                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4696                               PPC_SEGMENT | PPC_EXTERN)
4697 #define POWERPC_MSRM_740     (0x000000000005FF77ULL)
4698 #define POWERPC_MMU_740      (POWERPC_MMU_32B)
4699 #define POWERPC_EXCP_740     (POWERPC_EXCP_7x0)
4700 #define POWERPC_INPUT_740    (PPC_FLAGS_INPUT_6xx)
4701 #define POWERPC_BFDM_740     (bfd_mach_ppc_750)
4702 #define POWERPC_FLAG_740     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4703                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4704 #define check_pow_740        check_pow_hid0
4705
4706 static void init_proc_740 (CPUPPCState *env)
4707 {
4708     gen_spr_ne_601(env);
4709     gen_spr_7xx(env);
4710     /* Time base */
4711     gen_tbl(env);
4712     /* Thermal management */
4713     gen_spr_thrm(env);
4714     /* Hardware implementation registers */
4715     /* XXX : not implemented */
4716     spr_register(env, SPR_HID0, "HID0",
4717                  SPR_NOACCESS, SPR_NOACCESS,
4718                  &spr_read_generic, &spr_write_generic,
4719                  0x00000000);
4720     /* XXX : not implemented */
4721     spr_register(env, SPR_HID1, "HID1",
4722                  SPR_NOACCESS, SPR_NOACCESS,
4723                  &spr_read_generic, &spr_write_generic,
4724                  0x00000000);
4725     /* Memory management */
4726     gen_low_BATs(env);
4727     init_excp_7x0(env);
4728     env->dcache_line_size = 32;
4729     env->icache_line_size = 32;
4730     /* Allocate hardware IRQ controller */
4731     ppc6xx_irq_init(env);
4732 }
4733
4734 /* PowerPC 750                                                               */
4735 #define POWERPC_INSNS_750    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4736                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4737                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4738                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4739                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4740                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4741                               PPC_SEGMENT | PPC_EXTERN)
4742 #define POWERPC_MSRM_750     (0x000000000005FF77ULL)
4743 #define POWERPC_MMU_750      (POWERPC_MMU_32B)
4744 #define POWERPC_EXCP_750     (POWERPC_EXCP_7x0)
4745 #define POWERPC_INPUT_750    (PPC_FLAGS_INPUT_6xx)
4746 #define POWERPC_BFDM_750     (bfd_mach_ppc_750)
4747 #define POWERPC_FLAG_750     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4748                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4749 #define check_pow_750        check_pow_hid0
4750
4751 static void init_proc_750 (CPUPPCState *env)
4752 {
4753     gen_spr_ne_601(env);
4754     gen_spr_7xx(env);
4755     /* XXX : not implemented */
4756     spr_register(env, SPR_L2CR, "L2CR",
4757                  SPR_NOACCESS, SPR_NOACCESS,
4758                  &spr_read_generic, &spr_write_generic,
4759                  0x00000000);
4760     /* Time base */
4761     gen_tbl(env);
4762     /* Thermal management */
4763     gen_spr_thrm(env);
4764     /* Hardware implementation registers */
4765     /* XXX : not implemented */
4766     spr_register(env, SPR_HID0, "HID0",
4767                  SPR_NOACCESS, SPR_NOACCESS,
4768                  &spr_read_generic, &spr_write_generic,
4769                  0x00000000);
4770     /* XXX : not implemented */
4771     spr_register(env, SPR_HID1, "HID1",
4772                  SPR_NOACCESS, SPR_NOACCESS,
4773                  &spr_read_generic, &spr_write_generic,
4774                  0x00000000);
4775     /* Memory management */
4776     gen_low_BATs(env);
4777     /* XXX: high BATs are also present but are known to be bugged on
4778      *      die version 1.x
4779      */
4780     init_excp_7x0(env);
4781     env->dcache_line_size = 32;
4782     env->icache_line_size = 32;
4783     /* Allocate hardware IRQ controller */
4784     ppc6xx_irq_init(env);
4785 }
4786
4787 /* PowerPC 750 CL                                                            */
4788 /* XXX: not implemented:
4789  * cache lock instructions:
4790  * dcbz_l
4791  * floating point paired instructions
4792  * psq_lux
4793  * psq_lx
4794  * psq_stux
4795  * psq_stx
4796  * ps_abs
4797  * ps_add
4798  * ps_cmpo0
4799  * ps_cmpo1
4800  * ps_cmpu0
4801  * ps_cmpu1
4802  * ps_div
4803  * ps_madd
4804  * ps_madds0
4805  * ps_madds1
4806  * ps_merge00
4807  * ps_merge01
4808  * ps_merge10
4809  * ps_merge11
4810  * ps_mr
4811  * ps_msub
4812  * ps_mul
4813  * ps_muls0
4814  * ps_muls1
4815  * ps_nabs
4816  * ps_neg
4817  * ps_nmadd
4818  * ps_nmsub
4819  * ps_res
4820  * ps_rsqrte
4821  * ps_sel
4822  * ps_sub
4823  * ps_sum0
4824  * ps_sum1
4825  */
4826 #define POWERPC_INSNS_750cl  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4827                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4828                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4829                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4830                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4831                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4832                               PPC_SEGMENT | PPC_EXTERN)
4833 #define POWERPC_MSRM_750cl   (0x000000000005FF77ULL)
4834 #define POWERPC_MMU_750cl    (POWERPC_MMU_32B)
4835 #define POWERPC_EXCP_750cl   (POWERPC_EXCP_7x0)
4836 #define POWERPC_INPUT_750cl  (PPC_FLAGS_INPUT_6xx)
4837 #define POWERPC_BFDM_750cl   (bfd_mach_ppc_750)
4838 #define POWERPC_FLAG_750cl   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4839                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4840 #define check_pow_750cl      check_pow_hid0
4841
4842 static void init_proc_750cl (CPUPPCState *env)
4843 {
4844     gen_spr_ne_601(env);
4845     gen_spr_7xx(env);
4846     /* XXX : not implemented */
4847     spr_register(env, SPR_L2CR, "L2CR",
4848                  SPR_NOACCESS, SPR_NOACCESS,
4849                  &spr_read_generic, &spr_write_generic,
4850                  0x00000000);
4851     /* Time base */
4852     gen_tbl(env);
4853     /* Thermal management */
4854     /* Those registers are fake on 750CL */
4855     spr_register(env, SPR_THRM1, "THRM1",
4856                  SPR_NOACCESS, SPR_NOACCESS,
4857                  &spr_read_generic, &spr_write_generic,
4858                  0x00000000);
4859     spr_register(env, SPR_THRM2, "THRM2",
4860                  SPR_NOACCESS, SPR_NOACCESS,
4861                  &spr_read_generic, &spr_write_generic,
4862                  0x00000000);
4863     spr_register(env, SPR_THRM3, "THRM3",
4864                  SPR_NOACCESS, SPR_NOACCESS,
4865                  &spr_read_generic, &spr_write_generic,
4866                  0x00000000);
4867     /* XXX: not implemented */
4868     spr_register(env, SPR_750_TDCL, "TDCL",
4869                  SPR_NOACCESS, SPR_NOACCESS,
4870                  &spr_read_generic, &spr_write_generic,
4871                  0x00000000);
4872     spr_register(env, SPR_750_TDCH, "TDCH",
4873                  SPR_NOACCESS, SPR_NOACCESS,
4874                  &spr_read_generic, &spr_write_generic,
4875                  0x00000000);
4876     /* DMA */
4877     /* XXX : not implemented */
4878     spr_register(env, SPR_750_WPAR, "WPAR",
4879                  SPR_NOACCESS, SPR_NOACCESS,
4880                  &spr_read_generic, &spr_write_generic,
4881                  0x00000000);
4882     spr_register(env, SPR_750_DMAL, "DMAL",
4883                  SPR_NOACCESS, SPR_NOACCESS,
4884                  &spr_read_generic, &spr_write_generic,
4885                  0x00000000);
4886     spr_register(env, SPR_750_DMAU, "DMAU",
4887                  SPR_NOACCESS, SPR_NOACCESS,
4888                  &spr_read_generic, &spr_write_generic,
4889                  0x00000000);
4890     /* Hardware implementation registers */
4891     /* XXX : not implemented */
4892     spr_register(env, SPR_HID0, "HID0",
4893                  SPR_NOACCESS, SPR_NOACCESS,
4894                  &spr_read_generic, &spr_write_generic,
4895                  0x00000000);
4896     /* XXX : not implemented */
4897     spr_register(env, SPR_HID1, "HID1",
4898                  SPR_NOACCESS, SPR_NOACCESS,
4899                  &spr_read_generic, &spr_write_generic,
4900                  0x00000000);
4901     /* XXX : not implemented */
4902     spr_register(env, SPR_750CL_HID2, "HID2",
4903                  SPR_NOACCESS, SPR_NOACCESS,
4904                  &spr_read_generic, &spr_write_generic,
4905                  0x00000000);
4906     /* XXX : not implemented */
4907     spr_register(env, SPR_750CL_HID4, "HID4",
4908                  SPR_NOACCESS, SPR_NOACCESS,
4909                  &spr_read_generic, &spr_write_generic,
4910                  0x00000000);
4911     /* Quantization registers */
4912     /* XXX : not implemented */
4913     spr_register(env, SPR_750_GQR0, "GQR0",
4914                  SPR_NOACCESS, SPR_NOACCESS,
4915                  &spr_read_generic, &spr_write_generic,
4916                  0x00000000);
4917     /* XXX : not implemented */
4918     spr_register(env, SPR_750_GQR1, "GQR1",
4919                  SPR_NOACCESS, SPR_NOACCESS,
4920                  &spr_read_generic, &spr_write_generic,
4921                  0x00000000);
4922     /* XXX : not implemented */
4923     spr_register(env, SPR_750_GQR2, "GQR2",
4924                  SPR_NOACCESS, SPR_NOACCESS,
4925                  &spr_read_generic, &spr_write_generic,
4926                  0x00000000);
4927     /* XXX : not implemented */
4928     spr_register(env, SPR_750_GQR3, "GQR3",
4929                  SPR_NOACCESS, SPR_NOACCESS,
4930                  &spr_read_generic, &spr_write_generic,
4931                  0x00000000);
4932     /* XXX : not implemented */
4933     spr_register(env, SPR_750_GQR4, "GQR4",
4934                  SPR_NOACCESS, SPR_NOACCESS,
4935                  &spr_read_generic, &spr_write_generic,
4936                  0x00000000);
4937     /* XXX : not implemented */
4938     spr_register(env, SPR_750_GQR5, "GQR5",
4939                  SPR_NOACCESS, SPR_NOACCESS,
4940                  &spr_read_generic, &spr_write_generic,
4941                  0x00000000);
4942     /* XXX : not implemented */
4943     spr_register(env, SPR_750_GQR6, "GQR6",
4944                  SPR_NOACCESS, SPR_NOACCESS,
4945                  &spr_read_generic, &spr_write_generic,
4946                  0x00000000);
4947     /* XXX : not implemented */
4948     spr_register(env, SPR_750_GQR7, "GQR7",
4949                  SPR_NOACCESS, SPR_NOACCESS,
4950                  &spr_read_generic, &spr_write_generic,
4951                  0x00000000);
4952     /* Memory management */
4953     gen_low_BATs(env);
4954     /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4955     gen_high_BATs(env);
4956     init_excp_750cl(env);
4957     env->dcache_line_size = 32;
4958     env->icache_line_size = 32;
4959     /* Allocate hardware IRQ controller */
4960     ppc6xx_irq_init(env);
4961 }
4962
4963 /* PowerPC 750CX                                                             */
4964 #define POWERPC_INSNS_750cx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4965                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4966                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4967                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4968                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4969                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4970                               PPC_SEGMENT | PPC_EXTERN)
4971 #define POWERPC_MSRM_750cx   (0x000000000005FF77ULL)
4972 #define POWERPC_MMU_750cx    (POWERPC_MMU_32B)
4973 #define POWERPC_EXCP_750cx   (POWERPC_EXCP_7x0)
4974 #define POWERPC_INPUT_750cx  (PPC_FLAGS_INPUT_6xx)
4975 #define POWERPC_BFDM_750cx   (bfd_mach_ppc_750)
4976 #define POWERPC_FLAG_750cx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4977                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4978 #define check_pow_750cx      check_pow_hid0
4979
4980 static void init_proc_750cx (CPUPPCState *env)
4981 {
4982     gen_spr_ne_601(env);
4983     gen_spr_7xx(env);
4984     /* XXX : not implemented */
4985     spr_register(env, SPR_L2CR, "L2CR",
4986                  SPR_NOACCESS, SPR_NOACCESS,
4987                  &spr_read_generic, &spr_write_generic,
4988                  0x00000000);
4989     /* Time base */
4990     gen_tbl(env);
4991     /* Thermal management */
4992     gen_spr_thrm(env);
4993     /* This register is not implemented but is present for compatibility */
4994     spr_register(env, SPR_SDA, "SDA",
4995                  SPR_NOACCESS, SPR_NOACCESS,
4996                  &spr_read_generic, &spr_write_generic,
4997                  0x00000000);
4998     /* Hardware implementation registers */
4999     /* XXX : not implemented */
5000     spr_register(env, SPR_HID0, "HID0",
5001                  SPR_NOACCESS, SPR_NOACCESS,
5002                  &spr_read_generic, &spr_write_generic,
5003                  0x00000000);
5004     /* XXX : not implemented */
5005     spr_register(env, SPR_HID1, "HID1",
5006                  SPR_NOACCESS, SPR_NOACCESS,
5007                  &spr_read_generic, &spr_write_generic,
5008                  0x00000000);
5009     /* Memory management */
5010     gen_low_BATs(env);
5011     /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5012     gen_high_BATs(env);
5013     init_excp_750cx(env);
5014     env->dcache_line_size = 32;
5015     env->icache_line_size = 32;
5016     /* Allocate hardware IRQ controller */
5017     ppc6xx_irq_init(env);
5018 }
5019
5020 /* PowerPC 750FX                                                             */
5021 #define POWERPC_INSNS_750fx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5022                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5023                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5024                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5025                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5026                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5027                               PPC_SEGMENT  | PPC_EXTERN)
5028 #define POWERPC_MSRM_750fx   (0x000000000005FF77ULL)
5029 #define POWERPC_MMU_750fx    (POWERPC_MMU_32B)
5030 #define POWERPC_EXCP_750fx   (POWERPC_EXCP_7x0)
5031 #define POWERPC_INPUT_750fx  (PPC_FLAGS_INPUT_6xx)
5032 #define POWERPC_BFDM_750fx   (bfd_mach_ppc_750)
5033 #define POWERPC_FLAG_750fx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5034                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5035 #define check_pow_750fx      check_pow_hid0
5036
5037 static void init_proc_750fx (CPUPPCState *env)
5038 {
5039     gen_spr_ne_601(env);
5040     gen_spr_7xx(env);
5041     /* XXX : not implemented */
5042     spr_register(env, SPR_L2CR, "L2CR",
5043                  SPR_NOACCESS, SPR_NOACCESS,
5044                  &spr_read_generic, &spr_write_generic,
5045                  0x00000000);
5046     /* Time base */
5047     gen_tbl(env);
5048     /* Thermal management */
5049     gen_spr_thrm(env);
5050     /* XXX : not implemented */
5051     spr_register(env, SPR_750_THRM4, "THRM4",
5052                  SPR_NOACCESS, SPR_NOACCESS,
5053                  &spr_read_generic, &spr_write_generic,
5054                  0x00000000);
5055     /* Hardware implementation registers */
5056     /* XXX : not implemented */
5057     spr_register(env, SPR_HID0, "HID0",
5058                  SPR_NOACCESS, SPR_NOACCESS,
5059                  &spr_read_generic, &spr_write_generic,
5060                  0x00000000);
5061     /* XXX : not implemented */
5062     spr_register(env, SPR_HID1, "HID1",
5063                  SPR_NOACCESS, SPR_NOACCESS,
5064                  &spr_read_generic, &spr_write_generic,
5065                  0x00000000);
5066     /* XXX : not implemented */
5067     spr_register(env, SPR_750FX_HID2, "HID2",
5068                  SPR_NOACCESS, SPR_NOACCESS,
5069                  &spr_read_generic, &spr_write_generic,
5070                  0x00000000);
5071     /* Memory management */
5072     gen_low_BATs(env);
5073     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5074     gen_high_BATs(env);
5075     init_excp_7x0(env);
5076     env->dcache_line_size = 32;
5077     env->icache_line_size = 32;
5078     /* Allocate hardware IRQ controller */
5079     ppc6xx_irq_init(env);
5080 }
5081
5082 /* PowerPC 750GX                                                             */
5083 #define POWERPC_INSNS_750gx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5084                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5085                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5086                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5087                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5088                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5089                               PPC_SEGMENT  | PPC_EXTERN)
5090 #define POWERPC_MSRM_750gx   (0x000000000005FF77ULL)
5091 #define POWERPC_MMU_750gx    (POWERPC_MMU_32B)
5092 #define POWERPC_EXCP_750gx   (POWERPC_EXCP_7x0)
5093 #define POWERPC_INPUT_750gx  (PPC_FLAGS_INPUT_6xx)
5094 #define POWERPC_BFDM_750gx   (bfd_mach_ppc_750)
5095 #define POWERPC_FLAG_750gx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5096                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5097 #define check_pow_750gx      check_pow_hid0
5098
5099 static void init_proc_750gx (CPUPPCState *env)
5100 {
5101     gen_spr_ne_601(env);
5102     gen_spr_7xx(env);
5103     /* XXX : not implemented (XXX: different from 750fx) */
5104     spr_register(env, SPR_L2CR, "L2CR",
5105                  SPR_NOACCESS, SPR_NOACCESS,
5106                  &spr_read_generic, &spr_write_generic,
5107                  0x00000000);
5108     /* Time base */
5109     gen_tbl(env);
5110     /* Thermal management */
5111     gen_spr_thrm(env);
5112     /* XXX : not implemented */
5113     spr_register(env, SPR_750_THRM4, "THRM4",
5114                  SPR_NOACCESS, SPR_NOACCESS,
5115                  &spr_read_generic, &spr_write_generic,
5116                  0x00000000);
5117     /* Hardware implementation registers */
5118     /* XXX : not implemented (XXX: different from 750fx) */
5119     spr_register(env, SPR_HID0, "HID0",
5120                  SPR_NOACCESS, SPR_NOACCESS,
5121                  &spr_read_generic, &spr_write_generic,
5122                  0x00000000);
5123     /* XXX : not implemented */
5124     spr_register(env, SPR_HID1, "HID1",
5125                  SPR_NOACCESS, SPR_NOACCESS,
5126                  &spr_read_generic, &spr_write_generic,
5127                  0x00000000);
5128     /* XXX : not implemented (XXX: different from 750fx) */
5129     spr_register(env, SPR_750FX_HID2, "HID2",
5130                  SPR_NOACCESS, SPR_NOACCESS,
5131                  &spr_read_generic, &spr_write_generic,
5132                  0x00000000);
5133     /* Memory management */
5134     gen_low_BATs(env);
5135     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5136     gen_high_BATs(env);
5137     init_excp_7x0(env);
5138     env->dcache_line_size = 32;
5139     env->icache_line_size = 32;
5140     /* Allocate hardware IRQ controller */
5141     ppc6xx_irq_init(env);
5142 }
5143
5144 /* PowerPC 745                                                               */
5145 #define POWERPC_INSNS_745    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5146                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5147                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5148                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5149                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5150                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5151                               PPC_SEGMENT | PPC_EXTERN)
5152 #define POWERPC_MSRM_745     (0x000000000005FF77ULL)
5153 #define POWERPC_MMU_745      (POWERPC_MMU_SOFT_6xx)
5154 #define POWERPC_EXCP_745     (POWERPC_EXCP_7x5)
5155 #define POWERPC_INPUT_745    (PPC_FLAGS_INPUT_6xx)
5156 #define POWERPC_BFDM_745     (bfd_mach_ppc_750)
5157 #define POWERPC_FLAG_745     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5158                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5159 #define check_pow_745        check_pow_hid0
5160
5161 static void init_proc_745 (CPUPPCState *env)
5162 {
5163     gen_spr_ne_601(env);
5164     gen_spr_7xx(env);
5165     gen_spr_G2_755(env);
5166     /* Time base */
5167     gen_tbl(env);
5168     /* Thermal management */
5169     gen_spr_thrm(env);
5170     /* Hardware implementation registers */
5171     /* XXX : not implemented */
5172     spr_register(env, SPR_HID0, "HID0",
5173                  SPR_NOACCESS, SPR_NOACCESS,
5174                  &spr_read_generic, &spr_write_generic,
5175                  0x00000000);
5176     /* XXX : not implemented */
5177     spr_register(env, SPR_HID1, "HID1",
5178                  SPR_NOACCESS, SPR_NOACCESS,
5179                  &spr_read_generic, &spr_write_generic,
5180                  0x00000000);
5181     /* XXX : not implemented */
5182     spr_register(env, SPR_HID2, "HID2",
5183                  SPR_NOACCESS, SPR_NOACCESS,
5184                  &spr_read_generic, &spr_write_generic,
5185                  0x00000000);
5186     /* Memory management */
5187     gen_low_BATs(env);
5188     gen_high_BATs(env);
5189     gen_6xx_7xx_soft_tlb(env, 64, 2);
5190     init_excp_7x5(env);
5191     env->dcache_line_size = 32;
5192     env->icache_line_size = 32;
5193     /* Allocate hardware IRQ controller */
5194     ppc6xx_irq_init(env);
5195 }
5196
5197 /* PowerPC 755                                                               */
5198 #define POWERPC_INSNS_755    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5199                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5200                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5201                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5202                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5203                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5204                               PPC_SEGMENT | PPC_EXTERN)
5205 #define POWERPC_MSRM_755     (0x000000000005FF77ULL)
5206 #define POWERPC_MMU_755      (POWERPC_MMU_SOFT_6xx)
5207 #define POWERPC_EXCP_755     (POWERPC_EXCP_7x5)
5208 #define POWERPC_INPUT_755    (PPC_FLAGS_INPUT_6xx)
5209 #define POWERPC_BFDM_755     (bfd_mach_ppc_750)
5210 #define POWERPC_FLAG_755     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5211                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5212 #define check_pow_755        check_pow_hid0
5213
5214 static void init_proc_755 (CPUPPCState *env)
5215 {
5216     gen_spr_ne_601(env);
5217     gen_spr_7xx(env);
5218     gen_spr_G2_755(env);
5219     /* Time base */
5220     gen_tbl(env);
5221     /* L2 cache control */
5222     /* XXX : not implemented */
5223     spr_register(env, SPR_L2CR, "L2CR",
5224                  SPR_NOACCESS, SPR_NOACCESS,
5225                  &spr_read_generic, &spr_write_generic,
5226                  0x00000000);
5227     /* XXX : not implemented */
5228     spr_register(env, SPR_L2PMCR, "L2PMCR",
5229                  SPR_NOACCESS, SPR_NOACCESS,
5230                  &spr_read_generic, &spr_write_generic,
5231                  0x00000000);
5232     /* Thermal management */
5233     gen_spr_thrm(env);
5234     /* Hardware implementation registers */
5235     /* XXX : not implemented */
5236     spr_register(env, SPR_HID0, "HID0",
5237                  SPR_NOACCESS, SPR_NOACCESS,
5238                  &spr_read_generic, &spr_write_generic,
5239                  0x00000000);
5240     /* XXX : not implemented */
5241     spr_register(env, SPR_HID1, "HID1",
5242                  SPR_NOACCESS, SPR_NOACCESS,
5243                  &spr_read_generic, &spr_write_generic,
5244                  0x00000000);
5245     /* XXX : not implemented */
5246     spr_register(env, SPR_HID2, "HID2",
5247                  SPR_NOACCESS, SPR_NOACCESS,
5248                  &spr_read_generic, &spr_write_generic,
5249                  0x00000000);
5250     /* Memory management */
5251     gen_low_BATs(env);
5252     gen_high_BATs(env);
5253     gen_6xx_7xx_soft_tlb(env, 64, 2);
5254     init_excp_7x5(env);
5255     env->dcache_line_size = 32;
5256     env->icache_line_size = 32;
5257     /* Allocate hardware IRQ controller */
5258     ppc6xx_irq_init(env);
5259 }
5260
5261 /* PowerPC 7400 (aka G4)                                                     */
5262 #define POWERPC_INSNS_7400   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5263                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5264                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5265                               PPC_FLOAT_STFIWX |                              \
5266                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5267                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5268                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5269                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5270                               PPC_MEM_TLBIA |                                 \
5271                               PPC_SEGMENT | PPC_EXTERN |                      \
5272                               PPC_ALTIVEC)
5273 #define POWERPC_MSRM_7400    (0x000000000205FF77ULL)
5274 #define POWERPC_MMU_7400     (POWERPC_MMU_32B)
5275 #define POWERPC_EXCP_7400    (POWERPC_EXCP_74xx)
5276 #define POWERPC_INPUT_7400   (PPC_FLAGS_INPUT_6xx)
5277 #define POWERPC_BFDM_7400    (bfd_mach_ppc_7400)
5278 #define POWERPC_FLAG_7400    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5279                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5280                               POWERPC_FLAG_BUS_CLK)
5281 #define check_pow_7400       check_pow_hid0
5282
5283 static void init_proc_7400 (CPUPPCState *env)
5284 {
5285     gen_spr_ne_601(env);
5286     gen_spr_7xx(env);
5287     /* Time base */
5288     gen_tbl(env);
5289     /* 74xx specific SPR */
5290     gen_spr_74xx(env);
5291     /* XXX : not implemented */
5292     spr_register(env, SPR_UBAMR, "UBAMR",
5293                  &spr_read_ureg, SPR_NOACCESS,
5294                  &spr_read_ureg, SPR_NOACCESS,
5295                  0x00000000);
5296     /* XXX: this seems not implemented on all revisions. */
5297     /* XXX : not implemented */
5298     spr_register(env, SPR_MSSCR1, "MSSCR1",
5299                  SPR_NOACCESS, SPR_NOACCESS,
5300                  &spr_read_generic, &spr_write_generic,
5301                  0x00000000);
5302     /* Thermal management */
5303     gen_spr_thrm(env);
5304     /* Memory management */
5305     gen_low_BATs(env);
5306     init_excp_7400(env);
5307     env->dcache_line_size = 32;
5308     env->icache_line_size = 32;
5309     /* Allocate hardware IRQ controller */
5310     ppc6xx_irq_init(env);
5311 }
5312
5313 /* PowerPC 7410 (aka G4)                                                     */
5314 #define POWERPC_INSNS_7410   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5315                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5316                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5317                               PPC_FLOAT_STFIWX |                              \
5318                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5319                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5320                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5321                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5322                               PPC_MEM_TLBIA |                                 \
5323                               PPC_SEGMENT | PPC_EXTERN |                      \
5324                               PPC_ALTIVEC)
5325 #define POWERPC_MSRM_7410    (0x000000000205FF77ULL)
5326 #define POWERPC_MMU_7410     (POWERPC_MMU_32B)
5327 #define POWERPC_EXCP_7410    (POWERPC_EXCP_74xx)
5328 #define POWERPC_INPUT_7410   (PPC_FLAGS_INPUT_6xx)
5329 #define POWERPC_BFDM_7410    (bfd_mach_ppc_7400)
5330 #define POWERPC_FLAG_7410    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5331                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5332                               POWERPC_FLAG_BUS_CLK)
5333 #define check_pow_7410       check_pow_hid0
5334
5335 static void init_proc_7410 (CPUPPCState *env)
5336 {
5337     gen_spr_ne_601(env);
5338     gen_spr_7xx(env);
5339     /* Time base */
5340     gen_tbl(env);
5341     /* 74xx specific SPR */
5342     gen_spr_74xx(env);
5343     /* XXX : not implemented */
5344     spr_register(env, SPR_UBAMR, "UBAMR",
5345                  &spr_read_ureg, SPR_NOACCESS,
5346                  &spr_read_ureg, SPR_NOACCESS,
5347                  0x00000000);
5348     /* Thermal management */
5349     gen_spr_thrm(env);
5350     /* L2PMCR */
5351     /* XXX : not implemented */
5352     spr_register(env, SPR_L2PMCR, "L2PMCR",
5353                  SPR_NOACCESS, SPR_NOACCESS,
5354                  &spr_read_generic, &spr_write_generic,
5355                  0x00000000);
5356     /* LDSTDB */
5357     /* XXX : not implemented */
5358     spr_register(env, SPR_LDSTDB, "LDSTDB",
5359                  SPR_NOACCESS, SPR_NOACCESS,
5360                  &spr_read_generic, &spr_write_generic,
5361                  0x00000000);
5362     /* Memory management */
5363     gen_low_BATs(env);
5364     init_excp_7400(env);
5365     env->dcache_line_size = 32;
5366     env->icache_line_size = 32;
5367     /* Allocate hardware IRQ controller */
5368     ppc6xx_irq_init(env);
5369 }
5370
5371 /* PowerPC 7440 (aka G4)                                                     */
5372 #define POWERPC_INSNS_7440   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5373                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5374                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5375                               PPC_FLOAT_STFIWX |                              \
5376                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5377                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5378                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5379                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5380                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5381                               PPC_SEGMENT | PPC_EXTERN |                      \
5382                               PPC_ALTIVEC)
5383 #define POWERPC_MSRM_7440    (0x000000000205FF77ULL)
5384 #define POWERPC_MMU_7440     (POWERPC_MMU_SOFT_74xx)
5385 #define POWERPC_EXCP_7440    (POWERPC_EXCP_74xx)
5386 #define POWERPC_INPUT_7440   (PPC_FLAGS_INPUT_6xx)
5387 #define POWERPC_BFDM_7440    (bfd_mach_ppc_7400)
5388 #define POWERPC_FLAG_7440    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5389                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5390                               POWERPC_FLAG_BUS_CLK)
5391 #define check_pow_7440       check_pow_hid0_74xx
5392
5393 __attribute__ (( unused ))
5394 static void init_proc_7440 (CPUPPCState *env)
5395 {
5396     gen_spr_ne_601(env);
5397     gen_spr_7xx(env);
5398     /* Time base */
5399     gen_tbl(env);
5400     /* 74xx specific SPR */
5401     gen_spr_74xx(env);
5402     /* XXX : not implemented */
5403     spr_register(env, SPR_UBAMR, "UBAMR",
5404                  &spr_read_ureg, SPR_NOACCESS,
5405                  &spr_read_ureg, SPR_NOACCESS,
5406                  0x00000000);
5407     /* LDSTCR */
5408     /* XXX : not implemented */
5409     spr_register(env, SPR_LDSTCR, "LDSTCR",
5410                  SPR_NOACCESS, SPR_NOACCESS,
5411                  &spr_read_generic, &spr_write_generic,
5412                  0x00000000);
5413     /* ICTRL */
5414     /* XXX : not implemented */
5415     spr_register(env, SPR_ICTRL, "ICTRL",
5416                  SPR_NOACCESS, SPR_NOACCESS,
5417                  &spr_read_generic, &spr_write_generic,
5418                  0x00000000);
5419     /* MSSSR0 */
5420     /* XXX : not implemented */
5421     spr_register(env, SPR_MSSSR0, "MSSSR0",
5422                  SPR_NOACCESS, SPR_NOACCESS,
5423                  &spr_read_generic, &spr_write_generic,
5424                  0x00000000);
5425     /* PMC */
5426     /* XXX : not implemented */
5427     spr_register(env, SPR_PMC5, "PMC5",
5428                  SPR_NOACCESS, SPR_NOACCESS,
5429                  &spr_read_generic, &spr_write_generic,
5430                  0x00000000);
5431     /* XXX : not implemented */
5432     spr_register(env, SPR_UPMC5, "UPMC5",
5433                  &spr_read_ureg, SPR_NOACCESS,
5434                  &spr_read_ureg, SPR_NOACCESS,
5435                  0x00000000);
5436     /* XXX : not implemented */
5437     spr_register(env, SPR_PMC6, "PMC6",
5438                  SPR_NOACCESS, SPR_NOACCESS,
5439                  &spr_read_generic, &spr_write_generic,
5440                  0x00000000);
5441     /* XXX : not implemented */
5442     spr_register(env, SPR_UPMC6, "UPMC6",
5443                  &spr_read_ureg, SPR_NOACCESS,
5444                  &spr_read_ureg, SPR_NOACCESS,
5445                  0x00000000);
5446     /* Memory management */
5447     gen_low_BATs(env);
5448     gen_74xx_soft_tlb(env, 128, 2);
5449     init_excp_7450(env);
5450     env->dcache_line_size = 32;
5451     env->icache_line_size = 32;
5452     /* Allocate hardware IRQ controller */
5453     ppc6xx_irq_init(env);
5454 }
5455
5456 /* PowerPC 7450 (aka G4)                                                     */
5457 #define POWERPC_INSNS_7450   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5458                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5459                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5460                               PPC_FLOAT_STFIWX |                              \
5461                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5462                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5463                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5464                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5465                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5466                               PPC_SEGMENT | PPC_EXTERN |                      \
5467                               PPC_ALTIVEC)
5468 #define POWERPC_MSRM_7450    (0x000000000205FF77ULL)
5469 #define POWERPC_MMU_7450     (POWERPC_MMU_SOFT_74xx)
5470 #define POWERPC_EXCP_7450    (POWERPC_EXCP_74xx)
5471 #define POWERPC_INPUT_7450   (PPC_FLAGS_INPUT_6xx)
5472 #define POWERPC_BFDM_7450    (bfd_mach_ppc_7400)
5473 #define POWERPC_FLAG_7450    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5474                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5475                               POWERPC_FLAG_BUS_CLK)
5476 #define check_pow_7450       check_pow_hid0_74xx
5477
5478 __attribute__ (( unused ))
5479 static void init_proc_7450 (CPUPPCState *env)
5480 {
5481     gen_spr_ne_601(env);
5482     gen_spr_7xx(env);
5483     /* Time base */
5484     gen_tbl(env);
5485     /* 74xx specific SPR */
5486     gen_spr_74xx(env);
5487     /* Level 3 cache control */
5488     gen_l3_ctrl(env);
5489     /* L3ITCR1 */
5490     /* XXX : not implemented */
5491     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5492                  SPR_NOACCESS, SPR_NOACCESS,
5493                  &spr_read_generic, &spr_write_generic,
5494                  0x00000000);
5495     /* L3ITCR2 */
5496     /* XXX : not implemented */
5497     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5498                  SPR_NOACCESS, SPR_NOACCESS,
5499                  &spr_read_generic, &spr_write_generic,
5500                  0x00000000);
5501     /* L3ITCR3 */
5502     /* XXX : not implemented */
5503     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5504                  SPR_NOACCESS, SPR_NOACCESS,
5505                  &spr_read_generic, &spr_write_generic,
5506                  0x00000000);
5507     /* L3OHCR */
5508     /* XXX : not implemented */
5509     spr_register(env, SPR_L3OHCR, "L3OHCR",
5510                  SPR_NOACCESS, SPR_NOACCESS,
5511                  &spr_read_generic, &spr_write_generic,
5512                  0x00000000);
5513     /* XXX : not implemented */
5514     spr_register(env, SPR_UBAMR, "UBAMR",
5515                  &spr_read_ureg, SPR_NOACCESS,
5516                  &spr_read_ureg, SPR_NOACCESS,
5517                  0x00000000);
5518     /* LDSTCR */
5519     /* XXX : not implemented */
5520     spr_register(env, SPR_LDSTCR, "LDSTCR",
5521                  SPR_NOACCESS, SPR_NOACCESS,
5522                  &spr_read_generic, &spr_write_generic,
5523                  0x00000000);
5524     /* ICTRL */
5525     /* XXX : not implemented */
5526     spr_register(env, SPR_ICTRL, "ICTRL",
5527                  SPR_NOACCESS, SPR_NOACCESS,
5528                  &spr_read_generic, &spr_write_generic,
5529                  0x00000000);
5530     /* MSSSR0 */
5531     /* XXX : not implemented */
5532     spr_register(env, SPR_MSSSR0, "MSSSR0",
5533                  SPR_NOACCESS, SPR_NOACCESS,
5534                  &spr_read_generic, &spr_write_generic,
5535                  0x00000000);
5536     /* PMC */
5537     /* XXX : not implemented */
5538     spr_register(env, SPR_PMC5, "PMC5",
5539                  SPR_NOACCESS, SPR_NOACCESS,
5540                  &spr_read_generic, &spr_write_generic,
5541                  0x00000000);
5542     /* XXX : not implemented */
5543     spr_register(env, SPR_UPMC5, "UPMC5",
5544                  &spr_read_ureg, SPR_NOACCESS,
5545                  &spr_read_ureg, SPR_NOACCESS,
5546                  0x00000000);
5547     /* XXX : not implemented */
5548     spr_register(env, SPR_PMC6, "PMC6",
5549                  SPR_NOACCESS, SPR_NOACCESS,
5550                  &spr_read_generic, &spr_write_generic,
5551                  0x00000000);
5552     /* XXX : not implemented */
5553     spr_register(env, SPR_UPMC6, "UPMC6",
5554                  &spr_read_ureg, SPR_NOACCESS,
5555                  &spr_read_ureg, SPR_NOACCESS,
5556                  0x00000000);
5557     /* Memory management */
5558     gen_low_BATs(env);
5559     gen_74xx_soft_tlb(env, 128, 2);
5560     init_excp_7450(env);
5561     env->dcache_line_size = 32;
5562     env->icache_line_size = 32;
5563     /* Allocate hardware IRQ controller */
5564     ppc6xx_irq_init(env);
5565 }
5566
5567 /* PowerPC 7445 (aka G4)                                                     */
5568 #define POWERPC_INSNS_7445   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5569                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5570                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5571                               PPC_FLOAT_STFIWX |                              \
5572                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5573                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5574                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5575                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5576                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5577                               PPC_SEGMENT | PPC_EXTERN |                      \
5578                               PPC_ALTIVEC)
5579 #define POWERPC_MSRM_7445    (0x000000000205FF77ULL)
5580 #define POWERPC_MMU_7445     (POWERPC_MMU_SOFT_74xx)
5581 #define POWERPC_EXCP_7445    (POWERPC_EXCP_74xx)
5582 #define POWERPC_INPUT_7445   (PPC_FLAGS_INPUT_6xx)
5583 #define POWERPC_BFDM_7445    (bfd_mach_ppc_7400)
5584 #define POWERPC_FLAG_7445    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5585                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5586                               POWERPC_FLAG_BUS_CLK)
5587 #define check_pow_7445       check_pow_hid0_74xx
5588
5589 __attribute__ (( unused ))
5590 static void init_proc_7445 (CPUPPCState *env)
5591 {
5592     gen_spr_ne_601(env);
5593     gen_spr_7xx(env);
5594     /* Time base */
5595     gen_tbl(env);
5596     /* 74xx specific SPR */
5597     gen_spr_74xx(env);
5598     /* LDSTCR */
5599     /* XXX : not implemented */
5600     spr_register(env, SPR_LDSTCR, "LDSTCR",
5601                  SPR_NOACCESS, SPR_NOACCESS,
5602                  &spr_read_generic, &spr_write_generic,
5603                  0x00000000);
5604     /* ICTRL */
5605     /* XXX : not implemented */
5606     spr_register(env, SPR_ICTRL, "ICTRL",
5607                  SPR_NOACCESS, SPR_NOACCESS,
5608                  &spr_read_generic, &spr_write_generic,
5609                  0x00000000);
5610     /* MSSSR0 */
5611     /* XXX : not implemented */
5612     spr_register(env, SPR_MSSSR0, "MSSSR0",
5613                  SPR_NOACCESS, SPR_NOACCESS,
5614                  &spr_read_generic, &spr_write_generic,
5615                  0x00000000);
5616     /* PMC */
5617     /* XXX : not implemented */
5618     spr_register(env, SPR_PMC5, "PMC5",
5619                  SPR_NOACCESS, SPR_NOACCESS,
5620                  &spr_read_generic, &spr_write_generic,
5621                  0x00000000);
5622     /* XXX : not implemented */
5623     spr_register(env, SPR_UPMC5, "UPMC5",
5624                  &spr_read_ureg, SPR_NOACCESS,
5625                  &spr_read_ureg, SPR_NOACCESS,
5626                  0x00000000);
5627     /* XXX : not implemented */
5628     spr_register(env, SPR_PMC6, "PMC6",
5629                  SPR_NOACCESS, SPR_NOACCESS,
5630                  &spr_read_generic, &spr_write_generic,
5631                  0x00000000);
5632     /* XXX : not implemented */
5633     spr_register(env, SPR_UPMC6, "UPMC6",
5634                  &spr_read_ureg, SPR_NOACCESS,
5635                  &spr_read_ureg, SPR_NOACCESS,
5636                  0x00000000);
5637     /* SPRGs */
5638     spr_register(env, SPR_SPRG4, "SPRG4",
5639                  SPR_NOACCESS, SPR_NOACCESS,
5640                  &spr_read_generic, &spr_write_generic,
5641                  0x00000000);
5642     spr_register(env, SPR_USPRG4, "USPRG4",
5643                  &spr_read_ureg, SPR_NOACCESS,
5644                  &spr_read_ureg, SPR_NOACCESS,
5645                  0x00000000);
5646     spr_register(env, SPR_SPRG5, "SPRG5",
5647                  SPR_NOACCESS, SPR_NOACCESS,
5648                  &spr_read_generic, &spr_write_generic,
5649                  0x00000000);
5650     spr_register(env, SPR_USPRG5, "USPRG5",
5651                  &spr_read_ureg, SPR_NOACCESS,
5652                  &spr_read_ureg, SPR_NOACCESS,
5653                  0x00000000);
5654     spr_register(env, SPR_SPRG6, "SPRG6",
5655                  SPR_NOACCESS, SPR_NOACCESS,
5656                  &spr_read_generic, &spr_write_generic,
5657                  0x00000000);
5658     spr_register(env, SPR_USPRG6, "USPRG6",
5659                  &spr_read_ureg, SPR_NOACCESS,
5660                  &spr_read_ureg, SPR_NOACCESS,
5661                  0x00000000);
5662     spr_register(env, SPR_SPRG7, "SPRG7",
5663                  SPR_NOACCESS, SPR_NOACCESS,
5664                  &spr_read_generic, &spr_write_generic,
5665                  0x00000000);
5666     spr_register(env, SPR_USPRG7, "USPRG7",
5667                  &spr_read_ureg, SPR_NOACCESS,
5668                  &spr_read_ureg, SPR_NOACCESS,
5669                  0x00000000);
5670     /* Memory management */
5671     gen_low_BATs(env);
5672     gen_high_BATs(env);
5673     gen_74xx_soft_tlb(env, 128, 2);
5674     init_excp_7450(env);
5675     env->dcache_line_size = 32;
5676     env->icache_line_size = 32;
5677     /* Allocate hardware IRQ controller */
5678     ppc6xx_irq_init(env);
5679 }
5680
5681 /* PowerPC 7455 (aka G4)                                                     */
5682 #define POWERPC_INSNS_7455   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5683                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5684                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5685                               PPC_FLOAT_STFIWX |                              \
5686                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5687                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5688                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5689                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5690                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5691                               PPC_SEGMENT | PPC_EXTERN |                      \
5692                               PPC_ALTIVEC)
5693 #define POWERPC_MSRM_7455    (0x000000000205FF77ULL)
5694 #define POWERPC_MMU_7455     (POWERPC_MMU_SOFT_74xx)
5695 #define POWERPC_EXCP_7455    (POWERPC_EXCP_74xx)
5696 #define POWERPC_INPUT_7455   (PPC_FLAGS_INPUT_6xx)
5697 #define POWERPC_BFDM_7455    (bfd_mach_ppc_7400)
5698 #define POWERPC_FLAG_7455    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5699                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5700                               POWERPC_FLAG_BUS_CLK)
5701 #define check_pow_7455       check_pow_hid0_74xx
5702
5703 __attribute__ (( unused ))
5704 static void init_proc_7455 (CPUPPCState *env)
5705 {
5706     gen_spr_ne_601(env);
5707     gen_spr_7xx(env);
5708     /* Time base */
5709     gen_tbl(env);
5710     /* 74xx specific SPR */
5711     gen_spr_74xx(env);
5712     /* Level 3 cache control */
5713     gen_l3_ctrl(env);
5714     /* LDSTCR */
5715     /* XXX : not implemented */
5716     spr_register(env, SPR_LDSTCR, "LDSTCR",
5717                  SPR_NOACCESS, SPR_NOACCESS,
5718                  &spr_read_generic, &spr_write_generic,
5719                  0x00000000);
5720     /* ICTRL */
5721     /* XXX : not implemented */
5722     spr_register(env, SPR_ICTRL, "ICTRL",
5723                  SPR_NOACCESS, SPR_NOACCESS,
5724                  &spr_read_generic, &spr_write_generic,
5725                  0x00000000);
5726     /* MSSSR0 */
5727     /* XXX : not implemented */
5728     spr_register(env, SPR_MSSSR0, "MSSSR0",
5729                  SPR_NOACCESS, SPR_NOACCESS,
5730                  &spr_read_generic, &spr_write_generic,
5731                  0x00000000);
5732     /* PMC */
5733     /* XXX : not implemented */
5734     spr_register(env, SPR_PMC5, "PMC5",
5735                  SPR_NOACCESS, SPR_NOACCESS,
5736                  &spr_read_generic, &spr_write_generic,
5737                  0x00000000);
5738     /* XXX : not implemented */
5739     spr_register(env, SPR_UPMC5, "UPMC5",
5740                  &spr_read_ureg, SPR_NOACCESS,
5741                  &spr_read_ureg, SPR_NOACCESS,
5742                  0x00000000);
5743     /* XXX : not implemented */
5744     spr_register(env, SPR_PMC6, "PMC6",
5745                  SPR_NOACCESS, SPR_NOACCESS,
5746                  &spr_read_generic, &spr_write_generic,
5747                  0x00000000);
5748     /* XXX : not implemented */
5749     spr_register(env, SPR_UPMC6, "UPMC6",
5750                  &spr_read_ureg, SPR_NOACCESS,
5751                  &spr_read_ureg, SPR_NOACCESS,
5752                  0x00000000);
5753     /* SPRGs */
5754     spr_register(env, SPR_SPRG4, "SPRG4",
5755                  SPR_NOACCESS, SPR_NOACCESS,
5756                  &spr_read_generic, &spr_write_generic,
5757                  0x00000000);
5758     spr_register(env, SPR_USPRG4, "USPRG4",
5759                  &spr_read_ureg, SPR_NOACCESS,
5760                  &spr_read_ureg, SPR_NOACCESS,
5761                  0x00000000);
5762     spr_register(env, SPR_SPRG5, "SPRG5",
5763                  SPR_NOACCESS, SPR_NOACCESS,
5764                  &spr_read_generic, &spr_write_generic,
5765                  0x00000000);
5766     spr_register(env, SPR_USPRG5, "USPRG5",
5767                  &spr_read_ureg, SPR_NOACCESS,
5768                  &spr_read_ureg, SPR_NOACCESS,
5769                  0x00000000);
5770     spr_register(env, SPR_SPRG6, "SPRG6",
5771                  SPR_NOACCESS, SPR_NOACCESS,
5772                  &spr_read_generic, &spr_write_generic,
5773                  0x00000000);
5774     spr_register(env, SPR_USPRG6, "USPRG6",
5775                  &spr_read_ureg, SPR_NOACCESS,
5776                  &spr_read_ureg, SPR_NOACCESS,
5777                  0x00000000);
5778     spr_register(env, SPR_SPRG7, "SPRG7",
5779                  SPR_NOACCESS, SPR_NOACCESS,
5780                  &spr_read_generic, &spr_write_generic,
5781                  0x00000000);
5782     spr_register(env, SPR_USPRG7, "USPRG7",
5783                  &spr_read_ureg, SPR_NOACCESS,
5784                  &spr_read_ureg, SPR_NOACCESS,
5785                  0x00000000);
5786     /* Memory management */
5787     gen_low_BATs(env);
5788     gen_high_BATs(env);
5789     gen_74xx_soft_tlb(env, 128, 2);
5790     init_excp_7450(env);
5791     env->dcache_line_size = 32;
5792     env->icache_line_size = 32;
5793     /* Allocate hardware IRQ controller */
5794     ppc6xx_irq_init(env);
5795 }
5796
5797 /* PowerPC 7457 (aka G4)                                                     */
5798 #define POWERPC_INSNS_7457   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5799                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5800                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5801                               PPC_FLOAT_STFIWX |                              \
5802                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5803                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5804                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5805                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5806                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5807                               PPC_SEGMENT | PPC_EXTERN |                      \
5808                               PPC_ALTIVEC)
5809 #define POWERPC_MSRM_7457    (0x000000000205FF77ULL)
5810 #define POWERPC_MMU_7457     (POWERPC_MMU_SOFT_74xx)
5811 #define POWERPC_EXCP_7457    (POWERPC_EXCP_74xx)
5812 #define POWERPC_INPUT_7457   (PPC_FLAGS_INPUT_6xx)
5813 #define POWERPC_BFDM_7457    (bfd_mach_ppc_7400)
5814 #define POWERPC_FLAG_7457    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5815                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5816                               POWERPC_FLAG_BUS_CLK)
5817 #define check_pow_7457       check_pow_hid0_74xx
5818
5819 __attribute__ (( unused ))
5820 static void init_proc_7457 (CPUPPCState *env)
5821 {
5822     gen_spr_ne_601(env);
5823     gen_spr_7xx(env);
5824     /* Time base */
5825     gen_tbl(env);
5826     /* 74xx specific SPR */
5827     gen_spr_74xx(env);
5828     /* Level 3 cache control */
5829     gen_l3_ctrl(env);
5830     /* L3ITCR1 */
5831     /* XXX : not implemented */
5832     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5833                  SPR_NOACCESS, SPR_NOACCESS,
5834                  &spr_read_generic, &spr_write_generic,
5835                  0x00000000);
5836     /* L3ITCR2 */
5837     /* XXX : not implemented */
5838     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5839                  SPR_NOACCESS, SPR_NOACCESS,
5840                  &spr_read_generic, &spr_write_generic,
5841                  0x00000000);
5842     /* L3ITCR3 */
5843     /* XXX : not implemented */
5844     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5845                  SPR_NOACCESS, SPR_NOACCESS,
5846                  &spr_read_generic, &spr_write_generic,
5847                  0x00000000);
5848     /* L3OHCR */
5849     /* XXX : not implemented */
5850     spr_register(env, SPR_L3OHCR, "L3OHCR",
5851                  SPR_NOACCESS, SPR_NOACCESS,
5852                  &spr_read_generic, &spr_write_generic,
5853                  0x00000000);
5854     /* LDSTCR */
5855     /* XXX : not implemented */
5856     spr_register(env, SPR_LDSTCR, "LDSTCR",
5857                  SPR_NOACCESS, SPR_NOACCESS,
5858                  &spr_read_generic, &spr_write_generic,
5859                  0x00000000);
5860     /* ICTRL */
5861     /* XXX : not implemented */
5862     spr_register(env, SPR_ICTRL, "ICTRL",
5863                  SPR_NOACCESS, SPR_NOACCESS,
5864                  &spr_read_generic, &spr_write_generic,
5865                  0x00000000);
5866     /* MSSSR0 */
5867     /* XXX : not implemented */
5868     spr_register(env, SPR_MSSSR0, "MSSSR0",
5869                  SPR_NOACCESS, SPR_NOACCESS,
5870                  &spr_read_generic, &spr_write_generic,
5871                  0x00000000);
5872     /* PMC */
5873     /* XXX : not implemented */
5874     spr_register(env, SPR_PMC5, "PMC5",
5875                  SPR_NOACCESS, SPR_NOACCESS,
5876                  &spr_read_generic, &spr_write_generic,
5877                  0x00000000);
5878     /* XXX : not implemented */
5879     spr_register(env, SPR_UPMC5, "UPMC5",
5880                  &spr_read_ureg, SPR_NOACCESS,
5881                  &spr_read_ureg, SPR_NOACCESS,
5882                  0x00000000);
5883     /* XXX : not implemented */
5884     spr_register(env, SPR_PMC6, "PMC6",
5885                  SPR_NOACCESS, SPR_NOACCESS,
5886                  &spr_read_generic, &spr_write_generic,
5887                  0x00000000);
5888     /* XXX : not implemented */
5889     spr_register(env, SPR_UPMC6, "UPMC6",
5890                  &spr_read_ureg, SPR_NOACCESS,
5891                  &spr_read_ureg, SPR_NOACCESS,
5892                  0x00000000);
5893     /* SPRGs */
5894     spr_register(env, SPR_SPRG4, "SPRG4",
5895                  SPR_NOACCESS, SPR_NOACCESS,
5896                  &spr_read_generic, &spr_write_generic,
5897                  0x00000000);
5898     spr_register(env, SPR_USPRG4, "USPRG4",
5899                  &spr_read_ureg, SPR_NOACCESS,
5900                  &spr_read_ureg, SPR_NOACCESS,
5901                  0x00000000);
5902     spr_register(env, SPR_SPRG5, "SPRG5",
5903                  SPR_NOACCESS, SPR_NOACCESS,
5904                  &spr_read_generic, &spr_write_generic,
5905                  0x00000000);
5906     spr_register(env, SPR_USPRG5, "USPRG5",
5907                  &spr_read_ureg, SPR_NOACCESS,
5908                  &spr_read_ureg, SPR_NOACCESS,
5909                  0x00000000);
5910     spr_register(env, SPR_SPRG6, "SPRG6",
5911                  SPR_NOACCESS, SPR_NOACCESS,
5912                  &spr_read_generic, &spr_write_generic,
5913                  0x00000000);
5914     spr_register(env, SPR_USPRG6, "USPRG6",
5915                  &spr_read_ureg, SPR_NOACCESS,
5916                  &spr_read_ureg, SPR_NOACCESS,
5917                  0x00000000);
5918     spr_register(env, SPR_SPRG7, "SPRG7",
5919                  SPR_NOACCESS, SPR_NOACCESS,
5920                  &spr_read_generic, &spr_write_generic,
5921                  0x00000000);
5922     spr_register(env, SPR_USPRG7, "USPRG7",
5923                  &spr_read_ureg, SPR_NOACCESS,
5924                  &spr_read_ureg, SPR_NOACCESS,
5925                  0x00000000);
5926     /* Memory management */
5927     gen_low_BATs(env);
5928     gen_high_BATs(env);
5929     gen_74xx_soft_tlb(env, 128, 2);
5930     init_excp_7450(env);
5931     env->dcache_line_size = 32;
5932     env->icache_line_size = 32;
5933     /* Allocate hardware IRQ controller */
5934     ppc6xx_irq_init(env);
5935 }
5936
5937 #if defined (TARGET_PPC64)
5938 /* PowerPC 970                                                               */
5939 #define POWERPC_INSNS_970    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5940                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5941                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5942                               PPC_FLOAT_STFIWX |                              \
5943                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
5944                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5945                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5946                               PPC_64B | PPC_ALTIVEC |                         \
5947                               PPC_SEGMENT_64B | PPC_SLBI)
5948 #define POWERPC_MSRM_970     (0x900000000204FF36ULL)
5949 #define POWERPC_MMU_970      (POWERPC_MMU_64B)
5950 //#define POWERPC_EXCP_970     (POWERPC_EXCP_970)
5951 #define POWERPC_INPUT_970    (PPC_FLAGS_INPUT_970)
5952 #define POWERPC_BFDM_970     (bfd_mach_ppc64)
5953 #define POWERPC_FLAG_970     (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5954                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5955                               POWERPC_FLAG_BUS_CLK)
5956
5957 #if defined(CONFIG_USER_ONLY)
5958 #define POWERPC970_HID5_INIT 0x00000080
5959 #else
5960 #define POWERPC970_HID5_INIT 0x00000000
5961 #endif
5962
5963 static int check_pow_970 (CPUPPCState *env)
5964 {
5965     if (env->spr[SPR_HID0] & 0x00600000)
5966         return 1;
5967
5968     return 0;
5969 }
5970
5971 static void init_proc_970 (CPUPPCState *env)
5972 {
5973     gen_spr_ne_601(env);
5974     gen_spr_7xx(env);
5975     /* Time base */
5976     gen_tbl(env);
5977     /* Hardware implementation registers */
5978     /* XXX : not implemented */
5979     spr_register(env, SPR_HID0, "HID0",
5980                  SPR_NOACCESS, SPR_NOACCESS,
5981                  &spr_read_generic, &spr_write_clear,
5982                  0x60000000);
5983     /* XXX : not implemented */
5984     spr_register(env, SPR_HID1, "HID1",
5985                  SPR_NOACCESS, SPR_NOACCESS,
5986                  &spr_read_generic, &spr_write_generic,
5987                  0x00000000);
5988     /* XXX : not implemented */
5989     spr_register(env, SPR_750FX_HID2, "HID2",
5990                  SPR_NOACCESS, SPR_NOACCESS,
5991                  &spr_read_generic, &spr_write_generic,
5992                  0x00000000);
5993     /* XXX : not implemented */
5994     spr_register(env, SPR_970_HID5, "HID5",
5995                  SPR_NOACCESS, SPR_NOACCESS,
5996                  &spr_read_generic, &spr_write_generic,
5997                  POWERPC970_HID5_INIT);
5998     /* XXX : not implemented */
5999     spr_register(env, SPR_L2CR, "L2CR",
6000                  SPR_NOACCESS, SPR_NOACCESS,
6001                  &spr_read_generic, &spr_write_generic,
6002                  0x00000000);
6003     /* Memory management */
6004     /* XXX: not correct */
6005     gen_low_BATs(env);
6006     /* XXX : not implemented */
6007     spr_register(env, SPR_MMUCFG, "MMUCFG",
6008                  SPR_NOACCESS, SPR_NOACCESS,
6009                  &spr_read_generic, SPR_NOACCESS,
6010                  0x00000000); /* TOFIX */
6011     /* XXX : not implemented */
6012     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6013                  SPR_NOACCESS, SPR_NOACCESS,
6014                  &spr_read_generic, &spr_write_generic,
6015                  0x00000000); /* TOFIX */
6016     spr_register(env, SPR_HIOR, "SPR_HIOR",
6017                  SPR_NOACCESS, SPR_NOACCESS,
6018                  &spr_read_hior, &spr_write_hior,
6019                  0x00000000);
6020 #if !defined(CONFIG_USER_ONLY)
6021     env->slb_nr = 32;
6022 #endif
6023     init_excp_970(env);
6024     env->dcache_line_size = 128;
6025     env->icache_line_size = 128;
6026     /* Allocate hardware IRQ controller */
6027     ppc970_irq_init(env);
6028     /* Can't find information on what this should be on reset.  This
6029      * value is the one used by 74xx processors. */
6030     vscr_init(env, 0x00010000);
6031 }
6032
6033 /* PowerPC 970FX (aka G5)                                                    */
6034 #define POWERPC_INSNS_970FX  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6035                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6036                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6037                               PPC_FLOAT_STFIWX |                              \
6038                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6039                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6040                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6041                               PPC_64B | PPC_ALTIVEC |                         \
6042                               PPC_SEGMENT_64B | PPC_SLBI)
6043 #define POWERPC_MSRM_970FX   (0x800000000204FF36ULL)
6044 #define POWERPC_MMU_970FX    (POWERPC_MMU_64B)
6045 #define POWERPC_EXCP_970FX   (POWERPC_EXCP_970)
6046 #define POWERPC_INPUT_970FX  (PPC_FLAGS_INPUT_970)
6047 #define POWERPC_BFDM_970FX   (bfd_mach_ppc64)
6048 #define POWERPC_FLAG_970FX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6049                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6050                               POWERPC_FLAG_BUS_CLK)
6051
6052 static int check_pow_970FX (CPUPPCState *env)
6053 {
6054     if (env->spr[SPR_HID0] & 0x00600000)
6055         return 1;
6056
6057     return 0;
6058 }
6059
6060 static void init_proc_970FX (CPUPPCState *env)
6061 {
6062     gen_spr_ne_601(env);
6063     gen_spr_7xx(env);
6064     /* Time base */
6065     gen_tbl(env);
6066     /* Hardware implementation registers */
6067     /* XXX : not implemented */
6068     spr_register(env, SPR_HID0, "HID0",
6069                  SPR_NOACCESS, SPR_NOACCESS,
6070                  &spr_read_generic, &spr_write_clear,
6071                  0x60000000);
6072     /* XXX : not implemented */
6073     spr_register(env, SPR_HID1, "HID1",
6074                  SPR_NOACCESS, SPR_NOACCESS,
6075                  &spr_read_generic, &spr_write_generic,
6076                  0x00000000);
6077     /* XXX : not implemented */
6078     spr_register(env, SPR_750FX_HID2, "HID2",
6079                  SPR_NOACCESS, SPR_NOACCESS,
6080                  &spr_read_generic, &spr_write_generic,
6081                  0x00000000);
6082     /* XXX : not implemented */
6083     spr_register(env, SPR_970_HID5, "HID5",
6084                  SPR_NOACCESS, SPR_NOACCESS,
6085                  &spr_read_generic, &spr_write_generic,
6086                  POWERPC970_HID5_INIT);
6087     /* XXX : not implemented */
6088     spr_register(env, SPR_L2CR, "L2CR",
6089                  SPR_NOACCESS, SPR_NOACCESS,
6090                  &spr_read_generic, &spr_write_generic,
6091                  0x00000000);
6092     /* Memory management */
6093     /* XXX: not correct */
6094     gen_low_BATs(env);
6095     /* XXX : not implemented */
6096     spr_register(env, SPR_MMUCFG, "MMUCFG",
6097                  SPR_NOACCESS, SPR_NOACCESS,
6098                  &spr_read_generic, SPR_NOACCESS,
6099                  0x00000000); /* TOFIX */
6100     /* XXX : not implemented */
6101     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6102                  SPR_NOACCESS, SPR_NOACCESS,
6103                  &spr_read_generic, &spr_write_generic,
6104                  0x00000000); /* TOFIX */
6105     spr_register(env, SPR_HIOR, "SPR_HIOR",
6106                  SPR_NOACCESS, SPR_NOACCESS,
6107                  &spr_read_hior, &spr_write_hior,
6108                  0x00000000);
6109     spr_register(env, SPR_CTRL, "SPR_CTRL",
6110                  SPR_NOACCESS, SPR_NOACCESS,
6111                  &spr_read_generic, &spr_write_generic,
6112                  0x00000000);
6113     spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6114                  SPR_NOACCESS, SPR_NOACCESS,
6115                  &spr_read_generic, &spr_write_generic,
6116                  0x00000000);
6117     spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6118                  &spr_read_generic, &spr_write_generic,
6119                  &spr_read_generic, &spr_write_generic,
6120                  0x00000000);
6121 #if !defined(CONFIG_USER_ONLY)
6122     env->slb_nr = 64;
6123 #endif
6124     init_excp_970(env);
6125     env->dcache_line_size = 128;
6126     env->icache_line_size = 128;
6127     /* Allocate hardware IRQ controller */
6128     ppc970_irq_init(env);
6129     /* Can't find information on what this should be on reset.  This
6130      * value is the one used by 74xx processors. */
6131     vscr_init(env, 0x00010000);
6132 }
6133
6134 /* PowerPC 970 GX                                                            */
6135 #define POWERPC_INSNS_970GX  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6136                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6137                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6138                               PPC_FLOAT_STFIWX |                              \
6139                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6140                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6141                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6142                               PPC_64B | PPC_ALTIVEC |                         \
6143                               PPC_SEGMENT_64B | PPC_SLBI)
6144 #define POWERPC_MSRM_970GX   (0x800000000204FF36ULL)
6145 #define POWERPC_MMU_970GX    (POWERPC_MMU_64B)
6146 #define POWERPC_EXCP_970GX   (POWERPC_EXCP_970)
6147 #define POWERPC_INPUT_970GX  (PPC_FLAGS_INPUT_970)
6148 #define POWERPC_BFDM_970GX   (bfd_mach_ppc64)
6149 #define POWERPC_FLAG_970GX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6150                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6151                               POWERPC_FLAG_BUS_CLK)
6152
6153 static int check_pow_970GX (CPUPPCState *env)
6154 {
6155     if (env->spr[SPR_HID0] & 0x00600000)
6156         return 1;
6157
6158     return 0;
6159 }
6160
6161 static void init_proc_970GX (CPUPPCState *env)
6162 {
6163     gen_spr_ne_601(env);
6164     gen_spr_7xx(env);
6165     /* Time base */
6166     gen_tbl(env);
6167     /* Hardware implementation registers */
6168     /* XXX : not implemented */
6169     spr_register(env, SPR_HID0, "HID0",
6170                  SPR_NOACCESS, SPR_NOACCESS,
6171                  &spr_read_generic, &spr_write_clear,
6172                  0x60000000);
6173     /* XXX : not implemented */
6174     spr_register(env, SPR_HID1, "HID1",
6175                  SPR_NOACCESS, SPR_NOACCESS,
6176                  &spr_read_generic, &spr_write_generic,
6177                  0x00000000);
6178     /* XXX : not implemented */
6179     spr_register(env, SPR_750FX_HID2, "HID2",
6180                  SPR_NOACCESS, SPR_NOACCESS,
6181                  &spr_read_generic, &spr_write_generic,
6182                  0x00000000);
6183     /* XXX : not implemented */
6184     spr_register(env, SPR_970_HID5, "HID5",
6185                  SPR_NOACCESS, SPR_NOACCESS,
6186                  &spr_read_generic, &spr_write_generic,
6187                  POWERPC970_HID5_INIT);
6188     /* XXX : not implemented */
6189     spr_register(env, SPR_L2CR, "L2CR",
6190                  SPR_NOACCESS, SPR_NOACCESS,
6191                  &spr_read_generic, &spr_write_generic,
6192                  0x00000000);
6193     /* Memory management */
6194     /* XXX: not correct */
6195     gen_low_BATs(env);
6196     /* XXX : not implemented */
6197     spr_register(env, SPR_MMUCFG, "MMUCFG",
6198                  SPR_NOACCESS, SPR_NOACCESS,
6199                  &spr_read_generic, SPR_NOACCESS,
6200                  0x00000000); /* TOFIX */
6201     /* XXX : not implemented */
6202     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6203                  SPR_NOACCESS, SPR_NOACCESS,
6204                  &spr_read_generic, &spr_write_generic,
6205                  0x00000000); /* TOFIX */
6206     spr_register(env, SPR_HIOR, "SPR_HIOR",
6207                  SPR_NOACCESS, SPR_NOACCESS,
6208                  &spr_read_hior, &spr_write_hior,
6209                  0x00000000);
6210 #if !defined(CONFIG_USER_ONLY)
6211     env->slb_nr = 32;
6212 #endif
6213     init_excp_970(env);
6214     env->dcache_line_size = 128;
6215     env->icache_line_size = 128;
6216     /* Allocate hardware IRQ controller */
6217     ppc970_irq_init(env);
6218     /* Can't find information on what this should be on reset.  This
6219      * value is the one used by 74xx processors. */
6220     vscr_init(env, 0x00010000);
6221 }
6222
6223 /* PowerPC 970 MP                                                            */
6224 #define POWERPC_INSNS_970MP  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6225                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6226                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6227                               PPC_FLOAT_STFIWX |                              \
6228                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6229                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6230                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6231                               PPC_64B | PPC_ALTIVEC |                         \
6232                               PPC_SEGMENT_64B | PPC_SLBI)
6233 #define POWERPC_MSRM_970MP   (0x900000000204FF36ULL)
6234 #define POWERPC_MMU_970MP    (POWERPC_MMU_64B)
6235 #define POWERPC_EXCP_970MP   (POWERPC_EXCP_970)
6236 #define POWERPC_INPUT_970MP  (PPC_FLAGS_INPUT_970)
6237 #define POWERPC_BFDM_970MP   (bfd_mach_ppc64)
6238 #define POWERPC_FLAG_970MP   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6239                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6240                               POWERPC_FLAG_BUS_CLK)
6241
6242 static int check_pow_970MP (CPUPPCState *env)
6243 {
6244     if (env->spr[SPR_HID0] & 0x01C00000)
6245         return 1;
6246
6247     return 0;
6248 }
6249
6250 static void init_proc_970MP (CPUPPCState *env)
6251 {
6252     gen_spr_ne_601(env);
6253     gen_spr_7xx(env);
6254     /* Time base */
6255     gen_tbl(env);
6256     /* Hardware implementation registers */
6257     /* XXX : not implemented */
6258     spr_register(env, SPR_HID0, "HID0",
6259                  SPR_NOACCESS, SPR_NOACCESS,
6260                  &spr_read_generic, &spr_write_clear,
6261                  0x60000000);
6262     /* XXX : not implemented */
6263     spr_register(env, SPR_HID1, "HID1",
6264                  SPR_NOACCESS, SPR_NOACCESS,
6265                  &spr_read_generic, &spr_write_generic,
6266                  0x00000000);
6267     /* XXX : not implemented */
6268     spr_register(env, SPR_750FX_HID2, "HID2",
6269                  SPR_NOACCESS, SPR_NOACCESS,
6270                  &spr_read_generic, &spr_write_generic,
6271                  0x00000000);
6272     /* XXX : not implemented */
6273     spr_register(env, SPR_970_HID5, "HID5",
6274                  SPR_NOACCESS, SPR_NOACCESS,
6275                  &spr_read_generic, &spr_write_generic,
6276                  POWERPC970_HID5_INIT);
6277     /* XXX : not implemented */
6278     spr_register(env, SPR_L2CR, "L2CR",
6279                  SPR_NOACCESS, SPR_NOACCESS,
6280                  &spr_read_generic, &spr_write_generic,
6281                  0x00000000);
6282     /* Memory management */
6283     /* XXX: not correct */
6284     gen_low_BATs(env);
6285     /* XXX : not implemented */
6286     spr_register(env, SPR_MMUCFG, "MMUCFG",
6287                  SPR_NOACCESS, SPR_NOACCESS,
6288                  &spr_read_generic, SPR_NOACCESS,
6289                  0x00000000); /* TOFIX */
6290     /* XXX : not implemented */
6291     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6292                  SPR_NOACCESS, SPR_NOACCESS,
6293                  &spr_read_generic, &spr_write_generic,
6294                  0x00000000); /* TOFIX */
6295     spr_register(env, SPR_HIOR, "SPR_HIOR",
6296                  SPR_NOACCESS, SPR_NOACCESS,
6297                  &spr_read_hior, &spr_write_hior,
6298                  0x00000000);
6299 #if !defined(CONFIG_USER_ONLY)
6300     env->slb_nr = 32;
6301 #endif
6302     init_excp_970(env);
6303     env->dcache_line_size = 128;
6304     env->icache_line_size = 128;
6305     /* Allocate hardware IRQ controller */
6306     ppc970_irq_init(env);
6307     /* Can't find information on what this should be on reset.  This
6308      * value is the one used by 74xx processors. */
6309     vscr_init(env, 0x00010000);
6310 }
6311
6312 /* PowerPC 620                                                               */
6313 #define POWERPC_INSNS_620    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6314                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6315                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6316                               PPC_FLOAT_STFIWX |                              \
6317                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
6318                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6319                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6320                               PPC_SEGMENT | PPC_EXTERN |                      \
6321                               PPC_64B | PPC_SLBI)
6322 #define POWERPC_MSRM_620     (0x800000000005FF77ULL)
6323 //#define POWERPC_MMU_620      (POWERPC_MMU_620)
6324 #define POWERPC_EXCP_620     (POWERPC_EXCP_970)
6325 #define POWERPC_INPUT_620    (PPC_FLAGS_INPUT_6xx)
6326 #define POWERPC_BFDM_620     (bfd_mach_ppc64)
6327 #define POWERPC_FLAG_620     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |            \
6328                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6329 #define check_pow_620        check_pow_nocheck /* Check this */
6330
6331 __attribute__ (( unused ))
6332 static void init_proc_620 (CPUPPCState *env)
6333 {
6334     gen_spr_ne_601(env);
6335     gen_spr_620(env);
6336     /* Time base */
6337     gen_tbl(env);
6338     /* Hardware implementation registers */
6339     /* XXX : not implemented */
6340     spr_register(env, SPR_HID0, "HID0",
6341                  SPR_NOACCESS, SPR_NOACCESS,
6342                  &spr_read_generic, &spr_write_generic,
6343                  0x00000000);
6344     /* Memory management */
6345     gen_low_BATs(env);
6346     init_excp_620(env);
6347     env->dcache_line_size = 64;
6348     env->icache_line_size = 64;
6349     /* Allocate hardware IRQ controller */
6350     ppc6xx_irq_init(env);
6351 }
6352 #endif /* defined (TARGET_PPC64) */
6353
6354 /* Default 32 bits PowerPC target will be 604 */
6355 #define CPU_POWERPC_PPC32     CPU_POWERPC_604
6356 #define POWERPC_INSNS_PPC32   POWERPC_INSNS_604
6357 #define POWERPC_MSRM_PPC32    POWERPC_MSRM_604
6358 #define POWERPC_MMU_PPC32     POWERPC_MMU_604
6359 #define POWERPC_EXCP_PPC32    POWERPC_EXCP_604
6360 #define POWERPC_INPUT_PPC32   POWERPC_INPUT_604
6361 #define POWERPC_BFDM_PPC32    POWERPC_BFDM_604
6362 #define POWERPC_FLAG_PPC32    POWERPC_FLAG_604
6363 #define check_pow_PPC32       check_pow_604
6364 #define init_proc_PPC32       init_proc_604
6365
6366 /* Default 64 bits PowerPC target will be 970 FX */
6367 #define CPU_POWERPC_PPC64     CPU_POWERPC_970FX
6368 #define POWERPC_INSNS_PPC64   POWERPC_INSNS_970FX
6369 #define POWERPC_MSRM_PPC64    POWERPC_MSRM_970FX
6370 #define POWERPC_MMU_PPC64     POWERPC_MMU_970FX
6371 #define POWERPC_EXCP_PPC64    POWERPC_EXCP_970FX
6372 #define POWERPC_INPUT_PPC64   POWERPC_INPUT_970FX
6373 #define POWERPC_BFDM_PPC64    POWERPC_BFDM_970FX
6374 #define POWERPC_FLAG_PPC64    POWERPC_FLAG_970FX
6375 #define check_pow_PPC64       check_pow_970FX
6376 #define init_proc_PPC64       init_proc_970FX
6377
6378 /* Default PowerPC target will be PowerPC 32 */
6379 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6380 #define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC64
6381 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6382 #define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC64
6383 #define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC64
6384 #define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC64
6385 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6386 #define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC64
6387 #define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC64
6388 #define check_pow_DEFAULT     check_pow_PPC64
6389 #define init_proc_DEFAULT     init_proc_PPC64
6390 #else
6391 #define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC32
6392 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6393 #define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC32
6394 #define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC32
6395 #define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC32
6396 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6397 #define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC32
6398 #define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC32
6399 #define check_pow_DEFAULT     check_pow_PPC32
6400 #define init_proc_DEFAULT     init_proc_PPC32
6401 #endif
6402
6403 /*****************************************************************************/
6404 /* PVR definitions for most known PowerPC                                    */
6405 enum {
6406     /* PowerPC 401 family */
6407     /* Generic PowerPC 401 */
6408 #define CPU_POWERPC_401              CPU_POWERPC_401G2
6409     /* PowerPC 401 cores */
6410     CPU_POWERPC_401A1              = 0x00210000,
6411     CPU_POWERPC_401B2              = 0x00220000,
6412 #if 0
6413     CPU_POWERPC_401B3              = xxx,
6414 #endif
6415     CPU_POWERPC_401C2              = 0x00230000,
6416     CPU_POWERPC_401D2              = 0x00240000,
6417     CPU_POWERPC_401E2              = 0x00250000,
6418     CPU_POWERPC_401F2              = 0x00260000,
6419     CPU_POWERPC_401G2              = 0x00270000,
6420     /* PowerPC 401 microcontrolers */
6421 #if 0
6422     CPU_POWERPC_401GF              = xxx,
6423 #endif
6424 #define CPU_POWERPC_IOP480           CPU_POWERPC_401B2
6425     /* IBM Processor for Network Resources */
6426     CPU_POWERPC_COBRA              = 0x10100000, /* XXX: 405 ? */
6427 #if 0
6428     CPU_POWERPC_XIPCHIP            = xxx,
6429 #endif
6430     /* PowerPC 403 family */
6431     /* Generic PowerPC 403 */
6432 #define CPU_POWERPC_403              CPU_POWERPC_403GC
6433     /* PowerPC 403 microcontrollers */
6434     CPU_POWERPC_403GA              = 0x00200011,
6435     CPU_POWERPC_403GB              = 0x00200100,
6436     CPU_POWERPC_403GC              = 0x00200200,
6437     CPU_POWERPC_403GCX             = 0x00201400,
6438 #if 0
6439     CPU_POWERPC_403GP              = xxx,
6440 #endif
6441     /* PowerPC 405 family */
6442     /* Generic PowerPC 405 */
6443 #define CPU_POWERPC_405              CPU_POWERPC_405D4
6444     /* PowerPC 405 cores */
6445 #if 0
6446     CPU_POWERPC_405A3              = xxx,
6447 #endif
6448 #if 0
6449     CPU_POWERPC_405A4              = xxx,
6450 #endif
6451 #if 0
6452     CPU_POWERPC_405B3              = xxx,
6453 #endif
6454 #if 0
6455     CPU_POWERPC_405B4              = xxx,
6456 #endif
6457 #if 0
6458     CPU_POWERPC_405C3              = xxx,
6459 #endif
6460 #if 0
6461     CPU_POWERPC_405C4              = xxx,
6462 #endif
6463     CPU_POWERPC_405D2              = 0x20010000,
6464 #if 0
6465     CPU_POWERPC_405D3              = xxx,
6466 #endif
6467     CPU_POWERPC_405D4              = 0x41810000,
6468 #if 0
6469     CPU_POWERPC_405D5              = xxx,
6470 #endif
6471 #if 0
6472     CPU_POWERPC_405E4              = xxx,
6473 #endif
6474 #if 0
6475     CPU_POWERPC_405F4              = xxx,
6476 #endif
6477 #if 0
6478     CPU_POWERPC_405F5              = xxx,
6479 #endif
6480 #if 0
6481     CPU_POWERPC_405F6              = xxx,
6482 #endif
6483     /* PowerPC 405 microcontrolers */
6484     /* XXX: missing 0x200108a0 */
6485 #define CPU_POWERPC_405CR            CPU_POWERPC_405CRc
6486     CPU_POWERPC_405CRa             = 0x40110041,
6487     CPU_POWERPC_405CRb             = 0x401100C5,
6488     CPU_POWERPC_405CRc             = 0x40110145,
6489     CPU_POWERPC_405EP              = 0x51210950,
6490 #if 0
6491     CPU_POWERPC_405EXr             = xxx,
6492 #endif
6493     CPU_POWERPC_405EZ              = 0x41511460, /* 0x51210950 ? */
6494 #if 0
6495     CPU_POWERPC_405FX              = xxx,
6496 #endif
6497 #define CPU_POWERPC_405GP            CPU_POWERPC_405GPd
6498     CPU_POWERPC_405GPa             = 0x40110000,
6499     CPU_POWERPC_405GPb             = 0x40110040,
6500     CPU_POWERPC_405GPc             = 0x40110082,
6501     CPU_POWERPC_405GPd             = 0x401100C4,
6502 #define CPU_POWERPC_405GPe           CPU_POWERPC_405CRc
6503     CPU_POWERPC_405GPR             = 0x50910951,
6504 #if 0
6505     CPU_POWERPC_405H               = xxx,
6506 #endif
6507 #if 0
6508     CPU_POWERPC_405L               = xxx,
6509 #endif
6510     CPU_POWERPC_405LP              = 0x41F10000,
6511 #if 0
6512     CPU_POWERPC_405PM              = xxx,
6513 #endif
6514 #if 0
6515     CPU_POWERPC_405PS              = xxx,
6516 #endif
6517 #if 0
6518     CPU_POWERPC_405S               = xxx,
6519 #endif
6520     /* IBM network processors */
6521     CPU_POWERPC_NPE405H            = 0x414100C0,
6522     CPU_POWERPC_NPE405H2           = 0x41410140,
6523     CPU_POWERPC_NPE405L            = 0x416100C0,
6524     CPU_POWERPC_NPE4GS3            = 0x40B10000,
6525 #if 0
6526     CPU_POWERPC_NPCxx1             = xxx,
6527 #endif
6528 #if 0
6529     CPU_POWERPC_NPR161             = xxx,
6530 #endif
6531 #if 0
6532     CPU_POWERPC_LC77700            = xxx,
6533 #endif
6534     /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6535 #if 0
6536     CPU_POWERPC_STB01000           = xxx,
6537 #endif
6538 #if 0
6539     CPU_POWERPC_STB01010           = xxx,
6540 #endif
6541 #if 0
6542     CPU_POWERPC_STB0210            = xxx, /* 401B3 */
6543 #endif
6544     CPU_POWERPC_STB03              = 0x40310000, /* 0x40130000 ? */
6545 #if 0
6546     CPU_POWERPC_STB043             = xxx,
6547 #endif
6548 #if 0
6549     CPU_POWERPC_STB045             = xxx,
6550 #endif
6551     CPU_POWERPC_STB04              = 0x41810000,
6552     CPU_POWERPC_STB25              = 0x51510950,
6553 #if 0
6554     CPU_POWERPC_STB130             = xxx,
6555 #endif
6556     /* Xilinx cores */
6557     CPU_POWERPC_X2VP4              = 0x20010820,
6558 #define CPU_POWERPC_X2VP7            CPU_POWERPC_X2VP4
6559     CPU_POWERPC_X2VP20             = 0x20010860,
6560 #define CPU_POWERPC_X2VP50           CPU_POWERPC_X2VP20
6561 #if 0
6562     CPU_POWERPC_ZL10310            = xxx,
6563 #endif
6564 #if 0
6565     CPU_POWERPC_ZL10311            = xxx,
6566 #endif
6567 #if 0
6568     CPU_POWERPC_ZL10320            = xxx,
6569 #endif
6570 #if 0
6571     CPU_POWERPC_ZL10321            = xxx,
6572 #endif
6573     /* PowerPC 440 family */
6574     /* Generic PowerPC 440 */
6575 #define CPU_POWERPC_440              CPU_POWERPC_440GXf
6576     /* PowerPC 440 cores */
6577 #if 0
6578     CPU_POWERPC_440A4              = xxx,
6579 #endif
6580     CPU_POWERPC_440_XILINX         = 0x7ff21910,
6581 #if 0
6582     CPU_POWERPC_440A5              = xxx,
6583 #endif
6584 #if 0
6585     CPU_POWERPC_440B4              = xxx,
6586 #endif
6587 #if 0
6588     CPU_POWERPC_440F5              = xxx,
6589 #endif
6590 #if 0
6591     CPU_POWERPC_440G5              = xxx,
6592 #endif
6593 #if 0
6594     CPU_POWERPC_440H4              = xxx,
6595 #endif
6596 #if 0
6597     CPU_POWERPC_440H6              = xxx,
6598 #endif
6599     /* PowerPC 440 microcontrolers */
6600 #define CPU_POWERPC_440EP            CPU_POWERPC_440EPb
6601     CPU_POWERPC_440EPa             = 0x42221850,
6602     CPU_POWERPC_440EPb             = 0x422218D3,
6603 #define CPU_POWERPC_440GP            CPU_POWERPC_440GPc
6604     CPU_POWERPC_440GPb             = 0x40120440,
6605     CPU_POWERPC_440GPc             = 0x40120481,
6606 #define CPU_POWERPC_440GR            CPU_POWERPC_440GRa
6607 #define CPU_POWERPC_440GRa           CPU_POWERPC_440EPb
6608     CPU_POWERPC_440GRX             = 0x200008D0,
6609 #define CPU_POWERPC_440EPX           CPU_POWERPC_440GRX
6610 #define CPU_POWERPC_440GX            CPU_POWERPC_440GXf
6611     CPU_POWERPC_440GXa             = 0x51B21850,
6612     CPU_POWERPC_440GXb             = 0x51B21851,
6613     CPU_POWERPC_440GXc             = 0x51B21892,
6614     CPU_POWERPC_440GXf             = 0x51B21894,
6615 #if 0
6616     CPU_POWERPC_440S               = xxx,
6617 #endif
6618     CPU_POWERPC_440SP              = 0x53221850,
6619     CPU_POWERPC_440SP2             = 0x53221891,
6620     CPU_POWERPC_440SPE             = 0x53421890,
6621     /* PowerPC 460 family */
6622 #if 0
6623     /* Generic PowerPC 464 */
6624 #define CPU_POWERPC_464              CPU_POWERPC_464H90
6625 #endif
6626     /* PowerPC 464 microcontrolers */
6627 #if 0
6628     CPU_POWERPC_464H90             = xxx,
6629 #endif
6630 #if 0
6631     CPU_POWERPC_464H90FP           = xxx,
6632 #endif
6633     /* Freescale embedded PowerPC cores */
6634     /* PowerPC MPC 5xx cores (aka RCPU) */
6635     CPU_POWERPC_MPC5xx             = 0x00020020,
6636 #define CPU_POWERPC_MGT560           CPU_POWERPC_MPC5xx
6637 #define CPU_POWERPC_MPC509           CPU_POWERPC_MPC5xx
6638 #define CPU_POWERPC_MPC533           CPU_POWERPC_MPC5xx
6639 #define CPU_POWERPC_MPC534           CPU_POWERPC_MPC5xx
6640 #define CPU_POWERPC_MPC555           CPU_POWERPC_MPC5xx
6641 #define CPU_POWERPC_MPC556           CPU_POWERPC_MPC5xx
6642 #define CPU_POWERPC_MPC560           CPU_POWERPC_MPC5xx
6643 #define CPU_POWERPC_MPC561           CPU_POWERPC_MPC5xx
6644 #define CPU_POWERPC_MPC562           CPU_POWERPC_MPC5xx
6645 #define CPU_POWERPC_MPC563           CPU_POWERPC_MPC5xx
6646 #define CPU_POWERPC_MPC564           CPU_POWERPC_MPC5xx
6647 #define CPU_POWERPC_MPC565           CPU_POWERPC_MPC5xx
6648 #define CPU_POWERPC_MPC566           CPU_POWERPC_MPC5xx
6649     /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6650     CPU_POWERPC_MPC8xx             = 0x00500000,
6651 #define CPU_POWERPC_MGT823           CPU_POWERPC_MPC8xx
6652 #define CPU_POWERPC_MPC821           CPU_POWERPC_MPC8xx
6653 #define CPU_POWERPC_MPC823           CPU_POWERPC_MPC8xx
6654 #define CPU_POWERPC_MPC850           CPU_POWERPC_MPC8xx
6655 #define CPU_POWERPC_MPC852T          CPU_POWERPC_MPC8xx
6656 #define CPU_POWERPC_MPC855T          CPU_POWERPC_MPC8xx
6657 #define CPU_POWERPC_MPC857           CPU_POWERPC_MPC8xx
6658 #define CPU_POWERPC_MPC859           CPU_POWERPC_MPC8xx
6659 #define CPU_POWERPC_MPC860           CPU_POWERPC_MPC8xx
6660 #define CPU_POWERPC_MPC862           CPU_POWERPC_MPC8xx
6661 #define CPU_POWERPC_MPC866           CPU_POWERPC_MPC8xx
6662 #define CPU_POWERPC_MPC870           CPU_POWERPC_MPC8xx
6663 #define CPU_POWERPC_MPC875           CPU_POWERPC_MPC8xx
6664 #define CPU_POWERPC_MPC880           CPU_POWERPC_MPC8xx
6665 #define CPU_POWERPC_MPC885           CPU_POWERPC_MPC8xx
6666     /* G2 cores (aka PowerQUICC-II) */
6667     CPU_POWERPC_G2                 = 0x00810011,
6668     CPU_POWERPC_G2H4               = 0x80811010,
6669     CPU_POWERPC_G2gp               = 0x80821010,
6670     CPU_POWERPC_G2ls               = 0x90810010,
6671     CPU_POWERPC_MPC603             = 0x00810100,
6672     CPU_POWERPC_G2_HIP3            = 0x00810101,
6673     CPU_POWERPC_G2_HIP4            = 0x80811014,
6674     /*   G2_LE core (aka PowerQUICC-II) */
6675     CPU_POWERPC_G2LE               = 0x80820010,
6676     CPU_POWERPC_G2LEgp             = 0x80822010,
6677     CPU_POWERPC_G2LEls             = 0xA0822010,
6678     CPU_POWERPC_G2LEgp1            = 0x80822011,
6679     CPU_POWERPC_G2LEgp3            = 0x80822013,
6680     /* MPC52xx microcontrollers  */
6681     /* XXX: MPC 5121 ? */
6682 #define CPU_POWERPC_MPC52xx          CPU_POWERPC_MPC5200
6683 #define CPU_POWERPC_MPC5200          CPU_POWERPC_MPC5200_v12
6684 #define CPU_POWERPC_MPC5200_v10      CPU_POWERPC_G2LEgp1
6685 #define CPU_POWERPC_MPC5200_v11      CPU_POWERPC_G2LEgp1
6686 #define CPU_POWERPC_MPC5200_v12      CPU_POWERPC_G2LEgp1
6687 #define CPU_POWERPC_MPC5200B         CPU_POWERPC_MPC5200B_v21
6688 #define CPU_POWERPC_MPC5200B_v20     CPU_POWERPC_G2LEgp1
6689 #define CPU_POWERPC_MPC5200B_v21     CPU_POWERPC_G2LEgp1
6690     /* MPC82xx microcontrollers */
6691 #define CPU_POWERPC_MPC82xx          CPU_POWERPC_MPC8280
6692 #define CPU_POWERPC_MPC8240          CPU_POWERPC_MPC603
6693 #define CPU_POWERPC_MPC8241          CPU_POWERPC_G2_HIP4
6694 #define CPU_POWERPC_MPC8245          CPU_POWERPC_G2_HIP4
6695 #define CPU_POWERPC_MPC8247          CPU_POWERPC_G2LEgp3
6696 #define CPU_POWERPC_MPC8248          CPU_POWERPC_G2LEgp3
6697 #define CPU_POWERPC_MPC8250          CPU_POWERPC_MPC8250_HiP4
6698 #define CPU_POWERPC_MPC8250_HiP3     CPU_POWERPC_G2_HIP3
6699 #define CPU_POWERPC_MPC8250_HiP4     CPU_POWERPC_G2_HIP4
6700 #define CPU_POWERPC_MPC8255          CPU_POWERPC_MPC8255_HiP4
6701 #define CPU_POWERPC_MPC8255_HiP3     CPU_POWERPC_G2_HIP3
6702 #define CPU_POWERPC_MPC8255_HiP4     CPU_POWERPC_G2_HIP4
6703 #define CPU_POWERPC_MPC8260          CPU_POWERPC_MPC8260_HiP4
6704 #define CPU_POWERPC_MPC8260_HiP3     CPU_POWERPC_G2_HIP3
6705 #define CPU_POWERPC_MPC8260_HiP4     CPU_POWERPC_G2_HIP4
6706 #define CPU_POWERPC_MPC8264          CPU_POWERPC_MPC8264_HiP4
6707 #define CPU_POWERPC_MPC8264_HiP3     CPU_POWERPC_G2_HIP3
6708 #define CPU_POWERPC_MPC8264_HiP4     CPU_POWERPC_G2_HIP4
6709 #define CPU_POWERPC_MPC8265          CPU_POWERPC_MPC8265_HiP4
6710 #define CPU_POWERPC_MPC8265_HiP3     CPU_POWERPC_G2_HIP3
6711 #define CPU_POWERPC_MPC8265_HiP4     CPU_POWERPC_G2_HIP4
6712 #define CPU_POWERPC_MPC8266          CPU_POWERPC_MPC8266_HiP4
6713 #define CPU_POWERPC_MPC8266_HiP3     CPU_POWERPC_G2_HIP3
6714 #define CPU_POWERPC_MPC8266_HiP4     CPU_POWERPC_G2_HIP4
6715 #define CPU_POWERPC_MPC8270          CPU_POWERPC_G2LEgp3
6716 #define CPU_POWERPC_MPC8271          CPU_POWERPC_G2LEgp3
6717 #define CPU_POWERPC_MPC8272          CPU_POWERPC_G2LEgp3
6718 #define CPU_POWERPC_MPC8275          CPU_POWERPC_G2LEgp3
6719 #define CPU_POWERPC_MPC8280          CPU_POWERPC_G2LEgp3
6720     /* e200 family */
6721     /* e200 cores */
6722 #define CPU_POWERPC_e200             CPU_POWERPC_e200z6
6723 #if 0
6724     CPU_POWERPC_e200z0             = xxx,
6725 #endif
6726 #if 0
6727     CPU_POWERPC_e200z1             = xxx,
6728 #endif
6729 #if 0 /* ? */
6730     CPU_POWERPC_e200z3             = 0x81120000,
6731 #endif
6732     CPU_POWERPC_e200z5             = 0x81000000,
6733     CPU_POWERPC_e200z6             = 0x81120000,
6734     /* MPC55xx microcontrollers */
6735 #define CPU_POWERPC_MPC55xx          CPU_POWERPC_MPC5567
6736 #if 0
6737 #define CPU_POWERPC_MPC5514E         CPU_POWERPC_MPC5514E_v1
6738 #define CPU_POWERPC_MPC5514E_v0      CPU_POWERPC_e200z0
6739 #define CPU_POWERPC_MPC5514E_v1      CPU_POWERPC_e200z1
6740 #define CPU_POWERPC_MPC5514G         CPU_POWERPC_MPC5514G_v1
6741 #define CPU_POWERPC_MPC5514G_v0      CPU_POWERPC_e200z0
6742 #define CPU_POWERPC_MPC5514G_v1      CPU_POWERPC_e200z1
6743 #define CPU_POWERPC_MPC5515S         CPU_POWERPC_e200z1
6744 #define CPU_POWERPC_MPC5516E         CPU_POWERPC_MPC5516E_v1
6745 #define CPU_POWERPC_MPC5516E_v0      CPU_POWERPC_e200z0
6746 #define CPU_POWERPC_MPC5516E_v1      CPU_POWERPC_e200z1
6747 #define CPU_POWERPC_MPC5516G         CPU_POWERPC_MPC5516G_v1
6748 #define CPU_POWERPC_MPC5516G_v0      CPU_POWERPC_e200z0
6749 #define CPU_POWERPC_MPC5516G_v1      CPU_POWERPC_e200z1
6750 #define CPU_POWERPC_MPC5516S         CPU_POWERPC_e200z1
6751 #endif
6752 #if 0
6753 #define CPU_POWERPC_MPC5533          CPU_POWERPC_e200z3
6754 #define CPU_POWERPC_MPC5534          CPU_POWERPC_e200z3
6755 #endif
6756 #define CPU_POWERPC_MPC5553          CPU_POWERPC_e200z6
6757 #define CPU_POWERPC_MPC5554          CPU_POWERPC_e200z6
6758 #define CPU_POWERPC_MPC5561          CPU_POWERPC_e200z6
6759 #define CPU_POWERPC_MPC5565          CPU_POWERPC_e200z6
6760 #define CPU_POWERPC_MPC5566          CPU_POWERPC_e200z6
6761 #define CPU_POWERPC_MPC5567          CPU_POWERPC_e200z6
6762     /* e300 family */
6763     /* e300 cores */
6764 #define CPU_POWERPC_e300             CPU_POWERPC_e300c3
6765     CPU_POWERPC_e300c1             = 0x00830010,
6766     CPU_POWERPC_e300c2             = 0x00840010,
6767     CPU_POWERPC_e300c3             = 0x00850010,
6768     CPU_POWERPC_e300c4             = 0x00860010,
6769     /* MPC83xx microcontrollers */
6770 #define CPU_POWERPC_MPC831x          CPU_POWERPC_e300c3
6771 #define CPU_POWERPC_MPC832x          CPU_POWERPC_e300c2
6772 #define CPU_POWERPC_MPC834x          CPU_POWERPC_e300c1
6773 #define CPU_POWERPC_MPC835x          CPU_POWERPC_e300c1
6774 #define CPU_POWERPC_MPC836x          CPU_POWERPC_e300c1
6775 #define CPU_POWERPC_MPC837x          CPU_POWERPC_e300c4
6776     /* e500 family */
6777     /* e500 cores  */
6778 #define CPU_POWERPC_e500             CPU_POWERPC_e500v2_v22
6779 #define CPU_POWERPC_e500v1           CPU_POWERPC_e500v1_v20
6780 #define CPU_POWERPC_e500v2           CPU_POWERPC_e500v2_v22
6781     CPU_POWERPC_e500v1_v10         = 0x80200010,
6782     CPU_POWERPC_e500v1_v20         = 0x80200020,
6783     CPU_POWERPC_e500v2_v10         = 0x80210010,
6784     CPU_POWERPC_e500v2_v11         = 0x80210011,
6785     CPU_POWERPC_e500v2_v20         = 0x80210020,
6786     CPU_POWERPC_e500v2_v21         = 0x80210021,
6787     CPU_POWERPC_e500v2_v22         = 0x80210022,
6788     CPU_POWERPC_e500v2_v30         = 0x80210030,
6789     /* MPC85xx microcontrollers */
6790 #define CPU_POWERPC_MPC8533          CPU_POWERPC_MPC8533_v11
6791 #define CPU_POWERPC_MPC8533_v10      CPU_POWERPC_e500v2_v21
6792 #define CPU_POWERPC_MPC8533_v11      CPU_POWERPC_e500v2_v22
6793 #define CPU_POWERPC_MPC8533E         CPU_POWERPC_MPC8533E_v11
6794 #define CPU_POWERPC_MPC8533E_v10     CPU_POWERPC_e500v2_v21
6795 #define CPU_POWERPC_MPC8533E_v11     CPU_POWERPC_e500v2_v22
6796 #define CPU_POWERPC_MPC8540          CPU_POWERPC_MPC8540_v21
6797 #define CPU_POWERPC_MPC8540_v10      CPU_POWERPC_e500v1_v10
6798 #define CPU_POWERPC_MPC8540_v20      CPU_POWERPC_e500v1_v20
6799 #define CPU_POWERPC_MPC8540_v21      CPU_POWERPC_e500v1_v20
6800 #define CPU_POWERPC_MPC8541          CPU_POWERPC_MPC8541_v11
6801 #define CPU_POWERPC_MPC8541_v10      CPU_POWERPC_e500v1_v20
6802 #define CPU_POWERPC_MPC8541_v11      CPU_POWERPC_e500v1_v20
6803 #define CPU_POWERPC_MPC8541E         CPU_POWERPC_MPC8541E_v11
6804 #define CPU_POWERPC_MPC8541E_v10     CPU_POWERPC_e500v1_v20
6805 #define CPU_POWERPC_MPC8541E_v11     CPU_POWERPC_e500v1_v20
6806 #define CPU_POWERPC_MPC8543          CPU_POWERPC_MPC8543_v21
6807 #define CPU_POWERPC_MPC8543_v10      CPU_POWERPC_e500v2_v10
6808 #define CPU_POWERPC_MPC8543_v11      CPU_POWERPC_e500v2_v11
6809 #define CPU_POWERPC_MPC8543_v20      CPU_POWERPC_e500v2_v20
6810 #define CPU_POWERPC_MPC8543_v21      CPU_POWERPC_e500v2_v21
6811 #define CPU_POWERPC_MPC8543E         CPU_POWERPC_MPC8543E_v21
6812 #define CPU_POWERPC_MPC8543E_v10     CPU_POWERPC_e500v2_v10
6813 #define CPU_POWERPC_MPC8543E_v11     CPU_POWERPC_e500v2_v11
6814 #define CPU_POWERPC_MPC8543E_v20     CPU_POWERPC_e500v2_v20
6815 #define CPU_POWERPC_MPC8543E_v21     CPU_POWERPC_e500v2_v21
6816 #define CPU_POWERPC_MPC8544          CPU_POWERPC_MPC8544_v11
6817 #define CPU_POWERPC_MPC8544_v10      CPU_POWERPC_e500v2_v21
6818 #define CPU_POWERPC_MPC8544_v11      CPU_POWERPC_e500v2_v22
6819 #define CPU_POWERPC_MPC8544E_v11     CPU_POWERPC_e500v2_v22
6820 #define CPU_POWERPC_MPC8544E         CPU_POWERPC_MPC8544E_v11
6821 #define CPU_POWERPC_MPC8544E_v10     CPU_POWERPC_e500v2_v21
6822 #define CPU_POWERPC_MPC8545          CPU_POWERPC_MPC8545_v21
6823 #define CPU_POWERPC_MPC8545_v10      CPU_POWERPC_e500v2_v10
6824 #define CPU_POWERPC_MPC8545_v20      CPU_POWERPC_e500v2_v20
6825 #define CPU_POWERPC_MPC8545_v21      CPU_POWERPC_e500v2_v21
6826 #define CPU_POWERPC_MPC8545E         CPU_POWERPC_MPC8545E_v21
6827 #define CPU_POWERPC_MPC8545E_v10     CPU_POWERPC_e500v2_v10
6828 #define CPU_POWERPC_MPC8545E_v20     CPU_POWERPC_e500v2_v20
6829 #define CPU_POWERPC_MPC8545E_v21     CPU_POWERPC_e500v2_v21
6830 #define CPU_POWERPC_MPC8547E         CPU_POWERPC_MPC8545E_v21
6831 #define CPU_POWERPC_MPC8547E_v10     CPU_POWERPC_e500v2_v10
6832 #define CPU_POWERPC_MPC8547E_v20     CPU_POWERPC_e500v2_v20
6833 #define CPU_POWERPC_MPC8547E_v21     CPU_POWERPC_e500v2_v21
6834 #define CPU_POWERPC_MPC8548          CPU_POWERPC_MPC8548_v21
6835 #define CPU_POWERPC_MPC8548_v10      CPU_POWERPC_e500v2_v10
6836 #define CPU_POWERPC_MPC8548_v11      CPU_POWERPC_e500v2_v11
6837 #define CPU_POWERPC_MPC8548_v20      CPU_POWERPC_e500v2_v20
6838 #define CPU_POWERPC_MPC8548_v21      CPU_POWERPC_e500v2_v21
6839 #define CPU_POWERPC_MPC8548E         CPU_POWERPC_MPC8548E_v21
6840 #define CPU_POWERPC_MPC8548E_v10     CPU_POWERPC_e500v2_v10
6841 #define CPU_POWERPC_MPC8548E_v11     CPU_POWERPC_e500v2_v11
6842 #define CPU_POWERPC_MPC8548E_v20     CPU_POWERPC_e500v2_v20
6843 #define CPU_POWERPC_MPC8548E_v21     CPU_POWERPC_e500v2_v21
6844 #define CPU_POWERPC_MPC8555          CPU_POWERPC_MPC8555_v11
6845 #define CPU_POWERPC_MPC8555_v10      CPU_POWERPC_e500v2_v10
6846 #define CPU_POWERPC_MPC8555_v11      CPU_POWERPC_e500v2_v11
6847 #define CPU_POWERPC_MPC8555E         CPU_POWERPC_MPC8555E_v11
6848 #define CPU_POWERPC_MPC8555E_v10     CPU_POWERPC_e500v2_v10
6849 #define CPU_POWERPC_MPC8555E_v11     CPU_POWERPC_e500v2_v11
6850 #define CPU_POWERPC_MPC8560          CPU_POWERPC_MPC8560_v21
6851 #define CPU_POWERPC_MPC8560_v10      CPU_POWERPC_e500v2_v10
6852 #define CPU_POWERPC_MPC8560_v20      CPU_POWERPC_e500v2_v20
6853 #define CPU_POWERPC_MPC8560_v21      CPU_POWERPC_e500v2_v21
6854 #define CPU_POWERPC_MPC8567          CPU_POWERPC_e500v2_v22
6855 #define CPU_POWERPC_MPC8567E         CPU_POWERPC_e500v2_v22
6856 #define CPU_POWERPC_MPC8568          CPU_POWERPC_e500v2_v22
6857 #define CPU_POWERPC_MPC8568E         CPU_POWERPC_e500v2_v22
6858 #define CPU_POWERPC_MPC8572          CPU_POWERPC_e500v2_v30
6859 #define CPU_POWERPC_MPC8572E         CPU_POWERPC_e500v2_v30
6860     /* e600 family */
6861     /* e600 cores */
6862     CPU_POWERPC_e600               = 0x80040010,
6863     /* MPC86xx microcontrollers */
6864 #define CPU_POWERPC_MPC8610          CPU_POWERPC_e600
6865 #define CPU_POWERPC_MPC8641          CPU_POWERPC_e600
6866 #define CPU_POWERPC_MPC8641D         CPU_POWERPC_e600
6867     /* PowerPC 6xx cores */
6868 #define CPU_POWERPC_601              CPU_POWERPC_601_v2
6869     CPU_POWERPC_601_v0             = 0x00010001,
6870     CPU_POWERPC_601_v1             = 0x00010001,
6871 #define CPU_POWERPC_601v             CPU_POWERPC_601_v2
6872     CPU_POWERPC_601_v2             = 0x00010002,
6873     CPU_POWERPC_602                = 0x00050100,
6874     CPU_POWERPC_603                = 0x00030100,
6875 #define CPU_POWERPC_603E             CPU_POWERPC_603E_v41
6876     CPU_POWERPC_603E_v11           = 0x00060101,
6877     CPU_POWERPC_603E_v12           = 0x00060102,
6878     CPU_POWERPC_603E_v13           = 0x00060103,
6879     CPU_POWERPC_603E_v14           = 0x00060104,
6880     CPU_POWERPC_603E_v22           = 0x00060202,
6881     CPU_POWERPC_603E_v3            = 0x00060300,
6882     CPU_POWERPC_603E_v4            = 0x00060400,
6883     CPU_POWERPC_603E_v41           = 0x00060401,
6884     CPU_POWERPC_603E7t             = 0x00071201,
6885     CPU_POWERPC_603E7v             = 0x00070100,
6886     CPU_POWERPC_603E7v1            = 0x00070101,
6887     CPU_POWERPC_603E7v2            = 0x00070201,
6888     CPU_POWERPC_603E7              = 0x00070200,
6889     CPU_POWERPC_603P               = 0x00070000,
6890 #define CPU_POWERPC_603R             CPU_POWERPC_603E7t
6891     /* XXX: missing 0x00040303 (604) */
6892     CPU_POWERPC_604                = 0x00040103,
6893 #define CPU_POWERPC_604E             CPU_POWERPC_604E_v24
6894     /* XXX: missing 0x00091203 */
6895     /* XXX: missing 0x00092110 */
6896     /* XXX: missing 0x00092120 */
6897     CPU_POWERPC_604E_v10           = 0x00090100,
6898     CPU_POWERPC_604E_v22           = 0x00090202,
6899     CPU_POWERPC_604E_v24           = 0x00090204,
6900     /* XXX: missing 0x000a0100 */
6901     /* XXX: missing 0x00093102 */
6902     CPU_POWERPC_604R               = 0x000a0101,
6903 #if 0
6904     CPU_POWERPC_604EV              = xxx, /* XXX: same as 604R ? */
6905 #endif
6906     /* PowerPC 740/750 cores (aka G3) */
6907     /* XXX: missing 0x00084202 */
6908 #define CPU_POWERPC_7x0              CPU_POWERPC_7x0_v31
6909     CPU_POWERPC_7x0_v10            = 0x00080100,
6910     CPU_POWERPC_7x0_v20            = 0x00080200,
6911     CPU_POWERPC_7x0_v21            = 0x00080201,
6912     CPU_POWERPC_7x0_v22            = 0x00080202,
6913     CPU_POWERPC_7x0_v30            = 0x00080300,
6914     CPU_POWERPC_7x0_v31            = 0x00080301,
6915     CPU_POWERPC_740E               = 0x00080100,
6916     CPU_POWERPC_750E               = 0x00080200,
6917     CPU_POWERPC_7x0P               = 0x10080000,
6918     /* XXX: missing 0x00087010 (CL ?) */
6919 #define CPU_POWERPC_750CL            CPU_POWERPC_750CL_v20
6920     CPU_POWERPC_750CL_v10          = 0x00087200,
6921     CPU_POWERPC_750CL_v20          = 0x00087210, /* aka rev E */
6922 #define CPU_POWERPC_750CX            CPU_POWERPC_750CX_v22
6923     CPU_POWERPC_750CX_v10          = 0x00082100,
6924     CPU_POWERPC_750CX_v20          = 0x00082200,
6925     CPU_POWERPC_750CX_v21          = 0x00082201,
6926     CPU_POWERPC_750CX_v22          = 0x00082202,
6927 #define CPU_POWERPC_750CXE           CPU_POWERPC_750CXE_v31b
6928     CPU_POWERPC_750CXE_v21         = 0x00082211,
6929     CPU_POWERPC_750CXE_v22         = 0x00082212,
6930     CPU_POWERPC_750CXE_v23         = 0x00082213,
6931     CPU_POWERPC_750CXE_v24         = 0x00082214,
6932     CPU_POWERPC_750CXE_v24b        = 0x00083214,
6933     CPU_POWERPC_750CXE_v30         = 0x00082310,
6934     CPU_POWERPC_750CXE_v31         = 0x00082311,
6935     CPU_POWERPC_750CXE_v31b        = 0x00083311,
6936     CPU_POWERPC_750CXR             = 0x00083410,
6937     CPU_POWERPC_750FL              = 0x70000203,
6938 #define CPU_POWERPC_750FX            CPU_POWERPC_750FX_v23
6939     CPU_POWERPC_750FX_v10          = 0x70000100,
6940     CPU_POWERPC_750FX_v20          = 0x70000200,
6941     CPU_POWERPC_750FX_v21          = 0x70000201,
6942     CPU_POWERPC_750FX_v22          = 0x70000202,
6943     CPU_POWERPC_750FX_v23          = 0x70000203,
6944     CPU_POWERPC_750GL              = 0x70020102,
6945 #define CPU_POWERPC_750GX            CPU_POWERPC_750GX_v12
6946     CPU_POWERPC_750GX_v10          = 0x70020100,
6947     CPU_POWERPC_750GX_v11          = 0x70020101,
6948     CPU_POWERPC_750GX_v12          = 0x70020102,
6949 #define CPU_POWERPC_750L             CPU_POWERPC_750L_v32 /* Aka LoneStar */
6950     CPU_POWERPC_750L_v20           = 0x00088200,
6951     CPU_POWERPC_750L_v21           = 0x00088201,
6952     CPU_POWERPC_750L_v22           = 0x00088202,
6953     CPU_POWERPC_750L_v30           = 0x00088300,
6954     CPU_POWERPC_750L_v32           = 0x00088302,
6955     /* PowerPC 745/755 cores */
6956 #define CPU_POWERPC_7x5              CPU_POWERPC_7x5_v28
6957     CPU_POWERPC_7x5_v10            = 0x00083100,
6958     CPU_POWERPC_7x5_v11            = 0x00083101,
6959     CPU_POWERPC_7x5_v20            = 0x00083200,
6960     CPU_POWERPC_7x5_v21            = 0x00083201,
6961     CPU_POWERPC_7x5_v22            = 0x00083202, /* aka D */
6962     CPU_POWERPC_7x5_v23            = 0x00083203, /* aka E */
6963     CPU_POWERPC_7x5_v24            = 0x00083204,
6964     CPU_POWERPC_7x5_v25            = 0x00083205,
6965     CPU_POWERPC_7x5_v26            = 0x00083206,
6966     CPU_POWERPC_7x5_v27            = 0x00083207,
6967     CPU_POWERPC_7x5_v28            = 0x00083208,
6968 #if 0
6969     CPU_POWERPC_7x5P               = xxx,
6970 #endif
6971     /* PowerPC 74xx cores (aka G4) */
6972     /* XXX: missing 0x000C1101 */
6973 #define CPU_POWERPC_7400             CPU_POWERPC_7400_v29
6974     CPU_POWERPC_7400_v10           = 0x000C0100,
6975     CPU_POWERPC_7400_v11           = 0x000C0101,
6976     CPU_POWERPC_7400_v20           = 0x000C0200,
6977     CPU_POWERPC_7400_v21           = 0x000C0201,
6978     CPU_POWERPC_7400_v22           = 0x000C0202,
6979     CPU_POWERPC_7400_v26           = 0x000C0206,
6980     CPU_POWERPC_7400_v27           = 0x000C0207,
6981     CPU_POWERPC_7400_v28           = 0x000C0208,
6982     CPU_POWERPC_7400_v29           = 0x000C0209,
6983 #define CPU_POWERPC_7410             CPU_POWERPC_7410_v14
6984     CPU_POWERPC_7410_v10           = 0x800C1100,
6985     CPU_POWERPC_7410_v11           = 0x800C1101,
6986     CPU_POWERPC_7410_v12           = 0x800C1102, /* aka C */
6987     CPU_POWERPC_7410_v13           = 0x800C1103, /* aka D */
6988     CPU_POWERPC_7410_v14           = 0x800C1104, /* aka E */
6989 #define CPU_POWERPC_7448             CPU_POWERPC_7448_v21
6990     CPU_POWERPC_7448_v10           = 0x80040100,
6991     CPU_POWERPC_7448_v11           = 0x80040101,
6992     CPU_POWERPC_7448_v20           = 0x80040200,
6993     CPU_POWERPC_7448_v21           = 0x80040201,
6994 #define CPU_POWERPC_7450             CPU_POWERPC_7450_v21
6995     CPU_POWERPC_7450_v10           = 0x80000100,
6996     CPU_POWERPC_7450_v11           = 0x80000101,
6997     CPU_POWERPC_7450_v12           = 0x80000102,
6998     CPU_POWERPC_7450_v20           = 0x80000200, /* aka A, B, C, D: 2.04 */
6999     CPU_POWERPC_7450_v21           = 0x80000201, /* aka E */
7000 #define CPU_POWERPC_74x1             CPU_POWERPC_74x1_v23
7001     CPU_POWERPC_74x1_v23           = 0x80000203, /* aka G: 2.3 */
7002     /* XXX: this entry might be a bug in some documentation */
7003     CPU_POWERPC_74x1_v210          = 0x80000210, /* aka G: 2.3 ? */
7004 #define CPU_POWERPC_74x5             CPU_POWERPC_74x5_v32
7005     CPU_POWERPC_74x5_v10           = 0x80010100,
7006     /* XXX: missing 0x80010200 */
7007     CPU_POWERPC_74x5_v21           = 0x80010201, /* aka C: 2.1 */
7008     CPU_POWERPC_74x5_v32           = 0x80010302,
7009     CPU_POWERPC_74x5_v33           = 0x80010303, /* aka F: 3.3 */
7010     CPU_POWERPC_74x5_v34           = 0x80010304, /* aka G: 3.4 */
7011 #define CPU_POWERPC_74x7             CPU_POWERPC_74x7_v12
7012     CPU_POWERPC_74x7_v10           = 0x80020100, /* aka A: 1.0 */
7013     CPU_POWERPC_74x7_v11           = 0x80020101, /* aka B: 1.1 */
7014     CPU_POWERPC_74x7_v12           = 0x80020102, /* aka C: 1.2 */
7015 #define CPU_POWERPC_74x7A            CPU_POWERPC_74x7A_v12
7016     CPU_POWERPC_74x7A_v10          = 0x80030100, /* aka A: 1.0 */
7017     CPU_POWERPC_74x7A_v11          = 0x80030101, /* aka B: 1.1 */
7018     CPU_POWERPC_74x7A_v12          = 0x80030102, /* aka C: 1.2 */
7019     /* 64 bits PowerPC */
7020 #if defined(TARGET_PPC64)
7021     CPU_POWERPC_620                = 0x00140000,
7022     CPU_POWERPC_630                = 0x00400000,
7023     CPU_POWERPC_631                = 0x00410104,
7024     CPU_POWERPC_POWER4             = 0x00350000,
7025     CPU_POWERPC_POWER4P            = 0x00380000,
7026      /* XXX: missing 0x003A0201 */
7027     CPU_POWERPC_POWER5             = 0x003A0203,
7028 #define CPU_POWERPC_POWER5GR         CPU_POWERPC_POWER5
7029     CPU_POWERPC_POWER5P            = 0x003B0000,
7030 #define CPU_POWERPC_POWER5GS         CPU_POWERPC_POWER5P
7031     CPU_POWERPC_POWER6             = 0x003E0000,
7032     CPU_POWERPC_POWER6_5           = 0x0F000001, /* POWER6 in POWER5 mode */
7033     CPU_POWERPC_POWER6A            = 0x0F000002,
7034     CPU_POWERPC_970                = 0x00390202,
7035 #define CPU_POWERPC_970FX            CPU_POWERPC_970FX_v31
7036     CPU_POWERPC_970FX_v10          = 0x00391100,
7037     CPU_POWERPC_970FX_v20          = 0x003C0200,
7038     CPU_POWERPC_970FX_v21          = 0x003C0201,
7039     CPU_POWERPC_970FX_v30          = 0x003C0300,
7040     CPU_POWERPC_970FX_v31          = 0x003C0301,
7041     CPU_POWERPC_970GX              = 0x00450000,
7042 #define CPU_POWERPC_970MP            CPU_POWERPC_970MP_v11
7043     CPU_POWERPC_970MP_v10          = 0x00440100,
7044     CPU_POWERPC_970MP_v11          = 0x00440101,
7045 #define CPU_POWERPC_CELL             CPU_POWERPC_CELL_v32
7046     CPU_POWERPC_CELL_v10           = 0x00700100,
7047     CPU_POWERPC_CELL_v20           = 0x00700400,
7048     CPU_POWERPC_CELL_v30           = 0x00700500,
7049     CPU_POWERPC_CELL_v31           = 0x00700501,
7050 #define CPU_POWERPC_CELL_v32         CPU_POWERPC_CELL_v31
7051     CPU_POWERPC_RS64               = 0x00330000,
7052     CPU_POWERPC_RS64II             = 0x00340000,
7053     CPU_POWERPC_RS64III            = 0x00360000,
7054     CPU_POWERPC_RS64IV             = 0x00370000,
7055 #endif /* defined(TARGET_PPC64) */
7056     /* Original POWER */
7057     /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7058      * POWER2 (RIOS2) & RSC2 (P2SC) here
7059      */
7060 #if 0
7061     CPU_POWER                      = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7062 #endif
7063 #if 0
7064     CPU_POWER2                     = xxx, /* 0x40000 ? */
7065 #endif
7066     /* PA Semi core */
7067     CPU_POWERPC_PA6T               = 0x00900000,
7068 };
7069
7070 /* System version register (used on MPC 8xxx)                                */
7071 enum {
7072     POWERPC_SVR_NONE               = 0x00000000,
7073 #define POWERPC_SVR_52xx             POWERPC_SVR_5200
7074 #define POWERPC_SVR_5200             POWERPC_SVR_5200_v12
7075     POWERPC_SVR_5200_v10           = 0x80110010,
7076     POWERPC_SVR_5200_v11           = 0x80110011,
7077     POWERPC_SVR_5200_v12           = 0x80110012,
7078 #define POWERPC_SVR_5200B            POWERPC_SVR_5200B_v21
7079     POWERPC_SVR_5200B_v20          = 0x80110020,
7080     POWERPC_SVR_5200B_v21          = 0x80110021,
7081 #define POWERPC_SVR_55xx             POWERPC_SVR_5567
7082 #if 0
7083     POWERPC_SVR_5533               = xxx,
7084 #endif
7085 #if 0
7086     POWERPC_SVR_5534               = xxx,
7087 #endif
7088 #if 0
7089     POWERPC_SVR_5553               = xxx,
7090 #endif
7091 #if 0
7092     POWERPC_SVR_5554               = xxx,
7093 #endif
7094 #if 0
7095     POWERPC_SVR_5561               = xxx,
7096 #endif
7097 #if 0
7098     POWERPC_SVR_5565               = xxx,
7099 #endif
7100 #if 0
7101     POWERPC_SVR_5566               = xxx,
7102 #endif
7103 #if 0
7104     POWERPC_SVR_5567               = xxx,
7105 #endif
7106 #if 0
7107     POWERPC_SVR_8313               = xxx,
7108 #endif
7109 #if 0
7110     POWERPC_SVR_8313E              = xxx,
7111 #endif
7112 #if 0
7113     POWERPC_SVR_8314               = xxx,
7114 #endif
7115 #if 0
7116     POWERPC_SVR_8314E              = xxx,
7117 #endif
7118 #if 0
7119     POWERPC_SVR_8315               = xxx,
7120 #endif
7121 #if 0
7122     POWERPC_SVR_8315E              = xxx,
7123 #endif
7124 #if 0
7125     POWERPC_SVR_8321               = xxx,
7126 #endif
7127 #if 0
7128     POWERPC_SVR_8321E              = xxx,
7129 #endif
7130 #if 0
7131     POWERPC_SVR_8323               = xxx,
7132 #endif
7133 #if 0
7134     POWERPC_SVR_8323E              = xxx,
7135 #endif
7136     POWERPC_SVR_8343               = 0x80570010,
7137     POWERPC_SVR_8343A              = 0x80570030,
7138     POWERPC_SVR_8343E              = 0x80560010,
7139     POWERPC_SVR_8343EA             = 0x80560030,
7140 #define POWERPC_SVR_8347             POWERPC_SVR_8347T
7141     POWERPC_SVR_8347P              = 0x80550010, /* PBGA package */
7142     POWERPC_SVR_8347T              = 0x80530010, /* TBGA package */
7143 #define POWERPC_SVR_8347A            POWERPC_SVR_8347AT
7144     POWERPC_SVR_8347AP             = 0x80550030, /* PBGA package */
7145     POWERPC_SVR_8347AT             = 0x80530030, /* TBGA package */
7146 #define POWERPC_SVR_8347E            POWERPC_SVR_8347ET
7147     POWERPC_SVR_8347EP             = 0x80540010, /* PBGA package */
7148     POWERPC_SVR_8347ET             = 0x80520010, /* TBGA package */
7149 #define POWERPC_SVR_8347EA            POWERPC_SVR_8347EAT
7150     POWERPC_SVR_8347EAP            = 0x80540030, /* PBGA package */
7151     POWERPC_SVR_8347EAT            = 0x80520030, /* TBGA package */
7152     POWERPC_SVR_8349               = 0x80510010,
7153     POWERPC_SVR_8349A              = 0x80510030,
7154     POWERPC_SVR_8349E              = 0x80500010,
7155     POWERPC_SVR_8349EA             = 0x80500030,
7156 #if 0
7157     POWERPC_SVR_8358E              = xxx,
7158 #endif
7159 #if 0
7160     POWERPC_SVR_8360E              = xxx,
7161 #endif
7162 #define POWERPC_SVR_E500             0x40000000
7163     POWERPC_SVR_8377               = 0x80C70010 | POWERPC_SVR_E500,
7164     POWERPC_SVR_8377E              = 0x80C60010 | POWERPC_SVR_E500,
7165     POWERPC_SVR_8378               = 0x80C50010 | POWERPC_SVR_E500,
7166     POWERPC_SVR_8378E              = 0x80C40010 | POWERPC_SVR_E500,
7167     POWERPC_SVR_8379               = 0x80C30010 | POWERPC_SVR_E500,
7168     POWERPC_SVR_8379E              = 0x80C00010 | POWERPC_SVR_E500,
7169 #define POWERPC_SVR_8533             POWERPC_SVR_8533_v11
7170     POWERPC_SVR_8533_v10           = 0x80340010 | POWERPC_SVR_E500,
7171     POWERPC_SVR_8533_v11           = 0x80340011 | POWERPC_SVR_E500,
7172 #define POWERPC_SVR_8533E            POWERPC_SVR_8533E_v11
7173     POWERPC_SVR_8533E_v10          = 0x803C0010 | POWERPC_SVR_E500,
7174     POWERPC_SVR_8533E_v11          = 0x803C0011 | POWERPC_SVR_E500,
7175 #define POWERPC_SVR_8540             POWERPC_SVR_8540_v21
7176     POWERPC_SVR_8540_v10           = 0x80300010 | POWERPC_SVR_E500,
7177     POWERPC_SVR_8540_v20           = 0x80300020 | POWERPC_SVR_E500,
7178     POWERPC_SVR_8540_v21           = 0x80300021 | POWERPC_SVR_E500,
7179 #define POWERPC_SVR_8541             POWERPC_SVR_8541_v11
7180     POWERPC_SVR_8541_v10           = 0x80720010 | POWERPC_SVR_E500,
7181     POWERPC_SVR_8541_v11           = 0x80720011 | POWERPC_SVR_E500,
7182 #define POWERPC_SVR_8541E            POWERPC_SVR_8541E_v11
7183     POWERPC_SVR_8541E_v10          = 0x807A0010 | POWERPC_SVR_E500,
7184     POWERPC_SVR_8541E_v11          = 0x807A0011 | POWERPC_SVR_E500,
7185 #define POWERPC_SVR_8543             POWERPC_SVR_8543_v21
7186     POWERPC_SVR_8543_v10           = 0x80320010 | POWERPC_SVR_E500,
7187     POWERPC_SVR_8543_v11           = 0x80320011 | POWERPC_SVR_E500,
7188     POWERPC_SVR_8543_v20           = 0x80320020 | POWERPC_SVR_E500,
7189     POWERPC_SVR_8543_v21           = 0x80320021 | POWERPC_SVR_E500,
7190 #define POWERPC_SVR_8543E            POWERPC_SVR_8543E_v21
7191     POWERPC_SVR_8543E_v10          = 0x803A0010 | POWERPC_SVR_E500,
7192     POWERPC_SVR_8543E_v11          = 0x803A0011 | POWERPC_SVR_E500,
7193     POWERPC_SVR_8543E_v20          = 0x803A0020 | POWERPC_SVR_E500,
7194     POWERPC_SVR_8543E_v21          = 0x803A0021 | POWERPC_SVR_E500,
7195 #define POWERPC_SVR_8544             POWERPC_SVR_8544_v11
7196     POWERPC_SVR_8544_v10           = 0x80340110 | POWERPC_SVR_E500,
7197     POWERPC_SVR_8544_v11           = 0x80340111 | POWERPC_SVR_E500,
7198 #define POWERPC_SVR_8544E            POWERPC_SVR_8544E_v11
7199     POWERPC_SVR_8544E_v10          = 0x803C0110 | POWERPC_SVR_E500,
7200     POWERPC_SVR_8544E_v11          = 0x803C0111 | POWERPC_SVR_E500,
7201 #define POWERPC_SVR_8545             POWERPC_SVR_8545_v21
7202     POWERPC_SVR_8545_v20           = 0x80310220 | POWERPC_SVR_E500,
7203     POWERPC_SVR_8545_v21           = 0x80310221 | POWERPC_SVR_E500,
7204 #define POWERPC_SVR_8545E            POWERPC_SVR_8545E_v21
7205     POWERPC_SVR_8545E_v20          = 0x80390220 | POWERPC_SVR_E500,
7206     POWERPC_SVR_8545E_v21          = 0x80390221 | POWERPC_SVR_E500,
7207 #define POWERPC_SVR_8547E            POWERPC_SVR_8547E_v21
7208     POWERPC_SVR_8547E_v20          = 0x80390120 | POWERPC_SVR_E500,
7209     POWERPC_SVR_8547E_v21          = 0x80390121 | POWERPC_SVR_E500,
7210 #define POWERPC_SVR_8548             POWERPC_SVR_8548_v21
7211     POWERPC_SVR_8548_v10           = 0x80310010 | POWERPC_SVR_E500,
7212     POWERPC_SVR_8548_v11           = 0x80310011 | POWERPC_SVR_E500,
7213     POWERPC_SVR_8548_v20           = 0x80310020 | POWERPC_SVR_E500,
7214     POWERPC_SVR_8548_v21           = 0x80310021 | POWERPC_SVR_E500,
7215 #define POWERPC_SVR_8548E            POWERPC_SVR_8548E_v21
7216     POWERPC_SVR_8548E_v10          = 0x80390010 | POWERPC_SVR_E500,
7217     POWERPC_SVR_8548E_v11          = 0x80390011 | POWERPC_SVR_E500,
7218     POWERPC_SVR_8548E_v20          = 0x80390020 | POWERPC_SVR_E500,
7219     POWERPC_SVR_8548E_v21          = 0x80390021 | POWERPC_SVR_E500,
7220 #define POWERPC_SVR_8555             POWERPC_SVR_8555_v11
7221     POWERPC_SVR_8555_v10           = 0x80710010 | POWERPC_SVR_E500,
7222     POWERPC_SVR_8555_v11           = 0x80710011 | POWERPC_SVR_E500,
7223 #define POWERPC_SVR_8555E            POWERPC_SVR_8555_v11
7224     POWERPC_SVR_8555E_v10          = 0x80790010 | POWERPC_SVR_E500,
7225     POWERPC_SVR_8555E_v11          = 0x80790011 | POWERPC_SVR_E500,
7226 #define POWERPC_SVR_8560             POWERPC_SVR_8560_v21
7227     POWERPC_SVR_8560_v10           = 0x80700010 | POWERPC_SVR_E500,
7228     POWERPC_SVR_8560_v20           = 0x80700020 | POWERPC_SVR_E500,
7229     POWERPC_SVR_8560_v21           = 0x80700021 | POWERPC_SVR_E500,
7230     POWERPC_SVR_8567               = 0x80750111 | POWERPC_SVR_E500,
7231     POWERPC_SVR_8567E              = 0x807D0111 | POWERPC_SVR_E500,
7232     POWERPC_SVR_8568               = 0x80750011 | POWERPC_SVR_E500,
7233     POWERPC_SVR_8568E              = 0x807D0011 | POWERPC_SVR_E500,
7234     POWERPC_SVR_8572               = 0x80E00010 | POWERPC_SVR_E500,
7235     POWERPC_SVR_8572E              = 0x80E80010 | POWERPC_SVR_E500,
7236 #if 0
7237     POWERPC_SVR_8610               = xxx,
7238 #endif
7239     POWERPC_SVR_8641               = 0x80900021,
7240     POWERPC_SVR_8641D              = 0x80900121,
7241 };
7242
7243 /*****************************************************************************/
7244 /* PowerPC CPU definitions                                                   */
7245 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type)                             \
7246     {                                                                         \
7247         .name        = _name,                                                 \
7248         .pvr         = _pvr,                                                  \
7249         .svr         = _svr,                                                  \
7250         .insns_flags = glue(POWERPC_INSNS_,_type),                            \
7251         .msr_mask    = glue(POWERPC_MSRM_,_type),                             \
7252         .mmu_model   = glue(POWERPC_MMU_,_type),                              \
7253         .excp_model  = glue(POWERPC_EXCP_,_type),                             \
7254         .bus_model   = glue(POWERPC_INPUT_,_type),                            \
7255         .bfd_mach    = glue(POWERPC_BFDM_,_type),                             \
7256         .flags       = glue(POWERPC_FLAG_,_type),                             \
7257         .init_proc   = &glue(init_proc_,_type),                               \
7258         .check_pow   = &glue(check_pow_,_type),                               \
7259     }
7260 #define POWERPC_DEF(_name, _pvr, _type)                                       \
7261 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7262
7263 static const ppc_def_t ppc_defs[] = {
7264     /* Embedded PowerPC                                                      */
7265     /* PowerPC 401 family                                                    */
7266     /* Generic PowerPC 401 */
7267     POWERPC_DEF("401",           CPU_POWERPC_401,                    401),
7268     /* PowerPC 401 cores                                                     */
7269     /* PowerPC 401A1 */
7270     POWERPC_DEF("401A1",         CPU_POWERPC_401A1,                  401),
7271     /* PowerPC 401B2                                                         */
7272     POWERPC_DEF("401B2",         CPU_POWERPC_401B2,                  401x2),
7273 #if defined (TODO)
7274     /* PowerPC 401B3                                                         */
7275     POWERPC_DEF("401B3",         CPU_POWERPC_401B3,                  401x3),
7276 #endif
7277     /* PowerPC 401C2                                                         */
7278     POWERPC_DEF("401C2",         CPU_POWERPC_401C2,                  401x2),
7279     /* PowerPC 401D2                                                         */
7280     POWERPC_DEF("401D2",         CPU_POWERPC_401D2,                  401x2),
7281     /* PowerPC 401E2                                                         */
7282     POWERPC_DEF("401E2",         CPU_POWERPC_401E2,                  401x2),
7283     /* PowerPC 401F2                                                         */
7284     POWERPC_DEF("401F2",         CPU_POWERPC_401F2,                  401x2),
7285     /* PowerPC 401G2                                                         */
7286     /* XXX: to be checked */
7287     POWERPC_DEF("401G2",         CPU_POWERPC_401G2,                  401x2),
7288     /* PowerPC 401 microcontrolers                                           */
7289 #if defined (TODO)
7290     /* PowerPC 401GF                                                         */
7291     POWERPC_DEF("401GF",         CPU_POWERPC_401GF,                  401),
7292 #endif
7293     /* IOP480 (401 microcontroler)                                           */
7294     POWERPC_DEF("IOP480",        CPU_POWERPC_IOP480,                 IOP480),
7295     /* IBM Processor for Network Resources                                   */
7296     POWERPC_DEF("Cobra",         CPU_POWERPC_COBRA,                  401),
7297 #if defined (TODO)
7298     POWERPC_DEF("Xipchip",       CPU_POWERPC_XIPCHIP,                401),
7299 #endif
7300     /* PowerPC 403 family                                                    */
7301     /* Generic PowerPC 403                                                   */
7302     POWERPC_DEF("403",           CPU_POWERPC_403,                    403),
7303     /* PowerPC 403 microcontrolers                                           */
7304     /* PowerPC 403 GA                                                        */
7305     POWERPC_DEF("403GA",         CPU_POWERPC_403GA,                  403),
7306     /* PowerPC 403 GB                                                        */
7307     POWERPC_DEF("403GB",         CPU_POWERPC_403GB,                  403),
7308     /* PowerPC 403 GC                                                        */
7309     POWERPC_DEF("403GC",         CPU_POWERPC_403GC,                  403),
7310     /* PowerPC 403 GCX                                                       */
7311     POWERPC_DEF("403GCX",        CPU_POWERPC_403GCX,                 403GCX),
7312 #if defined (TODO)
7313     /* PowerPC 403 GP                                                        */
7314     POWERPC_DEF("403GP",         CPU_POWERPC_403GP,                  403),
7315 #endif
7316     /* PowerPC 405 family                                                    */
7317     /* Generic PowerPC 405                                                   */
7318     POWERPC_DEF("405",           CPU_POWERPC_405,                    405),
7319     /* PowerPC 405 cores                                                     */
7320 #if defined (TODO)
7321     /* PowerPC 405 A3                                                        */
7322     POWERPC_DEF("405A3",         CPU_POWERPC_405A3,                  405),
7323 #endif
7324 #if defined (TODO)
7325     /* PowerPC 405 A4                                                        */
7326     POWERPC_DEF("405A4",         CPU_POWERPC_405A4,                  405),
7327 #endif
7328 #if defined (TODO)
7329     /* PowerPC 405 B3                                                        */
7330     POWERPC_DEF("405B3",         CPU_POWERPC_405B3,                  405),
7331 #endif
7332 #if defined (TODO)
7333     /* PowerPC 405 B4                                                        */
7334     POWERPC_DEF("405B4",         CPU_POWERPC_405B4,                  405),
7335 #endif
7336 #if defined (TODO)
7337     /* PowerPC 405 C3                                                        */
7338     POWERPC_DEF("405C3",         CPU_POWERPC_405C3,                  405),
7339 #endif
7340 #if defined (TODO)
7341     /* PowerPC 405 C4                                                        */
7342     POWERPC_DEF("405C4",         CPU_POWERPC_405C4,                  405),
7343 #endif
7344     /* PowerPC 405 D2                                                        */
7345     POWERPC_DEF("405D2",         CPU_POWERPC_405D2,                  405),
7346 #if defined (TODO)
7347     /* PowerPC 405 D3                                                        */
7348     POWERPC_DEF("405D3",         CPU_POWERPC_405D3,                  405),
7349 #endif
7350     /* PowerPC 405 D4                                                        */
7351     POWERPC_DEF("405D4",         CPU_POWERPC_405D4,                  405),
7352 #if defined (TODO)
7353     /* PowerPC 405 D5                                                        */
7354     POWERPC_DEF("405D5",         CPU_POWERPC_405D5,                  405),
7355 #endif
7356 #if defined (TODO)
7357     /* PowerPC 405 E4                                                        */
7358     POWERPC_DEF("405E4",         CPU_POWERPC_405E4,                  405),
7359 #endif
7360 #if defined (TODO)
7361     /* PowerPC 405 F4                                                        */
7362     POWERPC_DEF("405F4",         CPU_POWERPC_405F4,                  405),
7363 #endif
7364 #if defined (TODO)
7365     /* PowerPC 405 F5                                                        */
7366     POWERPC_DEF("405F5",         CPU_POWERPC_405F5,                  405),
7367 #endif
7368 #if defined (TODO)
7369     /* PowerPC 405 F6                                                        */
7370     POWERPC_DEF("405F6",         CPU_POWERPC_405F6,                  405),
7371 #endif
7372     /* PowerPC 405 microcontrolers                                           */
7373     /* PowerPC 405 CR                                                        */
7374     POWERPC_DEF("405CR",         CPU_POWERPC_405CR,                  405),
7375     /* PowerPC 405 CRa                                                       */
7376     POWERPC_DEF("405CRa",        CPU_POWERPC_405CRa,                 405),
7377     /* PowerPC 405 CRb                                                       */
7378     POWERPC_DEF("405CRb",        CPU_POWERPC_405CRb,                 405),
7379     /* PowerPC 405 CRc                                                       */
7380     POWERPC_DEF("405CRc",        CPU_POWERPC_405CRc,                 405),
7381     /* PowerPC 405 EP                                                        */
7382     POWERPC_DEF("405EP",         CPU_POWERPC_405EP,                  405),
7383 #if defined(TODO)
7384     /* PowerPC 405 EXr                                                       */
7385     POWERPC_DEF("405EXr",        CPU_POWERPC_405EXr,                 405),
7386 #endif
7387     /* PowerPC 405 EZ                                                        */
7388     POWERPC_DEF("405EZ",         CPU_POWERPC_405EZ,                  405),
7389 #if defined(TODO)
7390     /* PowerPC 405 FX                                                        */
7391     POWERPC_DEF("405FX",         CPU_POWERPC_405FX,                  405),
7392 #endif
7393     /* PowerPC 405 GP                                                        */
7394     POWERPC_DEF("405GP",         CPU_POWERPC_405GP,                  405),
7395     /* PowerPC 405 GPa                                                       */
7396     POWERPC_DEF("405GPa",        CPU_POWERPC_405GPa,                 405),
7397     /* PowerPC 405 GPb                                                       */
7398     POWERPC_DEF("405GPb",        CPU_POWERPC_405GPb,                 405),
7399     /* PowerPC 405 GPc                                                       */
7400     POWERPC_DEF("405GPc",        CPU_POWERPC_405GPc,                 405),
7401     /* PowerPC 405 GPd                                                       */
7402     POWERPC_DEF("405GPd",        CPU_POWERPC_405GPd,                 405),
7403     /* PowerPC 405 GPe                                                       */
7404     POWERPC_DEF("405GPe",        CPU_POWERPC_405GPe,                 405),
7405     /* PowerPC 405 GPR                                                       */
7406     POWERPC_DEF("405GPR",        CPU_POWERPC_405GPR,                 405),
7407 #if defined(TODO)
7408     /* PowerPC 405 H                                                         */
7409     POWERPC_DEF("405H",          CPU_POWERPC_405H,                   405),
7410 #endif
7411 #if defined(TODO)
7412     /* PowerPC 405 L                                                         */
7413     POWERPC_DEF("405L",          CPU_POWERPC_405L,                   405),
7414 #endif
7415     /* PowerPC 405 LP                                                        */
7416     POWERPC_DEF("405LP",         CPU_POWERPC_405LP,                  405),
7417 #if defined(TODO)
7418     /* PowerPC 405 PM                                                        */
7419     POWERPC_DEF("405PM",         CPU_POWERPC_405PM,                  405),
7420 #endif
7421 #if defined(TODO)
7422     /* PowerPC 405 PS                                                        */
7423     POWERPC_DEF("405PS",         CPU_POWERPC_405PS,                  405),
7424 #endif
7425 #if defined(TODO)
7426     /* PowerPC 405 S                                                         */
7427     POWERPC_DEF("405S",          CPU_POWERPC_405S,                   405),
7428 #endif
7429     /* Npe405 H                                                              */
7430     POWERPC_DEF("Npe405H",       CPU_POWERPC_NPE405H,                405),
7431     /* Npe405 H2                                                             */
7432     POWERPC_DEF("Npe405H2",      CPU_POWERPC_NPE405H2,               405),
7433     /* Npe405 L                                                              */
7434     POWERPC_DEF("Npe405L",       CPU_POWERPC_NPE405L,                405),
7435     /* Npe4GS3                                                               */
7436     POWERPC_DEF("Npe4GS3",       CPU_POWERPC_NPE4GS3,                405),
7437 #if defined (TODO)
7438     POWERPC_DEF("Npcxx1",        CPU_POWERPC_NPCxx1,                 405),
7439 #endif
7440 #if defined (TODO)
7441     POWERPC_DEF("Npr161",        CPU_POWERPC_NPR161,                 405),
7442 #endif
7443 #if defined (TODO)
7444     /* PowerPC LC77700 (Sanyo)                                               */
7445     POWERPC_DEF("LC77700",       CPU_POWERPC_LC77700,                405),
7446 #endif
7447     /* PowerPC 401/403/405 based set-top-box microcontrolers                 */
7448 #if defined (TODO)
7449     /* STB010000                                                             */
7450     POWERPC_DEF("STB01000",      CPU_POWERPC_STB01000,               401x2),
7451 #endif
7452 #if defined (TODO)
7453     /* STB01010                                                              */
7454     POWERPC_DEF("STB01010",      CPU_POWERPC_STB01010,               401x2),
7455 #endif
7456 #if defined (TODO)
7457     /* STB0210                                                               */
7458     POWERPC_DEF("STB0210",       CPU_POWERPC_STB0210,                401x3),
7459 #endif
7460     /* STB03xx                                                               */
7461     POWERPC_DEF("STB03",         CPU_POWERPC_STB03,                  405),
7462 #if defined (TODO)
7463     /* STB043x                                                               */
7464     POWERPC_DEF("STB043",        CPU_POWERPC_STB043,                 405),
7465 #endif
7466 #if defined (TODO)
7467     /* STB045x                                                               */
7468     POWERPC_DEF("STB045",        CPU_POWERPC_STB045,                 405),
7469 #endif
7470     /* STB04xx                                                               */
7471     POWERPC_DEF("STB04",         CPU_POWERPC_STB04,                  405),
7472     /* STB25xx                                                               */
7473     POWERPC_DEF("STB25",         CPU_POWERPC_STB25,                  405),
7474 #if defined (TODO)
7475     /* STB130                                                                */
7476     POWERPC_DEF("STB130",        CPU_POWERPC_STB130,                 405),
7477 #endif
7478     /* Xilinx PowerPC 405 cores                                              */
7479     POWERPC_DEF("x2vp4",         CPU_POWERPC_X2VP4,                  405),
7480     POWERPC_DEF("x2vp7",         CPU_POWERPC_X2VP7,                  405),
7481     POWERPC_DEF("x2vp20",        CPU_POWERPC_X2VP20,                 405),
7482     POWERPC_DEF("x2vp50",        CPU_POWERPC_X2VP50,                 405),
7483 #if defined (TODO)
7484     /* Zarlink ZL10310                                                       */
7485     POWERPC_DEF("zl10310",       CPU_POWERPC_ZL10310,                405),
7486 #endif
7487 #if defined (TODO)
7488     /* Zarlink ZL10311                                                       */
7489     POWERPC_DEF("zl10311",       CPU_POWERPC_ZL10311,                405),
7490 #endif
7491 #if defined (TODO)
7492     /* Zarlink ZL10320                                                       */
7493     POWERPC_DEF("zl10320",       CPU_POWERPC_ZL10320,                405),
7494 #endif
7495 #if defined (TODO)
7496     /* Zarlink ZL10321                                                       */
7497     POWERPC_DEF("zl10321",       CPU_POWERPC_ZL10321,                405),
7498 #endif
7499     /* PowerPC 440 family                                                    */
7500 #if defined(TODO_USER_ONLY)
7501     /* Generic PowerPC 440                                                   */
7502     POWERPC_DEF("440",           CPU_POWERPC_440,                    440GP),
7503 #endif
7504     /* PowerPC 440 cores                                                     */
7505 #if defined (TODO)
7506     /* PowerPC 440 A4                                                        */
7507     POWERPC_DEF("440A4",         CPU_POWERPC_440A4,                  440x4),
7508 #endif
7509     /* PowerPC 440 Xilinx 5                                                  */
7510     POWERPC_DEF("440-Xilinx",    CPU_POWERPC_440_XILINX,             440x5),
7511 #if defined (TODO)
7512     /* PowerPC 440 A5                                                        */
7513     POWERPC_DEF("440A5",         CPU_POWERPC_440A5,                  440x5),
7514 #endif
7515 #if defined (TODO)
7516     /* PowerPC 440 B4                                                        */
7517     POWERPC_DEF("440B4",         CPU_POWERPC_440B4,                  440x4),
7518 #endif
7519 #if defined (TODO)
7520     /* PowerPC 440 G4                                                        */
7521     POWERPC_DEF("440G4",         CPU_POWERPC_440G4,                  440x4),
7522 #endif
7523 #if defined (TODO)
7524     /* PowerPC 440 F5                                                        */
7525     POWERPC_DEF("440F5",         CPU_POWERPC_440F5,                  440x5),
7526 #endif
7527 #if defined (TODO)
7528     /* PowerPC 440 G5                                                        */
7529     POWERPC_DEF("440G5",         CPU_POWERPC_440G5,                  440x5),
7530 #endif
7531 #if defined (TODO)
7532     /* PowerPC 440H4                                                         */
7533     POWERPC_DEF("440H4",         CPU_POWERPC_440H4,                  440x4),
7534 #endif
7535 #if defined (TODO)
7536     /* PowerPC 440H6                                                         */
7537     POWERPC_DEF("440H6",         CPU_POWERPC_440H6,                  440Gx5),
7538 #endif
7539     /* PowerPC 440 microcontrolers                                           */
7540 #if defined(TODO_USER_ONLY)
7541     /* PowerPC 440 EP                                                        */
7542     POWERPC_DEF("440EP",         CPU_POWERPC_440EP,                  440EP),
7543 #endif
7544 #if defined(TODO_USER_ONLY)
7545     /* PowerPC 440 EPa                                                       */
7546     POWERPC_DEF("440EPa",        CPU_POWERPC_440EPa,                 440EP),
7547 #endif
7548 #if defined(TODO_USER_ONLY)
7549     /* PowerPC 440 EPb                                                       */
7550     POWERPC_DEF("440EPb",        CPU_POWERPC_440EPb,                 440EP),
7551 #endif
7552 #if defined(TODO_USER_ONLY)
7553     /* PowerPC 440 EPX                                                       */
7554     POWERPC_DEF("440EPX",        CPU_POWERPC_440EPX,                 440EP),
7555 #endif
7556 #if defined(TODO_USER_ONLY)
7557     /* PowerPC 440 GP                                                        */
7558     POWERPC_DEF("440GP",         CPU_POWERPC_440GP,                  440GP),
7559 #endif
7560 #if defined(TODO_USER_ONLY)
7561     /* PowerPC 440 GPb                                                       */
7562     POWERPC_DEF("440GPb",        CPU_POWERPC_440GPb,                 440GP),
7563 #endif
7564 #if defined(TODO_USER_ONLY)
7565     /* PowerPC 440 GPc                                                       */
7566     POWERPC_DEF("440GPc",        CPU_POWERPC_440GPc,                 440GP),
7567 #endif
7568 #if defined(TODO_USER_ONLY)
7569     /* PowerPC 440 GR                                                        */
7570     POWERPC_DEF("440GR",         CPU_POWERPC_440GR,                  440x5),
7571 #endif
7572 #if defined(TODO_USER_ONLY)
7573     /* PowerPC 440 GRa                                                       */
7574     POWERPC_DEF("440GRa",        CPU_POWERPC_440GRa,                 440x5),
7575 #endif
7576 #if defined(TODO_USER_ONLY)
7577     /* PowerPC 440 GRX                                                       */
7578     POWERPC_DEF("440GRX",        CPU_POWERPC_440GRX,                 440x5),
7579 #endif
7580 #if defined(TODO_USER_ONLY)
7581     /* PowerPC 440 GX                                                        */
7582     POWERPC_DEF("440GX",         CPU_POWERPC_440GX,                  440EP),
7583 #endif
7584 #if defined(TODO_USER_ONLY)
7585     /* PowerPC 440 GXa                                                       */
7586     POWERPC_DEF("440GXa",        CPU_POWERPC_440GXa,                 440EP),
7587 #endif
7588 #if defined(TODO_USER_ONLY)
7589     /* PowerPC 440 GXb                                                       */
7590     POWERPC_DEF("440GXb",        CPU_POWERPC_440GXb,                 440EP),
7591 #endif
7592 #if defined(TODO_USER_ONLY)
7593     /* PowerPC 440 GXc                                                       */
7594     POWERPC_DEF("440GXc",        CPU_POWERPC_440GXc,                 440EP),
7595 #endif
7596 #if defined(TODO_USER_ONLY)
7597     /* PowerPC 440 GXf                                                       */
7598     POWERPC_DEF("440GXf",        CPU_POWERPC_440GXf,                 440EP),
7599 #endif
7600 #if defined(TODO)
7601     /* PowerPC 440 S                                                         */
7602     POWERPC_DEF("440S",          CPU_POWERPC_440S,                   440),
7603 #endif
7604 #if defined(TODO_USER_ONLY)
7605     /* PowerPC 440 SP                                                        */
7606     POWERPC_DEF("440SP",         CPU_POWERPC_440SP,                  440EP),
7607 #endif
7608 #if defined(TODO_USER_ONLY)
7609     /* PowerPC 440 SP2                                                       */
7610     POWERPC_DEF("440SP2",        CPU_POWERPC_440SP2,                 440EP),
7611 #endif
7612 #if defined(TODO_USER_ONLY)
7613     /* PowerPC 440 SPE                                                       */
7614     POWERPC_DEF("440SPE",        CPU_POWERPC_440SPE,                 440EP),
7615 #endif
7616     /* PowerPC 460 family                                                    */
7617 #if defined (TODO)
7618     /* Generic PowerPC 464                                                   */
7619     POWERPC_DEF("464",           CPU_POWERPC_464,                    460),
7620 #endif
7621     /* PowerPC 464 microcontrolers                                           */
7622 #if defined (TODO)
7623     /* PowerPC 464H90                                                        */
7624     POWERPC_DEF("464H90",        CPU_POWERPC_464H90,                 460),
7625 #endif
7626 #if defined (TODO)
7627     /* PowerPC 464H90F                                                       */
7628     POWERPC_DEF("464H90F",       CPU_POWERPC_464H90F,                460F),
7629 #endif
7630     /* Freescale embedded PowerPC cores                                      */
7631     /* MPC5xx family (aka RCPU)                                              */
7632 #if defined(TODO_USER_ONLY)
7633     /* Generic MPC5xx core                                                   */
7634     POWERPC_DEF("MPC5xx",        CPU_POWERPC_MPC5xx,                 MPC5xx),
7635 #endif
7636 #if defined(TODO_USER_ONLY)
7637     /* Codename for MPC5xx core                                              */
7638     POWERPC_DEF("RCPU",          CPU_POWERPC_MPC5xx,                 MPC5xx),
7639 #endif
7640     /* MPC5xx microcontrollers                                               */
7641 #if defined(TODO_USER_ONLY)
7642     /* MGT560                                                                */
7643     POWERPC_DEF("MGT560",        CPU_POWERPC_MGT560,                 MPC5xx),
7644 #endif
7645 #if defined(TODO_USER_ONLY)
7646     /* MPC509                                                                */
7647     POWERPC_DEF("MPC509",        CPU_POWERPC_MPC509,                 MPC5xx),
7648 #endif
7649 #if defined(TODO_USER_ONLY)
7650     /* MPC533                                                                */
7651     POWERPC_DEF("MPC533",        CPU_POWERPC_MPC533,                 MPC5xx),
7652 #endif
7653 #if defined(TODO_USER_ONLY)
7654     /* MPC534                                                                */
7655     POWERPC_DEF("MPC534",        CPU_POWERPC_MPC534,                 MPC5xx),
7656 #endif
7657 #if defined(TODO_USER_ONLY)
7658     /* MPC555                                                                */
7659     POWERPC_DEF("MPC555",        CPU_POWERPC_MPC555,                 MPC5xx),
7660 #endif
7661 #if defined(TODO_USER_ONLY)
7662     /* MPC556                                                                */
7663     POWERPC_DEF("MPC556",        CPU_POWERPC_MPC556,                 MPC5xx),
7664 #endif
7665 #if defined(TODO_USER_ONLY)
7666     /* MPC560                                                                */
7667     POWERPC_DEF("MPC560",        CPU_POWERPC_MPC560,                 MPC5xx),
7668 #endif
7669 #if defined(TODO_USER_ONLY)
7670     /* MPC561                                                                */
7671     POWERPC_DEF("MPC561",        CPU_POWERPC_MPC561,                 MPC5xx),
7672 #endif
7673 #if defined(TODO_USER_ONLY)
7674     /* MPC562                                                                */
7675     POWERPC_DEF("MPC562",        CPU_POWERPC_MPC562,                 MPC5xx),
7676 #endif
7677 #if defined(TODO_USER_ONLY)
7678     /* MPC563                                                                */
7679     POWERPC_DEF("MPC563",        CPU_POWERPC_MPC563,                 MPC5xx),
7680 #endif
7681 #if defined(TODO_USER_ONLY)
7682     /* MPC564                                                                */
7683     POWERPC_DEF("MPC564",        CPU_POWERPC_MPC564,                 MPC5xx),
7684 #endif
7685 #if defined(TODO_USER_ONLY)
7686     /* MPC565                                                                */
7687     POWERPC_DEF("MPC565",        CPU_POWERPC_MPC565,                 MPC5xx),
7688 #endif
7689 #if defined(TODO_USER_ONLY)
7690     /* MPC566                                                                */
7691     POWERPC_DEF("MPC566",        CPU_POWERPC_MPC566,                 MPC5xx),
7692 #endif
7693     /* MPC8xx family (aka PowerQUICC)                                        */
7694 #if defined(TODO_USER_ONLY)
7695     /* Generic MPC8xx core                                                   */
7696     POWERPC_DEF("MPC8xx",        CPU_POWERPC_MPC8xx,                 MPC8xx),
7697 #endif
7698 #if defined(TODO_USER_ONLY)
7699     /* Codename for MPC8xx core                                              */
7700     POWERPC_DEF("PowerQUICC",    CPU_POWERPC_MPC8xx,                 MPC8xx),
7701 #endif
7702     /* MPC8xx microcontrollers                                               */
7703 #if defined(TODO_USER_ONLY)
7704     /* MGT823                                                                */
7705     POWERPC_DEF("MGT823",        CPU_POWERPC_MGT823,                 MPC8xx),
7706 #endif
7707 #if defined(TODO_USER_ONLY)
7708     /* MPC821                                                                */
7709     POWERPC_DEF("MPC821",        CPU_POWERPC_MPC821,                 MPC8xx),
7710 #endif
7711 #if defined(TODO_USER_ONLY)
7712     /* MPC823                                                                */
7713     POWERPC_DEF("MPC823",        CPU_POWERPC_MPC823,                 MPC8xx),
7714 #endif
7715 #if defined(TODO_USER_ONLY)
7716     /* MPC850                                                                */
7717     POWERPC_DEF("MPC850",        CPU_POWERPC_MPC850,                 MPC8xx),
7718 #endif
7719 #if defined(TODO_USER_ONLY)
7720     /* MPC852T                                                               */
7721     POWERPC_DEF("MPC852T",       CPU_POWERPC_MPC852T,                MPC8xx),
7722 #endif
7723 #if defined(TODO_USER_ONLY)
7724     /* MPC855T                                                               */
7725     POWERPC_DEF("MPC855T",       CPU_POWERPC_MPC855T,                MPC8xx),
7726 #endif
7727 #if defined(TODO_USER_ONLY)
7728     /* MPC857                                                                */
7729     POWERPC_DEF("MPC857",        CPU_POWERPC_MPC857,                 MPC8xx),
7730 #endif
7731 #if defined(TODO_USER_ONLY)
7732     /* MPC859                                                                */
7733     POWERPC_DEF("MPC859",        CPU_POWERPC_MPC859,                 MPC8xx),
7734 #endif
7735 #if defined(TODO_USER_ONLY)
7736     /* MPC860                                                                */
7737     POWERPC_DEF("MPC860",        CPU_POWERPC_MPC860,                 MPC8xx),
7738 #endif
7739 #if defined(TODO_USER_ONLY)
7740     /* MPC862                                                                */
7741     POWERPC_DEF("MPC862",        CPU_POWERPC_MPC862,                 MPC8xx),
7742 #endif
7743 #if defined(TODO_USER_ONLY)
7744     /* MPC866                                                                */
7745     POWERPC_DEF("MPC866",        CPU_POWERPC_MPC866,                 MPC8xx),
7746 #endif
7747 #if defined(TODO_USER_ONLY)
7748     /* MPC870                                                                */
7749     POWERPC_DEF("MPC870",        CPU_POWERPC_MPC870,                 MPC8xx),
7750 #endif
7751 #if defined(TODO_USER_ONLY)
7752     /* MPC875                                                                */
7753     POWERPC_DEF("MPC875",        CPU_POWERPC_MPC875,                 MPC8xx),
7754 #endif
7755 #if defined(TODO_USER_ONLY)
7756     /* MPC880                                                                */
7757     POWERPC_DEF("MPC880",        CPU_POWERPC_MPC880,                 MPC8xx),
7758 #endif
7759 #if defined(TODO_USER_ONLY)
7760     /* MPC885                                                                */
7761     POWERPC_DEF("MPC885",        CPU_POWERPC_MPC885,                 MPC8xx),
7762 #endif
7763     /* MPC82xx family (aka PowerQUICC-II)                                    */
7764     /* Generic MPC52xx core                                                  */
7765     POWERPC_DEF_SVR("MPC52xx",
7766                     CPU_POWERPC_MPC52xx,      POWERPC_SVR_52xx,      G2LE),
7767     /* Generic MPC82xx core                                                  */
7768     POWERPC_DEF("MPC82xx",       CPU_POWERPC_MPC82xx,                G2),
7769     /* Codename for MPC82xx                                                  */
7770     POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx,                G2),
7771     /* PowerPC G2 core                                                       */
7772     POWERPC_DEF("G2",            CPU_POWERPC_G2,                     G2),
7773     /* PowerPC G2 H4 core                                                    */
7774     POWERPC_DEF("G2H4",          CPU_POWERPC_G2H4,                   G2),
7775     /* PowerPC G2 GP core                                                    */
7776     POWERPC_DEF("G2GP",          CPU_POWERPC_G2gp,                   G2),
7777     /* PowerPC G2 LS core                                                    */
7778     POWERPC_DEF("G2LS",          CPU_POWERPC_G2ls,                   G2),
7779     /* PowerPC G2 HiP3 core                                                  */
7780     POWERPC_DEF("G2HiP3",        CPU_POWERPC_G2_HIP3,                G2),
7781     /* PowerPC G2 HiP4 core                                                  */
7782     POWERPC_DEF("G2HiP4",        CPU_POWERPC_G2_HIP4,                G2),
7783     /* PowerPC MPC603 core                                                   */
7784     POWERPC_DEF("MPC603",        CPU_POWERPC_MPC603,                 603E),
7785     /* PowerPC G2le core (same as G2 plus little-endian mode support)        */
7786     POWERPC_DEF("G2le",          CPU_POWERPC_G2LE,                   G2LE),
7787     /* PowerPC G2LE GP core                                                  */
7788     POWERPC_DEF("G2leGP",        CPU_POWERPC_G2LEgp,                 G2LE),
7789     /* PowerPC G2LE LS core                                                  */
7790     POWERPC_DEF("G2leLS",        CPU_POWERPC_G2LEls,                 G2LE),
7791     /* PowerPC G2LE GP1 core                                                 */
7792     POWERPC_DEF("G2leGP1",       CPU_POWERPC_G2LEgp1,                G2LE),
7793     /* PowerPC G2LE GP3 core                                                 */
7794     POWERPC_DEF("G2leGP3",       CPU_POWERPC_G2LEgp1,                G2LE),
7795     /* PowerPC MPC603 microcontrollers                                       */
7796     /* MPC8240                                                               */
7797     POWERPC_DEF("MPC8240",       CPU_POWERPC_MPC8240,                603E),
7798     /* PowerPC G2 microcontrollers                                           */
7799 #if defined(TODO)
7800     /* MPC5121                                                               */
7801     POWERPC_DEF_SVR("MPC5121",
7802                     CPU_POWERPC_MPC5121,      POWERPC_SVR_5121,      G2LE),
7803 #endif
7804     /* MPC5200                                                               */
7805     POWERPC_DEF_SVR("MPC5200",
7806                     CPU_POWERPC_MPC5200,      POWERPC_SVR_5200,      G2LE),
7807     /* MPC5200 v1.0                                                          */
7808     POWERPC_DEF_SVR("MPC5200_v10",
7809                     CPU_POWERPC_MPC5200_v10,  POWERPC_SVR_5200_v10,  G2LE),
7810     /* MPC5200 v1.1                                                          */
7811     POWERPC_DEF_SVR("MPC5200_v11",
7812                     CPU_POWERPC_MPC5200_v11,  POWERPC_SVR_5200_v11,  G2LE),
7813     /* MPC5200 v1.2                                                          */
7814     POWERPC_DEF_SVR("MPC5200_v12",
7815                     CPU_POWERPC_MPC5200_v12,  POWERPC_SVR_5200_v12,  G2LE),
7816     /* MPC5200B                                                              */
7817     POWERPC_DEF_SVR("MPC5200B",
7818                     CPU_POWERPC_MPC5200B,     POWERPC_SVR_5200B,     G2LE),
7819     /* MPC5200B v2.0                                                         */
7820     POWERPC_DEF_SVR("MPC5200B_v20",
7821                     CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
7822     /* MPC5200B v2.1                                                         */
7823     POWERPC_DEF_SVR("MPC5200B_v21",
7824                     CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
7825     /* MPC8241                                                               */
7826     POWERPC_DEF("MPC8241",       CPU_POWERPC_MPC8241,                G2),
7827     /* MPC8245                                                               */
7828     POWERPC_DEF("MPC8245",       CPU_POWERPC_MPC8245,                G2),
7829     /* MPC8247                                                               */
7830     POWERPC_DEF("MPC8247",       CPU_POWERPC_MPC8247,                G2LE),
7831     /* MPC8248                                                               */
7832     POWERPC_DEF("MPC8248",       CPU_POWERPC_MPC8248,                G2LE),
7833     /* MPC8250                                                               */
7834     POWERPC_DEF("MPC8250",       CPU_POWERPC_MPC8250,                G2),
7835     /* MPC8250 HiP3                                                          */
7836     POWERPC_DEF("MPC8250_HiP3",  CPU_POWERPC_MPC8250_HiP3,           G2),
7837     /* MPC8250 HiP4                                                          */
7838     POWERPC_DEF("MPC8250_HiP4",  CPU_POWERPC_MPC8250_HiP4,           G2),
7839     /* MPC8255                                                               */
7840     POWERPC_DEF("MPC8255",       CPU_POWERPC_MPC8255,                G2),
7841     /* MPC8255 HiP3                                                          */
7842     POWERPC_DEF("MPC8255_HiP3",  CPU_POWERPC_MPC8255_HiP3,           G2),
7843     /* MPC8255 HiP4                                                          */
7844     POWERPC_DEF("MPC8255_HiP4",  CPU_POWERPC_MPC8255_HiP4,           G2),
7845     /* MPC8260                                                               */
7846     POWERPC_DEF("MPC8260",       CPU_POWERPC_MPC8260,                G2),
7847     /* MPC8260 HiP3                                                          */
7848     POWERPC_DEF("MPC8260_HiP3",  CPU_POWERPC_MPC8260_HiP3,           G2),
7849     /* MPC8260 HiP4                                                          */
7850     POWERPC_DEF("MPC8260_HiP4",  CPU_POWERPC_MPC8260_HiP4,           G2),
7851     /* MPC8264                                                               */
7852     POWERPC_DEF("MPC8264",       CPU_POWERPC_MPC8264,                G2),
7853     /* MPC8264 HiP3                                                          */
7854     POWERPC_DEF("MPC8264_HiP3",  CPU_POWERPC_MPC8264_HiP3,           G2),
7855     /* MPC8264 HiP4                                                          */
7856     POWERPC_DEF("MPC8264_HiP4",  CPU_POWERPC_MPC8264_HiP4,           G2),
7857     /* MPC8265                                                               */
7858     POWERPC_DEF("MPC8265",       CPU_POWERPC_MPC8265,                G2),
7859     /* MPC8265 HiP3                                                          */
7860     POWERPC_DEF("MPC8265_HiP3",  CPU_POWERPC_MPC8265_HiP3,           G2),
7861     /* MPC8265 HiP4                                                          */
7862     POWERPC_DEF("MPC8265_HiP4",  CPU_POWERPC_MPC8265_HiP4,           G2),
7863     /* MPC8266                                                               */
7864     POWERPC_DEF("MPC8266",       CPU_POWERPC_MPC8266,                G2),
7865     /* MPC8266 HiP3                                                          */
7866     POWERPC_DEF("MPC8266_HiP3",  CPU_POWERPC_MPC8266_HiP3,           G2),
7867     /* MPC8266 HiP4                                                          */
7868     POWERPC_DEF("MPC8266_HiP4",  CPU_POWERPC_MPC8266_HiP4,           G2),
7869     /* MPC8270                                                               */
7870     POWERPC_DEF("MPC8270",       CPU_POWERPC_MPC8270,                G2LE),
7871     /* MPC8271                                                               */
7872     POWERPC_DEF("MPC8271",       CPU_POWERPC_MPC8271,                G2LE),
7873     /* MPC8272                                                               */
7874     POWERPC_DEF("MPC8272",       CPU_POWERPC_MPC8272,                G2LE),
7875     /* MPC8275                                                               */
7876     POWERPC_DEF("MPC8275",       CPU_POWERPC_MPC8275,                G2LE),
7877     /* MPC8280                                                               */
7878     POWERPC_DEF("MPC8280",       CPU_POWERPC_MPC8280,                G2LE),
7879     /* e200 family                                                           */
7880     /* Generic PowerPC e200 core                                             */
7881     POWERPC_DEF("e200",          CPU_POWERPC_e200,                   e200),
7882     /* Generic MPC55xx core                                                  */
7883 #if defined (TODO)
7884     POWERPC_DEF_SVR("MPC55xx",
7885                     CPU_POWERPC_MPC55xx,      POWERPC_SVR_55xx,      e200),
7886 #endif
7887 #if defined (TODO)
7888     /* PowerPC e200z0 core                                                   */
7889     POWERPC_DEF("e200z0",        CPU_POWERPC_e200z0,                 e200),
7890 #endif
7891 #if defined (TODO)
7892     /* PowerPC e200z1 core                                                   */
7893     POWERPC_DEF("e200z1",        CPU_POWERPC_e200z1,                 e200),
7894 #endif
7895 #if defined (TODO)
7896     /* PowerPC e200z3 core                                                   */
7897     POWERPC_DEF("e200z3",        CPU_POWERPC_e200z3,                 e200),
7898 #endif
7899     /* PowerPC e200z5 core                                                   */
7900     POWERPC_DEF("e200z5",        CPU_POWERPC_e200z5,                 e200),
7901     /* PowerPC e200z6 core                                                   */
7902     POWERPC_DEF("e200z6",        CPU_POWERPC_e200z6,                 e200),
7903     /* PowerPC e200 microcontrollers                                         */
7904 #if defined (TODO)
7905     /* MPC5514E                                                              */
7906     POWERPC_DEF_SVR("MPC5514E",
7907                     CPU_POWERPC_MPC5514E,     POWERPC_SVR_5514E,     e200),
7908 #endif
7909 #if defined (TODO)
7910     /* MPC5514E v0                                                           */
7911     POWERPC_DEF_SVR("MPC5514E_v0",
7912                     CPU_POWERPC_MPC5514E_v0,  POWERPC_SVR_5514E_v0,  e200),
7913 #endif
7914 #if defined (TODO)
7915     /* MPC5514E v1                                                           */
7916     POWERPC_DEF_SVR("MPC5514E_v1",
7917                     CPU_POWERPC_MPC5514E_v1,  POWERPC_SVR_5514E_v1,  e200),
7918 #endif
7919 #if defined (TODO)
7920     /* MPC5514G                                                              */
7921     POWERPC_DEF_SVR("MPC5514G",
7922                     CPU_POWERPC_MPC5514G,     POWERPC_SVR_5514G,     e200),
7923 #endif
7924 #if defined (TODO)
7925     /* MPC5514G v0                                                           */
7926     POWERPC_DEF_SVR("MPC5514G_v0",
7927                     CPU_POWERPC_MPC5514G_v0,  POWERPC_SVR_5514G_v0,  e200),
7928 #endif
7929 #if defined (TODO)
7930     /* MPC5514G v1                                                           */
7931     POWERPC_DEF_SVR("MPC5514G_v1",
7932                     CPU_POWERPC_MPC5514G_v1,  POWERPC_SVR_5514G_v1,  e200),
7933 #endif
7934 #if defined (TODO)
7935     /* MPC5515S                                                              */
7936     POWERPC_DEF_SVR("MPC5515S",
7937                     CPU_POWERPC_MPC5515S,     POWERPC_SVR_5515S,     e200),
7938 #endif
7939 #if defined (TODO)
7940     /* MPC5516E                                                              */
7941     POWERPC_DEF_SVR("MPC5516E",
7942                     CPU_POWERPC_MPC5516E,     POWERPC_SVR_5516E,     e200),
7943 #endif
7944 #if defined (TODO)
7945     /* MPC5516E v0                                                           */
7946     POWERPC_DEF_SVR("MPC5516E_v0",
7947                     CPU_POWERPC_MPC5516E_v0,  POWERPC_SVR_5516E_v0,  e200),
7948 #endif
7949 #if defined (TODO)
7950     /* MPC5516E v1                                                           */
7951     POWERPC_DEF_SVR("MPC5516E_v1",
7952                     CPU_POWERPC_MPC5516E_v1,  POWERPC_SVR_5516E_v1,  e200),
7953 #endif
7954 #if defined (TODO)
7955     /* MPC5516G                                                              */
7956     POWERPC_DEF_SVR("MPC5516G",
7957                     CPU_POWERPC_MPC5516G,     POWERPC_SVR_5516G,     e200),
7958 #endif
7959 #if defined (TODO)
7960     /* MPC5516G v0                                                           */
7961     POWERPC_DEF_SVR("MPC5516G_v0",
7962                     CPU_POWERPC_MPC5516G_v0,  POWERPC_SVR_5516G_v0,  e200),
7963 #endif
7964 #if defined (TODO)
7965     /* MPC5516G v1                                                           */
7966     POWERPC_DEF_SVR("MPC5516G_v1",
7967                     CPU_POWERPC_MPC5516G_v1,  POWERPC_SVR_5516G_v1,  e200),
7968 #endif
7969 #if defined (TODO)
7970     /* MPC5516S                                                              */
7971     POWERPC_DEF_SVR("MPC5516S",
7972                     CPU_POWERPC_MPC5516S,     POWERPC_SVR_5516S,     e200),
7973 #endif
7974 #if defined (TODO)
7975     /* MPC5533                                                               */
7976     POWERPC_DEF_SVR("MPC5533",
7977                     CPU_POWERPC_MPC5533,      POWERPC_SVR_5533,      e200),
7978 #endif
7979 #if defined (TODO)
7980     /* MPC5534                                                               */
7981     POWERPC_DEF_SVR("MPC5534",
7982                     CPU_POWERPC_MPC5534,      POWERPC_SVR_5534,      e200),
7983 #endif
7984 #if defined (TODO)
7985     /* MPC5553                                                               */
7986     POWERPC_DEF_SVR("MPC5553",
7987                     CPU_POWERPC_MPC5553,      POWERPC_SVR_5553,      e200),
7988 #endif
7989 #if defined (TODO)
7990     /* MPC5554                                                               */
7991     POWERPC_DEF_SVR("MPC5554",
7992                     CPU_POWERPC_MPC5554,      POWERPC_SVR_5554,      e200),
7993 #endif
7994 #if defined (TODO)
7995     /* MPC5561                                                               */
7996     POWERPC_DEF_SVR("MPC5561",
7997                     CPU_POWERPC_MPC5561,      POWERPC_SVR_5561,      e200),
7998 #endif
7999 #if defined (TODO)
8000     /* MPC5565                                                               */
8001     POWERPC_DEF_SVR("MPC5565",
8002                     CPU_POWERPC_MPC5565,      POWERPC_SVR_5565,      e200),
8003 #endif
8004 #if defined (TODO)
8005     /* MPC5566                                                               */
8006     POWERPC_DEF_SVR("MPC5566",
8007                     CPU_POWERPC_MPC5566,      POWERPC_SVR_5566,      e200),
8008 #endif
8009 #if defined (TODO)
8010     /* MPC5567                                                               */
8011     POWERPC_DEF_SVR("MPC5567",
8012                     CPU_POWERPC_MPC5567,      POWERPC_SVR_5567,      e200),
8013 #endif
8014     /* e300 family                                                           */
8015     /* Generic PowerPC e300 core                                             */
8016     POWERPC_DEF("e300",          CPU_POWERPC_e300,                   e300),
8017     /* PowerPC e300c1 core                                                   */
8018     POWERPC_DEF("e300c1",        CPU_POWERPC_e300c1,                 e300),
8019     /* PowerPC e300c2 core                                                   */
8020     POWERPC_DEF("e300c2",        CPU_POWERPC_e300c2,                 e300),
8021     /* PowerPC e300c3 core                                                   */
8022     POWERPC_DEF("e300c3",        CPU_POWERPC_e300c3,                 e300),
8023     /* PowerPC e300c4 core                                                   */
8024     POWERPC_DEF("e300c4",        CPU_POWERPC_e300c4,                 e300),
8025     /* PowerPC e300 microcontrollers                                         */
8026 #if defined (TODO)
8027     /* MPC8313                                                               */
8028     POWERPC_DEF_SVR("MPC8313",
8029                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8313,      e300),
8030 #endif
8031 #if defined (TODO)
8032     /* MPC8313E                                                              */
8033     POWERPC_DEF_SVR("MPC8313E",
8034                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8313E,     e300),
8035 #endif
8036 #if defined (TODO)
8037     /* MPC8314                                                               */
8038     POWERPC_DEF_SVR("MPC8314",
8039                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8314,      e300),
8040 #endif
8041 #if defined (TODO)
8042     /* MPC8314E                                                              */
8043     POWERPC_DEF_SVR("MPC8314E",
8044                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8314E,     e300),
8045 #endif
8046 #if defined (TODO)
8047     /* MPC8315                                                               */
8048     POWERPC_DEF_SVR("MPC8315",
8049                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8315,      e300),
8050 #endif
8051 #if defined (TODO)
8052     /* MPC8315E                                                              */
8053     POWERPC_DEF_SVR("MPC8315E",
8054                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8315E,     e300),
8055 #endif
8056 #if defined (TODO)
8057     /* MPC8321                                                               */
8058     POWERPC_DEF_SVR("MPC8321",
8059                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8321,      e300),
8060 #endif
8061 #if defined (TODO)
8062     /* MPC8321E                                                              */
8063     POWERPC_DEF_SVR("MPC8321E",
8064                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8321E,     e300),
8065 #endif
8066 #if defined (TODO)
8067     /* MPC8323                                                               */
8068     POWERPC_DEF_SVR("MPC8323",
8069                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8323,      e300),
8070 #endif
8071 #if defined (TODO)
8072     /* MPC8323E                                                              */
8073     POWERPC_DEF_SVR("MPC8323E",
8074                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8323E,     e300),
8075 #endif
8076     /* MPC8343                                                               */
8077     POWERPC_DEF_SVR("MPC8343",
8078                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343,      e300),
8079     /* MPC8343A                                                              */
8080     POWERPC_DEF_SVR("MPC8343A",
8081                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343A,     e300),
8082     /* MPC8343E                                                              */
8083     POWERPC_DEF_SVR("MPC8343E",
8084                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343E,     e300),
8085     /* MPC8343EA                                                             */
8086     POWERPC_DEF_SVR("MPC8343EA",
8087                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343EA,    e300),
8088     /* MPC8347                                                               */
8089     POWERPC_DEF_SVR("MPC8347",
8090                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347,      e300),
8091     /* MPC8347T                                                              */
8092     POWERPC_DEF_SVR("MPC8347T",
8093                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347T,     e300),
8094     /* MPC8347P                                                              */
8095     POWERPC_DEF_SVR("MPC8347P",
8096                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347P,     e300),
8097     /* MPC8347A                                                              */
8098     POWERPC_DEF_SVR("MPC8347A",
8099                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347A,     e300),
8100     /* MPC8347AT                                                             */
8101     POWERPC_DEF_SVR("MPC8347AT",
8102                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347AT,    e300),
8103     /* MPC8347AP                                                             */
8104     POWERPC_DEF_SVR("MPC8347AP",
8105                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347AP,    e300),
8106     /* MPC8347E                                                              */
8107     POWERPC_DEF_SVR("MPC8347E",
8108                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347E,     e300),
8109     /* MPC8347ET                                                             */
8110     POWERPC_DEF_SVR("MPC8347ET",
8111                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347ET,    e300),
8112     /* MPC8343EP                                                             */
8113     POWERPC_DEF_SVR("MPC8347EP",
8114                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EP,    e300),
8115     /* MPC8347EA                                                             */
8116     POWERPC_DEF_SVR("MPC8347EA",
8117                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EA,    e300),
8118     /* MPC8347EAT                                                            */
8119     POWERPC_DEF_SVR("MPC8347EAT",
8120                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EAT,   e300),
8121     /* MPC8343EAP                                                            */
8122     POWERPC_DEF_SVR("MPC8347EAP",
8123                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EAP,   e300),
8124     /* MPC8349                                                               */
8125     POWERPC_DEF_SVR("MPC8349",
8126                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349,      e300),
8127     /* MPC8349A                                                              */
8128     POWERPC_DEF_SVR("MPC8349A",
8129                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349A,     e300),
8130     /* MPC8349E                                                              */
8131     POWERPC_DEF_SVR("MPC8349E",
8132                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349E,     e300),
8133     /* MPC8349EA                                                             */
8134     POWERPC_DEF_SVR("MPC8349EA",
8135                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349EA,    e300),
8136 #if defined (TODO)
8137     /* MPC8358E                                                              */
8138     POWERPC_DEF_SVR("MPC8358E",
8139                     CPU_POWERPC_MPC835x,      POWERPC_SVR_8358E,     e300),
8140 #endif
8141 #if defined (TODO)
8142     /* MPC8360E                                                              */
8143     POWERPC_DEF_SVR("MPC8360E",
8144                     CPU_POWERPC_MPC836x,      POWERPC_SVR_8360E,     e300),
8145 #endif
8146     /* MPC8377                                                               */
8147     POWERPC_DEF_SVR("MPC8377",
8148                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8377,      e300),
8149     /* MPC8377E                                                              */
8150     POWERPC_DEF_SVR("MPC8377E",
8151                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8377E,     e300),
8152     /* MPC8378                                                               */
8153     POWERPC_DEF_SVR("MPC8378",
8154                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8378,      e300),
8155     /* MPC8378E                                                              */
8156     POWERPC_DEF_SVR("MPC8378E",
8157                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8378E,     e300),
8158     /* MPC8379                                                               */
8159     POWERPC_DEF_SVR("MPC8379",
8160                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8379,      e300),
8161     /* MPC8379E                                                              */
8162     POWERPC_DEF_SVR("MPC8379E",
8163                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8379E,     e300),
8164     /* e500 family                                                           */
8165     /* PowerPC e500 core                                                     */
8166     POWERPC_DEF("e500",          CPU_POWERPC_e500v2_v22,             e500v2),
8167     /* PowerPC e500v1 core                                                   */
8168     POWERPC_DEF("e500v1",        CPU_POWERPC_e500v1,                 e500v1),
8169     /* PowerPC e500 v1.0 core                                                */
8170     POWERPC_DEF("e500_v10",      CPU_POWERPC_e500v1_v10,             e500v1),
8171     /* PowerPC e500 v2.0 core                                                */
8172     POWERPC_DEF("e500_v20",      CPU_POWERPC_e500v1_v20,             e500v1),
8173     /* PowerPC e500v2 core                                                   */
8174     POWERPC_DEF("e500v2",        CPU_POWERPC_e500v2,                 e500v2),
8175     /* PowerPC e500v2 v1.0 core                                              */
8176     POWERPC_DEF("e500v2_v10",    CPU_POWERPC_e500v2_v10,             e500v2),
8177     /* PowerPC e500v2 v2.0 core                                              */
8178     POWERPC_DEF("e500v2_v20",    CPU_POWERPC_e500v2_v20,             e500v2),
8179     /* PowerPC e500v2 v2.1 core                                              */
8180     POWERPC_DEF("e500v2_v21",    CPU_POWERPC_e500v2_v21,             e500v2),
8181     /* PowerPC e500v2 v2.2 core                                              */
8182     POWERPC_DEF("e500v2_v22",    CPU_POWERPC_e500v2_v22,             e500v2),
8183     /* PowerPC e500v2 v3.0 core                                              */
8184     POWERPC_DEF("e500v2_v30",    CPU_POWERPC_e500v2_v30,             e500v2),
8185     /* PowerPC e500 microcontrollers                                         */
8186     /* MPC8533                                                               */
8187     POWERPC_DEF_SVR("MPC8533",
8188                     CPU_POWERPC_MPC8533,      POWERPC_SVR_8533,      e500v2),
8189     /* MPC8533 v1.0                                                          */
8190     POWERPC_DEF_SVR("MPC8533_v10",
8191                     CPU_POWERPC_MPC8533_v10,  POWERPC_SVR_8533_v10,  e500v2),
8192     /* MPC8533 v1.1                                                          */
8193     POWERPC_DEF_SVR("MPC8533_v11",
8194                     CPU_POWERPC_MPC8533_v11,  POWERPC_SVR_8533_v11,  e500v2),
8195     /* MPC8533E                                                              */
8196     POWERPC_DEF_SVR("MPC8533E",
8197                     CPU_POWERPC_MPC8533E,     POWERPC_SVR_8533E,     e500v2),
8198     /* MPC8533E v1.0                                                         */
8199     POWERPC_DEF_SVR("MPC8533E_v10",
8200                     CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
8201     POWERPC_DEF_SVR("MPC8533E_v11",
8202                     CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
8203     /* MPC8540                                                               */
8204     POWERPC_DEF_SVR("MPC8540",
8205                     CPU_POWERPC_MPC8540,      POWERPC_SVR_8540,      e500v1),
8206     /* MPC8540 v1.0                                                          */
8207     POWERPC_DEF_SVR("MPC8540_v10",
8208                     CPU_POWERPC_MPC8540_v10,  POWERPC_SVR_8540_v10,  e500v1),
8209     /* MPC8540 v2.0                                                          */
8210     POWERPC_DEF_SVR("MPC8540_v20",
8211                     CPU_POWERPC_MPC8540_v20,  POWERPC_SVR_8540_v20,  e500v1),
8212     /* MPC8540 v2.1                                                          */
8213     POWERPC_DEF_SVR("MPC8540_v21",
8214                     CPU_POWERPC_MPC8540_v21,  POWERPC_SVR_8540_v21,  e500v1),
8215     /* MPC8541                                                               */
8216     POWERPC_DEF_SVR("MPC8541",
8217                     CPU_POWERPC_MPC8541,      POWERPC_SVR_8541,      e500v1),
8218     /* MPC8541 v1.0                                                          */
8219     POWERPC_DEF_SVR("MPC8541_v10",
8220                     CPU_POWERPC_MPC8541_v10,  POWERPC_SVR_8541_v10,  e500v1),
8221     /* MPC8541 v1.1                                                          */
8222     POWERPC_DEF_SVR("MPC8541_v11",
8223                     CPU_POWERPC_MPC8541_v11,  POWERPC_SVR_8541_v11,  e500v1),
8224     /* MPC8541E                                                              */
8225     POWERPC_DEF_SVR("MPC8541E",
8226                     CPU_POWERPC_MPC8541E,     POWERPC_SVR_8541E,     e500v1),
8227     /* MPC8541E v1.0                                                         */
8228     POWERPC_DEF_SVR("MPC8541E_v10",
8229                     CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
8230     /* MPC8541E v1.1                                                         */
8231     POWERPC_DEF_SVR("MPC8541E_v11",
8232                     CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
8233     /* MPC8543                                                               */
8234     POWERPC_DEF_SVR("MPC8543",
8235                     CPU_POWERPC_MPC8543,      POWERPC_SVR_8543,      e500v2),
8236     /* MPC8543 v1.0                                                          */
8237     POWERPC_DEF_SVR("MPC8543_v10",
8238                     CPU_POWERPC_MPC8543_v10,  POWERPC_SVR_8543_v10,  e500v2),
8239     /* MPC8543 v1.1                                                          */
8240     POWERPC_DEF_SVR("MPC8543_v11",
8241                     CPU_POWERPC_MPC8543_v11,  POWERPC_SVR_8543_v11,  e500v2),
8242     /* MPC8543 v2.0                                                          */
8243     POWERPC_DEF_SVR("MPC8543_v20",
8244                     CPU_POWERPC_MPC8543_v20,  POWERPC_SVR_8543_v20,  e500v2),
8245     /* MPC8543 v2.1                                                          */
8246     POWERPC_DEF_SVR("MPC8543_v21",
8247                     CPU_POWERPC_MPC8543_v21,  POWERPC_SVR_8543_v21,  e500v2),
8248     /* MPC8543E                                                              */
8249     POWERPC_DEF_SVR("MPC8543E",
8250                     CPU_POWERPC_MPC8543E,     POWERPC_SVR_8543E,     e500v2),
8251     /* MPC8543E v1.0                                                         */
8252     POWERPC_DEF_SVR("MPC8543E_v10",
8253                     CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
8254     /* MPC8543E v1.1                                                         */
8255     POWERPC_DEF_SVR("MPC8543E_v11",
8256                     CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
8257     /* MPC8543E v2.0                                                         */
8258     POWERPC_DEF_SVR("MPC8543E_v20",
8259                     CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
8260     /* MPC8543E v2.1                                                         */
8261     POWERPC_DEF_SVR("MPC8543E_v21",
8262                     CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
8263     /* MPC8544                                                               */
8264     POWERPC_DEF_SVR("MPC8544",
8265                     CPU_POWERPC_MPC8544,      POWERPC_SVR_8544,      e500v2),
8266     /* MPC8544 v1.0                                                          */
8267     POWERPC_DEF_SVR("MPC8544_v10",
8268                     CPU_POWERPC_MPC8544_v10,  POWERPC_SVR_8544_v10,  e500v2),
8269     /* MPC8544 v1.1                                                          */
8270     POWERPC_DEF_SVR("MPC8544_v11",
8271                     CPU_POWERPC_MPC8544_v11,  POWERPC_SVR_8544_v11,  e500v2),
8272     /* MPC8544E                                                              */
8273     POWERPC_DEF_SVR("MPC8544E",
8274                     CPU_POWERPC_MPC8544E,     POWERPC_SVR_8544E,     e500v2),
8275     /* MPC8544E v1.0                                                         */
8276     POWERPC_DEF_SVR("MPC8544E_v10",
8277                     CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
8278     /* MPC8544E v1.1                                                         */
8279     POWERPC_DEF_SVR("MPC8544E_v11",
8280                     CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
8281     /* MPC8545                                                               */
8282     POWERPC_DEF_SVR("MPC8545",
8283                     CPU_POWERPC_MPC8545,      POWERPC_SVR_8545,      e500v2),
8284     /* MPC8545 v2.0                                                          */
8285     POWERPC_DEF_SVR("MPC8545_v20",
8286                     CPU_POWERPC_MPC8545_v20,  POWERPC_SVR_8545_v20,  e500v2),
8287     /* MPC8545 v2.1                                                          */
8288     POWERPC_DEF_SVR("MPC8545_v21",
8289                     CPU_POWERPC_MPC8545_v21,  POWERPC_SVR_8545_v21,  e500v2),
8290     /* MPC8545E                                                              */
8291     POWERPC_DEF_SVR("MPC8545E",
8292                     CPU_POWERPC_MPC8545E,     POWERPC_SVR_8545E,     e500v2),
8293     /* MPC8545E v2.0                                                         */
8294     POWERPC_DEF_SVR("MPC8545E_v20",
8295                     CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
8296     /* MPC8545E v2.1                                                         */
8297     POWERPC_DEF_SVR("MPC8545E_v21",
8298                     CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
8299     /* MPC8547E                                                              */
8300     POWERPC_DEF_SVR("MPC8547E",
8301                     CPU_POWERPC_MPC8547E,     POWERPC_SVR_8547E,     e500v2),
8302     /* MPC8547E v2.0                                                         */
8303     POWERPC_DEF_SVR("MPC8547E_v20",
8304                     CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
8305     /* MPC8547E v2.1                                                         */
8306     POWERPC_DEF_SVR("MPC8547E_v21",
8307                     CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
8308     /* MPC8548                                                               */
8309     POWERPC_DEF_SVR("MPC8548",
8310                     CPU_POWERPC_MPC8548,      POWERPC_SVR_8548,      e500v2),
8311     /* MPC8548 v1.0                                                          */
8312     POWERPC_DEF_SVR("MPC8548_v10",
8313                     CPU_POWERPC_MPC8548_v10,  POWERPC_SVR_8548_v10,  e500v2),
8314     /* MPC8548 v1.1                                                          */
8315     POWERPC_DEF_SVR("MPC8548_v11",
8316                     CPU_POWERPC_MPC8548_v11,  POWERPC_SVR_8548_v11,  e500v2),
8317     /* MPC8548 v2.0                                                          */
8318     POWERPC_DEF_SVR("MPC8548_v20",
8319                     CPU_POWERPC_MPC8548_v20,  POWERPC_SVR_8548_v20,  e500v2),
8320     /* MPC8548 v2.1                                                          */
8321     POWERPC_DEF_SVR("MPC8548_v21",
8322                     CPU_POWERPC_MPC8548_v21,  POWERPC_SVR_8548_v21,  e500v2),
8323     /* MPC8548E                                                              */
8324     POWERPC_DEF_SVR("MPC8548E",
8325                     CPU_POWERPC_MPC8548E,     POWERPC_SVR_8548E,     e500v2),
8326     /* MPC8548E v1.0                                                         */
8327     POWERPC_DEF_SVR("MPC8548E_v10",
8328                     CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
8329     /* MPC8548E v1.1                                                         */
8330     POWERPC_DEF_SVR("MPC8548E_v11",
8331                     CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
8332     /* MPC8548E v2.0                                                         */
8333     POWERPC_DEF_SVR("MPC8548E_v20",
8334                     CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
8335     /* MPC8548E v2.1                                                         */
8336     POWERPC_DEF_SVR("MPC8548E_v21",
8337                     CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
8338     /* MPC8555                                                               */
8339     POWERPC_DEF_SVR("MPC8555",
8340                     CPU_POWERPC_MPC8555,      POWERPC_SVR_8555,      e500v2),
8341     /* MPC8555 v1.0                                                          */
8342     POWERPC_DEF_SVR("MPC8555_v10",
8343                     CPU_POWERPC_MPC8555_v10,  POWERPC_SVR_8555_v10,  e500v2),
8344     /* MPC8555 v1.1                                                          */
8345     POWERPC_DEF_SVR("MPC8555_v11",
8346                     CPU_POWERPC_MPC8555_v11,  POWERPC_SVR_8555_v11,  e500v2),
8347     /* MPC8555E                                                              */
8348     POWERPC_DEF_SVR("MPC8555E",
8349                     CPU_POWERPC_MPC8555E,     POWERPC_SVR_8555E,     e500v2),
8350     /* MPC8555E v1.0                                                         */
8351     POWERPC_DEF_SVR("MPC8555E_v10",
8352                     CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
8353     /* MPC8555E v1.1                                                         */
8354     POWERPC_DEF_SVR("MPC8555E_v11",
8355                     CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
8356     /* MPC8560                                                               */
8357     POWERPC_DEF_SVR("MPC8560",
8358                     CPU_POWERPC_MPC8560,      POWERPC_SVR_8560,      e500v2),
8359     /* MPC8560 v1.0                                                          */
8360     POWERPC_DEF_SVR("MPC8560_v10",
8361                     CPU_POWERPC_MPC8560_v10,  POWERPC_SVR_8560_v10,  e500v2),
8362     /* MPC8560 v2.0                                                          */
8363     POWERPC_DEF_SVR("MPC8560_v20",
8364                     CPU_POWERPC_MPC8560_v20,  POWERPC_SVR_8560_v20,  e500v2),
8365     /* MPC8560 v2.1                                                          */
8366     POWERPC_DEF_SVR("MPC8560_v21",
8367                     CPU_POWERPC_MPC8560_v21,  POWERPC_SVR_8560_v21,  e500v2),
8368     /* MPC8567                                                               */
8369     POWERPC_DEF_SVR("MPC8567",
8370                     CPU_POWERPC_MPC8567,      POWERPC_SVR_8567,      e500v2),
8371     /* MPC8567E                                                              */
8372     POWERPC_DEF_SVR("MPC8567E",
8373                     CPU_POWERPC_MPC8567E,     POWERPC_SVR_8567E,     e500v2),
8374     /* MPC8568                                                               */
8375     POWERPC_DEF_SVR("MPC8568",
8376                     CPU_POWERPC_MPC8568,      POWERPC_SVR_8568,      e500v2),
8377     /* MPC8568E                                                              */
8378     POWERPC_DEF_SVR("MPC8568E",
8379                     CPU_POWERPC_MPC8568E,     POWERPC_SVR_8568E,     e500v2),
8380     /* MPC8572                                                               */
8381     POWERPC_DEF_SVR("MPC8572",
8382                     CPU_POWERPC_MPC8572,      POWERPC_SVR_8572,      e500v2),
8383     /* MPC8572E                                                              */
8384     POWERPC_DEF_SVR("MPC8572E",
8385                     CPU_POWERPC_MPC8572E,     POWERPC_SVR_8572E,     e500v2),
8386     /* e600 family                                                           */
8387     /* PowerPC e600 core                                                     */
8388     POWERPC_DEF("e600",          CPU_POWERPC_e600,                   7400),
8389     /* PowerPC e600 microcontrollers                                         */
8390 #if defined (TODO)
8391     /* MPC8610                                                               */
8392     POWERPC_DEF_SVR("MPC8610",
8393                     CPU_POWERPC_MPC8610,      POWERPC_SVR_8610,      7400),
8394 #endif
8395     /* MPC8641                                                               */
8396     POWERPC_DEF_SVR("MPC8641",
8397                     CPU_POWERPC_MPC8641,      POWERPC_SVR_8641,      7400),
8398     /* MPC8641D                                                              */
8399     POWERPC_DEF_SVR("MPC8641D",
8400                     CPU_POWERPC_MPC8641D,     POWERPC_SVR_8641D,     7400),
8401     /* 32 bits "classic" PowerPC                                             */
8402     /* PowerPC 6xx family                                                    */
8403     /* PowerPC 601                                                           */
8404     POWERPC_DEF("601",           CPU_POWERPC_601,                    601v),
8405     /* PowerPC 601v0                                                         */
8406     POWERPC_DEF("601_v0",        CPU_POWERPC_601_v0,                 601),
8407     /* PowerPC 601v1                                                         */
8408     POWERPC_DEF("601_v1",        CPU_POWERPC_601_v1,                 601),
8409     /* PowerPC 601v                                                          */
8410     POWERPC_DEF("601v",          CPU_POWERPC_601v,                   601v),
8411     /* PowerPC 601v2                                                         */
8412     POWERPC_DEF("601_v2",        CPU_POWERPC_601_v2,                 601v),
8413     /* PowerPC 602                                                           */
8414     POWERPC_DEF("602",           CPU_POWERPC_602,                    602),
8415     /* PowerPC 603                                                           */
8416     POWERPC_DEF("603",           CPU_POWERPC_603,                    603),
8417     /* Code name for PowerPC 603                                             */
8418     POWERPC_DEF("Vanilla",       CPU_POWERPC_603,                    603),
8419     /* PowerPC 603e (aka PID6)                                               */
8420     POWERPC_DEF("603e",          CPU_POWERPC_603E,                   603E),
8421     /* Code name for PowerPC 603e                                            */
8422     POWERPC_DEF("Stretch",       CPU_POWERPC_603E,                   603E),
8423     /* PowerPC 603e v1.1                                                     */
8424     POWERPC_DEF("603e_v1.1",     CPU_POWERPC_603E_v11,               603E),
8425     /* PowerPC 603e v1.2                                                     */
8426     POWERPC_DEF("603e_v1.2",     CPU_POWERPC_603E_v12,               603E),
8427     /* PowerPC 603e v1.3                                                     */
8428     POWERPC_DEF("603e_v1.3",     CPU_POWERPC_603E_v13,               603E),
8429     /* PowerPC 603e v1.4                                                     */
8430     POWERPC_DEF("603e_v1.4",     CPU_POWERPC_603E_v14,               603E),
8431     /* PowerPC 603e v2.2                                                     */
8432     POWERPC_DEF("603e_v2.2",     CPU_POWERPC_603E_v22,               603E),
8433     /* PowerPC 603e v3                                                       */
8434     POWERPC_DEF("603e_v3",       CPU_POWERPC_603E_v3,                603E),
8435     /* PowerPC 603e v4                                                       */
8436     POWERPC_DEF("603e_v4",       CPU_POWERPC_603E_v4,                603E),
8437     /* PowerPC 603e v4.1                                                     */
8438     POWERPC_DEF("603e_v4.1",     CPU_POWERPC_603E_v41,               603E),
8439     /* PowerPC 603e (aka PID7)                                               */
8440     POWERPC_DEF("603e7",         CPU_POWERPC_603E7,                  603E),
8441     /* PowerPC 603e7t                                                        */
8442     POWERPC_DEF("603e7t",        CPU_POWERPC_603E7t,                 603E),
8443     /* PowerPC 603e7v                                                        */
8444     POWERPC_DEF("603e7v",        CPU_POWERPC_603E7v,                 603E),
8445     /* Code name for PowerPC 603ev                                           */
8446     POWERPC_DEF("Vaillant",      CPU_POWERPC_603E7v,                 603E),
8447     /* PowerPC 603e7v1                                                       */
8448     POWERPC_DEF("603e7v1",       CPU_POWERPC_603E7v1,                603E),
8449     /* PowerPC 603e7v2                                                       */
8450     POWERPC_DEF("603e7v2",       CPU_POWERPC_603E7v2,                603E),
8451     /* PowerPC 603p (aka PID7v)                                              */
8452     POWERPC_DEF("603p",          CPU_POWERPC_603P,                   603E),
8453     /* PowerPC 603r (aka PID7t)                                              */
8454     POWERPC_DEF("603r",          CPU_POWERPC_603R,                   603E),
8455     /* Code name for PowerPC 603r                                            */
8456     POWERPC_DEF("Goldeneye",     CPU_POWERPC_603R,                   603E),
8457     /* PowerPC 604                                                           */
8458     POWERPC_DEF("604",           CPU_POWERPC_604,                    604),
8459     /* PowerPC 604e (aka PID9)                                               */
8460     POWERPC_DEF("604e",          CPU_POWERPC_604E,                   604E),
8461     /* Code name for PowerPC 604e                                            */
8462     POWERPC_DEF("Sirocco",       CPU_POWERPC_604E,                   604E),
8463     /* PowerPC 604e v1.0                                                     */
8464     POWERPC_DEF("604e_v1.0",     CPU_POWERPC_604E_v10,               604E),
8465     /* PowerPC 604e v2.2                                                     */
8466     POWERPC_DEF("604e_v2.2",     CPU_POWERPC_604E_v22,               604E),
8467     /* PowerPC 604e v2.4                                                     */
8468     POWERPC_DEF("604e_v2.4",     CPU_POWERPC_604E_v24,               604E),
8469     /* PowerPC 604r (aka PIDA)                                               */
8470     POWERPC_DEF("604r",          CPU_POWERPC_604R,                   604E),
8471     /* Code name for PowerPC 604r                                            */
8472     POWERPC_DEF("Mach5",         CPU_POWERPC_604R,                   604E),
8473 #if defined(TODO)
8474     /* PowerPC 604ev                                                         */
8475     POWERPC_DEF("604ev",         CPU_POWERPC_604EV,                  604E),
8476 #endif
8477     /* PowerPC 7xx family                                                    */
8478     /* Generic PowerPC 740 (G3)                                              */
8479     POWERPC_DEF("740",           CPU_POWERPC_7x0,                    740),
8480     /* Code name for PowerPC 740                                             */
8481     POWERPC_DEF("Arthur",        CPU_POWERPC_7x0,                    740),
8482     /* Generic PowerPC 750 (G3)                                              */
8483     POWERPC_DEF("750",           CPU_POWERPC_7x0,                    750),
8484     /* Code name for PowerPC 750                                             */
8485     POWERPC_DEF("Typhoon",       CPU_POWERPC_7x0,                    750),
8486     /* PowerPC 740/750 is also known as G3                                   */
8487     POWERPC_DEF("G3",            CPU_POWERPC_7x0,                    750),
8488     /* PowerPC 740 v1.0 (G3)                                                 */
8489     POWERPC_DEF("740_v1.0",      CPU_POWERPC_7x0_v10,                740),
8490     /* PowerPC 750 v1.0 (G3)                                                 */
8491     POWERPC_DEF("750_v1.0",      CPU_POWERPC_7x0_v10,                750),
8492     /* PowerPC 740 v2.0 (G3)                                                 */
8493     POWERPC_DEF("740_v2.0",      CPU_POWERPC_7x0_v20,                740),
8494     /* PowerPC 750 v2.0 (G3)                                                 */
8495     POWERPC_DEF("750_v2.0",      CPU_POWERPC_7x0_v20,                750),
8496     /* PowerPC 740 v2.1 (G3)                                                 */
8497     POWERPC_DEF("740_v2.1",      CPU_POWERPC_7x0_v21,                740),
8498     /* PowerPC 750 v2.1 (G3)                                                 */
8499     POWERPC_DEF("750_v2.1",      CPU_POWERPC_7x0_v21,                750),
8500     /* PowerPC 740 v2.2 (G3)                                                 */
8501     POWERPC_DEF("740_v2.2",      CPU_POWERPC_7x0_v22,                740),
8502     /* PowerPC 750 v2.2 (G3)                                                 */
8503     POWERPC_DEF("750_v2.2",      CPU_POWERPC_7x0_v22,                750),
8504     /* PowerPC 740 v3.0 (G3)                                                 */
8505     POWERPC_DEF("740_v3.0",      CPU_POWERPC_7x0_v30,                740),
8506     /* PowerPC 750 v3.0 (G3)                                                 */
8507     POWERPC_DEF("750_v3.0",      CPU_POWERPC_7x0_v30,                750),
8508     /* PowerPC 740 v3.1 (G3)                                                 */
8509     POWERPC_DEF("740_v3.1",      CPU_POWERPC_7x0_v31,                740),
8510     /* PowerPC 750 v3.1 (G3)                                                 */
8511     POWERPC_DEF("750_v3.1",      CPU_POWERPC_7x0_v31,                750),
8512     /* PowerPC 740E (G3)                                                     */
8513     POWERPC_DEF("740e",          CPU_POWERPC_740E,                   740),
8514     /* PowerPC 750E (G3)                                                     */
8515     POWERPC_DEF("750e",          CPU_POWERPC_750E,                   750),
8516     /* PowerPC 740P (G3)                                                     */
8517     POWERPC_DEF("740p",          CPU_POWERPC_7x0P,                   740),
8518     /* PowerPC 750P (G3)                                                     */
8519     POWERPC_DEF("750p",          CPU_POWERPC_7x0P,                   750),
8520     /* Code name for PowerPC 740P/750P (G3)                                  */
8521     POWERPC_DEF("Conan/Doyle",   CPU_POWERPC_7x0P,                   750),
8522     /* PowerPC 750CL (G3 embedded)                                           */
8523     POWERPC_DEF("750cl",         CPU_POWERPC_750CL,                  750cl),
8524     /* PowerPC 750CL v1.0                                                    */
8525     POWERPC_DEF("750cl_v1.0",    CPU_POWERPC_750CL_v10,              750cl),
8526     /* PowerPC 750CL v2.0                                                    */
8527     POWERPC_DEF("750cl_v2.0",    CPU_POWERPC_750CL_v20,              750cl),
8528     /* PowerPC 750CX (G3 embedded)                                           */
8529     POWERPC_DEF("750cx",         CPU_POWERPC_750CX,                  750cx),
8530     /* PowerPC 750CX v1.0 (G3 embedded)                                      */
8531     POWERPC_DEF("750cx_v1.0",    CPU_POWERPC_750CX_v10,              750cx),
8532     /* PowerPC 750CX v2.1 (G3 embedded)                                      */
8533     POWERPC_DEF("750cx_v2.0",    CPU_POWERPC_750CX_v20,              750cx),
8534     /* PowerPC 750CX v2.1 (G3 embedded)                                      */
8535     POWERPC_DEF("750cx_v2.1",    CPU_POWERPC_750CX_v21,              750cx),
8536     /* PowerPC 750CX v2.2 (G3 embedded)                                      */
8537     POWERPC_DEF("750cx_v2.2",    CPU_POWERPC_750CX_v22,              750cx),
8538     /* PowerPC 750CXe (G3 embedded)                                          */
8539     POWERPC_DEF("750cxe",        CPU_POWERPC_750CXE,                 750cx),
8540     /* PowerPC 750CXe v2.1 (G3 embedded)                                     */
8541     POWERPC_DEF("750cxe_v2.1",   CPU_POWERPC_750CXE_v21,             750cx),
8542     /* PowerPC 750CXe v2.2 (G3 embedded)                                     */
8543     POWERPC_DEF("750cxe_v2.2",   CPU_POWERPC_750CXE_v22,             750cx),
8544     /* PowerPC 750CXe v2.3 (G3 embedded)                                     */
8545     POWERPC_DEF("750cxe_v2.3",   CPU_POWERPC_750CXE_v23,             750cx),
8546     /* PowerPC 750CXe v2.4 (G3 embedded)                                     */
8547     POWERPC_DEF("750cxe_v2.4",   CPU_POWERPC_750CXE_v24,             750cx),
8548     /* PowerPC 750CXe v2.4b (G3 embedded)                                    */
8549     POWERPC_DEF("750cxe_v2.4b",  CPU_POWERPC_750CXE_v24b,            750cx),
8550     /* PowerPC 750CXe v3.0 (G3 embedded)                                     */
8551     POWERPC_DEF("750cxe_v3.0",   CPU_POWERPC_750CXE_v30,             750cx),
8552     /* PowerPC 750CXe v3.1 (G3 embedded)                                     */
8553     POWERPC_DEF("750cxe_v3.1",   CPU_POWERPC_750CXE_v31,             750cx),
8554     /* PowerPC 750CXe v3.1b (G3 embedded)                                    */
8555     POWERPC_DEF("750cxe_v3.1b",  CPU_POWERPC_750CXE_v31b,            750cx),
8556     /* PowerPC 750CXr (G3 embedded)                                          */
8557     POWERPC_DEF("750cxr",        CPU_POWERPC_750CXR,                 750cx),
8558     /* PowerPC 750FL (G3 embedded)                                           */
8559     POWERPC_DEF("750fl",         CPU_POWERPC_750FL,                  750fx),
8560     /* PowerPC 750FX (G3 embedded)                                           */
8561     POWERPC_DEF("750fx",         CPU_POWERPC_750FX,                  750fx),
8562     /* PowerPC 750FX v1.0 (G3 embedded)                                      */
8563     POWERPC_DEF("750fx_v1.0",    CPU_POWERPC_750FX_v10,              750fx),
8564     /* PowerPC 750FX v2.0 (G3 embedded)                                      */
8565     POWERPC_DEF("750fx_v2.0",    CPU_POWERPC_750FX_v20,              750fx),
8566     /* PowerPC 750FX v2.1 (G3 embedded)                                      */
8567     POWERPC_DEF("750fx_v2.1",    CPU_POWERPC_750FX_v21,              750fx),
8568     /* PowerPC 750FX v2.2 (G3 embedded)                                      */
8569     POWERPC_DEF("750fx_v2.2",    CPU_POWERPC_750FX_v22,              750fx),
8570     /* PowerPC 750FX v2.3 (G3 embedded)                                      */
8571     POWERPC_DEF("750fx_v2.3",    CPU_POWERPC_750FX_v23,              750fx),
8572     /* PowerPC 750GL (G3 embedded)                                           */
8573     POWERPC_DEF("750gl",         CPU_POWERPC_750GL,                  750gx),
8574     /* PowerPC 750GX (G3 embedded)                                           */
8575     POWERPC_DEF("750gx",         CPU_POWERPC_750GX,                  750gx),
8576     /* PowerPC 750GX v1.0 (G3 embedded)                                      */
8577     POWERPC_DEF("750gx_v1.0",    CPU_POWERPC_750GX_v10,              750gx),
8578     /* PowerPC 750GX v1.1 (G3 embedded)                                      */
8579     POWERPC_DEF("750gx_v1.1",    CPU_POWERPC_750GX_v11,              750gx),
8580     /* PowerPC 750GX v1.2 (G3 embedded)                                      */
8581     POWERPC_DEF("750gx_v1.2",    CPU_POWERPC_750GX_v12,              750gx),
8582     /* PowerPC 750L (G3 embedded)                                            */
8583     POWERPC_DEF("750l",          CPU_POWERPC_750L,                   750),
8584     /* Code name for PowerPC 750L (G3 embedded)                              */
8585     POWERPC_DEF("LoneStar",      CPU_POWERPC_750L,                   750),
8586     /* PowerPC 750L v2.0 (G3 embedded)                                       */
8587     POWERPC_DEF("750l_v2.0",     CPU_POWERPC_750L_v20,               750),
8588     /* PowerPC 750L v2.1 (G3 embedded)                                       */
8589     POWERPC_DEF("750l_v2.1",     CPU_POWERPC_750L_v21,               750),
8590     /* PowerPC 750L v2.2 (G3 embedded)                                       */
8591     POWERPC_DEF("750l_v2.2",     CPU_POWERPC_750L_v22,               750),
8592     /* PowerPC 750L v3.0 (G3 embedded)                                       */
8593     POWERPC_DEF("750l_v3.0",     CPU_POWERPC_750L_v30,               750),
8594     /* PowerPC 750L v3.2 (G3 embedded)                                       */
8595     POWERPC_DEF("750l_v3.2",     CPU_POWERPC_750L_v32,               750),
8596     /* Generic PowerPC 745                                                   */
8597     POWERPC_DEF("745",           CPU_POWERPC_7x5,                    745),
8598     /* Generic PowerPC 755                                                   */
8599     POWERPC_DEF("755",           CPU_POWERPC_7x5,                    755),
8600     /* Code name for PowerPC 745/755                                         */
8601     POWERPC_DEF("Goldfinger",    CPU_POWERPC_7x5,                    755),
8602     /* PowerPC 745 v1.0                                                      */
8603     POWERPC_DEF("745_v1.0",      CPU_POWERPC_7x5_v10,                745),
8604     /* PowerPC 755 v1.0                                                      */
8605     POWERPC_DEF("755_v1.0",      CPU_POWERPC_7x5_v10,                755),
8606     /* PowerPC 745 v1.1                                                      */
8607     POWERPC_DEF("745_v1.1",      CPU_POWERPC_7x5_v11,                745),
8608     /* PowerPC 755 v1.1                                                      */
8609     POWERPC_DEF("755_v1.1",      CPU_POWERPC_7x5_v11,                755),
8610     /* PowerPC 745 v2.0                                                      */
8611     POWERPC_DEF("745_v2.0",      CPU_POWERPC_7x5_v20,                745),
8612     /* PowerPC 755 v2.0                                                      */
8613     POWERPC_DEF("755_v2.0",      CPU_POWERPC_7x5_v20,                755),
8614     /* PowerPC 745 v2.1                                                      */
8615     POWERPC_DEF("745_v2.1",      CPU_POWERPC_7x5_v21,                745),
8616     /* PowerPC 755 v2.1                                                      */
8617     POWERPC_DEF("755_v2.1",      CPU_POWERPC_7x5_v21,                755),
8618     /* PowerPC 745 v2.2                                                      */
8619     POWERPC_DEF("745_v2.2",      CPU_POWERPC_7x5_v22,                745),
8620     /* PowerPC 755 v2.2                                                      */
8621     POWERPC_DEF("755_v2.2",      CPU_POWERPC_7x5_v22,                755),
8622     /* PowerPC 745 v2.3                                                      */
8623     POWERPC_DEF("745_v2.3",      CPU_POWERPC_7x5_v23,                745),
8624     /* PowerPC 755 v2.3                                                      */
8625     POWERPC_DEF("755_v2.3",      CPU_POWERPC_7x5_v23,                755),
8626     /* PowerPC 745 v2.4                                                      */
8627     POWERPC_DEF("745_v2.4",      CPU_POWERPC_7x5_v24,                745),
8628     /* PowerPC 755 v2.4                                                      */
8629     POWERPC_DEF("755_v2.4",      CPU_POWERPC_7x5_v24,                755),
8630     /* PowerPC 745 v2.5                                                      */
8631     POWERPC_DEF("745_v2.5",      CPU_POWERPC_7x5_v25,                745),
8632     /* PowerPC 755 v2.5                                                      */
8633     POWERPC_DEF("755_v2.5",      CPU_POWERPC_7x5_v25,                755),
8634     /* PowerPC 745 v2.6                                                      */
8635     POWERPC_DEF("745_v2.6",      CPU_POWERPC_7x5_v26,                745),
8636     /* PowerPC 755 v2.6                                                      */
8637     POWERPC_DEF("755_v2.6",      CPU_POWERPC_7x5_v26,                755),
8638     /* PowerPC 745 v2.7                                                      */
8639     POWERPC_DEF("745_v2.7",      CPU_POWERPC_7x5_v27,                745),
8640     /* PowerPC 755 v2.7                                                      */
8641     POWERPC_DEF("755_v2.7",      CPU_POWERPC_7x5_v27,                755),
8642     /* PowerPC 745 v2.8                                                      */
8643     POWERPC_DEF("745_v2.8",      CPU_POWERPC_7x5_v28,                745),
8644     /* PowerPC 755 v2.8                                                      */
8645     POWERPC_DEF("755_v2.8",      CPU_POWERPC_7x5_v28,                755),
8646 #if defined (TODO)
8647     /* PowerPC 745P (G3)                                                     */
8648     POWERPC_DEF("745p",          CPU_POWERPC_7x5P,                   745),
8649     /* PowerPC 755P (G3)                                                     */
8650     POWERPC_DEF("755p",          CPU_POWERPC_7x5P,                   755),
8651 #endif
8652     /* PowerPC 74xx family                                                   */
8653     /* PowerPC 7400 (G4)                                                     */
8654     POWERPC_DEF("7400",          CPU_POWERPC_7400,                   7400),
8655     /* Code name for PowerPC 7400                                            */
8656     POWERPC_DEF("Max",           CPU_POWERPC_7400,                   7400),
8657     /* PowerPC 74xx is also well known as G4                                 */
8658     POWERPC_DEF("G4",            CPU_POWERPC_7400,                   7400),
8659     /* PowerPC 7400 v1.0 (G4)                                                */
8660     POWERPC_DEF("7400_v1.0",     CPU_POWERPC_7400_v10,               7400),
8661     /* PowerPC 7400 v1.1 (G4)                                                */
8662     POWERPC_DEF("7400_v1.1",     CPU_POWERPC_7400_v11,               7400),
8663     /* PowerPC 7400 v2.0 (G4)                                                */
8664     POWERPC_DEF("7400_v2.0",     CPU_POWERPC_7400_v20,               7400),
8665     /* PowerPC 7400 v2.1 (G4)                                                */
8666     POWERPC_DEF("7400_v2.1",     CPU_POWERPC_7400_v21,               7400),
8667     /* PowerPC 7400 v2.2 (G4)                                                */
8668     POWERPC_DEF("7400_v2.2",     CPU_POWERPC_7400_v22,               7400),
8669     /* PowerPC 7400 v2.6 (G4)                                                */
8670     POWERPC_DEF("7400_v2.6",     CPU_POWERPC_7400_v26,               7400),
8671     /* PowerPC 7400 v2.7 (G4)                                                */
8672     POWERPC_DEF("7400_v2.7",     CPU_POWERPC_7400_v27,               7400),
8673     /* PowerPC 7400 v2.8 (G4)                                                */
8674     POWERPC_DEF("7400_v2.8",     CPU_POWERPC_7400_v28,               7400),
8675     /* PowerPC 7400 v2.9 (G4)                                                */
8676     POWERPC_DEF("7400_v2.9",     CPU_POWERPC_7400_v29,               7400),
8677     /* PowerPC 7410 (G4)                                                     */
8678     POWERPC_DEF("7410",          CPU_POWERPC_7410,                   7410),
8679     /* Code name for PowerPC 7410                                            */
8680     POWERPC_DEF("Nitro",         CPU_POWERPC_7410,                   7410),
8681     /* PowerPC 7410 v1.0 (G4)                                                */
8682     POWERPC_DEF("7410_v1.0",     CPU_POWERPC_7410_v10,               7410),
8683     /* PowerPC 7410 v1.1 (G4)                                                */
8684     POWERPC_DEF("7410_v1.1",     CPU_POWERPC_7410_v11,               7410),
8685     /* PowerPC 7410 v1.2 (G4)                                                */
8686     POWERPC_DEF("7410_v1.2",     CPU_POWERPC_7410_v12,               7410),
8687     /* PowerPC 7410 v1.3 (G4)                                                */
8688     POWERPC_DEF("7410_v1.3",     CPU_POWERPC_7410_v13,               7410),
8689     /* PowerPC 7410 v1.4 (G4)                                                */
8690     POWERPC_DEF("7410_v1.4",     CPU_POWERPC_7410_v14,               7410),
8691     /* PowerPC 7448 (G4)                                                     */
8692     POWERPC_DEF("7448",          CPU_POWERPC_7448,                   7400),
8693     /* PowerPC 7448 v1.0 (G4)                                                */
8694     POWERPC_DEF("7448_v1.0",     CPU_POWERPC_7448_v10,               7400),
8695     /* PowerPC 7448 v1.1 (G4)                                                */
8696     POWERPC_DEF("7448_v1.1",     CPU_POWERPC_7448_v11,               7400),
8697     /* PowerPC 7448 v2.0 (G4)                                                */
8698     POWERPC_DEF("7448_v2.0",     CPU_POWERPC_7448_v20,               7400),
8699     /* PowerPC 7448 v2.1 (G4)                                                */
8700     POWERPC_DEF("7448_v2.1",     CPU_POWERPC_7448_v21,               7400),
8701     /* PowerPC 7450 (G4)                                                     */
8702     POWERPC_DEF("7450",          CPU_POWERPC_7450,                   7450),
8703     /* Code name for PowerPC 7450                                            */
8704     POWERPC_DEF("Vger",          CPU_POWERPC_7450,                   7450),
8705     /* PowerPC 7450 v1.0 (G4)                                                */
8706     POWERPC_DEF("7450_v1.0",     CPU_POWERPC_7450_v10,               7450),
8707     /* PowerPC 7450 v1.1 (G4)                                                */
8708     POWERPC_DEF("7450_v1.1",     CPU_POWERPC_7450_v11,               7450),
8709     /* PowerPC 7450 v1.2 (G4)                                                */
8710     POWERPC_DEF("7450_v1.2",     CPU_POWERPC_7450_v12,               7450),
8711     /* PowerPC 7450 v2.0 (G4)                                                */
8712     POWERPC_DEF("7450_v2.0",     CPU_POWERPC_7450_v20,               7450),
8713     /* PowerPC 7450 v2.1 (G4)                                                */
8714     POWERPC_DEF("7450_v2.1",     CPU_POWERPC_7450_v21,               7450),
8715     /* PowerPC 7441 (G4)                                                     */
8716     POWERPC_DEF("7441",          CPU_POWERPC_74x1,                   7440),
8717     /* PowerPC 7451 (G4)                                                     */
8718     POWERPC_DEF("7451",          CPU_POWERPC_74x1,                   7450),
8719     /* PowerPC 7441 v2.1 (G4)                                                */
8720     POWERPC_DEF("7441_v2.1",     CPU_POWERPC_7450_v21,               7440),
8721     /* PowerPC 7441 v2.3 (G4)                                                */
8722     POWERPC_DEF("7441_v2.3",     CPU_POWERPC_74x1_v23,               7440),
8723     /* PowerPC 7451 v2.3 (G4)                                                */
8724     POWERPC_DEF("7451_v2.3",     CPU_POWERPC_74x1_v23,               7450),
8725     /* PowerPC 7441 v2.10 (G4)                                                */
8726     POWERPC_DEF("7441_v2.10",    CPU_POWERPC_74x1_v210,              7440),
8727     /* PowerPC 7451 v2.10 (G4)                                               */
8728     POWERPC_DEF("7451_v2.10",    CPU_POWERPC_74x1_v210,              7450),
8729     /* PowerPC 7445 (G4)                                                     */
8730     POWERPC_DEF("7445",          CPU_POWERPC_74x5,                   7445),
8731     /* PowerPC 7455 (G4)                                                     */
8732     POWERPC_DEF("7455",          CPU_POWERPC_74x5,                   7455),
8733     /* Code name for PowerPC 7445/7455                                       */
8734     POWERPC_DEF("Apollo6",       CPU_POWERPC_74x5,                   7455),
8735     /* PowerPC 7445 v1.0 (G4)                                                */
8736     POWERPC_DEF("7445_v1.0",     CPU_POWERPC_74x5_v10,               7445),
8737     /* PowerPC 7455 v1.0 (G4)                                                */
8738     POWERPC_DEF("7455_v1.0",     CPU_POWERPC_74x5_v10,               7455),
8739     /* PowerPC 7445 v2.1 (G4)                                                */
8740     POWERPC_DEF("7445_v2.1",     CPU_POWERPC_74x5_v21,               7445),
8741     /* PowerPC 7455 v2.1 (G4)                                                */
8742     POWERPC_DEF("7455_v2.1",     CPU_POWERPC_74x5_v21,               7455),
8743     /* PowerPC 7445 v3.2 (G4)                                                */
8744     POWERPC_DEF("7445_v3.2",     CPU_POWERPC_74x5_v32,               7445),
8745     /* PowerPC 7455 v3.2 (G4)                                                */
8746     POWERPC_DEF("7455_v3.2",     CPU_POWERPC_74x5_v32,               7455),
8747     /* PowerPC 7445 v3.3 (G4)                                                */
8748     POWERPC_DEF("7445_v3.3",     CPU_POWERPC_74x5_v33,               7445),
8749     /* PowerPC 7455 v3.3 (G4)                                                */
8750     POWERPC_DEF("7455_v3.3",     CPU_POWERPC_74x5_v33,               7455),
8751     /* PowerPC 7445 v3.4 (G4)                                                */
8752     POWERPC_DEF("7445_v3.4",     CPU_POWERPC_74x5_v34,               7445),
8753     /* PowerPC 7455 v3.4 (G4)                                                */
8754     POWERPC_DEF("7455_v3.4",     CPU_POWERPC_74x5_v34,               7455),
8755     /* PowerPC 7447 (G4)                                                     */
8756     POWERPC_DEF("7447",          CPU_POWERPC_74x7,                   7445),
8757     /* PowerPC 7457 (G4)                                                     */
8758     POWERPC_DEF("7457",          CPU_POWERPC_74x7,                   7455),
8759     /* Code name for PowerPC 7447/7457                                       */
8760     POWERPC_DEF("Apollo7",       CPU_POWERPC_74x7,                   7455),
8761     /* PowerPC 7447 v1.0 (G4)                                                */
8762     POWERPC_DEF("7447_v1.0",     CPU_POWERPC_74x7_v10,               7445),
8763     /* PowerPC 7457 v1.0 (G4)                                                */
8764     POWERPC_DEF("7457_v1.0",     CPU_POWERPC_74x7_v10,               7455),
8765     /* PowerPC 7447 v1.1 (G4)                                                */
8766     POWERPC_DEF("7447_v1.1",     CPU_POWERPC_74x7_v11,               7445),
8767     /* PowerPC 7457 v1.1 (G4)                                                */
8768     POWERPC_DEF("7457_v1.1",     CPU_POWERPC_74x7_v11,               7455),
8769     /* PowerPC 7457 v1.2 (G4)                                                */
8770     POWERPC_DEF("7457_v1.2",     CPU_POWERPC_74x7_v12,               7455),
8771     /* PowerPC 7447A (G4)                                                    */
8772     POWERPC_DEF("7447A",         CPU_POWERPC_74x7A,                  7445),
8773     /* PowerPC 7457A (G4)                                                    */
8774     POWERPC_DEF("7457A",         CPU_POWERPC_74x7A,                  7455),
8775     /* PowerPC 7447A v1.0 (G4)                                               */
8776     POWERPC_DEF("7447A_v1.0",    CPU_POWERPC_74x7A_v10,              7445),
8777     /* PowerPC 7457A v1.0 (G4)                                               */
8778     POWERPC_DEF("7457A_v1.0",    CPU_POWERPC_74x7A_v10,              7455),
8779     /* Code name for PowerPC 7447A/7457A                                     */
8780     POWERPC_DEF("Apollo7PM",     CPU_POWERPC_74x7A_v10,              7455),
8781     /* PowerPC 7447A v1.1 (G4)                                               */
8782     POWERPC_DEF("7447A_v1.1",    CPU_POWERPC_74x7A_v11,              7445),
8783     /* PowerPC 7457A v1.1 (G4)                                               */
8784     POWERPC_DEF("7457A_v1.1",    CPU_POWERPC_74x7A_v11,              7455),
8785     /* PowerPC 7447A v1.2 (G4)                                               */
8786     POWERPC_DEF("7447A_v1.2",    CPU_POWERPC_74x7A_v12,              7445),
8787     /* PowerPC 7457A v1.2 (G4)                                               */
8788     POWERPC_DEF("7457A_v1.2",    CPU_POWERPC_74x7A_v12,              7455),
8789     /* 64 bits PowerPC                                                       */
8790 #if defined (TARGET_PPC64)
8791     /* PowerPC 620                                                           */
8792     POWERPC_DEF("620",           CPU_POWERPC_620,                    620),
8793     /* Code name for PowerPC 620                                             */
8794     POWERPC_DEF("Trident",       CPU_POWERPC_620,                    620),
8795 #if defined (TODO)
8796     /* PowerPC 630 (POWER3)                                                  */
8797     POWERPC_DEF("630",           CPU_POWERPC_630,                    630),
8798     POWERPC_DEF("POWER3",        CPU_POWERPC_630,                    630),
8799     /* Code names for POWER3                                                 */
8800     POWERPC_DEF("Boxer",         CPU_POWERPC_630,                    630),
8801     POWERPC_DEF("Dino",          CPU_POWERPC_630,                    630),
8802 #endif
8803 #if defined (TODO)
8804     /* PowerPC 631 (Power 3+)                                                */
8805     POWERPC_DEF("631",           CPU_POWERPC_631,                    631),
8806     POWERPC_DEF("POWER3+",       CPU_POWERPC_631,                    631),
8807 #endif
8808 #if defined (TODO)
8809     /* POWER4                                                                */
8810     POWERPC_DEF("POWER4",        CPU_POWERPC_POWER4,                 POWER4),
8811 #endif
8812 #if defined (TODO)
8813     /* POWER4p                                                               */
8814     POWERPC_DEF("POWER4+",       CPU_POWERPC_POWER4P,                POWER4P),
8815 #endif
8816 #if defined (TODO)
8817     /* POWER5                                                                */
8818     POWERPC_DEF("POWER5",        CPU_POWERPC_POWER5,                 POWER5),
8819     /* POWER5GR                                                              */
8820     POWERPC_DEF("POWER5gr",      CPU_POWERPC_POWER5GR,               POWER5),
8821 #endif
8822 #if defined (TODO)
8823     /* POWER5+                                                               */
8824     POWERPC_DEF("POWER5+",       CPU_POWERPC_POWER5P,                POWER5P),
8825     /* POWER5GS                                                              */
8826     POWERPC_DEF("POWER5gs",      CPU_POWERPC_POWER5GS,               POWER5P),
8827 #endif
8828 #if defined (TODO)
8829     /* POWER6                                                                */
8830     POWERPC_DEF("POWER6",        CPU_POWERPC_POWER6,                 POWER6),
8831     /* POWER6 running in POWER5 mode                                         */
8832     POWERPC_DEF("POWER6_5",      CPU_POWERPC_POWER6_5,               POWER5),
8833     /* POWER6A                                                               */
8834     POWERPC_DEF("POWER6A",       CPU_POWERPC_POWER6A,                POWER6),
8835 #endif
8836     /* PowerPC 970                                                           */
8837     POWERPC_DEF("970",           CPU_POWERPC_970,                    970),
8838     /* PowerPC 970FX (G5)                                                    */
8839     POWERPC_DEF("970fx",         CPU_POWERPC_970FX,                  970FX),
8840     /* PowerPC 970FX v1.0 (G5)                                               */
8841     POWERPC_DEF("970fx_v1.0",    CPU_POWERPC_970FX_v10,              970FX),
8842     /* PowerPC 970FX v2.0 (G5)                                               */
8843     POWERPC_DEF("970fx_v2.0",    CPU_POWERPC_970FX_v20,              970FX),
8844     /* PowerPC 970FX v2.1 (G5)                                               */
8845     POWERPC_DEF("970fx_v2.1",    CPU_POWERPC_970FX_v21,              970FX),
8846     /* PowerPC 970FX v3.0 (G5)                                               */
8847     POWERPC_DEF("970fx_v3.0",    CPU_POWERPC_970FX_v30,              970FX),
8848     /* PowerPC 970FX v3.1 (G5)                                               */
8849     POWERPC_DEF("970fx_v3.1",    CPU_POWERPC_970FX_v31,              970FX),
8850     /* PowerPC 970GX (G5)                                                    */
8851     POWERPC_DEF("970gx",         CPU_POWERPC_970GX,                  970GX),
8852     /* PowerPC 970MP                                                         */
8853     POWERPC_DEF("970mp",         CPU_POWERPC_970MP,                  970MP),
8854     /* PowerPC 970MP v1.0                                                    */
8855     POWERPC_DEF("970mp_v1.0",    CPU_POWERPC_970MP_v10,              970MP),
8856     /* PowerPC 970MP v1.1                                                    */
8857     POWERPC_DEF("970mp_v1.1",    CPU_POWERPC_970MP_v11,              970MP),
8858 #if defined (TODO)
8859     /* PowerPC Cell                                                          */
8860     POWERPC_DEF("Cell",          CPU_POWERPC_CELL,                   970),
8861 #endif
8862 #if defined (TODO)
8863     /* PowerPC Cell v1.0                                                     */
8864     POWERPC_DEF("Cell_v1.0",     CPU_POWERPC_CELL_v10,               970),
8865 #endif
8866 #if defined (TODO)
8867     /* PowerPC Cell v2.0                                                     */
8868     POWERPC_DEF("Cell_v2.0",     CPU_POWERPC_CELL_v20,               970),
8869 #endif
8870 #if defined (TODO)
8871     /* PowerPC Cell v3.0                                                     */
8872     POWERPC_DEF("Cell_v3.0",     CPU_POWERPC_CELL_v30,               970),
8873 #endif
8874 #if defined (TODO)
8875     /* PowerPC Cell v3.1                                                     */
8876     POWERPC_DEF("Cell_v3.1",     CPU_POWERPC_CELL_v31,               970),
8877 #endif
8878 #if defined (TODO)
8879     /* PowerPC Cell v3.2                                                     */
8880     POWERPC_DEF("Cell_v3.2",     CPU_POWERPC_CELL_v32,               970),
8881 #endif
8882 #if defined (TODO)
8883     /* RS64 (Apache/A35)                                                     */
8884     /* This one seems to support the whole POWER2 instruction set
8885      * and the PowerPC 64 one.
8886      */
8887     /* What about A10 & A30 ? */
8888     POWERPC_DEF("RS64",          CPU_POWERPC_RS64,                   RS64),
8889     POWERPC_DEF("Apache",        CPU_POWERPC_RS64,                   RS64),
8890     POWERPC_DEF("A35",           CPU_POWERPC_RS64,                   RS64),
8891 #endif
8892 #if defined (TODO)
8893     /* RS64-II (NorthStar/A50)                                               */
8894     POWERPC_DEF("RS64-II",       CPU_POWERPC_RS64II,                 RS64),
8895     POWERPC_DEF("NorthStar",     CPU_POWERPC_RS64II,                 RS64),
8896     POWERPC_DEF("A50",           CPU_POWERPC_RS64II,                 RS64),
8897 #endif
8898 #if defined (TODO)
8899     /* RS64-III (Pulsar)                                                     */
8900     POWERPC_DEF("RS64-III",      CPU_POWERPC_RS64III,                RS64),
8901     POWERPC_DEF("Pulsar",        CPU_POWERPC_RS64III,                RS64),
8902 #endif
8903 #if defined (TODO)
8904     /* RS64-IV (IceStar/IStar/SStar)                                         */
8905     POWERPC_DEF("RS64-IV",       CPU_POWERPC_RS64IV,                 RS64),
8906     POWERPC_DEF("IceStar",       CPU_POWERPC_RS64IV,                 RS64),
8907     POWERPC_DEF("IStar",         CPU_POWERPC_RS64IV,                 RS64),
8908     POWERPC_DEF("SStar",         CPU_POWERPC_RS64IV,                 RS64),
8909 #endif
8910 #endif /* defined (TARGET_PPC64) */
8911     /* POWER                                                                 */
8912 #if defined (TODO)
8913     /* Original POWER                                                        */
8914     POWERPC_DEF("POWER",         CPU_POWERPC_POWER,                  POWER),
8915     POWERPC_DEF("RIOS",          CPU_POWERPC_POWER,                  POWER),
8916     POWERPC_DEF("RSC",           CPU_POWERPC_POWER,                  POWER),
8917     POWERPC_DEF("RSC3308",       CPU_POWERPC_POWER,                  POWER),
8918     POWERPC_DEF("RSC4608",       CPU_POWERPC_POWER,                  POWER),
8919 #endif
8920 #if defined (TODO)
8921     /* POWER2                                                                */
8922     POWERPC_DEF("POWER2",        CPU_POWERPC_POWER2,                 POWER),
8923     POWERPC_DEF("RSC2",          CPU_POWERPC_POWER2,                 POWER),
8924     POWERPC_DEF("P2SC",          CPU_POWERPC_POWER2,                 POWER),
8925 #endif
8926     /* PA semi cores                                                         */
8927 #if defined (TODO)
8928     /* PA PA6T */
8929     POWERPC_DEF("PA6T",          CPU_POWERPC_PA6T,                   PA6T),
8930 #endif
8931     /* Generic PowerPCs                                                      */
8932 #if defined (TARGET_PPC64)
8933     POWERPC_DEF("ppc64",         CPU_POWERPC_PPC64,                  PPC64),
8934 #endif
8935     POWERPC_DEF("ppc32",         CPU_POWERPC_PPC32,                  PPC32),
8936     POWERPC_DEF("ppc",           CPU_POWERPC_DEFAULT,                DEFAULT),
8937     /* Fallback                                                              */
8938     POWERPC_DEF("default",       CPU_POWERPC_DEFAULT,                DEFAULT),
8939 };
8940
8941 /*****************************************************************************/
8942 /* Generic CPU instanciation routine                                         */
8943 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
8944 {
8945 #if !defined(CONFIG_USER_ONLY)
8946     int i;
8947
8948     env->irq_inputs = NULL;
8949     /* Set all exception vectors to an invalid address */
8950     for (i = 0; i < POWERPC_EXCP_NB; i++)
8951         env->excp_vectors[i] = (target_ulong)(-1ULL);
8952     env->hreset_excp_prefix = 0x00000000;
8953     env->ivor_mask = 0x00000000;
8954     env->ivpr_mask = 0x00000000;
8955     /* Default MMU definitions */
8956     env->nb_BATs = 0;
8957     env->nb_tlb = 0;
8958     env->nb_ways = 0;
8959 #endif
8960     /* Register SPR common to all PowerPC implementations */
8961     gen_spr_generic(env);
8962     spr_register(env, SPR_PVR, "PVR",
8963                  /* Linux permits userspace to read PVR */
8964 #if defined(CONFIG_LINUX_USER)
8965                  &spr_read_generic,
8966 #else
8967                  SPR_NOACCESS,
8968 #endif
8969                  SPR_NOACCESS,
8970                  &spr_read_generic, SPR_NOACCESS,
8971                  def->pvr);
8972     /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8973     if (def->svr != POWERPC_SVR_NONE) {
8974         if (def->svr & POWERPC_SVR_E500) {
8975             spr_register(env, SPR_E500_SVR, "SVR",
8976                          SPR_NOACCESS, SPR_NOACCESS,
8977                          &spr_read_generic, SPR_NOACCESS,
8978                          def->svr & ~POWERPC_SVR_E500);
8979         } else {
8980             spr_register(env, SPR_SVR, "SVR",
8981                          SPR_NOACCESS, SPR_NOACCESS,
8982                          &spr_read_generic, SPR_NOACCESS,
8983                          def->svr);
8984         }
8985     }
8986     /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8987     (*def->init_proc)(env);
8988 #if !defined(CONFIG_USER_ONLY)
8989     env->excp_prefix = env->hreset_excp_prefix;
8990 #endif
8991     /* MSR bits & flags consistency checks */
8992     if (env->msr_mask & (1 << 25)) {
8993         switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8994         case POWERPC_FLAG_SPE:
8995         case POWERPC_FLAG_VRE:
8996             break;
8997         default:
8998             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8999                     "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9000             exit(1);
9001         }
9002     } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9003         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9004                 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9005         exit(1);
9006     }
9007     if (env->msr_mask & (1 << 17)) {
9008         switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9009         case POWERPC_FLAG_TGPR:
9010         case POWERPC_FLAG_CE:
9011             break;
9012         default:
9013             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9014                     "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9015             exit(1);
9016         }
9017     } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9018         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9019                 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9020         exit(1);
9021     }
9022     if (env->msr_mask & (1 << 10)) {
9023         switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9024                               POWERPC_FLAG_UBLE)) {
9025         case POWERPC_FLAG_SE:
9026         case POWERPC_FLAG_DWE:
9027         case POWERPC_FLAG_UBLE:
9028             break;
9029         default:
9030             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9031                     "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9032                     "POWERPC_FLAG_UBLE\n");
9033             exit(1);
9034         }
9035     } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9036                              POWERPC_FLAG_UBLE)) {
9037         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9038                 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9039                 "POWERPC_FLAG_UBLE\n");
9040             exit(1);
9041     }
9042     if (env->msr_mask & (1 << 9)) {
9043         switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9044         case POWERPC_FLAG_BE:
9045         case POWERPC_FLAG_DE:
9046             break;
9047         default:
9048             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9049                     "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9050             exit(1);
9051         }
9052     } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9053         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9054                 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9055         exit(1);
9056     }
9057     if (env->msr_mask & (1 << 2)) {
9058         switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9059         case POWERPC_FLAG_PX:
9060         case POWERPC_FLAG_PMM:
9061             break;
9062         default:
9063             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9064                     "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9065             exit(1);
9066         }
9067     } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9068         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9069                 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9070         exit(1);
9071     }
9072     if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9073         fprintf(stderr, "PowerPC flags inconsistency\n"
9074                 "Should define the time-base and decrementer clock source\n");
9075         exit(1);
9076     }
9077     /* Allocate TLBs buffer when needed */
9078 #if !defined(CONFIG_USER_ONLY)
9079     if (env->nb_tlb != 0) {
9080         int nb_tlb = env->nb_tlb;
9081         if (env->id_tlbs != 0)
9082             nb_tlb *= 2;
9083         env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
9084         /* Pre-compute some useful values */
9085         env->tlb_per_way = env->nb_tlb / env->nb_ways;
9086     }
9087     if (env->irq_inputs == NULL) {
9088         fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9089                 " Attempt Qemu to crash very soon !\n");
9090     }
9091 #endif
9092     if (env->check_pow == NULL) {
9093         fprintf(stderr, "WARNING: no power management check handler "
9094                 "registered.\n"
9095                 " Attempt Qemu to crash very soon !\n");
9096     }
9097 }
9098
9099 #if defined(PPC_DUMP_CPU)
9100 static void dump_ppc_sprs (CPUPPCState *env)
9101 {
9102     ppc_spr_t *spr;
9103 #if !defined(CONFIG_USER_ONLY)
9104     uint32_t sr, sw;
9105 #endif
9106     uint32_t ur, uw;
9107     int i, j, n;
9108
9109     printf("Special purpose registers:\n");
9110     for (i = 0; i < 32; i++) {
9111         for (j = 0; j < 32; j++) {
9112             n = (i << 5) | j;
9113             spr = &env->spr_cb[n];
9114             uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9115             ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9116 #if !defined(CONFIG_USER_ONLY)
9117             sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9118             sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9119             if (sw || sr || uw || ur) {
9120                 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9121                        (i << 5) | j, (i << 5) | j, spr->name,
9122                        sw ? 'w' : '-', sr ? 'r' : '-',
9123                        uw ? 'w' : '-', ur ? 'r' : '-');
9124             }
9125 #else
9126             if (uw || ur) {
9127                 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9128                        (i << 5) | j, (i << 5) | j, spr->name,
9129                        uw ? 'w' : '-', ur ? 'r' : '-');
9130             }
9131 #endif
9132         }
9133     }
9134     fflush(stdout);
9135     fflush(stderr);
9136 }
9137 #endif
9138
9139 /*****************************************************************************/
9140 #include <stdlib.h>
9141 #include <string.h>
9142
9143 /* Opcode types */
9144 enum {
9145     PPC_DIRECT   = 0, /* Opcode routine        */
9146     PPC_INDIRECT = 1, /* Indirect opcode table */
9147 };
9148
9149 static inline int is_indirect_opcode (void *handler)
9150 {
9151     return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9152 }
9153
9154 static inline opc_handler_t **ind_table(void *handler)
9155 {
9156     return (opc_handler_t **)((unsigned long)handler & ~3);
9157 }
9158
9159 /* Instruction table creation */
9160 /* Opcodes tables creation */
9161 static void fill_new_table (opc_handler_t **table, int len)
9162 {
9163     int i;
9164
9165     for (i = 0; i < len; i++)
9166         table[i] = &invalid_handler;
9167 }
9168
9169 static int create_new_table (opc_handler_t **table, unsigned char idx)
9170 {
9171     opc_handler_t **tmp;
9172
9173     tmp = malloc(0x20 * sizeof(opc_handler_t));
9174     fill_new_table(tmp, 0x20);
9175     table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9176
9177     return 0;
9178 }
9179
9180 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9181                             opc_handler_t *handler)
9182 {
9183     if (table[idx] != &invalid_handler)
9184         return -1;
9185     table[idx] = handler;
9186
9187     return 0;
9188 }
9189
9190 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9191                                  unsigned char idx, opc_handler_t *handler)
9192 {
9193     if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9194         printf("*** ERROR: opcode %02x already assigned in main "
9195                "opcode table\n", idx);
9196 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9197         printf("           Registered handler '%s' - new handler '%s'\n",
9198                ppc_opcodes[idx]->oname, handler->oname);
9199 #endif
9200         return -1;
9201     }
9202
9203     return 0;
9204 }
9205
9206 static int register_ind_in_table (opc_handler_t **table,
9207                                   unsigned char idx1, unsigned char idx2,
9208                                   opc_handler_t *handler)
9209 {
9210     if (table[idx1] == &invalid_handler) {
9211         if (create_new_table(table, idx1) < 0) {
9212             printf("*** ERROR: unable to create indirect table "
9213                    "idx=%02x\n", idx1);
9214             return -1;
9215         }
9216     } else {
9217         if (!is_indirect_opcode(table[idx1])) {
9218             printf("*** ERROR: idx %02x already assigned to a direct "
9219                    "opcode\n", idx1);
9220 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9221             printf("           Registered handler '%s' - new handler '%s'\n",
9222                    ind_table(table[idx1])[idx2]->oname, handler->oname);
9223 #endif
9224             return -1;
9225         }
9226     }
9227     if (handler != NULL &&
9228         insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9229         printf("*** ERROR: opcode %02x already assigned in "
9230                "opcode table %02x\n", idx2, idx1);
9231 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9232         printf("           Registered handler '%s' - new handler '%s'\n",
9233                ind_table(table[idx1])[idx2]->oname, handler->oname);
9234 #endif
9235         return -1;
9236     }
9237
9238     return 0;
9239 }
9240
9241 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9242                               unsigned char idx1, unsigned char idx2,
9243                               opc_handler_t *handler)
9244 {
9245     int ret;
9246
9247     ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9248
9249     return ret;
9250 }
9251
9252 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9253                                  unsigned char idx1, unsigned char idx2,
9254                                  unsigned char idx3, opc_handler_t *handler)
9255 {
9256     if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9257         printf("*** ERROR: unable to join indirect table idx "
9258                "[%02x-%02x]\n", idx1, idx2);
9259         return -1;
9260     }
9261     if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9262                               handler) < 0) {
9263         printf("*** ERROR: unable to insert opcode "
9264                "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9265         return -1;
9266     }
9267
9268     return 0;
9269 }
9270
9271 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9272 {
9273     if (insn->opc2 != 0xFF) {
9274         if (insn->opc3 != 0xFF) {
9275             if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9276                                      insn->opc3, &insn->handler) < 0)
9277                 return -1;
9278         } else {
9279             if (register_ind_insn(ppc_opcodes, insn->opc1,
9280                                   insn->opc2, &insn->handler) < 0)
9281                 return -1;
9282         }
9283     } else {
9284         if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9285             return -1;
9286     }
9287
9288     return 0;
9289 }
9290
9291 static int test_opcode_table (opc_handler_t **table, int len)
9292 {
9293     int i, count, tmp;
9294
9295     for (i = 0, count = 0; i < len; i++) {
9296         /* Consistency fixup */
9297         if (table[i] == NULL)
9298             table[i] = &invalid_handler;
9299         if (table[i] != &invalid_handler) {
9300             if (is_indirect_opcode(table[i])) {
9301                 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9302                 if (tmp == 0) {
9303                     free(table[i]);
9304                     table[i] = &invalid_handler;
9305                 } else {
9306                     count++;
9307                 }
9308             } else {
9309                 count++;
9310             }
9311         }
9312     }
9313
9314     return count;
9315 }
9316
9317 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9318 {
9319     if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9320         printf("*** WARNING: no opcode defined !\n");
9321 }
9322
9323 /*****************************************************************************/
9324 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9325 {
9326     opcode_t *opc;
9327
9328     fill_new_table(env->opcodes, 0x40);
9329     for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9330         if ((opc->handler.type & def->insns_flags) != 0) {
9331             if (register_insn(env->opcodes, opc) < 0) {
9332                 printf("*** ERROR initializing PowerPC instruction "
9333                        "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9334                        opc->opc3);
9335                 return -1;
9336             }
9337         }
9338     }
9339     fix_opcode_tables(env->opcodes);
9340     fflush(stdout);
9341     fflush(stderr);
9342
9343     return 0;
9344 }
9345
9346 #if defined(PPC_DUMP_CPU)
9347 static void dump_ppc_insns (CPUPPCState *env)
9348 {
9349     opc_handler_t **table, *handler;
9350     const char *p, *q;
9351     uint8_t opc1, opc2, opc3;
9352
9353     printf("Instructions set:\n");
9354     /* opc1 is 6 bits long */
9355     for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9356         table = env->opcodes;
9357         handler = table[opc1];
9358         if (is_indirect_opcode(handler)) {
9359             /* opc2 is 5 bits long */
9360             for (opc2 = 0; opc2 < 0x20; opc2++) {
9361                 table = env->opcodes;
9362                 handler = env->opcodes[opc1];
9363                 table = ind_table(handler);
9364                 handler = table[opc2];
9365                 if (is_indirect_opcode(handler)) {
9366                     table = ind_table(handler);
9367                     /* opc3 is 5 bits long */
9368                     for (opc3 = 0; opc3 < 0x20; opc3++) {
9369                         handler = table[opc3];
9370                         if (handler->handler != &gen_invalid) {
9371                             /* Special hack to properly dump SPE insns */
9372                             p = strchr(handler->oname, '_');
9373                             if (p == NULL) {
9374                                 printf("INSN: %02x %02x %02x (%02d %04d) : "
9375                                        "%s\n",
9376                                        opc1, opc2, opc3, opc1,
9377                                        (opc3 << 5) | opc2,
9378                                        handler->oname);
9379                             } else {
9380                                 q = "speundef";
9381                                 if ((p - handler->oname) != strlen(q) ||
9382                                     memcmp(handler->oname, q, strlen(q)) != 0) {
9383                                     /* First instruction */
9384                                     printf("INSN: %02x %02x %02x (%02d %04d) : "
9385                                            "%.*s\n",
9386                                            opc1, opc2 << 1, opc3, opc1,
9387                                            (opc3 << 6) | (opc2 << 1),
9388                                            (int)(p - handler->oname),
9389                                            handler->oname);
9390                                 }
9391                                 if (strcmp(p + 1, q) != 0) {
9392                                     /* Second instruction */
9393                                     printf("INSN: %02x %02x %02x (%02d %04d) : "
9394                                            "%s\n",
9395                                            opc1, (opc2 << 1) | 1, opc3, opc1,
9396                                            (opc3 << 6) | (opc2 << 1) | 1,
9397                                            p + 1);
9398                                 }
9399                             }
9400                         }
9401                     }
9402                 } else {
9403                     if (handler->handler != &gen_invalid) {
9404                         printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9405                                opc1, opc2, opc1, opc2, handler->oname);
9406                     }
9407                 }
9408             }
9409         } else {
9410             if (handler->handler != &gen_invalid) {
9411                 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9412                        opc1, opc1, handler->oname);
9413             }
9414         }
9415     }
9416 }
9417 #endif
9418
9419 static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9420 {
9421     if (n < 32) {
9422         stfq_p(mem_buf, env->fpr[n]);
9423         return 8;
9424     }
9425     if (n == 32) {
9426         /* FPSCR not implemented  */
9427         memset(mem_buf, 0, 4);
9428         return 4;
9429     }
9430     return 0;
9431 }
9432
9433 static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9434 {
9435     if (n < 32) {
9436         env->fpr[n] = ldfq_p(mem_buf);
9437         return 8;
9438     }
9439     if (n == 32) {
9440         /* FPSCR not implemented  */
9441         return 4;
9442     }
9443     return 0;
9444 }
9445
9446 static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9447 {
9448     if (n < 32) {
9449 #ifdef HOST_WORDS_BIGENDIAN
9450         stq_p(mem_buf, env->avr[n].u64[0]);
9451         stq_p(mem_buf+8, env->avr[n].u64[1]);
9452 #else
9453         stq_p(mem_buf, env->avr[n].u64[1]);
9454         stq_p(mem_buf+8, env->avr[n].u64[0]);
9455 #endif
9456         return 16;
9457     }
9458     if (n == 32) {
9459         stl_p(mem_buf, env->vscr);
9460         return 4;
9461     }
9462     if (n == 33) {
9463         stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9464         return 4;
9465     }
9466     return 0;
9467 }
9468
9469 static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9470 {
9471     if (n < 32) {
9472 #ifdef HOST_WORDS_BIGENDIAN
9473         env->avr[n].u64[0] = ldq_p(mem_buf);
9474         env->avr[n].u64[1] = ldq_p(mem_buf+8);
9475 #else
9476         env->avr[n].u64[1] = ldq_p(mem_buf);
9477         env->avr[n].u64[0] = ldq_p(mem_buf+8);
9478 #endif
9479         return 16;
9480     }
9481     if (n == 32) {
9482         env->vscr = ldl_p(mem_buf);
9483         return 4;
9484     }
9485     if (n == 33) {
9486         env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9487         return 4;
9488     }
9489     return 0;
9490 }
9491
9492 static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9493 {
9494     if (n < 32) {
9495 #if defined(TARGET_PPC64)
9496         stl_p(mem_buf, env->gpr[n] >> 32);
9497 #else
9498         stl_p(mem_buf, env->gprh[n]);
9499 #endif
9500         return 4;
9501     }
9502     if (n == 32) {
9503         stq_p(mem_buf, env->spe_acc);
9504         return 8;
9505     }
9506     if (n == 33) {
9507         stl_p(mem_buf, env->spe_fscr);
9508         return 4;
9509     }
9510     return 0;
9511 }
9512
9513 static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9514 {
9515     if (n < 32) {
9516 #if defined(TARGET_PPC64)
9517         target_ulong lo = (uint32_t)env->gpr[n];
9518         target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9519         env->gpr[n] = lo | hi;
9520 #else
9521         env->gprh[n] = ldl_p(mem_buf);
9522 #endif
9523         return 4;
9524     }
9525     if (n == 32) {
9526         env->spe_acc = ldq_p(mem_buf);
9527         return 8;
9528     }
9529     if (n == 33) {
9530         env->spe_fscr = ldl_p(mem_buf);
9531         return 4;
9532     }
9533     return 0;
9534 }
9535
9536 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9537 {
9538     env->msr_mask = def->msr_mask;
9539     env->mmu_model = def->mmu_model;
9540     env->excp_model = def->excp_model;
9541     env->bus_model = def->bus_model;
9542     env->insns_flags = def->insns_flags;
9543     env->flags = def->flags;
9544     env->bfd_mach = def->bfd_mach;
9545     env->check_pow = def->check_pow;
9546     if (create_ppc_opcodes(env, def) < 0)
9547         return -1;
9548     init_ppc_proc(env, def);
9549
9550     if (def->insns_flags & PPC_FLOAT) {
9551         gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9552                                  33, "power-fpu.xml", 0);
9553     }
9554     if (def->insns_flags & PPC_ALTIVEC) {
9555         gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9556                                  34, "power-altivec.xml", 0);
9557     }
9558     if (def->insns_flags & PPC_SPE) {
9559         gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9560                                  34, "power-spe.xml", 0);
9561     }
9562
9563 #if defined(PPC_DUMP_CPU)
9564     {
9565         const char *mmu_model, *excp_model, *bus_model;
9566         switch (env->mmu_model) {
9567         case POWERPC_MMU_32B:
9568             mmu_model = "PowerPC 32";
9569             break;
9570         case POWERPC_MMU_SOFT_6xx:
9571             mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9572             break;
9573         case POWERPC_MMU_SOFT_74xx:
9574             mmu_model = "PowerPC 74xx with software driven TLBs";
9575             break;
9576         case POWERPC_MMU_SOFT_4xx:
9577             mmu_model = "PowerPC 4xx with software driven TLBs";
9578             break;
9579         case POWERPC_MMU_SOFT_4xx_Z:
9580             mmu_model = "PowerPC 4xx with software driven TLBs "
9581                 "and zones protections";
9582             break;
9583         case POWERPC_MMU_REAL:
9584             mmu_model = "PowerPC real mode only";
9585             break;
9586         case POWERPC_MMU_MPC8xx:
9587             mmu_model = "PowerPC MPC8xx";
9588             break;
9589         case POWERPC_MMU_BOOKE:
9590             mmu_model = "PowerPC BookE";
9591             break;
9592         case POWERPC_MMU_BOOKE_FSL:
9593             mmu_model = "PowerPC BookE FSL";
9594             break;
9595         case POWERPC_MMU_601:
9596             mmu_model = "PowerPC 601";
9597             break;
9598 #if defined (TARGET_PPC64)
9599         case POWERPC_MMU_64B:
9600             mmu_model = "PowerPC 64";
9601             break;
9602         case POWERPC_MMU_620:
9603             mmu_model = "PowerPC 620";
9604             break;
9605 #endif
9606         default:
9607             mmu_model = "Unknown or invalid";
9608             break;
9609         }
9610         switch (env->excp_model) {
9611         case POWERPC_EXCP_STD:
9612             excp_model = "PowerPC";
9613             break;
9614         case POWERPC_EXCP_40x:
9615             excp_model = "PowerPC 40x";
9616             break;
9617         case POWERPC_EXCP_601:
9618             excp_model = "PowerPC 601";
9619             break;
9620         case POWERPC_EXCP_602:
9621             excp_model = "PowerPC 602";
9622             break;
9623         case POWERPC_EXCP_603:
9624             excp_model = "PowerPC 603";
9625             break;
9626         case POWERPC_EXCP_603E:
9627             excp_model = "PowerPC 603e";
9628             break;
9629         case POWERPC_EXCP_604:
9630             excp_model = "PowerPC 604";
9631             break;
9632         case POWERPC_EXCP_7x0:
9633             excp_model = "PowerPC 740/750";
9634             break;
9635         case POWERPC_EXCP_7x5:
9636             excp_model = "PowerPC 745/755";
9637             break;
9638         case POWERPC_EXCP_74xx:
9639             excp_model = "PowerPC 74xx";
9640             break;
9641         case POWERPC_EXCP_BOOKE:
9642             excp_model = "PowerPC BookE";
9643             break;
9644 #if defined (TARGET_PPC64)
9645         case POWERPC_EXCP_970:
9646             excp_model = "PowerPC 970";
9647             break;
9648 #endif
9649         default:
9650             excp_model = "Unknown or invalid";
9651             break;
9652         }
9653         switch (env->bus_model) {
9654         case PPC_FLAGS_INPUT_6xx:
9655             bus_model = "PowerPC 6xx";
9656             break;
9657         case PPC_FLAGS_INPUT_BookE:
9658             bus_model = "PowerPC BookE";
9659             break;
9660         case PPC_FLAGS_INPUT_405:
9661             bus_model = "PowerPC 405";
9662             break;
9663         case PPC_FLAGS_INPUT_401:
9664             bus_model = "PowerPC 401/403";
9665             break;
9666         case PPC_FLAGS_INPUT_RCPU:
9667             bus_model = "RCPU / MPC8xx";
9668             break;
9669 #if defined (TARGET_PPC64)
9670         case PPC_FLAGS_INPUT_970:
9671             bus_model = "PowerPC 970";
9672             break;
9673 #endif
9674         default:
9675             bus_model = "Unknown or invalid";
9676             break;
9677         }
9678         printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9679                "    MMU model        : %s\n",
9680                def->name, def->pvr, def->msr_mask, mmu_model);
9681 #if !defined(CONFIG_USER_ONLY)
9682         if (env->tlb != NULL) {
9683             printf("                       %d %s TLB in %d ways\n",
9684                    env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9685                    env->nb_ways);
9686         }
9687 #endif
9688         printf("    Exceptions model : %s\n"
9689                "    Bus model        : %s\n",
9690                excp_model, bus_model);
9691         printf("    MSR features     :\n");
9692         if (env->flags & POWERPC_FLAG_SPE)
9693             printf("                        signal processing engine enable"
9694                    "\n");
9695         else if (env->flags & POWERPC_FLAG_VRE)
9696             printf("                        vector processor enable\n");
9697         if (env->flags & POWERPC_FLAG_TGPR)
9698             printf("                        temporary GPRs\n");
9699         else if (env->flags & POWERPC_FLAG_CE)
9700             printf("                        critical input enable\n");
9701         if (env->flags & POWERPC_FLAG_SE)
9702             printf("                        single-step trace mode\n");
9703         else if (env->flags & POWERPC_FLAG_DWE)
9704             printf("                        debug wait enable\n");
9705         else if (env->flags & POWERPC_FLAG_UBLE)
9706             printf("                        user BTB lock enable\n");
9707         if (env->flags & POWERPC_FLAG_BE)
9708             printf("                        branch-step trace mode\n");
9709         else if (env->flags & POWERPC_FLAG_DE)
9710             printf("                        debug interrupt enable\n");
9711         if (env->flags & POWERPC_FLAG_PX)
9712             printf("                        inclusive protection\n");
9713         else if (env->flags & POWERPC_FLAG_PMM)
9714             printf("                        performance monitor mark\n");
9715         if (env->flags == POWERPC_FLAG_NONE)
9716             printf("                        none\n");
9717         printf("    Time-base/decrementer clock source: %s\n",
9718                env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9719     }
9720     dump_ppc_insns(env);
9721     dump_ppc_sprs(env);
9722     fflush(stdout);
9723 #endif
9724
9725     return 0;
9726 }
9727
9728 static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
9729 {
9730     const ppc_def_t *ret;
9731     uint32_t pvr_rev;
9732     int i, best, match, best_match, max;
9733
9734     ret = NULL;
9735     max = ARRAY_SIZE(ppc_defs);
9736     best = -1;
9737     pvr_rev = pvr & 0xFFFF;
9738     /* We want all specified bits to match */
9739     best_match = 32 - ctz32(pvr_rev);
9740     for (i = 0; i < max; i++) {
9741         /* We check that the 16 higher bits are the same to ensure the CPU
9742          * model will be the choosen one.
9743          */
9744         if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
9745             /* We want as much as possible of the low-level 16 bits
9746              * to be the same but we allow inexact matches.
9747              */
9748             match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
9749             /* We check '>=' instead of '>' because the PPC_defs table
9750              * is ordered by increasing revision.
9751              * Then, we will match the higher revision compatible
9752              * with the requested PVR
9753              */
9754             if (match >= best_match) {
9755                 best = i;
9756                 best_match = match;
9757             }
9758         }
9759     }
9760     if (best != -1)
9761         ret = &ppc_defs[best];
9762
9763     return ret;
9764 }
9765
9766 #include <ctype.h>
9767
9768 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
9769 {
9770     const ppc_def_t *ret;
9771     const char *p;
9772     int i, max, len;
9773
9774     /* Check if the given name is a PVR */
9775     len = strlen(name);
9776     if (len == 10 && name[0] == '0' && name[1] == 'x') {
9777         p = name + 2;
9778         goto check_pvr;
9779     } else if (len == 8) {
9780         p = name;
9781     check_pvr:
9782         for (i = 0; i < 8; i++) {
9783             if (!qemu_isxdigit(*p++))
9784                 break;
9785         }
9786         if (i == 8)
9787             return ppc_find_by_pvr(strtoul(name, NULL, 16));
9788     }
9789     ret = NULL;
9790     max = ARRAY_SIZE(ppc_defs);
9791     for (i = 0; i < max; i++) {
9792         if (strcasecmp(name, ppc_defs[i].name) == 0) {
9793             ret = &ppc_defs[i];
9794             break;
9795         }
9796     }
9797
9798     return ret;
9799 }
9800
9801 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
9802 {
9803     int i, max;
9804
9805     max = ARRAY_SIZE(ppc_defs);
9806     for (i = 0; i < max; i++) {
9807         (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
9808                        ppc_defs[i].name, ppc_defs[i].pvr);
9809     }
9810 }