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Use range_covers_byte
[qemu/lumag.git] / target-ppc / helper.c
blobf865d7ae4c1b5d8251c09b6d63c4c8b4d1b46006
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "helper_regs.h"
29 #include "qemu-common.h"
30 #include "kvm.h"
31
32 //#define DEBUG_MMU
33 //#define DEBUG_BATS
34 //#define DEBUG_SLB
35 //#define DEBUG_SOFTWARE_TLB
36 //#define DUMP_PAGE_TABLES
37 //#define DEBUG_EXCEPTIONS
38 //#define FLUSH_ALL_TLBS
39
40 #ifdef DEBUG_MMU
41 # define LOG_MMU(...) qemu_log(__VA_ARGS__)
42 # define LOG_MMU_STATE(env) log_cpu_state((env), 0)
43 #else
44 # define LOG_MMU(...) do { } while (0)
45 # define LOG_MMU_STATE(...) do { } while (0)
46 #endif
47
48
49 #ifdef DEBUG_SOFTWARE_TLB
50 # define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
51 #else
52 # define LOG_SWTLB(...) do { } while (0)
53 #endif
54
55 #ifdef DEBUG_BATS
56 # define LOG_BATS(...) qemu_log(__VA_ARGS__)
57 #else
58 # define LOG_BATS(...) do { } while (0)
59 #endif
60
61 #ifdef DEBUG_SLB
62 # define LOG_SLB(...) qemu_log(__VA_ARGS__)
63 #else
64 # define LOG_SLB(...) do { } while (0)
65 #endif
66
67 #ifdef DEBUG_EXCEPTIONS
68 # define LOG_EXCP(...) qemu_log(__VA_ARGS__)
69 #else
70 # define LOG_EXCP(...) do { } while (0)
71 #endif
72
73
74 /*****************************************************************************/
75 /* PowerPC MMU emulation */
76
77 #if defined(CONFIG_USER_ONLY)
78 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
79 int mmu_idx, int is_softmmu)
80 {
81 int exception, error_code;
82
83 if (rw == 2) {
84 exception = POWERPC_EXCP_ISI;
85 error_code = 0x40000000;
86 } else {
87 exception = POWERPC_EXCP_DSI;
88 error_code = 0x40000000;
89 if (rw)
90 error_code |= 0x02000000;
91 env->spr[SPR_DAR] = address;
92 env->spr[SPR_DSISR] = error_code;
93 }
94 env->exception_index = exception;
95 env->error_code = error_code;
96
97 return 1;
98 }
99
100 #else
101 /* Common routines used by software and hardware TLBs emulation */
102 static inline int pte_is_valid(target_ulong pte0)
103 {
104 return pte0 & 0x80000000 ? 1 : 0;
105 }
106
107 static inline void pte_invalidate(target_ulong *pte0)
108 {
109 *pte0 &= ~0x80000000;
110 }
111
112 #if defined(TARGET_PPC64)
113 static inline int pte64_is_valid(target_ulong pte0)
114 {
115 return pte0 & 0x0000000000000001ULL ? 1 : 0;
116 }
117
118 static inline void pte64_invalidate(target_ulong *pte0)
119 {
120 *pte0 &= ~0x0000000000000001ULL;
121 }
122 #endif
123
124 #define PTE_PTEM_MASK 0x7FFFFFBF
125 #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
126 #if defined(TARGET_PPC64)
127 #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
128 #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
129 #endif
130
131 static inline int pp_check(int key, int pp, int nx)
132 {
133 int access;
134
135 /* Compute access rights */
136 /* When pp is 3/7, the result is undefined. Set it to noaccess */
137 access = 0;
138 if (key == 0) {
139 switch (pp) {
140 case 0x0:
141 case 0x1:
142 case 0x2:
143 access |= PAGE_WRITE;
144 /* No break here */
145 case 0x3:
146 case 0x6:
147 access |= PAGE_READ;
148 break;
149 }
150 } else {
151 switch (pp) {
152 case 0x0:
153 case 0x6:
154 access = 0;
155 break;
156 case 0x1:
157 case 0x3:
158 access = PAGE_READ;
159 break;
160 case 0x2:
161 access = PAGE_READ | PAGE_WRITE;
162 break;
163 }
164 }
165 if (nx == 0)
166 access |= PAGE_EXEC;
167
168 return access;
169 }
170
171 static inline int check_prot(int prot, int rw, int access_type)
172 {
173 int ret;
174
175 if (access_type == ACCESS_CODE) {
176 if (prot & PAGE_EXEC)
177 ret = 0;
178 else
179 ret = -2;
180 } else if (rw) {
181 if (prot & PAGE_WRITE)
182 ret = 0;
183 else
184 ret = -2;
185 } else {
186 if (prot & PAGE_READ)
187 ret = 0;
188 else
189 ret = -2;
190 }
191
192 return ret;
193 }
194
195 static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,
196 target_ulong pte1, int h, int rw, int type)
197 {
198 target_ulong ptem, mmask;
199 int access, ret, pteh, ptev, pp;
200
201 ret = -1;
202 /* Check validity and table match */
203 #if defined(TARGET_PPC64)
204 if (is_64b) {
205 ptev = pte64_is_valid(pte0);
206 pteh = (pte0 >> 1) & 1;
207 } else
208 #endif
209 {
210 ptev = pte_is_valid(pte0);
211 pteh = (pte0 >> 6) & 1;
212 }
213 if (ptev && h == pteh) {
214 /* Check vsid & api */
215 #if defined(TARGET_PPC64)
216 if (is_64b) {
217 ptem = pte0 & PTE64_PTEM_MASK;
218 mmask = PTE64_CHECK_MASK;
219 pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);
220 ctx->nx = (pte1 >> 2) & 1; /* No execute bit */
221 ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */
222 } else
223 #endif
224 {
225 ptem = pte0 & PTE_PTEM_MASK;
226 mmask = PTE_CHECK_MASK;
227 pp = pte1 & 0x00000003;
228 }
229 if (ptem == ctx->ptem) {
230 if (ctx->raddr != (target_phys_addr_t)-1ULL) {
231 /* all matches should have equal RPN, WIMG & PP */
232 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
233 qemu_log("Bad RPN/WIMG/PP\n");
234 return -3;
235 }
236 }
237 /* Compute access rights */
238 access = pp_check(ctx->key, pp, ctx->nx);
239 /* Keep the matching PTE informations */
240 ctx->raddr = pte1;
241 ctx->prot = access;
242 ret = check_prot(ctx->prot, rw, type);
243 if (ret == 0) {
244 /* Access granted */
245 LOG_MMU("PTE access granted !\n");
246 } else {
247 /* Access right violation */
248 LOG_MMU("PTE access rejected\n");
249 }
250 }
251 }
252
253 return ret;
254 }
255
256 static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0,
257 target_ulong pte1, int h, int rw, int type)
258 {
259 return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
260 }
261
262 #if defined(TARGET_PPC64)
263 static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0,
264 target_ulong pte1, int h, int rw, int type)
265 {
266 return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
267 }
268 #endif
269
270 static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
271 int ret, int rw)
272 {
273 int store = 0;
274
275 /* Update page flags */
276 if (!(*pte1p & 0x00000100)) {
277 /* Update accessed flag */
278 *pte1p |= 0x00000100;
279 store = 1;
280 }
281 if (!(*pte1p & 0x00000080)) {
282 if (rw == 1 && ret == 0) {
283 /* Update changed flag */
284 *pte1p |= 0x00000080;
285 store = 1;
286 } else {
287 /* Force page fault for first write access */
288 ctx->prot &= ~PAGE_WRITE;
289 }
290 }
291
292 return store;
293 }
294
295 /* Software driven TLB helpers */
296 static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way,
297 int is_code)
298 {
299 int nr;
300
301 /* Select TLB num in a way from address */
302 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
303 /* Select TLB way */
304 nr += env->tlb_per_way * way;
305 /* 6xx have separate TLBs for instructions and data */
306 if (is_code && env->id_tlbs == 1)
307 nr += env->nb_tlb;
308
309 return nr;
310 }
311
312 static inline void ppc6xx_tlb_invalidate_all(CPUState *env)
313 {
314 ppc6xx_tlb_t *tlb;
315 int nr, max;
316
317 //LOG_SWTLB("Invalidate all TLBs\n");
318 /* Invalidate all defined software TLB */
319 max = env->nb_tlb;
320 if (env->id_tlbs == 1)
321 max *= 2;
322 for (nr = 0; nr < max; nr++) {
323 tlb = &env->tlb[nr].tlb6;
324 pte_invalidate(&tlb->pte0);
325 }
326 tlb_flush(env, 1);
327 }
328
329 static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env,
330 target_ulong eaddr,
331 int is_code, int match_epn)
332 {
333 #if !defined(FLUSH_ALL_TLBS)
334 ppc6xx_tlb_t *tlb;
335 int way, nr;
336
337 /* Invalidate ITLB + DTLB, all ways */
338 for (way = 0; way < env->nb_ways; way++) {
339 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
340 tlb = &env->tlb[nr].tlb6;
341 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
342 LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,
343 env->nb_tlb, eaddr);
344 pte_invalidate(&tlb->pte0);
345 tlb_flush_page(env, tlb->EPN);
346 }
347 }
348 #else
349 /* XXX: PowerPC specification say this is valid as well */
350 ppc6xx_tlb_invalidate_all(env);
351 #endif
352 }
353
354 static inline void ppc6xx_tlb_invalidate_virt(CPUState *env,
355 target_ulong eaddr, int is_code)
356 {
357 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
358 }
359
360 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
361 target_ulong pte0, target_ulong pte1)
362 {
363 ppc6xx_tlb_t *tlb;
364 int nr;
365
366 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
367 tlb = &env->tlb[nr].tlb6;
368 LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
369 " PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);
370 /* Invalidate any pending reference in Qemu for this virtual address */
371 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
372 tlb->pte0 = pte0;
373 tlb->pte1 = pte1;
374 tlb->EPN = EPN;
375 /* Store last way for LRU mechanism */
376 env->last_way = way;
377 }
378
379 static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx,
380 target_ulong eaddr, int rw, int access_type)
381 {
382 ppc6xx_tlb_t *tlb;
383 int nr, best, way;
384 int ret;
385
386 best = -1;
387 ret = -1; /* No TLB found */
388 for (way = 0; way < env->nb_ways; way++) {
389 nr = ppc6xx_tlb_getnum(env, eaddr, way,
390 access_type == ACCESS_CODE ? 1 : 0);
391 tlb = &env->tlb[nr].tlb6;
392 /* This test "emulates" the PTE index match for hardware TLBs */
393 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
394 LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx
395 "] <> " TARGET_FMT_lx "\n", nr, env->nb_tlb,
396 pte_is_valid(tlb->pte0) ? "valid" : "inval",
397 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
398 continue;
399 }
400 LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx " <> " TARGET_FMT_lx " "
401 TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb,
402 pte_is_valid(tlb->pte0) ? "valid" : "inval",
403 tlb->EPN, eaddr, tlb->pte1,
404 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
405 switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
406 case -3:
407 /* TLB inconsistency */
408 return -1;
409 case -2:
410 /* Access violation */
411 ret = -2;
412 best = nr;
413 break;
414 case -1:
415 default:
416 /* No match */
417 break;
418 case 0:
419 /* access granted */
420 /* XXX: we should go on looping to check all TLBs consistency
421 * but we can speed-up the whole thing as the
422 * result would be undefined if TLBs are not consistent.
423 */
424 ret = 0;
425 best = nr;
426 goto done;
427 }
428 }
429 if (best != -1) {
430 done:
431 LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n",
432 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
433 /* Update page flags */
434 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
435 }
436
437 return ret;
438 }
439
440 /* Perform BAT hit & translation */
441 static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp,
442 int *protp, target_ulong *BATu,
443 target_ulong *BATl)
444 {
445 target_ulong bl;
446 int pp, valid, prot;
447
448 bl = (*BATu & 0x00001FFC) << 15;
449 valid = 0;
450 prot = 0;
451 if (((msr_pr == 0) && (*BATu & 0x00000002)) ||
452 ((msr_pr != 0) && (*BATu & 0x00000001))) {
453 valid = 1;
454 pp = *BATl & 0x00000003;
455 if (pp != 0) {
456 prot = PAGE_READ | PAGE_EXEC;
457 if (pp == 0x2)
458 prot |= PAGE_WRITE;
459 }
460 }
461 *blp = bl;
462 *validp = valid;
463 *protp = prot;
464 }
465
466 static inline void bat_601_size_prot(CPUState *env, target_ulong *blp,
467 int *validp, int *protp,
468 target_ulong *BATu, target_ulong *BATl)
469 {
470 target_ulong bl;
471 int key, pp, valid, prot;
472
473 bl = (*BATl & 0x0000003F) << 17;
474 LOG_BATS("b %02x ==> bl " TARGET_FMT_lx " msk " TARGET_FMT_lx "\n",
475 (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
476 prot = 0;
477 valid = (*BATl >> 6) & 1;
478 if (valid) {
479 pp = *BATu & 0x00000003;
480 if (msr_pr == 0)
481 key = (*BATu >> 3) & 1;
482 else
483 key = (*BATu >> 2) & 1;
484 prot = pp_check(key, pp, 0);
485 }
486 *blp = bl;
487 *validp = valid;
488 *protp = prot;
489 }
490
491 static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
492 int rw, int type)
493 {
494 target_ulong *BATlt, *BATut, *BATu, *BATl;
495 target_ulong BEPIl, BEPIu, bl;
496 int i, valid, prot;
497 int ret = -1;
498
499 LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
500 type == ACCESS_CODE ? 'I' : 'D', virtual);
501 switch (type) {
502 case ACCESS_CODE:
503 BATlt = env->IBAT[1];
504 BATut = env->IBAT[0];
505 break;
506 default:
507 BATlt = env->DBAT[1];
508 BATut = env->DBAT[0];
509 break;
510 }
511 for (i = 0; i < env->nb_BATs; i++) {
512 BATu = &BATut[i];
513 BATl = &BATlt[i];
514 BEPIu = *BATu & 0xF0000000;
515 BEPIl = *BATu & 0x0FFE0000;
516 if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
517 bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl);
518 } else {
519 bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
520 }
521 LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
522 " BATl " TARGET_FMT_lx "\n", __func__,
523 type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
524 if ((virtual & 0xF0000000) == BEPIu &&
525 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
526 /* BAT matches */
527 if (valid != 0) {
528 /* Get physical address */
529 ctx->raddr = (*BATl & 0xF0000000) |
530 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
531 (virtual & 0x0001F000);
532 /* Compute access rights */
533 ctx->prot = prot;
534 ret = check_prot(ctx->prot, rw, type);
535 if (ret == 0)
536 LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n",
537 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
538 ctx->prot & PAGE_WRITE ? 'W' : '-');
539 break;
540 }
541 }
542 }
543 if (ret < 0) {
544 #if defined(DEBUG_BATS)
545 if (qemu_log_enabled()) {
546 LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", virtual);
547 for (i = 0; i < 4; i++) {
548 BATu = &BATut[i];
549 BATl = &BATlt[i];
550 BEPIu = *BATu & 0xF0000000;
551 BEPIl = *BATu & 0x0FFE0000;
552 bl = (*BATu & 0x00001FFC) << 15;
553 LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
554 " BATl " TARGET_FMT_lx " \n\t" TARGET_FMT_lx " "
555 TARGET_FMT_lx " " TARGET_FMT_lx "\n",
556 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
557 *BATu, *BATl, BEPIu, BEPIl, bl);
558 }
559 }
560 #endif
561 }
562 /* No hit */
563 return ret;
564 }
565
566 /* PTE table lookup */
567 static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
568 int type, int target_page_bits)
569 {
570 target_ulong base, pte0, pte1;
571 int i, good = -1;
572 int ret, r;
573
574 ret = -1; /* No entry found */
575 base = ctx->pg_addr[h];
576 for (i = 0; i < 8; i++) {
577 #if defined(TARGET_PPC64)
578 if (is_64b) {
579 pte0 = ldq_phys(base + (i * 16));
580 pte1 = ldq_phys(base + (i * 16) + 8);
581
582 /* We have a TLB that saves 4K pages, so let's
583 * split a huge page to 4k chunks */
584 if (target_page_bits != TARGET_PAGE_BITS)
585 pte1 |= (ctx->eaddr & (( 1 << target_page_bits ) - 1))
586 & TARGET_PAGE_MASK;
587
588 r = pte64_check(ctx, pte0, pte1, h, rw, type);
589 LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "
590 TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
591 base + (i * 16), pte0, pte1, (int)(pte0 & 1), h,
592 (int)((pte0 >> 1) & 1), ctx->ptem);
593 } else
594 #endif
595 {
596 pte0 = ldl_phys(base + (i * 8));
597 pte1 = ldl_phys(base + (i * 8) + 4);
598 r = pte32_check(ctx, pte0, pte1, h, rw, type);
599 LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "
600 TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
601 base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h,
602 (int)((pte0 >> 6) & 1), ctx->ptem);
603 }
604 switch (r) {
605 case -3:
606 /* PTE inconsistency */
607 return -1;
608 case -2:
609 /* Access violation */
610 ret = -2;
611 good = i;
612 break;
613 case -1:
614 default:
615 /* No PTE match */
616 break;
617 case 0:
618 /* access granted */
619 /* XXX: we should go on looping to check all PTEs consistency
620 * but if we can speed-up the whole thing as the
621 * result would be undefined if PTEs are not consistent.
622 */
623 ret = 0;
624 good = i;
625 goto done;
626 }
627 }
628 if (good != -1) {
629 done:
630 LOG_MMU("found PTE at addr " TARGET_FMT_lx " prot=%01x ret=%d\n",
631 ctx->raddr, ctx->prot, ret);
632 /* Update page flags */
633 pte1 = ctx->raddr;
634 if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
635 #if defined(TARGET_PPC64)
636 if (is_64b) {
637 stq_phys_notdirty(base + (good * 16) + 8, pte1);
638 } else
639 #endif
640 {
641 stl_phys_notdirty(base + (good * 8) + 4, pte1);
642 }
643 }
644 }
645
646 return ret;
647 }
648
649 static inline int find_pte32(mmu_ctx_t *ctx, int h, int rw, int type,
650 int target_page_bits)
651 {
652 return _find_pte(ctx, 0, h, rw, type, target_page_bits);
653 }
654
655 #if defined(TARGET_PPC64)
656 static inline int find_pte64(mmu_ctx_t *ctx, int h, int rw, int type,
657 int target_page_bits)
658 {
659 return _find_pte(ctx, 1, h, rw, type, target_page_bits);
660 }
661 #endif
662
663 static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw,
664 int type, int target_page_bits)
665 {
666 #if defined(TARGET_PPC64)
667 if (env->mmu_model & POWERPC_MMU_64)
668 return find_pte64(ctx, h, rw, type, target_page_bits);
669 #endif
670
671 return find_pte32(ctx, h, rw, type, target_page_bits);
672 }
673
674 #if defined(TARGET_PPC64)
675 static ppc_slb_t *slb_get_entry(CPUPPCState *env, int nr)
676 {
677 ppc_slb_t *retval = &env->slb[nr];
678
679 #if 0 // XXX implement bridge mode?
680 if (env->spr[SPR_ASR] & 1) {
681 target_phys_addr_t sr_base;
682
683 sr_base = env->spr[SPR_ASR] & 0xfffffffffffff000;
684 sr_base += (12 * nr);
685
686 retval->tmp64 = ldq_phys(sr_base);
687 retval->tmp = ldl_phys(sr_base + 8);
688 }
689 #endif
690
691 return retval;
692 }
693
694 static void slb_set_entry(CPUPPCState *env, int nr, ppc_slb_t *slb)
695 {
696 ppc_slb_t *entry = &env->slb[nr];
697
698 if (slb == entry)
699 return;
700
701 entry->tmp64 = slb->tmp64;
702 entry->tmp = slb->tmp;
703 }
704
705 static inline int slb_is_valid(ppc_slb_t *slb)
706 {
707 return (int)(slb->tmp64 & 0x0000000008000000ULL);
708 }
709
710 static inline void slb_invalidate(ppc_slb_t *slb)
711 {
712 slb->tmp64 &= ~0x0000000008000000ULL;
713 }
714
715 static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr,
716 target_ulong *vsid, target_ulong *page_mask,
717 int *attr, int *target_page_bits)
718 {
719 target_ulong mask;
720 int n, ret;
721
722 ret = -5;
723 LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
724 mask = 0x0000000000000000ULL; /* Avoid gcc warning */
725 for (n = 0; n < env->slb_nr; n++) {
726 ppc_slb_t *slb = slb_get_entry(env, n);
727
728 LOG_SLB("%s: seg %d %016" PRIx64 " %08"
729 PRIx32 "\n", __func__, n, slb->tmp64, slb->tmp);
730 if (slb_is_valid(slb)) {
731 /* SLB entry is valid */
732 mask = 0xFFFFFFFFF0000000ULL;
733 if (slb->tmp & 0x8) {
734 /* 16 MB PTEs */
735 if (target_page_bits)
736 *target_page_bits = 24;
737 } else {
738 /* 4 KB PTEs */
739 if (target_page_bits)
740 *target_page_bits = TARGET_PAGE_BITS;
741 }
742 if ((eaddr & mask) == (slb->tmp64 & mask)) {
743 /* SLB match */
744 *vsid = ((slb->tmp64 << 24) | (slb->tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
745 *page_mask = ~mask;
746 *attr = slb->tmp & 0xFF;
747 ret = n;
748 break;
749 }
750 }
751 }
752
753 return ret;
754 }
755
756 void ppc_slb_invalidate_all (CPUPPCState *env)
757 {
758 int n, do_invalidate;
759
760 do_invalidate = 0;
761 /* XXX: Warning: slbia never invalidates the first segment */
762 for (n = 1; n < env->slb_nr; n++) {
763 ppc_slb_t *slb = slb_get_entry(env, n);
764
765 if (slb_is_valid(slb)) {
766 slb_invalidate(slb);
767 slb_set_entry(env, n, slb);
768 /* XXX: given the fact that segment size is 256 MB or 1TB,
769 * and we still don't have a tlb_flush_mask(env, n, mask)
770 * in Qemu, we just invalidate all TLBs
771 */
772 do_invalidate = 1;
773 }
774 }
775 if (do_invalidate)
776 tlb_flush(env, 1);
777 }
778
779 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
780 {
781 target_ulong vsid, page_mask;
782 int attr;
783 int n;
784
785 n = slb_lookup(env, T0, &vsid, &page_mask, &attr, NULL);
786 if (n >= 0) {
787 ppc_slb_t *slb = slb_get_entry(env, n);
788
789 if (slb_is_valid(slb)) {
790 slb_invalidate(slb);
791 slb_set_entry(env, n, slb);
792 /* XXX: given the fact that segment size is 256 MB or 1TB,
793 * and we still don't have a tlb_flush_mask(env, n, mask)
794 * in Qemu, we just invalidate all TLBs
795 */
796 tlb_flush(env, 1);
797 }
798 }
799 }
800
801 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
802 {
803 target_ulong rt;
804 ppc_slb_t *slb = slb_get_entry(env, slb_nr);
805
806 if (slb_is_valid(slb)) {
807 /* SLB entry is valid */
808 /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
809 rt = slb->tmp >> 8; /* 65:88 => 40:63 */
810 rt |= (slb->tmp64 & 0x7) << 24; /* 62:64 => 37:39 */
811 /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
812 rt |= ((slb->tmp >> 4) & 0xF) << 27;
813 } else {
814 rt = 0;
815 }
816 LOG_SLB("%s: %016" PRIx64 " %08" PRIx32 " => %d "
817 TARGET_FMT_lx "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt);
818
819 return rt;
820 }
821
822 void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)
823 {
824 ppc_slb_t *slb;
825
826 uint64_t vsid;
827 uint64_t esid;
828 int flags, valid, slb_nr;
829
830 vsid = rs >> 12;
831 flags = ((rs >> 8) & 0xf);
832
833 esid = rb >> 28;
834 valid = (rb & (1 << 27));
835 slb_nr = rb & 0xfff;
836
837 slb = slb_get_entry(env, slb_nr);
838 slb->tmp64 = (esid << 28) | valid | (vsid >> 24);
839 slb->tmp = (vsid << 8) | (flags << 3);
840
841 LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
842 " %08" PRIx32 "\n", __func__, slb_nr, rb, rs, slb->tmp64,
843 slb->tmp);
844
845 slb_set_entry(env, slb_nr, slb);
846 }
847 #endif /* defined(TARGET_PPC64) */
848
849 /* Perform segment based translation */
850 static inline target_phys_addr_t get_pgaddr(target_phys_addr_t sdr1,
851 int sdr_sh,
852 target_phys_addr_t hash,
853 target_phys_addr_t mask)
854 {
855 return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask);
856 }
857
858 static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
859 target_ulong eaddr, int rw, int type)
860 {
861 target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
862 target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
863 #if defined(TARGET_PPC64)
864 int attr;
865 #endif
866 int ds, vsid_sh, sdr_sh, pr, target_page_bits;
867 int ret, ret2;
868
869 pr = msr_pr;
870 #if defined(TARGET_PPC64)
871 if (env->mmu_model & POWERPC_MMU_64) {
872 LOG_MMU("Check SLBs\n");
873 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr,
874 &target_page_bits);
875 if (ret < 0)
876 return ret;
877 ctx->key = ((attr & 0x40) && (pr != 0)) ||
878 ((attr & 0x80) && (pr == 0)) ? 1 : 0;
879 ds = 0;
880 ctx->nx = attr & 0x10 ? 1 : 0;
881 ctx->eaddr = eaddr;
882 vsid_mask = 0x00003FFFFFFFFF80ULL;
883 vsid_sh = 7;
884 sdr_sh = 18;
885 sdr_mask = 0x3FF80;
886 } else
887 #endif /* defined(TARGET_PPC64) */
888 {
889 sr = env->sr[eaddr >> 28];
890 page_mask = 0x0FFFFFFF;
891 ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
892 ((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
893 ds = sr & 0x80000000 ? 1 : 0;
894 ctx->nx = sr & 0x10000000 ? 1 : 0;
895 vsid = sr & 0x00FFFFFF;
896 vsid_mask = 0x01FFFFC0;
897 vsid_sh = 6;
898 sdr_sh = 16;
899 sdr_mask = 0xFFC0;
900 target_page_bits = TARGET_PAGE_BITS;
901 LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
902 TARGET_FMT_lx " lr=" TARGET_FMT_lx
903 " ir=%d dr=%d pr=%d %d t=%d\n",
904 eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
905 (int)msr_dr, pr != 0 ? 1 : 0, rw, type);
906 }
907 LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
908 ctx->key, ds, ctx->nx, vsid);
909 ret = -1;
910 if (!ds) {
911 /* Check if instruction fetch is allowed, if needed */
912 if (type != ACCESS_CODE || ctx->nx == 0) {
913 /* Page address translation */
914 /* Primary table address */
915 sdr = env->sdr1;
916 pgidx = (eaddr & page_mask) >> target_page_bits;
917 #if defined(TARGET_PPC64)
918 if (env->mmu_model & POWERPC_MMU_64) {
919 htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F));
920 /* XXX: this is false for 1 TB segments */
921 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
922 } else
923 #endif
924 {
925 htab_mask = sdr & 0x000001FF;
926 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
927 }
928 mask = (htab_mask << sdr_sh) | sdr_mask;
929 LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
930 " mask " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
931 sdr, sdr_sh, hash, mask, page_mask);
932 ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
933 /* Secondary table address */
934 hash = (~hash) & vsid_mask;
935 LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
936 " mask " TARGET_FMT_plx "\n", sdr, sdr_sh, hash, mask);
937 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
938 #if defined(TARGET_PPC64)
939 if (env->mmu_model & POWERPC_MMU_64) {
940 /* Only 5 bits of the page index are used in the AVPN */
941 if (target_page_bits > 23) {
942 ctx->ptem = (vsid << 12) |
943 ((pgidx << (target_page_bits - 16)) & 0xF80);
944 } else {
945 ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
946 }
947 } else
948 #endif
949 {
950 ctx->ptem = (vsid << 7) | (pgidx >> 10);
951 }
952 /* Initialize real address with an invalid value */
953 ctx->raddr = (target_phys_addr_t)-1ULL;
954 if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
955 env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
956 /* Software TLB search */
957 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
958 } else {
959 LOG_MMU("0 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
960 "api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
961 " pg_addr=" TARGET_FMT_plx "\n",
962 sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
963 /* Primary table lookup */
964 ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
965 if (ret < 0) {
966 /* Secondary table lookup */
967 if (eaddr != 0xEFFFFFFF)
968 LOG_MMU("1 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
969 "api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
970 " pg_addr=" TARGET_FMT_plx "\n", sdr, vsid,
971 pgidx, hash, ctx->pg_addr[1]);
972 ret2 = find_pte(env, ctx, 1, rw, type,
973 target_page_bits);
974 if (ret2 != -1)
975 ret = ret2;
976 }
977 }
978 #if defined (DUMP_PAGE_TABLES)
979 if (qemu_log_enabled()) {
980 target_phys_addr_t curaddr;
981 uint32_t a0, a1, a2, a3;
982 qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
983 "\n", sdr, mask + 0x80);
984 for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
985 curaddr += 16) {
986 a0 = ldl_phys(curaddr);
987 a1 = ldl_phys(curaddr + 4);
988 a2 = ldl_phys(curaddr + 8);
989 a3 = ldl_phys(curaddr + 12);
990 if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
991 qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
992 curaddr, a0, a1, a2, a3);
993 }
994 }
995 }
996 #endif
997 } else {
998 LOG_MMU("No access allowed\n");
999 ret = -3;
1000 }
1001 } else {
1002 LOG_MMU("direct store...\n");
1003 /* Direct-store segment : absolutely *BUGGY* for now */
1004 switch (type) {
1005 case ACCESS_INT:
1006 /* Integer load/store : only access allowed */
1007 break;
1008 case ACCESS_CODE:
1009 /* No code fetch is allowed in direct-store areas */
1010 return -4;
1011 case ACCESS_FLOAT:
1012 /* Floating point load/store */
1013 return -4;
1014 case ACCESS_RES:
1015 /* lwarx, ldarx or srwcx. */
1016 return -4;
1017 case ACCESS_CACHE:
1018 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
1019 /* Should make the instruction do no-op.
1020 * As it already do no-op, it's quite easy :-)
1021 */
1022 ctx->raddr = eaddr;
1023 return 0;
1024 case ACCESS_EXT:
1025 /* eciwx or ecowx */
1026 return -4;
1027 default:
1028 qemu_log("ERROR: instruction should not need "
1029 "address translation\n");
1030 return -4;
1031 }
1032 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
1033 ctx->raddr = eaddr;
1034 ret = 2;
1035 } else {
1036 ret = -2;
1037 }
1038 }
1039
1040 return ret;
1041 }
1042
1043 /* Generic TLB check function for embedded PowerPC implementations */
1044 static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
1045 target_phys_addr_t *raddrp,
1046 target_ulong address, uint32_t pid, int ext,
1047 int i)
1048 {
1049 target_ulong mask;
1050
1051 /* Check valid flag */
1052 if (!(tlb->prot & PAGE_VALID)) {
1053 return -1;
1054 }
1055 mask = ~(tlb->size - 1);
1056 LOG_SWTLB("%s: TLB %d address " TARGET_FMT_lx " PID %u <=> " TARGET_FMT_lx
1057 " " TARGET_FMT_lx " %u\n", __func__, i, address, pid, tlb->EPN,
1058 mask, (uint32_t)tlb->PID);
1059 /* Check PID */
1060 if (tlb->PID != 0 && tlb->PID != pid)
1061 return -1;
1062 /* Check effective address */
1063 if ((address & mask) != tlb->EPN)
1064 return -1;
1065 *raddrp = (tlb->RPN & mask) | (address & ~mask);
1066 #if (TARGET_PHYS_ADDR_BITS >= 36)
1067 if (ext) {
1068 /* Extend the physical address to 36 bits */
1069 *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
1070 }
1071 #endif
1072
1073 return 0;
1074 }
1075
1076 /* Generic TLB search function for PowerPC embedded implementations */
1077 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
1078 {
1079 ppcemb_tlb_t *tlb;
1080 target_phys_addr_t raddr;
1081 int i, ret;
1082
1083 /* Default return value is no match */
1084 ret = -1;
1085 for (i = 0; i < env->nb_tlb; i++) {
1086 tlb = &env->tlb[i].tlbe;
1087 if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
1088 ret = i;
1089 break;
1090 }
1091 }
1092
1093 return ret;
1094 }
1095
1096 /* Helpers specific to PowerPC 40x implementations */
1097 static inline void ppc4xx_tlb_invalidate_all(CPUState *env)
1098 {
1099 ppcemb_tlb_t *tlb;
1100 int i;
1101
1102 for (i = 0; i < env->nb_tlb; i++) {
1103 tlb = &env->tlb[i].tlbe;
1104 tlb->prot &= ~PAGE_VALID;
1105 }
1106 tlb_flush(env, 1);
1107 }
1108
1109 static inline void ppc4xx_tlb_invalidate_virt(CPUState *env,
1110 target_ulong eaddr, uint32_t pid)
1111 {
1112 #if !defined(FLUSH_ALL_TLBS)
1113 ppcemb_tlb_t *tlb;
1114 target_phys_addr_t raddr;
1115 target_ulong page, end;
1116 int i;
1117
1118 for (i = 0; i < env->nb_tlb; i++) {
1119 tlb = &env->tlb[i].tlbe;
1120 if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
1121 end = tlb->EPN + tlb->size;
1122 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
1123 tlb_flush_page(env, page);
1124 tlb->prot &= ~PAGE_VALID;
1125 break;
1126 }
1127 }
1128 #else
1129 ppc4xx_tlb_invalidate_all(env);
1130 #endif
1131 }
1132
1133 static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1134 target_ulong address, int rw, int access_type)
1135 {
1136 ppcemb_tlb_t *tlb;
1137 target_phys_addr_t raddr;
1138 int i, ret, zsel, zpr, pr;
1139
1140 ret = -1;
1141 raddr = (target_phys_addr_t)-1ULL;
1142 pr = msr_pr;
1143 for (i = 0; i < env->nb_tlb; i++) {
1144 tlb = &env->tlb[i].tlbe;
1145 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1146 env->spr[SPR_40x_PID], 0, i) < 0)
1147 continue;
1148 zsel = (tlb->attr >> 4) & 0xF;
1149 zpr = (env->spr[SPR_40x_ZPR] >> (30 - (2 * zsel))) & 0x3;
1150 LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
1151 __func__, i, zsel, zpr, rw, tlb->attr);
1152 /* Check execute enable bit */
1153 switch (zpr) {
1154 case 0x2:
1155 if (pr != 0)
1156 goto check_perms;
1157 /* No break here */
1158 case 0x3:
1159 /* All accesses granted */
1160 ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1161 ret = 0;
1162 break;
1163 case 0x0:
1164 if (pr != 0) {
1165 /* Raise Zone protection fault. */
1166 env->spr[SPR_40x_ESR] = 1 << 22;
1167 ctx->prot = 0;
1168 ret = -2;
1169 break;
1170 }
1171 /* No break here */
1172 case 0x1:
1173 check_perms:
1174 /* Check from TLB entry */
1175 /* XXX: there is a problem here or in the TLB fill code... */
1176 ctx->prot = tlb->prot;
1177 ctx->prot |= PAGE_EXEC;
1178 ret = check_prot(ctx->prot, rw, access_type);
1179 if (ret == -2)
1180 env->spr[SPR_40x_ESR] = 0;
1181 break;
1182 }
1183 if (ret >= 0) {
1184 ctx->raddr = raddr;
1185 LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx
1186 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1187 ret);
1188 return 0;
1189 }
1190 }
1191 LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx
1192 " %d %d\n", __func__, address, raddr, ctx->prot, ret);
1193
1194 return ret;
1195 }
1196
1197 void store_40x_sler (CPUPPCState *env, uint32_t val)
1198 {
1199 /* XXX: TO BE FIXED */
1200 if (val != 0x00000000) {
1201 cpu_abort(env, "Little-endian regions are not supported by now\n");
1202 }
1203 env->spr[SPR_405_SLER] = val;
1204 }
1205
1206 static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1207 target_ulong address, int rw,
1208 int access_type)
1209 {
1210 ppcemb_tlb_t *tlb;
1211 target_phys_addr_t raddr;
1212 int i, prot, ret;
1213
1214 ret = -1;
1215 raddr = (target_phys_addr_t)-1ULL;
1216 for (i = 0; i < env->nb_tlb; i++) {
1217 tlb = &env->tlb[i].tlbe;
1218 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1219 env->spr[SPR_BOOKE_PID], 1, i) < 0)
1220 continue;
1221 if (msr_pr != 0)
1222 prot = tlb->prot & 0xF;
1223 else
1224 prot = (tlb->prot >> 4) & 0xF;
1225 /* Check the address space */
1226 if (access_type == ACCESS_CODE) {
1227 if (msr_ir != (tlb->attr & 1))
1228 continue;
1229 ctx->prot = prot;
1230 if (prot & PAGE_EXEC) {
1231 ret = 0;
1232 break;
1233 }
1234 ret = -3;
1235 } else {
1236 if (msr_dr != (tlb->attr & 1))
1237 continue;
1238 ctx->prot = prot;
1239 if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1240 ret = 0;
1241 break;
1242 }
1243 ret = -2;
1244 }
1245 }
1246 if (ret >= 0)
1247 ctx->raddr = raddr;
1248
1249 return ret;
1250 }
1251
1252 static inline int check_physical(CPUState *env, mmu_ctx_t *ctx,
1253 target_ulong eaddr, int rw)
1254 {
1255 int in_plb, ret;
1256
1257 ctx->raddr = eaddr;
1258 ctx->prot = PAGE_READ | PAGE_EXEC;
1259 ret = 0;
1260 switch (env->mmu_model) {
1261 case POWERPC_MMU_32B:
1262 case POWERPC_MMU_601:
1263 case POWERPC_MMU_SOFT_6xx:
1264 case POWERPC_MMU_SOFT_74xx:
1265 case POWERPC_MMU_SOFT_4xx:
1266 case POWERPC_MMU_REAL:
1267 case POWERPC_MMU_BOOKE:
1268 ctx->prot |= PAGE_WRITE;
1269 break;
1270 #if defined(TARGET_PPC64)
1271 case POWERPC_MMU_620:
1272 case POWERPC_MMU_64B:
1273 /* Real address are 60 bits long */
1274 ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
1275 ctx->prot |= PAGE_WRITE;
1276 break;
1277 #endif
1278 case POWERPC_MMU_SOFT_4xx_Z:
1279 if (unlikely(msr_pe != 0)) {
1280 /* 403 family add some particular protections,
1281 * using PBL/PBU registers for accesses with no translation.
1282 */
1283 in_plb =
1284 /* Check PLB validity */
1285 (env->pb[0] < env->pb[1] &&
1286 /* and address in plb area */
1287 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1288 (env->pb[2] < env->pb[3] &&
1289 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1290 if (in_plb ^ msr_px) {
1291 /* Access in protected area */
1292 if (rw == 1) {
1293 /* Access is not allowed */
1294 ret = -2;
1295 }
1296 } else {
1297 /* Read-write access is allowed */
1298 ctx->prot |= PAGE_WRITE;
1299 }
1300 }
1301 break;
1302 case POWERPC_MMU_MPC8xx:
1303 /* XXX: TODO */
1304 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1305 break;
1306 case POWERPC_MMU_BOOKE_FSL:
1307 /* XXX: TODO */
1308 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1309 break;
1310 default:
1311 cpu_abort(env, "Unknown or invalid MMU model\n");
1312 return -1;
1313 }
1314
1315 return ret;
1316 }
1317
1318 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1319 int rw, int access_type)
1320 {
1321 int ret;
1322
1323 #if 0
1324 qemu_log("%s\n", __func__);
1325 #endif
1326 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1327 (access_type != ACCESS_CODE && msr_dr == 0)) {
1328 /* No address translation */
1329 ret = check_physical(env, ctx, eaddr, rw);
1330 } else {
1331 ret = -1;
1332 switch (env->mmu_model) {
1333 case POWERPC_MMU_32B:
1334 case POWERPC_MMU_601:
1335 case POWERPC_MMU_SOFT_6xx:
1336 case POWERPC_MMU_SOFT_74xx:
1337 /* Try to find a BAT */
1338 if (env->nb_BATs != 0)
1339 ret = get_bat(env, ctx, eaddr, rw, access_type);
1340 #if defined(TARGET_PPC64)
1341 case POWERPC_MMU_620:
1342 case POWERPC_MMU_64B:
1343 #endif
1344 if (ret < 0) {
1345 /* We didn't match any BAT entry or don't have BATs */
1346 ret = get_segment(env, ctx, eaddr, rw, access_type);
1347 }
1348 break;
1349 case POWERPC_MMU_SOFT_4xx:
1350 case POWERPC_MMU_SOFT_4xx_Z:
1351 ret = mmu40x_get_physical_address(env, ctx, eaddr,
1352 rw, access_type);
1353 break;
1354 case POWERPC_MMU_BOOKE:
1355 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1356 rw, access_type);
1357 break;
1358 case POWERPC_MMU_MPC8xx:
1359 /* XXX: TODO */
1360 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1361 break;
1362 case POWERPC_MMU_BOOKE_FSL:
1363 /* XXX: TODO */
1364 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1365 return -1;
1366 case POWERPC_MMU_REAL:
1367 cpu_abort(env, "PowerPC in real mode do not do any translation\n");
1368 return -1;
1369 default:
1370 cpu_abort(env, "Unknown or invalid MMU model\n");
1371 return -1;
1372 }
1373 }
1374 #if 0
1375 qemu_log("%s address " TARGET_FMT_lx " => %d " TARGET_FMT_plx "\n",
1376 __func__, eaddr, ret, ctx->raddr);
1377 #endif
1378
1379 return ret;
1380 }
1381
1382 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
1383 {
1384 mmu_ctx_t ctx;
1385
1386 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0))
1387 return -1;
1388
1389 return ctx.raddr & TARGET_PAGE_MASK;
1390 }
1391
1392 /* Perform address translation */
1393 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1394 int mmu_idx, int is_softmmu)
1395 {
1396 mmu_ctx_t ctx;
1397 int access_type;
1398 int ret = 0;
1399
1400 if (rw == 2) {
1401 /* code access */
1402 rw = 0;
1403 access_type = ACCESS_CODE;
1404 } else {
1405 /* data access */
1406 access_type = env->access_type;
1407 }
1408 ret = get_physical_address(env, &ctx, address, rw, access_type);
1409 if (ret == 0) {
1410 tlb_set_page(env, address & TARGET_PAGE_MASK,
1411 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1412 mmu_idx, TARGET_PAGE_SIZE);
1413 ret = 0;
1414 } else if (ret < 0) {
1415 LOG_MMU_STATE(env);
1416 if (access_type == ACCESS_CODE) {
1417 switch (ret) {
1418 case -1:
1419 /* No matches in page tables or TLB */
1420 switch (env->mmu_model) {
1421 case POWERPC_MMU_SOFT_6xx:
1422 env->exception_index = POWERPC_EXCP_IFTLB;
1423 env->error_code = 1 << 18;
1424 env->spr[SPR_IMISS] = address;
1425 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
1426 goto tlb_miss;
1427 case POWERPC_MMU_SOFT_74xx:
1428 env->exception_index = POWERPC_EXCP_IFTLB;
1429 goto tlb_miss_74xx;
1430 case POWERPC_MMU_SOFT_4xx:
1431 case POWERPC_MMU_SOFT_4xx_Z:
1432 env->exception_index = POWERPC_EXCP_ITLB;
1433 env->error_code = 0;
1434 env->spr[SPR_40x_DEAR] = address;
1435 env->spr[SPR_40x_ESR] = 0x00000000;
1436 break;
1437 case POWERPC_MMU_32B:
1438 case POWERPC_MMU_601:
1439 #if defined(TARGET_PPC64)
1440 case POWERPC_MMU_620:
1441 case POWERPC_MMU_64B:
1442 #endif
1443 env->exception_index = POWERPC_EXCP_ISI;
1444 env->error_code = 0x40000000;
1445 break;
1446 case POWERPC_MMU_BOOKE:
1447 /* XXX: TODO */
1448 cpu_abort(env, "BookE MMU model is not implemented\n");
1449 return -1;
1450 case POWERPC_MMU_BOOKE_FSL:
1451 /* XXX: TODO */
1452 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1453 return -1;
1454 case POWERPC_MMU_MPC8xx:
1455 /* XXX: TODO */
1456 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1457 break;
1458 case POWERPC_MMU_REAL:
1459 cpu_abort(env, "PowerPC in real mode should never raise "
1460 "any MMU exceptions\n");
1461 return -1;
1462 default:
1463 cpu_abort(env, "Unknown or invalid MMU model\n");
1464 return -1;
1465 }
1466 break;
1467 case -2:
1468 /* Access rights violation */
1469 env->exception_index = POWERPC_EXCP_ISI;
1470 env->error_code = 0x08000000;
1471 break;
1472 case -3:
1473 /* No execute protection violation */
1474 env->exception_index = POWERPC_EXCP_ISI;
1475 env->error_code = 0x10000000;
1476 break;
1477 case -4:
1478 /* Direct store exception */
1479 /* No code fetch is allowed in direct-store areas */
1480 env->exception_index = POWERPC_EXCP_ISI;
1481 env->error_code = 0x10000000;
1482 break;
1483 #if defined(TARGET_PPC64)
1484 case -5:
1485 /* No match in segment table */
1486 if (env->mmu_model == POWERPC_MMU_620) {
1487 env->exception_index = POWERPC_EXCP_ISI;
1488 /* XXX: this might be incorrect */
1489 env->error_code = 0x40000000;
1490 } else {
1491 env->exception_index = POWERPC_EXCP_ISEG;
1492 env->error_code = 0;
1493 }
1494 break;
1495 #endif
1496 }
1497 } else {
1498 switch (ret) {
1499 case -1:
1500 /* No matches in page tables or TLB */
1501 switch (env->mmu_model) {
1502 case POWERPC_MMU_SOFT_6xx:
1503 if (rw == 1) {
1504 env->exception_index = POWERPC_EXCP_DSTLB;
1505 env->error_code = 1 << 16;
1506 } else {
1507 env->exception_index = POWERPC_EXCP_DLTLB;
1508 env->error_code = 0;
1509 }
1510 env->spr[SPR_DMISS] = address;
1511 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1512 tlb_miss:
1513 env->error_code |= ctx.key << 19;
1514 env->spr[SPR_HASH1] = ctx.pg_addr[0];
1515 env->spr[SPR_HASH2] = ctx.pg_addr[1];
1516 break;
1517 case POWERPC_MMU_SOFT_74xx:
1518 if (rw == 1) {
1519 env->exception_index = POWERPC_EXCP_DSTLB;
1520 } else {
1521 env->exception_index = POWERPC_EXCP_DLTLB;
1522 }
1523 tlb_miss_74xx:
1524 /* Implement LRU algorithm */
1525 env->error_code = ctx.key << 19;
1526 env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
1527 ((env->last_way + 1) & (env->nb_ways - 1));
1528 env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
1529 break;
1530 case POWERPC_MMU_SOFT_4xx:
1531 case POWERPC_MMU_SOFT_4xx_Z:
1532 env->exception_index = POWERPC_EXCP_DTLB;
1533 env->error_code = 0;
1534 env->spr[SPR_40x_DEAR] = address;
1535 if (rw)
1536 env->spr[SPR_40x_ESR] = 0x00800000;
1537 else
1538 env->spr[SPR_40x_ESR] = 0x00000000;
1539 break;
1540 case POWERPC_MMU_32B:
1541 case POWERPC_MMU_601:
1542 #if defined(TARGET_PPC64)
1543 case POWERPC_MMU_620:
1544 case POWERPC_MMU_64B:
1545 #endif
1546 env->exception_index = POWERPC_EXCP_DSI;
1547 env->error_code = 0;
1548 env->spr[SPR_DAR] = address;
1549 if (rw == 1)
1550 env->spr[SPR_DSISR] = 0x42000000;
1551 else
1552 env->spr[SPR_DSISR] = 0x40000000;
1553 break;
1554 case POWERPC_MMU_MPC8xx:
1555 /* XXX: TODO */
1556 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1557 break;
1558 case POWERPC_MMU_BOOKE:
1559 /* XXX: TODO */
1560 cpu_abort(env, "BookE MMU model is not implemented\n");
1561 return -1;
1562 case POWERPC_MMU_BOOKE_FSL:
1563 /* XXX: TODO */
1564 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1565 return -1;
1566 case POWERPC_MMU_REAL:
1567 cpu_abort(env, "PowerPC in real mode should never raise "
1568 "any MMU exceptions\n");
1569 return -1;
1570 default:
1571 cpu_abort(env, "Unknown or invalid MMU model\n");
1572 return -1;
1573 }
1574 break;
1575 case -2:
1576 /* Access rights violation */
1577 env->exception_index = POWERPC_EXCP_DSI;
1578 env->error_code = 0;
1579 if (env->mmu_model == POWERPC_MMU_SOFT_4xx
1580 || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) {
1581 env->spr[SPR_40x_DEAR] = address;
1582 if (rw) {
1583 env->spr[SPR_40x_ESR] |= 0x00800000;
1584 }
1585 } else {
1586 env->spr[SPR_DAR] = address;
1587 if (rw == 1) {
1588 env->spr[SPR_DSISR] = 0x0A000000;
1589 } else {
1590 env->spr[SPR_DSISR] = 0x08000000;
1591 }
1592 }
1593 break;
1594 case -4:
1595 /* Direct store exception */
1596 switch (access_type) {
1597 case ACCESS_FLOAT:
1598 /* Floating point load/store */
1599 env->exception_index = POWERPC_EXCP_ALIGN;
1600 env->error_code = POWERPC_EXCP_ALIGN_FP;
1601 env->spr[SPR_DAR] = address;
1602 break;
1603 case ACCESS_RES:
1604 /* lwarx, ldarx or stwcx. */
1605 env->exception_index = POWERPC_EXCP_DSI;
1606 env->error_code = 0;
1607 env->spr[SPR_DAR] = address;
1608 if (rw == 1)
1609 env->spr[SPR_DSISR] = 0x06000000;
1610 else
1611 env->spr[SPR_DSISR] = 0x04000000;
1612 break;
1613 case ACCESS_EXT:
1614 /* eciwx or ecowx */
1615 env->exception_index = POWERPC_EXCP_DSI;
1616 env->error_code = 0;
1617 env->spr[SPR_DAR] = address;
1618 if (rw == 1)
1619 env->spr[SPR_DSISR] = 0x06100000;
1620 else
1621 env->spr[SPR_DSISR] = 0x04100000;
1622 break;
1623 default:
1624 printf("DSI: invalid exception (%d)\n", ret);
1625 env->exception_index = POWERPC_EXCP_PROGRAM;
1626 env->error_code =
1627 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1628 env->spr[SPR_DAR] = address;
1629 break;
1630 }
1631 break;
1632 #if defined(TARGET_PPC64)
1633 case -5:
1634 /* No match in segment table */
1635 if (env->mmu_model == POWERPC_MMU_620) {
1636 env->exception_index = POWERPC_EXCP_DSI;
1637 env->error_code = 0;
1638 env->spr[SPR_DAR] = address;
1639 /* XXX: this might be incorrect */
1640 if (rw == 1)
1641 env->spr[SPR_DSISR] = 0x42000000;
1642 else
1643 env->spr[SPR_DSISR] = 0x40000000;
1644 } else {
1645 env->exception_index = POWERPC_EXCP_DSEG;
1646 env->error_code = 0;
1647 env->spr[SPR_DAR] = address;
1648 }
1649 break;
1650 #endif
1651 }
1652 }
1653 #if 0
1654 printf("%s: set exception to %d %02x\n", __func__,
1655 env->exception, env->error_code);
1656 #endif
1657 ret = 1;
1658 }
1659
1660 return ret;
1661 }
1662
1663 /*****************************************************************************/
1664 /* BATs management */
1665 #if !defined(FLUSH_ALL_TLBS)
1666 static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
1667 target_ulong mask)
1668 {
1669 target_ulong base, end, page;
1670
1671 base = BATu & ~0x0001FFFF;
1672 end = base + mask + 0x00020000;
1673 LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " ("
1674 TARGET_FMT_lx ")\n", base, end, mask);
1675 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1676 tlb_flush_page(env, page);
1677 LOG_BATS("Flush done\n");
1678 }
1679 #endif
1680
1681 static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr,
1682 target_ulong value)
1683 {
1684 LOG_BATS("Set %cBAT%d%c to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", ID,
1685 nr, ul == 0 ? 'u' : 'l', value, env->nip);
1686 }
1687
1688 void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1689 {
1690 target_ulong mask;
1691
1692 dump_store_bat(env, 'I', 0, nr, value);
1693 if (env->IBAT[0][nr] != value) {
1694 mask = (value << 15) & 0x0FFE0000UL;
1695 #if !defined(FLUSH_ALL_TLBS)
1696 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1697 #endif
1698 /* When storing valid upper BAT, mask BEPI and BRPN
1699 * and invalidate all TLBs covered by this BAT
1700 */
1701 mask = (value << 15) & 0x0FFE0000UL;
1702 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1703 (value & ~0x0001FFFFUL & ~mask);
1704 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1705 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1706 #if !defined(FLUSH_ALL_TLBS)
1707 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1708 #else
1709 tlb_flush(env, 1);
1710 #endif
1711 }
1712 }
1713
1714 void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1715 {
1716 dump_store_bat(env, 'I', 1, nr, value);
1717 env->IBAT[1][nr] = value;
1718 }
1719
1720 void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1721 {
1722 target_ulong mask;
1723
1724 dump_store_bat(env, 'D', 0, nr, value);
1725 if (env->DBAT[0][nr] != value) {
1726 /* When storing valid upper BAT, mask BEPI and BRPN
1727 * and invalidate all TLBs covered by this BAT
1728 */
1729 mask = (value << 15) & 0x0FFE0000UL;
1730 #if !defined(FLUSH_ALL_TLBS)
1731 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1732 #endif
1733 mask = (value << 15) & 0x0FFE0000UL;
1734 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1735 (value & ~0x0001FFFFUL & ~mask);
1736 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1737 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1738 #if !defined(FLUSH_ALL_TLBS)
1739 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1740 #else
1741 tlb_flush(env, 1);
1742 #endif
1743 }
1744 }
1745
1746 void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1747 {
1748 dump_store_bat(env, 'D', 1, nr, value);
1749 env->DBAT[1][nr] = value;
1750 }
1751
1752 void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value)
1753 {
1754 target_ulong mask;
1755 #if defined(FLUSH_ALL_TLBS)
1756 int do_inval;
1757 #endif
1758
1759 dump_store_bat(env, 'I', 0, nr, value);
1760 if (env->IBAT[0][nr] != value) {
1761 #if defined(FLUSH_ALL_TLBS)
1762 do_inval = 0;
1763 #endif
1764 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1765 if (env->IBAT[1][nr] & 0x40) {
1766 /* Invalidate BAT only if it is valid */
1767 #if !defined(FLUSH_ALL_TLBS)
1768 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1769 #else
1770 do_inval = 1;
1771 #endif
1772 }
1773 /* When storing valid upper BAT, mask BEPI and BRPN
1774 * and invalidate all TLBs covered by this BAT
1775 */
1776 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1777 (value & ~0x0001FFFFUL & ~mask);
1778 env->DBAT[0][nr] = env->IBAT[0][nr];
1779 if (env->IBAT[1][nr] & 0x40) {
1780 #if !defined(FLUSH_ALL_TLBS)
1781 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1782 #else
1783 do_inval = 1;
1784 #endif
1785 }
1786 #if defined(FLUSH_ALL_TLBS)
1787 if (do_inval)
1788 tlb_flush(env, 1);
1789 #endif
1790 }
1791 }
1792
1793 void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value)
1794 {
1795 target_ulong mask;
1796 #if defined(FLUSH_ALL_TLBS)
1797 int do_inval;
1798 #endif
1799
1800 dump_store_bat(env, 'I', 1, nr, value);
1801 if (env->IBAT[1][nr] != value) {
1802 #if defined(FLUSH_ALL_TLBS)
1803 do_inval = 0;
1804 #endif
1805 if (env->IBAT[1][nr] & 0x40) {
1806 #if !defined(FLUSH_ALL_TLBS)
1807 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1808 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1809 #else
1810 do_inval = 1;
1811 #endif
1812 }
1813 if (value & 0x40) {
1814 #if !defined(FLUSH_ALL_TLBS)
1815 mask = (value << 17) & 0x0FFE0000UL;
1816 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1817 #else
1818 do_inval = 1;
1819 #endif
1820 }
1821 env->IBAT[1][nr] = value;
1822 env->DBAT[1][nr] = value;
1823 #if defined(FLUSH_ALL_TLBS)
1824 if (do_inval)
1825 tlb_flush(env, 1);
1826 #endif
1827 }
1828 }
1829
1830 /*****************************************************************************/
1831 /* TLB management */
1832 void ppc_tlb_invalidate_all (CPUPPCState *env)
1833 {
1834 switch (env->mmu_model) {
1835 case POWERPC_MMU_SOFT_6xx:
1836 case POWERPC_MMU_SOFT_74xx:
1837 ppc6xx_tlb_invalidate_all(env);
1838 break;
1839 case POWERPC_MMU_SOFT_4xx:
1840 case POWERPC_MMU_SOFT_4xx_Z:
1841 ppc4xx_tlb_invalidate_all(env);
1842 break;
1843 case POWERPC_MMU_REAL:
1844 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1845 break;
1846 case POWERPC_MMU_MPC8xx:
1847 /* XXX: TODO */
1848 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1849 break;
1850 case POWERPC_MMU_BOOKE:
1851 /* XXX: TODO */
1852 cpu_abort(env, "BookE MMU model is not implemented\n");
1853 break;
1854 case POWERPC_MMU_BOOKE_FSL:
1855 /* XXX: TODO */
1856 if (!kvm_enabled())
1857 cpu_abort(env, "BookE MMU model is not implemented\n");
1858 break;
1859 case POWERPC_MMU_32B:
1860 case POWERPC_MMU_601:
1861 #if defined(TARGET_PPC64)
1862 case POWERPC_MMU_620:
1863 case POWERPC_MMU_64B:
1864 #endif /* defined(TARGET_PPC64) */
1865 tlb_flush(env, 1);
1866 break;
1867 default:
1868 /* XXX: TODO */
1869 cpu_abort(env, "Unknown MMU model\n");
1870 break;
1871 }
1872 }
1873
1874 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
1875 {
1876 #if !defined(FLUSH_ALL_TLBS)
1877 addr &= TARGET_PAGE_MASK;
1878 switch (env->mmu_model) {
1879 case POWERPC_MMU_SOFT_6xx:
1880 case POWERPC_MMU_SOFT_74xx:
1881 ppc6xx_tlb_invalidate_virt(env, addr, 0);
1882 if (env->id_tlbs == 1)
1883 ppc6xx_tlb_invalidate_virt(env, addr, 1);
1884 break;
1885 case POWERPC_MMU_SOFT_4xx:
1886 case POWERPC_MMU_SOFT_4xx_Z:
1887 ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1888 break;
1889 case POWERPC_MMU_REAL:
1890 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1891 break;
1892 case POWERPC_MMU_MPC8xx:
1893 /* XXX: TODO */
1894 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1895 break;
1896 case POWERPC_MMU_BOOKE:
1897 /* XXX: TODO */
1898 cpu_abort(env, "BookE MMU model is not implemented\n");
1899 break;
1900 case POWERPC_MMU_BOOKE_FSL:
1901 /* XXX: TODO */
1902 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1903 break;
1904 case POWERPC_MMU_32B:
1905 case POWERPC_MMU_601:
1906 /* tlbie invalidate TLBs for all segments */
1907 addr &= ~((target_ulong)-1ULL << 28);
1908 /* XXX: this case should be optimized,
1909 * giving a mask to tlb_flush_page
1910 */
1911 tlb_flush_page(env, addr | (0x0 << 28));
1912 tlb_flush_page(env, addr | (0x1 << 28));
1913 tlb_flush_page(env, addr | (0x2 << 28));
1914 tlb_flush_page(env, addr | (0x3 << 28));
1915 tlb_flush_page(env, addr | (0x4 << 28));
1916 tlb_flush_page(env, addr | (0x5 << 28));
1917 tlb_flush_page(env, addr | (0x6 << 28));
1918 tlb_flush_page(env, addr | (0x7 << 28));
1919 tlb_flush_page(env, addr | (0x8 << 28));
1920 tlb_flush_page(env, addr | (0x9 << 28));
1921 tlb_flush_page(env, addr | (0xA << 28));
1922 tlb_flush_page(env, addr | (0xB << 28));
1923 tlb_flush_page(env, addr | (0xC << 28));
1924 tlb_flush_page(env, addr | (0xD << 28));
1925 tlb_flush_page(env, addr | (0xE << 28));
1926 tlb_flush_page(env, addr | (0xF << 28));
1927 break;
1928 #if defined(TARGET_PPC64)
1929 case POWERPC_MMU_620:
1930 case POWERPC_MMU_64B:
1931 /* tlbie invalidate TLBs for all segments */
1932 /* XXX: given the fact that there are too many segments to invalidate,
1933 * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
1934 * we just invalidate all TLBs
1935 */
1936 tlb_flush(env, 1);
1937 break;
1938 #endif /* defined(TARGET_PPC64) */
1939 default:
1940 /* XXX: TODO */
1941 cpu_abort(env, "Unknown MMU model\n");
1942 break;
1943 }
1944 #else
1945 ppc_tlb_invalidate_all(env);
1946 #endif
1947 }
1948
1949 /*****************************************************************************/
1950 /* Special registers manipulation */
1951 #if defined(TARGET_PPC64)
1952 void ppc_store_asr (CPUPPCState *env, target_ulong value)
1953 {
1954 if (env->asr != value) {
1955 env->asr = value;
1956 tlb_flush(env, 1);
1957 }
1958 }
1959 #endif
1960
1961 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
1962 {
1963 LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value);
1964 if (env->sdr1 != value) {
1965 /* XXX: for PowerPC 64, should check that the HTABSIZE value
1966 * is <= 28
1967 */
1968 env->sdr1 = value;
1969 tlb_flush(env, 1);
1970 }
1971 }
1972
1973 #if defined(TARGET_PPC64)
1974 target_ulong ppc_load_sr (CPUPPCState *env, int slb_nr)
1975 {
1976 // XXX
1977 return 0;
1978 }
1979 #endif
1980
1981 void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1982 {
1983 LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
1984 srnum, value, env->sr[srnum]);
1985 #if defined(TARGET_PPC64)
1986 if (env->mmu_model & POWERPC_MMU_64) {
1987 uint64_t rb = 0, rs = 0;
1988
1989 /* ESID = srnum */
1990 rb |= ((uint32_t)srnum & 0xf) << 28;
1991 /* Set the valid bit */
1992 rb |= 1 << 27;
1993 /* Index = ESID */
1994 rb |= (uint32_t)srnum;
1995
1996 /* VSID = VSID */
1997 rs |= (value & 0xfffffff) << 12;
1998 /* flags = flags */
1999 rs |= ((value >> 27) & 0xf) << 9;
2000
2001 ppc_store_slb(env, rb, rs);
2002 } else
2003 #endif
2004 if (env->sr[srnum] != value) {
2005 env->sr[srnum] = value;
2006 /* Invalidating 256MB of virtual memory in 4kB pages is way longer than
2007 flusing the whole TLB. */
2008 #if !defined(FLUSH_ALL_TLBS) && 0
2009 {
2010 target_ulong page, end;
2011 /* Invalidate 256 MB of virtual memory */
2012 page = (16 << 20) * srnum;
2013 end = page + (16 << 20);
2014 for (; page != end; page += TARGET_PAGE_SIZE)
2015 tlb_flush_page(env, page);
2016 }
2017 #else
2018 tlb_flush(env, 1);
2019 #endif
2020 }
2021 }
2022 #endif /* !defined (CONFIG_USER_ONLY) */
2023
2024 /* GDBstub can read and write MSR... */
2025 void ppc_store_msr (CPUPPCState *env, target_ulong value)
2026 {
2027 hreg_store_msr(env, value, 0);
2028 }
2029
2030 /*****************************************************************************/
2031 /* Exception processing */
2032 #if defined (CONFIG_USER_ONLY)
2033 void do_interrupt (CPUState *env)
2034 {
2035 env->exception_index = POWERPC_EXCP_NONE;
2036 env->error_code = 0;
2037 }
2038
2039 void ppc_hw_interrupt (CPUState *env)
2040 {
2041 env->exception_index = POWERPC_EXCP_NONE;
2042 env->error_code = 0;
2043 }
2044 #else /* defined (CONFIG_USER_ONLY) */
2045 static inline void dump_syscall(CPUState *env)
2046 {
2047 qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
2048 " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
2049 " nip=" TARGET_FMT_lx "\n",
2050 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
2051 ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
2052 ppc_dump_gpr(env, 6), env->nip);
2053 }
2054
2055 /* Note that this function should be greatly optimized
2056 * when called with a constant excp, from ppc_hw_interrupt
2057 */
2058 static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
2059 {
2060 target_ulong msr, new_msr, vector;
2061 int srr0, srr1, asrr0, asrr1;
2062 int lpes0, lpes1, lev;
2063
2064 if (0) {
2065 /* XXX: find a suitable condition to enable the hypervisor mode */
2066 lpes0 = (env->spr[SPR_LPCR] >> 1) & 1;
2067 lpes1 = (env->spr[SPR_LPCR] >> 2) & 1;
2068 } else {
2069 /* Those values ensure we won't enter the hypervisor mode */
2070 lpes0 = 0;
2071 lpes1 = 1;
2072 }
2073
2074 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
2075 " => %08x (%02x)\n", env->nip, excp, env->error_code);
2076
2077 /* new srr1 value excluding must-be-zero bits */
2078 msr = env->msr & ~0x783f0000ULL;
2079
2080 /* new interrupt handler msr */
2081 new_msr = env->msr & ((target_ulong)1 << MSR_ME);
2082
2083 /* target registers */
2084 srr0 = SPR_SRR0;
2085 srr1 = SPR_SRR1;
2086 asrr0 = -1;
2087 asrr1 = -1;
2088
2089 switch (excp) {
2090 case POWERPC_EXCP_NONE:
2091 /* Should never happen */
2092 return;
2093 case POWERPC_EXCP_CRITICAL: /* Critical input */
2094 switch (excp_model) {
2095 case POWERPC_EXCP_40x:
2096 srr0 = SPR_40x_SRR2;
2097 srr1 = SPR_40x_SRR3;
2098 break;
2099 case POWERPC_EXCP_BOOKE:
2100 srr0 = SPR_BOOKE_CSRR0;
2101 srr1 = SPR_BOOKE_CSRR1;
2102 break;
2103 case POWERPC_EXCP_G2:
2104 break;
2105 default:
2106 goto excp_invalid;
2107 }
2108 goto store_next;
2109 case POWERPC_EXCP_MCHECK: /* Machine check exception */
2110 if (msr_me == 0) {
2111 /* Machine check exception is not enabled.
2112 * Enter checkstop state.
2113 */
2114 if (qemu_log_enabled()) {
2115 qemu_log("Machine check while not allowed. "
2116 "Entering checkstop state\n");
2117 } else {
2118 fprintf(stderr, "Machine check while not allowed. "
2119 "Entering checkstop state\n");
2120 }
2121 env->halted = 1;
2122 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
2123 }
2124 if (0) {
2125 /* XXX: find a suitable condition to enable the hypervisor mode */
2126 new_msr |= (target_ulong)MSR_HVB;
2127 }
2128
2129 /* machine check exceptions don't have ME set */
2130 new_msr &= ~((target_ulong)1 << MSR_ME);
2131
2132 /* XXX: should also have something loaded in DAR / DSISR */
2133 switch (excp_model) {
2134 case POWERPC_EXCP_40x:
2135 srr0 = SPR_40x_SRR2;
2136 srr1 = SPR_40x_SRR3;
2137 break;
2138 case POWERPC_EXCP_BOOKE:
2139 srr0 = SPR_BOOKE_MCSRR0;
2140 srr1 = SPR_BOOKE_MCSRR1;
2141 asrr0 = SPR_BOOKE_CSRR0;
2142 asrr1 = SPR_BOOKE_CSRR1;
2143 break;
2144 default:
2145 break;
2146 }
2147 goto store_next;
2148 case POWERPC_EXCP_DSI: /* Data storage exception */
2149 LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
2150 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
2151 if (lpes1 == 0)
2152 new_msr |= (target_ulong)MSR_HVB;
2153 goto store_next;
2154 case POWERPC_EXCP_ISI: /* Instruction storage exception */
2155 LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
2156 "\n", msr, env->nip);
2157 if (lpes1 == 0)
2158 new_msr |= (target_ulong)MSR_HVB;
2159 msr |= env->error_code;
2160 goto store_next;
2161 case POWERPC_EXCP_EXTERNAL: /* External input */
2162 if (lpes0 == 1)
2163 new_msr |= (target_ulong)MSR_HVB;
2164 goto store_next;
2165 case POWERPC_EXCP_ALIGN: /* Alignment exception */
2166 if (lpes1 == 0)
2167 new_msr |= (target_ulong)MSR_HVB;
2168 /* XXX: this is false */
2169 /* Get rS/rD and rA from faulting opcode */
2170 env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
2171 goto store_current;
2172 case POWERPC_EXCP_PROGRAM: /* Program exception */
2173 switch (env->error_code & ~0xF) {
2174 case POWERPC_EXCP_FP:
2175 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
2176 LOG_EXCP("Ignore floating point exception\n");
2177 env->exception_index = POWERPC_EXCP_NONE;
2178 env->error_code = 0;
2179 return;
2180 }
2181 if (lpes1 == 0)
2182 new_msr |= (target_ulong)MSR_HVB;
2183 msr |= 0x00100000;
2184 if (msr_fe0 == msr_fe1)
2185 goto store_next;
2186 msr |= 0x00010000;
2187 break;
2188 case POWERPC_EXCP_INVAL:
2189 LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
2190 if (lpes1 == 0)
2191 new_msr |= (target_ulong)MSR_HVB;
2192 msr |= 0x00080000;
2193 break;
2194 case POWERPC_EXCP_PRIV:
2195 if (lpes1 == 0)
2196 new_msr |= (target_ulong)MSR_HVB;
2197 msr |= 0x00040000;
2198 break;
2199 case POWERPC_EXCP_TRAP:
2200 if (lpes1 == 0)
2201 new_msr |= (target_ulong)MSR_HVB;
2202 msr |= 0x00020000;
2203 break;
2204 default:
2205 /* Should never occur */
2206 cpu_abort(env, "Invalid program exception %d. Aborting\n",
2207 env->error_code);
2208 break;
2209 }
2210 goto store_current;
2211 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
2212 if (lpes1 == 0)
2213 new_msr |= (target_ulong)MSR_HVB;
2214 goto store_current;
2215 case POWERPC_EXCP_SYSCALL: /* System call exception */
2216 /* NOTE: this is a temporary hack to support graphics OSI
2217 calls from the MOL driver */
2218 /* XXX: To be removed */
2219 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
2220 env->osi_call) {
2221 if (env->osi_call(env) != 0) {
2222 env->exception_index = POWERPC_EXCP_NONE;
2223 env->error_code = 0;
2224 return;
2225 }
2226 }
2227 dump_syscall(env);
2228 lev = env->error_code;
2229 if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
2230 new_msr |= (target_ulong)MSR_HVB;
2231 goto store_next;
2232 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
2233 goto store_current;
2234 case POWERPC_EXCP_DECR: /* Decrementer exception */
2235 if (lpes1 == 0)
2236 new_msr |= (target_ulong)MSR_HVB;
2237 goto store_next;
2238 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
2239 /* FIT on 4xx */
2240 LOG_EXCP("FIT exception\n");
2241 goto store_next;
2242 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
2243 LOG_EXCP("WDT exception\n");
2244 switch (excp_model) {
2245 case POWERPC_EXCP_BOOKE:
2246 srr0 = SPR_BOOKE_CSRR0;
2247 srr1 = SPR_BOOKE_CSRR1;
2248 break;
2249 default:
2250 break;
2251 }
2252 goto store_next;
2253 case POWERPC_EXCP_DTLB: /* Data TLB error */
2254 goto store_next;
2255 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
2256 goto store_next;
2257 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
2258 switch (excp_model) {
2259 case POWERPC_EXCP_BOOKE:
2260 srr0 = SPR_BOOKE_DSRR0;
2261 srr1 = SPR_BOOKE_DSRR1;
2262 asrr0 = SPR_BOOKE_CSRR0;
2263 asrr1 = SPR_BOOKE_CSRR1;
2264 break;
2265 default:
2266 break;
2267 }
2268 /* XXX: TODO */
2269 cpu_abort(env, "Debug exception is not implemented yet !\n");
2270 goto store_next;
2271 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
2272 goto store_current;
2273 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
2274 /* XXX: TODO */
2275 cpu_abort(env, "Embedded floating point data exception "
2276 "is not implemented yet !\n");
2277 goto store_next;
2278 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
2279 /* XXX: TODO */
2280 cpu_abort(env, "Embedded floating point round exception "
2281 "is not implemented yet !\n");
2282 goto store_next;
2283 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
2284 /* XXX: TODO */
2285 cpu_abort(env,
2286 "Performance counter exception is not implemented yet !\n");
2287 goto store_next;
2288 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
2289 /* XXX: TODO */
2290 cpu_abort(env,
2291 "Embedded doorbell interrupt is not implemented yet !\n");
2292 goto store_next;
2293 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
2294 switch (excp_model) {
2295 case POWERPC_EXCP_BOOKE:
2296 srr0 = SPR_BOOKE_CSRR0;
2297 srr1 = SPR_BOOKE_CSRR1;
2298 break;
2299 default:
2300 break;
2301 }
2302 /* XXX: TODO */
2303 cpu_abort(env, "Embedded doorbell critical interrupt "
2304 "is not implemented yet !\n");
2305 goto store_next;
2306 case POWERPC_EXCP_RESET: /* System reset exception */
2307 if (msr_pow) {
2308 /* indicate that we resumed from power save mode */
2309 msr |= 0x10000;
2310 } else {
2311 new_msr &= ~((target_ulong)1 << MSR_ME);
2312 }
2313
2314 if (0) {
2315 /* XXX: find a suitable condition to enable the hypervisor mode */
2316 new_msr |= (target_ulong)MSR_HVB;
2317 }
2318 goto store_next;
2319 case POWERPC_EXCP_DSEG: /* Data segment exception */
2320 if (lpes1 == 0)
2321 new_msr |= (target_ulong)MSR_HVB;
2322 goto store_next;
2323 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
2324 if (lpes1 == 0)
2325 new_msr |= (target_ulong)MSR_HVB;
2326 goto store_next;
2327 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
2328 srr0 = SPR_HSRR0;
2329 srr1 = SPR_HSRR1;
2330 new_msr |= (target_ulong)MSR_HVB;
2331 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
2332 goto store_next;
2333 case POWERPC_EXCP_TRACE: /* Trace exception */
2334 if (lpes1 == 0)
2335 new_msr |= (target_ulong)MSR_HVB;
2336 goto store_next;
2337 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
2338 srr0 = SPR_HSRR0;
2339 srr1 = SPR_HSRR1;
2340 new_msr |= (target_ulong)MSR_HVB;
2341 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
2342 goto store_next;
2343 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
2344 srr0 = SPR_HSRR0;
2345 srr1 = SPR_HSRR1;
2346 new_msr |= (target_ulong)MSR_HVB;
2347 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
2348 goto store_next;
2349 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
2350 srr0 = SPR_HSRR0;
2351 srr1 = SPR_HSRR1;
2352 new_msr |= (target_ulong)MSR_HVB;
2353 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
2354 goto store_next;
2355 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
2356 srr0 = SPR_HSRR0;
2357 srr1 = SPR_HSRR1;
2358 new_msr |= (target_ulong)MSR_HVB;
2359 new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
2360 goto store_next;
2361 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
2362 if (lpes1 == 0)
2363 new_msr |= (target_ulong)MSR_HVB;
2364 goto store_current;
2365 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
2366 LOG_EXCP("PIT exception\n");
2367 goto store_next;
2368 case POWERPC_EXCP_IO: /* IO error exception */
2369 /* XXX: TODO */
2370 cpu_abort(env, "601 IO error exception is not implemented yet !\n");
2371 goto store_next;
2372 case POWERPC_EXCP_RUNM: /* Run mode exception */
2373 /* XXX: TODO */
2374 cpu_abort(env, "601 run mode exception is not implemented yet !\n");
2375 goto store_next;
2376 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
2377 /* XXX: TODO */
2378 cpu_abort(env, "602 emulation trap exception "
2379 "is not implemented yet !\n");
2380 goto store_next;
2381 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
2382 if (lpes1 == 0) /* XXX: check this */
2383 new_msr |= (target_ulong)MSR_HVB;
2384 switch (excp_model) {
2385 case POWERPC_EXCP_602:
2386 case POWERPC_EXCP_603:
2387 case POWERPC_EXCP_603E:
2388 case POWERPC_EXCP_G2:
2389 goto tlb_miss_tgpr;
2390 case POWERPC_EXCP_7x5:
2391 goto tlb_miss;
2392 case POWERPC_EXCP_74xx:
2393 goto tlb_miss_74xx;
2394 default:
2395 cpu_abort(env, "Invalid instruction TLB miss exception\n");
2396 break;
2397 }
2398 break;
2399 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
2400 if (lpes1 == 0) /* XXX: check this */
2401 new_msr |= (target_ulong)MSR_HVB;
2402 switch (excp_model) {
2403 case POWERPC_EXCP_602:
2404 case POWERPC_EXCP_603:
2405 case POWERPC_EXCP_603E:
2406 case POWERPC_EXCP_G2:
2407 goto tlb_miss_tgpr;
2408 case POWERPC_EXCP_7x5:
2409 goto tlb_miss;
2410 case POWERPC_EXCP_74xx:
2411 goto tlb_miss_74xx;
2412 default:
2413 cpu_abort(env, "Invalid data load TLB miss exception\n");
2414 break;
2415 }
2416 break;
2417 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
2418 if (lpes1 == 0) /* XXX: check this */
2419 new_msr |= (target_ulong)MSR_HVB;
2420 switch (excp_model) {
2421 case POWERPC_EXCP_602:
2422 case POWERPC_EXCP_603:
2423 case POWERPC_EXCP_603E:
2424 case POWERPC_EXCP_G2:
2425 tlb_miss_tgpr:
2426 /* Swap temporary saved registers with GPRs */
2427 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
2428 new_msr |= (target_ulong)1 << MSR_TGPR;
2429 hreg_swap_gpr_tgpr(env);
2430 }
2431 goto tlb_miss;
2432 case POWERPC_EXCP_7x5:
2433 tlb_miss:
2434 #if defined (DEBUG_SOFTWARE_TLB)
2435 if (qemu_log_enabled()) {
2436 const char *es;
2437 target_ulong *miss, *cmp;
2438 int en;
2439 if (excp == POWERPC_EXCP_IFTLB) {
2440 es = "I";
2441 en = 'I';
2442 miss = &env->spr[SPR_IMISS];
2443 cmp = &env->spr[SPR_ICMP];
2444 } else {
2445 if (excp == POWERPC_EXCP_DLTLB)
2446 es = "DL";
2447 else
2448 es = "DS";
2449 en = 'D';
2450 miss = &env->spr[SPR_DMISS];
2451 cmp = &env->spr[SPR_DCMP];
2452 }
2453 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
2454 TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
2455 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
2456 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2457 env->error_code);
2458 }
2459 #endif
2460 msr |= env->crf[0] << 28;
2461 msr |= env->error_code; /* key, D/I, S/L bits */
2462 /* Set way using a LRU mechanism */
2463 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2464 break;
2465 case POWERPC_EXCP_74xx:
2466 tlb_miss_74xx:
2467 #if defined (DEBUG_SOFTWARE_TLB)
2468 if (qemu_log_enabled()) {
2469 const char *es;
2470 target_ulong *miss, *cmp;
2471 int en;
2472 if (excp == POWERPC_EXCP_IFTLB) {
2473 es = "I";
2474 en = 'I';
2475 miss = &env->spr[SPR_TLBMISS];
2476 cmp = &env->spr[SPR_PTEHI];
2477 } else {
2478 if (excp == POWERPC_EXCP_DLTLB)
2479 es = "DL";
2480 else
2481 es = "DS";
2482 en = 'D';
2483 miss = &env->spr[SPR_TLBMISS];
2484 cmp = &env->spr[SPR_PTEHI];
2485 }
2486 qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
2487 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
2488 env->error_code);
2489 }
2490 #endif
2491 msr |= env->error_code; /* key bit */
2492 break;
2493 default:
2494 cpu_abort(env, "Invalid data store TLB miss exception\n");
2495 break;
2496 }
2497 goto store_next;
2498 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
2499 /* XXX: TODO */
2500 cpu_abort(env, "Floating point assist exception "
2501 "is not implemented yet !\n");
2502 goto store_next;
2503 case POWERPC_EXCP_DABR: /* Data address breakpoint */
2504 /* XXX: TODO */
2505 cpu_abort(env, "DABR exception is not implemented yet !\n");
2506 goto store_next;
2507 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
2508 /* XXX: TODO */
2509 cpu_abort(env, "IABR exception is not implemented yet !\n");
2510 goto store_next;
2511 case POWERPC_EXCP_SMI: /* System management interrupt */
2512 /* XXX: TODO */
2513 cpu_abort(env, "SMI exception is not implemented yet !\n");
2514 goto store_next;
2515 case POWERPC_EXCP_THERM: /* Thermal interrupt */
2516 /* XXX: TODO */
2517 cpu_abort(env, "Thermal management exception "
2518 "is not implemented yet !\n");
2519 goto store_next;
2520 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
2521 if (lpes1 == 0)
2522 new_msr |= (target_ulong)MSR_HVB;
2523 /* XXX: TODO */
2524 cpu_abort(env,
2525 "Performance counter exception is not implemented yet !\n");
2526 goto store_next;
2527 case POWERPC_EXCP_VPUA: /* Vector assist exception */
2528 /* XXX: TODO */
2529 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2530 goto store_next;
2531 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
2532 /* XXX: TODO */
2533 cpu_abort(env,
2534 "970 soft-patch exception is not implemented yet !\n");
2535 goto store_next;
2536 case POWERPC_EXCP_MAINT: /* Maintenance exception */
2537 /* XXX: TODO */
2538 cpu_abort(env,
2539 "970 maintenance exception is not implemented yet !\n");
2540 goto store_next;
2541 case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
2542 /* XXX: TODO */
2543 cpu_abort(env, "Maskable external exception "
2544 "is not implemented yet !\n");
2545 goto store_next;
2546 case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
2547 /* XXX: TODO */
2548 cpu_abort(env, "Non maskable external exception "
2549 "is not implemented yet !\n");
2550 goto store_next;
2551 default:
2552 excp_invalid:
2553 cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
2554 break;
2555 store_current:
2556 /* save current instruction location */
2557 env->spr[srr0] = env->nip - 4;
2558 break;
2559 store_next:
2560 /* save next instruction location */
2561 env->spr[srr0] = env->nip;
2562 break;
2563 }
2564 /* Save MSR */
2565 env->spr[srr1] = msr;
2566 /* If any alternate SRR register are defined, duplicate saved values */
2567 if (asrr0 != -1)
2568 env->spr[asrr0] = env->spr[srr0];
2569 if (asrr1 != -1)
2570 env->spr[asrr1] = env->spr[srr1];
2571 /* If we disactivated any translation, flush TLBs */
2572 if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR)))
2573 tlb_flush(env, 1);
2574
2575 if (msr_ile) {
2576 new_msr |= (target_ulong)1 << MSR_LE;
2577 }
2578
2579 /* Jump to handler */
2580 vector = env->excp_vectors[excp];
2581 if (vector == (target_ulong)-1ULL) {
2582 cpu_abort(env, "Raised an exception without defined vector %d\n",
2583 excp);
2584 }
2585 vector |= env->excp_prefix;
2586 #if defined(TARGET_PPC64)
2587 if (excp_model == POWERPC_EXCP_BOOKE) {
2588 if (!msr_icm) {
2589 vector = (uint32_t)vector;
2590 } else {
2591 new_msr |= (target_ulong)1 << MSR_CM;
2592 }
2593 } else {
2594 if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
2595 vector = (uint32_t)vector;
2596 } else {
2597 new_msr |= (target_ulong)1 << MSR_SF;
2598 }
2599 }
2600 #endif
2601 /* XXX: we don't use hreg_store_msr here as already have treated
2602 * any special case that could occur. Just store MSR and update hflags
2603 */
2604 env->msr = new_msr & env->msr_mask;
2605 hreg_compute_hflags(env);
2606 env->nip = vector;
2607 /* Reset exception state */
2608 env->exception_index = POWERPC_EXCP_NONE;
2609 env->error_code = 0;
2610 }
2611
2612 void do_interrupt (CPUState *env)
2613 {
2614 powerpc_excp(env, env->excp_model, env->exception_index);
2615 }
2616
2617 void ppc_hw_interrupt (CPUPPCState *env)
2618 {
2619 int hdice;
2620
2621 #if 0
2622 qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
2623 __func__, env, env->pending_interrupts,
2624 env->interrupt_request, (int)msr_me, (int)msr_ee);
2625 #endif
2626 /* External reset */
2627 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
2628 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
2629 powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
2630 return;
2631 }
2632 /* Machine check exception */
2633 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2634 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2635 powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
2636 return;
2637 }
2638 #if 0 /* TODO */
2639 /* External debug exception */
2640 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2641 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2642 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
2643 return;
2644 }
2645 #endif
2646 if (0) {
2647 /* XXX: find a suitable condition to enable the hypervisor mode */
2648 hdice = env->spr[SPR_LPCR] & 1;
2649 } else {
2650 hdice = 0;
2651 }
2652 if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) {
2653 /* Hypervisor decrementer exception */
2654 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2655 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2656 powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
2657 return;
2658 }
2659 }
2660 if (msr_ce != 0) {
2661 /* External critical interrupt */
2662 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
2663 /* Taking a critical external interrupt does not clear the external
2664 * critical interrupt status
2665 */
2666 #if 0
2667 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
2668 #endif
2669 powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
2670 return;
2671 }
2672 }
2673 if (msr_ee != 0) {
2674 /* Watchdog timer on embedded PowerPC */
2675 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2676 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2677 powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
2678 return;
2679 }
2680 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
2681 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
2682 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
2683 return;
2684 }
2685 /* Fixed interval timer on embedded PowerPC */
2686 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2687 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2688 powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
2689 return;
2690 }
2691 /* Programmable interval timer on embedded PowerPC */
2692 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2693 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2694 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
2695 return;
2696 }
2697 /* Decrementer exception */
2698 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2699 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2700 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
2701 return;
2702 }
2703 /* External interrupt */
2704 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2705 /* Taking an external interrupt does not clear the external
2706 * interrupt status
2707 */
2708 #if 0
2709 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2710 #endif
2711 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2712 return;
2713 }
2714 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
2715 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2716 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
2717 return;
2718 }
2719 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
2720 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
2721 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
2722 return;
2723 }
2724 /* Thermal interrupt */
2725 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2726 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2727 powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
2728 return;
2729 }
2730 }
2731 }
2732 #endif /* !CONFIG_USER_ONLY */
2733
2734 void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2735 {
2736 qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
2737 TARGET_FMT_lx "\n", RA, msr);
2738 }
2739
2740 void cpu_reset(CPUPPCState *env)
2741 {
2742 target_ulong msr;
2743
2744 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
2745 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
2746 log_cpu_state(env, 0);
2747 }
2748
2749 msr = (target_ulong)0;
2750 if (0) {
2751 /* XXX: find a suitable condition to enable the hypervisor mode */
2752 msr |= (target_ulong)MSR_HVB;
2753 }
2754 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
2755 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
2756 msr |= (target_ulong)1 << MSR_EP;
2757 #if defined (DO_SINGLE_STEP) && 0
2758 /* Single step trace mode */
2759 msr |= (target_ulong)1 << MSR_SE;
2760 msr |= (target_ulong)1 << MSR_BE;
2761 #endif
2762 #if defined(CONFIG_USER_ONLY)
2763 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
2764 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
2765 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
2766 msr |= (target_ulong)1 << MSR_PR;
2767 #else
2768 env->excp_prefix = env->hreset_excp_prefix;
2769 env->nip = env->hreset_vector | env->excp_prefix;
2770 if (env->mmu_model != POWERPC_MMU_REAL)
2771 ppc_tlb_invalidate_all(env);
2772 #endif
2773 env->msr = msr & env->msr_mask;
2774 #if defined(TARGET_PPC64)
2775 if (env->mmu_model & POWERPC_MMU_64)
2776 env->msr |= (1ULL << MSR_SF);
2777 #endif
2778 hreg_compute_hflags(env);
2779 env->reserve_addr = (target_ulong)-1ULL;
2780 /* Be sure no exception or interrupt is pending */
2781 env->pending_interrupts = 0;
2782 env->exception_index = POWERPC_EXCP_NONE;
2783 env->error_code = 0;
2784 /* Flush all TLBs */
2785 tlb_flush(env, 1);
2786 }
2787
2788 CPUPPCState *cpu_ppc_init (const char *cpu_model)
2789 {
2790 CPUPPCState *env;
2791 const ppc_def_t *def;
2792
2793 def = cpu_ppc_find_by_name(cpu_model);
2794 if (!def)
2795 return NULL;
2796
2797 env = qemu_mallocz(sizeof(CPUPPCState));
2798 cpu_exec_init(env);
2799 ppc_translate_init();
2800 env->cpu_model_str = cpu_model;
2801 cpu_ppc_register_internal(env, def);
2802
2803 qemu_init_vcpu(env);
2804
2805 return env;
2806 }
2807
2808 void cpu_ppc_close (CPUPPCState *env)
2809 {
2810 /* Should also remove all opcode tables... */
2811 qemu_free(env);
2812 }
various patches