2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
33 #include "qemu-common.h"
39 //#define MIPS_DEBUG_DISAS
40 //#define MIPS_DEBUG_SIGN_EXTENSIONS
42 /* MIPS major opcodes */
43 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
46 /* indirect opcode tables */
47 OPC_SPECIAL
= (0x00 << 26),
48 OPC_REGIMM
= (0x01 << 26),
49 OPC_CP0
= (0x10 << 26),
50 OPC_CP1
= (0x11 << 26),
51 OPC_CP2
= (0x12 << 26),
52 OPC_CP3
= (0x13 << 26),
53 OPC_SPECIAL2
= (0x1C << 26),
54 OPC_SPECIAL3
= (0x1F << 26),
55 /* arithmetic with immediate */
56 OPC_ADDI
= (0x08 << 26),
57 OPC_ADDIU
= (0x09 << 26),
58 OPC_SLTI
= (0x0A << 26),
59 OPC_SLTIU
= (0x0B << 26),
60 /* logic with immediate */
61 OPC_ANDI
= (0x0C << 26),
62 OPC_ORI
= (0x0D << 26),
63 OPC_XORI
= (0x0E << 26),
64 OPC_LUI
= (0x0F << 26),
65 /* arithmetic with immediate */
66 OPC_DADDI
= (0x18 << 26),
67 OPC_DADDIU
= (0x19 << 26),
68 /* Jump and branches */
70 OPC_JAL
= (0x03 << 26),
71 OPC_JALS
= OPC_JAL
| 0x5,
72 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
73 OPC_BEQL
= (0x14 << 26),
74 OPC_BNE
= (0x05 << 26),
75 OPC_BNEL
= (0x15 << 26),
76 OPC_BLEZ
= (0x06 << 26),
77 OPC_BLEZL
= (0x16 << 26),
78 OPC_BGTZ
= (0x07 << 26),
79 OPC_BGTZL
= (0x17 << 26),
80 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
81 OPC_JALXS
= OPC_JALX
| 0x5,
83 OPC_LDL
= (0x1A << 26),
84 OPC_LDR
= (0x1B << 26),
85 OPC_LB
= (0x20 << 26),
86 OPC_LH
= (0x21 << 26),
87 OPC_LWL
= (0x22 << 26),
88 OPC_LW
= (0x23 << 26),
89 OPC_LWPC
= OPC_LW
| 0x5,
90 OPC_LBU
= (0x24 << 26),
91 OPC_LHU
= (0x25 << 26),
92 OPC_LWR
= (0x26 << 26),
93 OPC_LWU
= (0x27 << 26),
94 OPC_SB
= (0x28 << 26),
95 OPC_SH
= (0x29 << 26),
96 OPC_SWL
= (0x2A << 26),
97 OPC_SW
= (0x2B << 26),
98 OPC_SDL
= (0x2C << 26),
99 OPC_SDR
= (0x2D << 26),
100 OPC_SWR
= (0x2E << 26),
101 OPC_LL
= (0x30 << 26),
102 OPC_LLD
= (0x34 << 26),
103 OPC_LD
= (0x37 << 26),
104 OPC_LDPC
= OPC_LD
| 0x5,
105 OPC_SC
= (0x38 << 26),
106 OPC_SCD
= (0x3C << 26),
107 OPC_SD
= (0x3F << 26),
108 /* Floating point load/store */
109 OPC_LWC1
= (0x31 << 26),
110 OPC_LWC2
= (0x32 << 26),
111 OPC_LDC1
= (0x35 << 26),
112 OPC_LDC2
= (0x36 << 26),
113 OPC_SWC1
= (0x39 << 26),
114 OPC_SWC2
= (0x3A << 26),
115 OPC_SDC1
= (0x3D << 26),
116 OPC_SDC2
= (0x3E << 26),
117 /* MDMX ASE specific */
118 OPC_MDMX
= (0x1E << 26),
119 /* Cache and prefetch */
120 OPC_CACHE
= (0x2F << 26),
121 OPC_PREF
= (0x33 << 26),
122 /* Reserved major opcode */
123 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
126 /* MIPS special opcodes */
127 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
131 OPC_SLL
= 0x00 | OPC_SPECIAL
,
132 /* NOP is SLL r0, r0, 0 */
133 /* SSNOP is SLL r0, r0, 1 */
134 /* EHB is SLL r0, r0, 3 */
135 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
136 OPC_ROTR
= OPC_SRL
| (1 << 21),
137 OPC_SRA
= 0x03 | OPC_SPECIAL
,
138 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
139 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
140 OPC_ROTRV
= OPC_SRLV
| (1 << 6),
141 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
142 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
143 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
144 OPC_DROTRV
= OPC_DSRLV
| (1 << 6),
145 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
146 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
147 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
148 OPC_DROTR
= OPC_DSRL
| (1 << 21),
149 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
150 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
151 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
152 OPC_DROTR32
= OPC_DSRL32
| (1 << 21),
153 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
154 /* Multiplication / division */
155 OPC_MULT
= 0x18 | OPC_SPECIAL
,
156 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
157 OPC_DIV
= 0x1A | OPC_SPECIAL
,
158 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
159 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
160 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
161 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
162 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
163 /* 2 registers arithmetic / logic */
164 OPC_ADD
= 0x20 | OPC_SPECIAL
,
165 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
166 OPC_SUB
= 0x22 | OPC_SPECIAL
,
167 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
168 OPC_AND
= 0x24 | OPC_SPECIAL
,
169 OPC_OR
= 0x25 | OPC_SPECIAL
,
170 OPC_XOR
= 0x26 | OPC_SPECIAL
,
171 OPC_NOR
= 0x27 | OPC_SPECIAL
,
172 OPC_SLT
= 0x2A | OPC_SPECIAL
,
173 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
174 OPC_DADD
= 0x2C | OPC_SPECIAL
,
175 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
176 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
177 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
179 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
180 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
181 OPC_JALRC
= OPC_JALR
| (0x5 << 6),
182 OPC_JALRS
= 0x10 | OPC_SPECIAL
| (0x5 << 6),
184 OPC_TGE
= 0x30 | OPC_SPECIAL
,
185 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
186 OPC_TLT
= 0x32 | OPC_SPECIAL
,
187 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
188 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
189 OPC_TNE
= 0x36 | OPC_SPECIAL
,
190 /* HI / LO registers load & stores */
191 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
192 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
193 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
194 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
195 /* Conditional moves */
196 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
197 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
199 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
202 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* unofficial */
203 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
204 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
205 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* unofficial */
206 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
208 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
209 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
210 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
211 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
212 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
213 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
214 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
217 /* Multiplication variants of the vr54xx. */
218 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
221 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
222 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
223 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
224 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
225 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
226 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
227 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
228 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
229 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
230 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
231 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
232 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
233 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
234 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
237 /* REGIMM (rt field) opcodes */
238 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
241 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
242 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
243 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
244 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
245 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
246 OPC_BLTZALS
= OPC_BLTZAL
| 0x5, /* microMIPS */
247 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
248 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
249 OPC_BGEZALS
= OPC_BGEZAL
| 0x5, /* microMIPS */
250 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
251 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
252 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
253 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
254 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
255 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
256 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
257 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
260 /* Special2 opcodes */
261 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
264 /* Multiply & xxx operations */
265 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
266 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
267 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
268 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
269 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
271 OPC_MULT_G_2F
= 0x10 | OPC_SPECIAL2
,
272 OPC_DMULT_G_2F
= 0x11 | OPC_SPECIAL2
,
273 OPC_MULTU_G_2F
= 0x12 | OPC_SPECIAL2
,
274 OPC_DMULTU_G_2F
= 0x13 | OPC_SPECIAL2
,
275 OPC_DIV_G_2F
= 0x14 | OPC_SPECIAL2
,
276 OPC_DDIV_G_2F
= 0x15 | OPC_SPECIAL2
,
277 OPC_DIVU_G_2F
= 0x16 | OPC_SPECIAL2
,
278 OPC_DDIVU_G_2F
= 0x17 | OPC_SPECIAL2
,
279 OPC_MOD_G_2F
= 0x1c | OPC_SPECIAL2
,
280 OPC_DMOD_G_2F
= 0x1d | OPC_SPECIAL2
,
281 OPC_MODU_G_2F
= 0x1e | OPC_SPECIAL2
,
282 OPC_DMODU_G_2F
= 0x1f | OPC_SPECIAL2
,
284 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
285 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
286 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
287 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
289 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
292 /* Special3 opcodes */
293 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
296 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
297 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
298 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
299 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
300 OPC_INS
= 0x04 | OPC_SPECIAL3
,
301 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
302 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
303 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
304 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
305 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
306 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
307 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
308 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
311 OPC_MULT_G_2E
= 0x18 | OPC_SPECIAL3
,
312 OPC_MULTU_G_2E
= 0x19 | OPC_SPECIAL3
,
313 OPC_DIV_G_2E
= 0x1A | OPC_SPECIAL3
,
314 OPC_DIVU_G_2E
= 0x1B | OPC_SPECIAL3
,
315 OPC_DMULT_G_2E
= 0x1C | OPC_SPECIAL3
,
316 OPC_DMULTU_G_2E
= 0x1D | OPC_SPECIAL3
,
317 OPC_DDIV_G_2E
= 0x1E | OPC_SPECIAL3
,
318 OPC_DDIVU_G_2E
= 0x1F | OPC_SPECIAL3
,
319 OPC_MOD_G_2E
= 0x22 | OPC_SPECIAL3
,
320 OPC_MODU_G_2E
= 0x23 | OPC_SPECIAL3
,
321 OPC_DMOD_G_2E
= 0x26 | OPC_SPECIAL3
,
322 OPC_DMODU_G_2E
= 0x27 | OPC_SPECIAL3
,
326 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
329 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
330 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
331 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
335 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
338 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
339 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
342 /* Coprocessor 0 (rs field) */
343 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
346 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
347 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
348 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
349 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
350 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
351 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
352 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
353 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
354 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
355 OPC_C0
= (0x10 << 21) | OPC_CP0
,
356 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
357 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
361 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
364 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
365 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
366 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
367 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
368 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
369 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
372 /* Coprocessor 0 (with rs == C0) */
373 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
376 OPC_TLBR
= 0x01 | OPC_C0
,
377 OPC_TLBWI
= 0x02 | OPC_C0
,
378 OPC_TLBWR
= 0x06 | OPC_C0
,
379 OPC_TLBP
= 0x08 | OPC_C0
,
380 OPC_RFE
= 0x10 | OPC_C0
,
381 OPC_ERET
= 0x18 | OPC_C0
,
382 OPC_DERET
= 0x1F | OPC_C0
,
383 OPC_WAIT
= 0x20 | OPC_C0
,
386 /* Coprocessor 1 (rs field) */
387 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
389 /* Values for the fmt field in FP instructions */
391 /* 0 - 15 are reserved */
392 FMT_S
= 16, /* single fp */
393 FMT_D
= 17, /* double fp */
394 FMT_E
= 18, /* extended fp */
395 FMT_Q
= 19, /* quad fp */
396 FMT_W
= 20, /* 32-bit fixed */
397 FMT_L
= 21, /* 64-bit fixed */
398 FMT_PS
= 22, /* paired single fp */
399 /* 23 - 31 are reserved */
403 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
404 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
405 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
406 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
407 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
408 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
409 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
410 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
411 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
412 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
413 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
414 OPC_S_FMT
= (FMT_S
<< 21) | OPC_CP1
,
415 OPC_D_FMT
= (FMT_D
<< 21) | OPC_CP1
,
416 OPC_E_FMT
= (FMT_E
<< 21) | OPC_CP1
,
417 OPC_Q_FMT
= (FMT_Q
<< 21) | OPC_CP1
,
418 OPC_W_FMT
= (FMT_W
<< 21) | OPC_CP1
,
419 OPC_L_FMT
= (FMT_L
<< 21) | OPC_CP1
,
420 OPC_PS_FMT
= (FMT_PS
<< 21) | OPC_CP1
,
423 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
424 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
427 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
428 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
429 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
430 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
434 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
435 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
439 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
440 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
443 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
446 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
447 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
448 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
449 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
450 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
451 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
452 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
453 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
454 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
457 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
460 OPC_LWXC1
= 0x00 | OPC_CP3
,
461 OPC_LDXC1
= 0x01 | OPC_CP3
,
462 OPC_LUXC1
= 0x05 | OPC_CP3
,
463 OPC_SWXC1
= 0x08 | OPC_CP3
,
464 OPC_SDXC1
= 0x09 | OPC_CP3
,
465 OPC_SUXC1
= 0x0D | OPC_CP3
,
466 OPC_PREFX
= 0x0F | OPC_CP3
,
467 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
468 OPC_MADD_S
= 0x20 | OPC_CP3
,
469 OPC_MADD_D
= 0x21 | OPC_CP3
,
470 OPC_MADD_PS
= 0x26 | OPC_CP3
,
471 OPC_MSUB_S
= 0x28 | OPC_CP3
,
472 OPC_MSUB_D
= 0x29 | OPC_CP3
,
473 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
474 OPC_NMADD_S
= 0x30 | OPC_CP3
,
475 OPC_NMADD_D
= 0x31 | OPC_CP3
,
476 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
477 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
478 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
479 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
482 /* global register indices */
483 static TCGv_ptr cpu_env
;
484 static TCGv cpu_gpr
[32], cpu_PC
;
485 static TCGv cpu_HI
[MIPS_DSP_ACC
], cpu_LO
[MIPS_DSP_ACC
], cpu_ACX
[MIPS_DSP_ACC
];
486 static TCGv cpu_dspctrl
, btarget
, bcond
;
487 static TCGv_i32 hflags
;
488 static TCGv_i32 fpu_fcr0
, fpu_fcr31
;
490 static uint32_t gen_opc_hflags
[OPC_BUF_SIZE
];
492 #include "gen-icount.h"
494 #define gen_helper_0i(name, arg) do { \
495 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
496 gen_helper_##name(helper_tmp); \
497 tcg_temp_free_i32(helper_tmp); \
500 #define gen_helper_1i(name, arg1, arg2) do { \
501 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
502 gen_helper_##name(arg1, helper_tmp); \
503 tcg_temp_free_i32(helper_tmp); \
506 #define gen_helper_2i(name, arg1, arg2, arg3) do { \
507 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
508 gen_helper_##name(arg1, arg2, helper_tmp); \
509 tcg_temp_free_i32(helper_tmp); \
512 #define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \
513 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
514 gen_helper_##name(arg1, arg2, arg3, helper_tmp); \
515 tcg_temp_free_i32(helper_tmp); \
518 typedef struct DisasContext
{
519 struct TranslationBlock
*tb
;
520 target_ulong pc
, saved_pc
;
522 int singlestep_enabled
;
523 /* Routine used to access memory */
525 uint32_t hflags
, saved_hflags
;
527 target_ulong btarget
;
531 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
532 * exception condition */
533 BS_STOP
= 1, /* We want to stop translation for any reason */
534 BS_BRANCH
= 2, /* We reached a branch condition */
535 BS_EXCP
= 3, /* We reached an exception condition */
538 static const char *regnames
[] =
539 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
540 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
541 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
542 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
544 static const char *regnames_HI
[] =
545 { "HI0", "HI1", "HI2", "HI3", };
547 static const char *regnames_LO
[] =
548 { "LO0", "LO1", "LO2", "LO3", };
550 static const char *regnames_ACX
[] =
551 { "ACX0", "ACX1", "ACX2", "ACX3", };
553 static const char *fregnames
[] =
554 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
555 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
556 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
557 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
559 #ifdef MIPS_DEBUG_DISAS
560 #define MIPS_DEBUG(fmt, ...) \
561 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
562 TARGET_FMT_lx ": %08x " fmt "\n", \
563 ctx->pc, ctx->opcode , ## __VA_ARGS__)
564 #define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
566 #define MIPS_DEBUG(fmt, ...) do { } while(0)
567 #define LOG_DISAS(...) do { } while (0)
570 #define MIPS_INVAL(op) \
572 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
573 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
576 /* General purpose registers moves. */
577 static inline void gen_load_gpr (TCGv t
, int reg
)
580 tcg_gen_movi_tl(t
, 0);
582 tcg_gen_mov_tl(t
, cpu_gpr
[reg
]);
585 static inline void gen_store_gpr (TCGv t
, int reg
)
588 tcg_gen_mov_tl(cpu_gpr
[reg
], t
);
591 /* Moves to/from ACX register. */
592 static inline void gen_load_ACX (TCGv t
, int reg
)
594 tcg_gen_mov_tl(t
, cpu_ACX
[reg
]);
597 static inline void gen_store_ACX (TCGv t
, int reg
)
599 tcg_gen_mov_tl(cpu_ACX
[reg
], t
);
602 /* Moves to/from shadow registers. */
603 static inline void gen_load_srsgpr (int from
, int to
)
605 TCGv t0
= tcg_temp_new();
608 tcg_gen_movi_tl(t0
, 0);
610 TCGv_i32 t2
= tcg_temp_new_i32();
611 TCGv_ptr addr
= tcg_temp_new_ptr();
613 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
614 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
615 tcg_gen_andi_i32(t2
, t2
, 0xf);
616 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
617 tcg_gen_ext_i32_ptr(addr
, t2
);
618 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
620 tcg_gen_ld_tl(t0
, addr
, sizeof(target_ulong
) * from
);
621 tcg_temp_free_ptr(addr
);
622 tcg_temp_free_i32(t2
);
624 gen_store_gpr(t0
, to
);
628 static inline void gen_store_srsgpr (int from
, int to
)
631 TCGv t0
= tcg_temp_new();
632 TCGv_i32 t2
= tcg_temp_new_i32();
633 TCGv_ptr addr
= tcg_temp_new_ptr();
635 gen_load_gpr(t0
, from
);
636 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
637 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
638 tcg_gen_andi_i32(t2
, t2
, 0xf);
639 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
640 tcg_gen_ext_i32_ptr(addr
, t2
);
641 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
643 tcg_gen_st_tl(t0
, addr
, sizeof(target_ulong
) * to
);
644 tcg_temp_free_ptr(addr
);
645 tcg_temp_free_i32(t2
);
650 /* Floating point register moves. */
651 static inline void gen_load_fpr32 (TCGv_i32 t
, int reg
)
653 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[FP_ENDIAN_IDX
]));
656 static inline void gen_store_fpr32 (TCGv_i32 t
, int reg
)
658 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[FP_ENDIAN_IDX
]));
661 static inline void gen_load_fpr32h (TCGv_i32 t
, int reg
)
663 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[!FP_ENDIAN_IDX
]));
666 static inline void gen_store_fpr32h (TCGv_i32 t
, int reg
)
668 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[!FP_ENDIAN_IDX
]));
671 static inline void gen_load_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
673 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
674 tcg_gen_ld_i64(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].d
));
676 TCGv_i32 t0
= tcg_temp_new_i32();
677 TCGv_i32 t1
= tcg_temp_new_i32();
678 gen_load_fpr32(t0
, reg
& ~1);
679 gen_load_fpr32(t1
, reg
| 1);
680 tcg_gen_concat_i32_i64(t
, t0
, t1
);
681 tcg_temp_free_i32(t0
);
682 tcg_temp_free_i32(t1
);
686 static inline void gen_store_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
688 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
689 tcg_gen_st_i64(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].d
));
691 TCGv_i64 t0
= tcg_temp_new_i64();
692 TCGv_i32 t1
= tcg_temp_new_i32();
693 tcg_gen_trunc_i64_i32(t1
, t
);
694 gen_store_fpr32(t1
, reg
& ~1);
695 tcg_gen_shri_i64(t0
, t
, 32);
696 tcg_gen_trunc_i64_i32(t1
, t0
);
697 gen_store_fpr32(t1
, reg
| 1);
698 tcg_temp_free_i32(t1
);
699 tcg_temp_free_i64(t0
);
703 static inline int get_fp_bit (int cc
)
712 static inline void gen_save_pc(target_ulong pc
)
714 tcg_gen_movi_tl(cpu_PC
, pc
);
717 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
719 LOG_DISAS("hflags %08x saved %08x\n", ctx
->hflags
, ctx
->saved_hflags
);
720 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
721 gen_save_pc(ctx
->pc
);
722 ctx
->saved_pc
= ctx
->pc
;
724 if (ctx
->hflags
!= ctx
->saved_hflags
) {
725 tcg_gen_movi_i32(hflags
, ctx
->hflags
);
726 ctx
->saved_hflags
= ctx
->hflags
;
727 switch (ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) {
733 tcg_gen_movi_tl(btarget
, ctx
->btarget
);
739 static inline void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
741 ctx
->saved_hflags
= ctx
->hflags
;
742 switch (ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) {
748 ctx
->btarget
= env
->btarget
;
754 generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
756 TCGv_i32 texcp
= tcg_const_i32(excp
);
757 TCGv_i32 terr
= tcg_const_i32(err
);
758 save_cpu_state(ctx
, 1);
759 gen_helper_raise_exception_err(texcp
, terr
);
760 tcg_temp_free_i32(terr
);
761 tcg_temp_free_i32(texcp
);
765 generate_exception (DisasContext
*ctx
, int excp
)
767 save_cpu_state(ctx
, 1);
768 gen_helper_0i(raise_exception
, excp
);
771 /* Addresses computation */
772 static inline void gen_op_addr_add (DisasContext
*ctx
, TCGv ret
, TCGv arg0
, TCGv arg1
)
774 tcg_gen_add_tl(ret
, arg0
, arg1
);
776 #if defined(TARGET_MIPS64)
777 /* For compatibility with 32-bit code, data reference in user mode
778 with Status_UX = 0 should be casted to 32-bit and sign extended.
779 See the MIPS64 PRA manual, section 4.10. */
780 if (((ctx
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
781 !(ctx
->hflags
& MIPS_HFLAG_UX
)) {
782 tcg_gen_ext32s_i64(ret
, ret
);
787 static inline void check_cp0_enabled(DisasContext
*ctx
)
789 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
790 generate_exception_err(ctx
, EXCP_CpU
, 0);
793 static inline void check_cp1_enabled(DisasContext
*ctx
)
795 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
796 generate_exception_err(ctx
, EXCP_CpU
, 1);
799 /* Verify that the processor is running with COP1X instructions enabled.
800 This is associated with the nabla symbol in the MIPS32 and MIPS64
803 static inline void check_cop1x(DisasContext
*ctx
)
805 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
)))
806 generate_exception(ctx
, EXCP_RI
);
809 /* Verify that the processor is running with 64-bit floating-point
810 operations enabled. */
812 static inline void check_cp1_64bitmode(DisasContext
*ctx
)
814 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
)))
815 generate_exception(ctx
, EXCP_RI
);
819 * Verify if floating point register is valid; an operation is not defined
820 * if bit 0 of any register specification is set and the FR bit in the
821 * Status register equals zero, since the register numbers specify an
822 * even-odd pair of adjacent coprocessor general registers. When the FR bit
823 * in the Status register equals one, both even and odd register numbers
824 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
826 * Multiple 64 bit wide registers can be checked by calling
827 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
829 static inline void check_cp1_registers(DisasContext
*ctx
, int regs
)
831 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
832 generate_exception(ctx
, EXCP_RI
);
835 /* This code generates a "reserved instruction" exception if the
836 CPU does not support the instruction set corresponding to flags. */
837 static inline void check_insn(CPUState
*env
, DisasContext
*ctx
, int flags
)
839 if (unlikely(!(env
->insn_flags
& flags
)))
840 generate_exception(ctx
, EXCP_RI
);
843 /* This code generates a "reserved instruction" exception if 64-bit
844 instructions are not enabled. */
845 static inline void check_mips_64(DisasContext
*ctx
)
847 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
848 generate_exception(ctx
, EXCP_RI
);
851 /* Define small wrappers for gen_load_fpr* so that we have a uniform
852 calling interface for 32 and 64-bit FPRs. No sense in changing
853 all callers for gen_load_fpr32 when we need the CTX parameter for
855 #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(x, y)
856 #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
857 #define FOP_CONDS(type, abs, fmt, ifmt, bits) \
858 static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
859 int ft, int fs, int cc) \
861 TCGv_i##bits fp0 = tcg_temp_new_i##bits (); \
862 TCGv_i##bits fp1 = tcg_temp_new_i##bits (); \
865 check_cp1_64bitmode(ctx); \
871 check_cp1_registers(ctx, fs | ft); \
879 gen_ldcmp_fpr##bits (ctx, fp0, fs); \
880 gen_ldcmp_fpr##bits (ctx, fp1, ft); \
882 case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\
883 case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\
884 case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); break;\
885 case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); break;\
886 case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); break;\
887 case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); break;\
888 case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); break;\
889 case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); break;\
890 case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); break;\
891 case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); break;\
892 case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); break;\
893 case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); break;\
894 case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); break;\
895 case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); break;\
896 case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); break;\
897 case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); break;\
900 tcg_temp_free_i##bits (fp0); \
901 tcg_temp_free_i##bits (fp1); \
904 FOP_CONDS(, 0, d
, FMT_D
, 64)
905 FOP_CONDS(abs
, 1, d
, FMT_D
, 64)
906 FOP_CONDS(, 0, s
, FMT_S
, 32)
907 FOP_CONDS(abs
, 1, s
, FMT_S
, 32)
908 FOP_CONDS(, 0, ps
, FMT_PS
, 64)
909 FOP_CONDS(abs
, 1, ps
, FMT_PS
, 64)
911 #undef gen_ldcmp_fpr32
912 #undef gen_ldcmp_fpr64
914 /* load/store instructions. */
915 #define OP_LD(insn,fname) \
916 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
918 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
925 #if defined(TARGET_MIPS64)
931 #define OP_ST(insn,fname) \
932 static inline void op_st_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
934 tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
939 #if defined(TARGET_MIPS64)
944 #ifdef CONFIG_USER_ONLY
945 #define OP_LD_ATOMIC(insn,fname) \
946 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
948 TCGv t0 = tcg_temp_new(); \
949 tcg_gen_mov_tl(t0, arg1); \
950 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
951 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
952 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
956 #define OP_LD_ATOMIC(insn,fname) \
957 static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
959 gen_helper_2i(insn, ret, arg1, ctx->mem_idx); \
962 OP_LD_ATOMIC(ll
,ld32s
);
963 #if defined(TARGET_MIPS64)
964 OP_LD_ATOMIC(lld
,ld64
);
968 #ifdef CONFIG_USER_ONLY
969 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
970 static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
972 TCGv t0 = tcg_temp_new(); \
973 int l1 = gen_new_label(); \
974 int l2 = gen_new_label(); \
976 tcg_gen_andi_tl(t0, arg2, almask); \
977 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
978 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
979 generate_exception(ctx, EXCP_AdES); \
981 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
982 tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
983 tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
984 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \
985 tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval)); \
986 gen_helper_0i(raise_exception, EXCP_SC); \
988 tcg_gen_movi_tl(t0, 0); \
989 gen_store_gpr(t0, rt); \
993 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
994 static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
996 TCGv t0 = tcg_temp_new(); \
997 gen_helper_3i(insn, t0, arg1, arg2, ctx->mem_idx); \
998 gen_store_gpr(t0, rt); \
1002 OP_ST_ATOMIC(sc
,st32
,ld32s
,0x3);
1003 #if defined(TARGET_MIPS64)
1004 OP_ST_ATOMIC(scd
,st64
,ld64
,0x7);
1008 static void gen_base_offset_addr (DisasContext
*ctx
, TCGv addr
,
1009 int base
, int16_t offset
)
1012 tcg_gen_movi_tl(addr
, offset
);
1013 } else if (offset
== 0) {
1014 gen_load_gpr(addr
, base
);
1016 tcg_gen_movi_tl(addr
, offset
);
1017 gen_op_addr_add(ctx
, addr
, cpu_gpr
[base
], addr
);
1021 static target_ulong
pc_relative_pc (DisasContext
*ctx
)
1023 target_ulong pc
= ctx
->pc
;
1025 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
1026 int branch_bytes
= ctx
->hflags
& MIPS_HFLAG_BDS16
? 2 : 4;
1031 pc
&= ~(target_ulong
)3;
1036 static void gen_ld (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1037 int rt
, int base
, int16_t offset
)
1039 const char *opn
= "ld";
1042 if (rt
== 0 && env
->insn_flags
& (INSN_LOONGSON2E
| INSN_LOONGSON2F
)) {
1043 /* Loongson CPU uses a load to zero register for prefetch.
1044 We emulate it as a NOP. On other CPU we must perform the
1045 actual memory access. */
1050 t0
= tcg_temp_new();
1051 t1
= tcg_temp_new();
1052 gen_base_offset_addr(ctx
, t0
, base
, offset
);
1055 #if defined(TARGET_MIPS64)
1057 save_cpu_state(ctx
, 0);
1058 op_ld_lwu(t0
, t0
, ctx
);
1059 gen_store_gpr(t0
, rt
);
1063 save_cpu_state(ctx
, 0);
1064 op_ld_ld(t0
, t0
, ctx
);
1065 gen_store_gpr(t0
, rt
);
1069 save_cpu_state(ctx
, 0);
1070 op_ld_lld(t0
, t0
, ctx
);
1071 gen_store_gpr(t0
, rt
);
1075 save_cpu_state(ctx
, 1);
1076 gen_load_gpr(t1
, rt
);
1077 gen_helper_3i(ldl
, t1
, t1
, t0
, ctx
->mem_idx
);
1078 gen_store_gpr(t1
, rt
);
1082 save_cpu_state(ctx
, 1);
1083 gen_load_gpr(t1
, rt
);
1084 gen_helper_3i(ldr
, t1
, t1
, t0
, ctx
->mem_idx
);
1085 gen_store_gpr(t1
, rt
);
1089 save_cpu_state(ctx
, 1);
1090 tcg_gen_movi_tl(t1
, pc_relative_pc(ctx
));
1091 gen_op_addr_add(ctx
, t0
, t0
, t1
);
1092 op_ld_ld(t0
, t0
, ctx
);
1093 gen_store_gpr(t0
, rt
);
1098 save_cpu_state(ctx
, 1);
1099 tcg_gen_movi_tl(t1
, pc_relative_pc(ctx
));
1100 gen_op_addr_add(ctx
, t0
, t0
, t1
);
1101 op_ld_lw(t0
, t0
, ctx
);
1102 gen_store_gpr(t0
, rt
);
1106 save_cpu_state(ctx
, 0);
1107 op_ld_lw(t0
, t0
, ctx
);
1108 gen_store_gpr(t0
, rt
);
1112 save_cpu_state(ctx
, 0);
1113 op_ld_lh(t0
, t0
, ctx
);
1114 gen_store_gpr(t0
, rt
);
1118 save_cpu_state(ctx
, 0);
1119 op_ld_lhu(t0
, t0
, ctx
);
1120 gen_store_gpr(t0
, rt
);
1124 save_cpu_state(ctx
, 0);
1125 op_ld_lb(t0
, t0
, ctx
);
1126 gen_store_gpr(t0
, rt
);
1130 save_cpu_state(ctx
, 0);
1131 op_ld_lbu(t0
, t0
, ctx
);
1132 gen_store_gpr(t0
, rt
);
1136 save_cpu_state(ctx
, 1);
1137 gen_load_gpr(t1
, rt
);
1138 gen_helper_3i(lwl
, t1
, t1
, t0
, ctx
->mem_idx
);
1139 gen_store_gpr(t1
, rt
);
1143 save_cpu_state(ctx
, 1);
1144 gen_load_gpr(t1
, rt
);
1145 gen_helper_3i(lwr
, t1
, t1
, t0
, ctx
->mem_idx
);
1146 gen_store_gpr(t1
, rt
);
1150 save_cpu_state(ctx
, 1);
1151 op_ld_ll(t0
, t0
, ctx
);
1152 gen_store_gpr(t0
, rt
);
1156 (void)opn
; /* avoid a compiler warning */
1157 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1163 static void gen_st (DisasContext
*ctx
, uint32_t opc
, int rt
,
1164 int base
, int16_t offset
)
1166 const char *opn
= "st";
1167 TCGv t0
= tcg_temp_new();
1168 TCGv t1
= tcg_temp_new();
1170 gen_base_offset_addr(ctx
, t0
, base
, offset
);
1171 gen_load_gpr(t1
, rt
);
1173 #if defined(TARGET_MIPS64)
1175 save_cpu_state(ctx
, 0);
1176 op_st_sd(t1
, t0
, ctx
);
1180 save_cpu_state(ctx
, 1);
1181 gen_helper_2i(sdl
, t1
, t0
, ctx
->mem_idx
);
1185 save_cpu_state(ctx
, 1);
1186 gen_helper_2i(sdr
, t1
, t0
, ctx
->mem_idx
);
1191 save_cpu_state(ctx
, 0);
1192 op_st_sw(t1
, t0
, ctx
);
1196 save_cpu_state(ctx
, 0);
1197 op_st_sh(t1
, t0
, ctx
);
1201 save_cpu_state(ctx
, 0);
1202 op_st_sb(t1
, t0
, ctx
);
1206 save_cpu_state(ctx
, 1);
1207 gen_helper_2i(swl
, t1
, t0
, ctx
->mem_idx
);
1211 save_cpu_state(ctx
, 1);
1212 gen_helper_2i(swr
, t1
, t0
, ctx
->mem_idx
);
1216 (void)opn
; /* avoid a compiler warning */
1217 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1223 /* Store conditional */
1224 static void gen_st_cond (DisasContext
*ctx
, uint32_t opc
, int rt
,
1225 int base
, int16_t offset
)
1227 const char *opn
= "st_cond";
1230 t0
= tcg_temp_local_new();
1232 gen_base_offset_addr(ctx
, t0
, base
, offset
);
1233 /* Don't do NOP if destination is zero: we must perform the actual
1236 t1
= tcg_temp_local_new();
1237 gen_load_gpr(t1
, rt
);
1239 #if defined(TARGET_MIPS64)
1241 save_cpu_state(ctx
, 0);
1242 op_st_scd(t1
, t0
, rt
, ctx
);
1247 save_cpu_state(ctx
, 1);
1248 op_st_sc(t1
, t0
, rt
, ctx
);
1252 (void)opn
; /* avoid a compiler warning */
1253 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1258 /* Load and store */
1259 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
1260 int base
, int16_t offset
)
1262 const char *opn
= "flt_ldst";
1263 TCGv t0
= tcg_temp_new();
1265 gen_base_offset_addr(ctx
, t0
, base
, offset
);
1266 /* Don't do NOP if destination is zero: we must perform the actual
1271 TCGv_i32 fp0
= tcg_temp_new_i32();
1273 tcg_gen_qemu_ld32s(t0
, t0
, ctx
->mem_idx
);
1274 tcg_gen_trunc_tl_i32(fp0
, t0
);
1275 gen_store_fpr32(fp0
, ft
);
1276 tcg_temp_free_i32(fp0
);
1282 TCGv_i32 fp0
= tcg_temp_new_i32();
1283 TCGv t1
= tcg_temp_new();
1285 gen_load_fpr32(fp0
, ft
);
1286 tcg_gen_extu_i32_tl(t1
, fp0
);
1287 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
1289 tcg_temp_free_i32(fp0
);
1295 TCGv_i64 fp0
= tcg_temp_new_i64();
1297 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
1298 gen_store_fpr64(ctx
, fp0
, ft
);
1299 tcg_temp_free_i64(fp0
);
1305 TCGv_i64 fp0
= tcg_temp_new_i64();
1307 gen_load_fpr64(ctx
, fp0
, ft
);
1308 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
1309 tcg_temp_free_i64(fp0
);
1315 generate_exception(ctx
, EXCP_RI
);
1318 (void)opn
; /* avoid a compiler warning */
1319 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1324 static void gen_cop1_ldst(CPUState
*env
, DisasContext
*ctx
,
1325 uint32_t op
, int rt
, int rs
, int16_t imm
)
1327 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
1328 check_cp1_enabled(ctx
);
1329 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
1331 generate_exception_err(ctx
, EXCP_CpU
, 1);
1335 /* Arithmetic with immediate operand */
1336 static void gen_arith_imm (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1337 int rt
, int rs
, int16_t imm
)
1339 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1340 const char *opn
= "imm arith";
1342 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1343 /* If no destination, treat it as a NOP.
1344 For addi, we must generate the overflow exception when needed. */
1351 TCGv t0
= tcg_temp_local_new();
1352 TCGv t1
= tcg_temp_new();
1353 TCGv t2
= tcg_temp_new();
1354 int l1
= gen_new_label();
1356 gen_load_gpr(t1
, rs
);
1357 tcg_gen_addi_tl(t0
, t1
, uimm
);
1358 tcg_gen_ext32s_tl(t0
, t0
);
1360 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
1361 tcg_gen_xori_tl(t2
, t0
, uimm
);
1362 tcg_gen_and_tl(t1
, t1
, t2
);
1364 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1366 /* operands of same sign, result different sign */
1367 generate_exception(ctx
, EXCP_OVERFLOW
);
1369 tcg_gen_ext32s_tl(t0
, t0
);
1370 gen_store_gpr(t0
, rt
);
1377 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1378 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
1380 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1384 #if defined(TARGET_MIPS64)
1387 TCGv t0
= tcg_temp_local_new();
1388 TCGv t1
= tcg_temp_new();
1389 TCGv t2
= tcg_temp_new();
1390 int l1
= gen_new_label();
1392 gen_load_gpr(t1
, rs
);
1393 tcg_gen_addi_tl(t0
, t1
, uimm
);
1395 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
1396 tcg_gen_xori_tl(t2
, t0
, uimm
);
1397 tcg_gen_and_tl(t1
, t1
, t2
);
1399 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1401 /* operands of same sign, result different sign */
1402 generate_exception(ctx
, EXCP_OVERFLOW
);
1404 gen_store_gpr(t0
, rt
);
1411 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1413 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1419 (void)opn
; /* avoid a compiler warning */
1420 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1423 /* Logic with immediate operand */
1424 static void gen_logic_imm (CPUState
*env
, uint32_t opc
, int rt
, int rs
, int16_t imm
)
1427 const char *opn
= "imm logic";
1430 /* If no destination, treat it as a NOP. */
1434 uimm
= (uint16_t)imm
;
1437 if (likely(rs
!= 0))
1438 tcg_gen_andi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1440 tcg_gen_movi_tl(cpu_gpr
[rt
], 0);
1445 tcg_gen_ori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1447 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1451 if (likely(rs
!= 0))
1452 tcg_gen_xori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1454 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1458 tcg_gen_movi_tl(cpu_gpr
[rt
], imm
<< 16);
1462 (void)opn
; /* avoid a compiler warning */
1463 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1466 /* Set on less than with immediate operand */
1467 static void gen_slt_imm (CPUState
*env
, uint32_t opc
, int rt
, int rs
, int16_t imm
)
1469 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1470 const char *opn
= "imm arith";
1474 /* If no destination, treat it as a NOP. */
1478 t0
= tcg_temp_new();
1479 gen_load_gpr(t0
, rs
);
1482 tcg_gen_setcondi_tl(TCG_COND_LT
, cpu_gpr
[rt
], t0
, uimm
);
1486 tcg_gen_setcondi_tl(TCG_COND_LTU
, cpu_gpr
[rt
], t0
, uimm
);
1490 (void)opn
; /* avoid a compiler warning */
1491 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1495 /* Shifts with immediate operand */
1496 static void gen_shift_imm(CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1497 int rt
, int rs
, int16_t imm
)
1499 target_ulong uimm
= ((uint16_t)imm
) & 0x1f;
1500 const char *opn
= "imm shift";
1504 /* If no destination, treat it as a NOP. */
1509 t0
= tcg_temp_new();
1510 gen_load_gpr(t0
, rs
);
1513 tcg_gen_shli_tl(t0
, t0
, uimm
);
1514 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1518 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
1523 tcg_gen_ext32u_tl(t0
, t0
);
1524 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1526 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1532 TCGv_i32 t1
= tcg_temp_new_i32();
1534 tcg_gen_trunc_tl_i32(t1
, t0
);
1535 tcg_gen_rotri_i32(t1
, t1
, uimm
);
1536 tcg_gen_ext_i32_tl(cpu_gpr
[rt
], t1
);
1537 tcg_temp_free_i32(t1
);
1539 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1543 #if defined(TARGET_MIPS64)
1545 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
);
1549 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
1553 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1558 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
);
1560 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
1565 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1569 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1573 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1577 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1582 (void)opn
; /* avoid a compiler warning */
1583 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1588 static void gen_arith (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1589 int rd
, int rs
, int rt
)
1591 const char *opn
= "arith";
1593 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1594 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1595 /* If no destination, treat it as a NOP.
1596 For add & sub, we must generate the overflow exception when needed. */
1604 TCGv t0
= tcg_temp_local_new();
1605 TCGv t1
= tcg_temp_new();
1606 TCGv t2
= tcg_temp_new();
1607 int l1
= gen_new_label();
1609 gen_load_gpr(t1
, rs
);
1610 gen_load_gpr(t2
, rt
);
1611 tcg_gen_add_tl(t0
, t1
, t2
);
1612 tcg_gen_ext32s_tl(t0
, t0
);
1613 tcg_gen_xor_tl(t1
, t1
, t2
);
1614 tcg_gen_xor_tl(t2
, t0
, t2
);
1615 tcg_gen_andc_tl(t1
, t2
, t1
);
1617 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1619 /* operands of same sign, result different sign */
1620 generate_exception(ctx
, EXCP_OVERFLOW
);
1622 gen_store_gpr(t0
, rd
);
1628 if (rs
!= 0 && rt
!= 0) {
1629 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1630 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1631 } else if (rs
== 0 && rt
!= 0) {
1632 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1633 } else if (rs
!= 0 && rt
== 0) {
1634 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1636 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1642 TCGv t0
= tcg_temp_local_new();
1643 TCGv t1
= tcg_temp_new();
1644 TCGv t2
= tcg_temp_new();
1645 int l1
= gen_new_label();
1647 gen_load_gpr(t1
, rs
);
1648 gen_load_gpr(t2
, rt
);
1649 tcg_gen_sub_tl(t0
, t1
, t2
);
1650 tcg_gen_ext32s_tl(t0
, t0
);
1651 tcg_gen_xor_tl(t2
, t1
, t2
);
1652 tcg_gen_xor_tl(t1
, t0
, t1
);
1653 tcg_gen_and_tl(t1
, t1
, t2
);
1655 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1657 /* operands of different sign, first operand and result different sign */
1658 generate_exception(ctx
, EXCP_OVERFLOW
);
1660 gen_store_gpr(t0
, rd
);
1666 if (rs
!= 0 && rt
!= 0) {
1667 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1668 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1669 } else if (rs
== 0 && rt
!= 0) {
1670 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1671 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1672 } else if (rs
!= 0 && rt
== 0) {
1673 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1675 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1679 #if defined(TARGET_MIPS64)
1682 TCGv t0
= tcg_temp_local_new();
1683 TCGv t1
= tcg_temp_new();
1684 TCGv t2
= tcg_temp_new();
1685 int l1
= gen_new_label();
1687 gen_load_gpr(t1
, rs
);
1688 gen_load_gpr(t2
, rt
);
1689 tcg_gen_add_tl(t0
, t1
, t2
);
1690 tcg_gen_xor_tl(t1
, t1
, t2
);
1691 tcg_gen_xor_tl(t2
, t0
, t2
);
1692 tcg_gen_andc_tl(t1
, t2
, t1
);
1694 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1696 /* operands of same sign, result different sign */
1697 generate_exception(ctx
, EXCP_OVERFLOW
);
1699 gen_store_gpr(t0
, rd
);
1705 if (rs
!= 0 && rt
!= 0) {
1706 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1707 } else if (rs
== 0 && rt
!= 0) {
1708 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1709 } else if (rs
!= 0 && rt
== 0) {
1710 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1712 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1718 TCGv t0
= tcg_temp_local_new();
1719 TCGv t1
= tcg_temp_new();
1720 TCGv t2
= tcg_temp_new();
1721 int l1
= gen_new_label();
1723 gen_load_gpr(t1
, rs
);
1724 gen_load_gpr(t2
, rt
);
1725 tcg_gen_sub_tl(t0
, t1
, t2
);
1726 tcg_gen_xor_tl(t2
, t1
, t2
);
1727 tcg_gen_xor_tl(t1
, t0
, t1
);
1728 tcg_gen_and_tl(t1
, t1
, t2
);
1730 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1732 /* operands of different sign, first operand and result different sign */
1733 generate_exception(ctx
, EXCP_OVERFLOW
);
1735 gen_store_gpr(t0
, rd
);
1741 if (rs
!= 0 && rt
!= 0) {
1742 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1743 } else if (rs
== 0 && rt
!= 0) {
1744 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1745 } else if (rs
!= 0 && rt
== 0) {
1746 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1748 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1754 if (likely(rs
!= 0 && rt
!= 0)) {
1755 tcg_gen_mul_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1756 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1758 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1763 (void)opn
; /* avoid a compiler warning */
1764 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1767 /* Conditional move */
1768 static void gen_cond_move (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1770 const char *opn
= "cond move";
1774 /* If no destination, treat it as a NOP.
1775 For add & sub, we must generate the overflow exception when needed. */
1780 l1
= gen_new_label();
1783 if (likely(rt
!= 0))
1784 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rt
], 0, l1
);
1790 if (likely(rt
!= 0))
1791 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rt
], 0, l1
);
1796 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1798 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1801 (void)opn
; /* avoid a compiler warning */
1802 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1806 static void gen_logic (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1808 const char *opn
= "logic";
1811 /* If no destination, treat it as a NOP. */
1818 if (likely(rs
!= 0 && rt
!= 0)) {
1819 tcg_gen_and_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1821 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1826 if (rs
!= 0 && rt
!= 0) {
1827 tcg_gen_nor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1828 } else if (rs
== 0 && rt
!= 0) {
1829 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1830 } else if (rs
!= 0 && rt
== 0) {
1831 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1833 tcg_gen_movi_tl(cpu_gpr
[rd
], ~((target_ulong
)0));
1838 if (likely(rs
!= 0 && rt
!= 0)) {
1839 tcg_gen_or_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1840 } else if (rs
== 0 && rt
!= 0) {
1841 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1842 } else if (rs
!= 0 && rt
== 0) {
1843 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1845 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1850 if (likely(rs
!= 0 && rt
!= 0)) {
1851 tcg_gen_xor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1852 } else if (rs
== 0 && rt
!= 0) {
1853 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1854 } else if (rs
!= 0 && rt
== 0) {
1855 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1857 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1862 (void)opn
; /* avoid a compiler warning */
1863 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1866 /* Set on lower than */
1867 static void gen_slt (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1869 const char *opn
= "slt";
1873 /* If no destination, treat it as a NOP. */
1878 t0
= tcg_temp_new();
1879 t1
= tcg_temp_new();
1880 gen_load_gpr(t0
, rs
);
1881 gen_load_gpr(t1
, rt
);
1884 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_gpr
[rd
], t0
, t1
);
1888 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_gpr
[rd
], t0
, t1
);
1892 (void)opn
; /* avoid a compiler warning */
1893 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1899 static void gen_shift (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1900 int rd
, int rs
, int rt
)
1902 const char *opn
= "shifts";
1906 /* If no destination, treat it as a NOP.
1907 For add & sub, we must generate the overflow exception when needed. */
1912 t0
= tcg_temp_new();
1913 t1
= tcg_temp_new();
1914 gen_load_gpr(t0
, rs
);
1915 gen_load_gpr(t1
, rt
);
1918 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1919 tcg_gen_shl_tl(t0
, t1
, t0
);
1920 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1924 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1925 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
1929 tcg_gen_ext32u_tl(t1
, t1
);
1930 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1931 tcg_gen_shr_tl(t0
, t1
, t0
);
1932 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1937 TCGv_i32 t2
= tcg_temp_new_i32();
1938 TCGv_i32 t3
= tcg_temp_new_i32();
1940 tcg_gen_trunc_tl_i32(t2
, t0
);
1941 tcg_gen_trunc_tl_i32(t3
, t1
);
1942 tcg_gen_andi_i32(t2
, t2
, 0x1f);
1943 tcg_gen_rotr_i32(t2
, t3
, t2
);
1944 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t2
);
1945 tcg_temp_free_i32(t2
);
1946 tcg_temp_free_i32(t3
);
1950 #if defined(TARGET_MIPS64)
1952 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1953 tcg_gen_shl_tl(cpu_gpr
[rd
], t1
, t0
);
1957 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1958 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
1962 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1963 tcg_gen_shr_tl(cpu_gpr
[rd
], t1
, t0
);
1967 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1968 tcg_gen_rotr_tl(cpu_gpr
[rd
], t1
, t0
);
1973 (void)opn
; /* avoid a compiler warning */
1974 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1979 /* Arithmetic on HI/LO registers */
1980 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1982 const char *opn
= "hilo";
1984 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1991 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_HI
[0]);
1995 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_LO
[0]);
2000 tcg_gen_mov_tl(cpu_HI
[0], cpu_gpr
[reg
]);
2002 tcg_gen_movi_tl(cpu_HI
[0], 0);
2007 tcg_gen_mov_tl(cpu_LO
[0], cpu_gpr
[reg
]);
2009 tcg_gen_movi_tl(cpu_LO
[0], 0);
2013 (void)opn
; /* avoid a compiler warning */
2014 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
2017 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
2020 const char *opn
= "mul/div";
2026 #if defined(TARGET_MIPS64)
2030 t0
= tcg_temp_local_new();
2031 t1
= tcg_temp_local_new();
2034 t0
= tcg_temp_new();
2035 t1
= tcg_temp_new();
2039 gen_load_gpr(t0
, rs
);
2040 gen_load_gpr(t1
, rt
);
2044 int l1
= gen_new_label();
2045 int l2
= gen_new_label();
2047 tcg_gen_ext32s_tl(t0
, t0
);
2048 tcg_gen_ext32s_tl(t1
, t1
);
2049 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2050 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, INT_MIN
, l2
);
2051 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1, l2
);
2053 tcg_gen_mov_tl(cpu_LO
[0], t0
);
2054 tcg_gen_movi_tl(cpu_HI
[0], 0);
2057 tcg_gen_div_tl(cpu_LO
[0], t0
, t1
);
2058 tcg_gen_rem_tl(cpu_HI
[0], t0
, t1
);
2059 tcg_gen_ext32s_tl(cpu_LO
[0], cpu_LO
[0]);
2060 tcg_gen_ext32s_tl(cpu_HI
[0], cpu_HI
[0]);
2067 int l1
= gen_new_label();
2069 tcg_gen_ext32u_tl(t0
, t0
);
2070 tcg_gen_ext32u_tl(t1
, t1
);
2071 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2072 tcg_gen_divu_tl(cpu_LO
[0], t0
, t1
);
2073 tcg_gen_remu_tl(cpu_HI
[0], t0
, t1
);
2074 tcg_gen_ext32s_tl(cpu_LO
[0], cpu_LO
[0]);
2075 tcg_gen_ext32s_tl(cpu_HI
[0], cpu_HI
[0]);
2082 TCGv_i64 t2
= tcg_temp_new_i64();
2083 TCGv_i64 t3
= tcg_temp_new_i64();
2085 tcg_gen_ext_tl_i64(t2
, t0
);
2086 tcg_gen_ext_tl_i64(t3
, t1
);
2087 tcg_gen_mul_i64(t2
, t2
, t3
);
2088 tcg_temp_free_i64(t3
);
2089 tcg_gen_trunc_i64_tl(t0
, t2
);
2090 tcg_gen_shri_i64(t2
, t2
, 32);
2091 tcg_gen_trunc_i64_tl(t1
, t2
);
2092 tcg_temp_free_i64(t2
);
2093 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2094 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2100 TCGv_i64 t2
= tcg_temp_new_i64();
2101 TCGv_i64 t3
= tcg_temp_new_i64();
2103 tcg_gen_ext32u_tl(t0
, t0
);
2104 tcg_gen_ext32u_tl(t1
, t1
);
2105 tcg_gen_extu_tl_i64(t2
, t0
);
2106 tcg_gen_extu_tl_i64(t3
, t1
);
2107 tcg_gen_mul_i64(t2
, t2
, t3
);
2108 tcg_temp_free_i64(t3
);
2109 tcg_gen_trunc_i64_tl(t0
, t2
);
2110 tcg_gen_shri_i64(t2
, t2
, 32);
2111 tcg_gen_trunc_i64_tl(t1
, t2
);
2112 tcg_temp_free_i64(t2
);
2113 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2114 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2118 #if defined(TARGET_MIPS64)
2121 int l1
= gen_new_label();
2122 int l2
= gen_new_label();
2124 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2125 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
2126 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
2127 tcg_gen_mov_tl(cpu_LO
[0], t0
);
2128 tcg_gen_movi_tl(cpu_HI
[0], 0);
2131 tcg_gen_div_i64(cpu_LO
[0], t0
, t1
);
2132 tcg_gen_rem_i64(cpu_HI
[0], t0
, t1
);
2139 int l1
= gen_new_label();
2141 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2142 tcg_gen_divu_i64(cpu_LO
[0], t0
, t1
);
2143 tcg_gen_remu_i64(cpu_HI
[0], t0
, t1
);
2149 gen_helper_dmult(t0
, t1
);
2153 gen_helper_dmultu(t0
, t1
);
2159 TCGv_i64 t2
= tcg_temp_new_i64();
2160 TCGv_i64 t3
= tcg_temp_new_i64();
2162 tcg_gen_ext_tl_i64(t2
, t0
);
2163 tcg_gen_ext_tl_i64(t3
, t1
);
2164 tcg_gen_mul_i64(t2
, t2
, t3
);
2165 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2166 tcg_gen_add_i64(t2
, t2
, t3
);
2167 tcg_temp_free_i64(t3
);
2168 tcg_gen_trunc_i64_tl(t0
, t2
);
2169 tcg_gen_shri_i64(t2
, t2
, 32);
2170 tcg_gen_trunc_i64_tl(t1
, t2
);
2171 tcg_temp_free_i64(t2
);
2172 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2173 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2179 TCGv_i64 t2
= tcg_temp_new_i64();
2180 TCGv_i64 t3
= tcg_temp_new_i64();
2182 tcg_gen_ext32u_tl(t0
, t0
);
2183 tcg_gen_ext32u_tl(t1
, t1
);
2184 tcg_gen_extu_tl_i64(t2
, t0
);
2185 tcg_gen_extu_tl_i64(t3
, t1
);
2186 tcg_gen_mul_i64(t2
, t2
, t3
);
2187 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2188 tcg_gen_add_i64(t2
, t2
, t3
);
2189 tcg_temp_free_i64(t3
);
2190 tcg_gen_trunc_i64_tl(t0
, t2
);
2191 tcg_gen_shri_i64(t2
, t2
, 32);
2192 tcg_gen_trunc_i64_tl(t1
, t2
);
2193 tcg_temp_free_i64(t2
);
2194 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2195 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2201 TCGv_i64 t2
= tcg_temp_new_i64();
2202 TCGv_i64 t3
= tcg_temp_new_i64();
2204 tcg_gen_ext_tl_i64(t2
, t0
);
2205 tcg_gen_ext_tl_i64(t3
, t1
);
2206 tcg_gen_mul_i64(t2
, t2
, t3
);
2207 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2208 tcg_gen_sub_i64(t2
, t3
, t2
);
2209 tcg_temp_free_i64(t3
);
2210 tcg_gen_trunc_i64_tl(t0
, t2
);
2211 tcg_gen_shri_i64(t2
, t2
, 32);
2212 tcg_gen_trunc_i64_tl(t1
, t2
);
2213 tcg_temp_free_i64(t2
);
2214 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2215 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2221 TCGv_i64 t2
= tcg_temp_new_i64();
2222 TCGv_i64 t3
= tcg_temp_new_i64();
2224 tcg_gen_ext32u_tl(t0
, t0
);
2225 tcg_gen_ext32u_tl(t1
, t1
);
2226 tcg_gen_extu_tl_i64(t2
, t0
);
2227 tcg_gen_extu_tl_i64(t3
, t1
);
2228 tcg_gen_mul_i64(t2
, t2
, t3
);
2229 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2230 tcg_gen_sub_i64(t2
, t3
, t2
);
2231 tcg_temp_free_i64(t3
);
2232 tcg_gen_trunc_i64_tl(t0
, t2
);
2233 tcg_gen_shri_i64(t2
, t2
, 32);
2234 tcg_gen_trunc_i64_tl(t1
, t2
);
2235 tcg_temp_free_i64(t2
);
2236 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2237 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2243 generate_exception(ctx
, EXCP_RI
);
2246 (void)opn
; /* avoid a compiler warning */
2247 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
2253 static void gen_mul_vr54xx (DisasContext
*ctx
, uint32_t opc
,
2254 int rd
, int rs
, int rt
)
2256 const char *opn
= "mul vr54xx";
2257 TCGv t0
= tcg_temp_new();
2258 TCGv t1
= tcg_temp_new();
2260 gen_load_gpr(t0
, rs
);
2261 gen_load_gpr(t1
, rt
);
2264 case OPC_VR54XX_MULS
:
2265 gen_helper_muls(t0
, t0
, t1
);
2268 case OPC_VR54XX_MULSU
:
2269 gen_helper_mulsu(t0
, t0
, t1
);
2272 case OPC_VR54XX_MACC
:
2273 gen_helper_macc(t0
, t0
, t1
);
2276 case OPC_VR54XX_MACCU
:
2277 gen_helper_maccu(t0
, t0
, t1
);
2280 case OPC_VR54XX_MSAC
:
2281 gen_helper_msac(t0
, t0
, t1
);
2284 case OPC_VR54XX_MSACU
:
2285 gen_helper_msacu(t0
, t0
, t1
);
2288 case OPC_VR54XX_MULHI
:
2289 gen_helper_mulhi(t0
, t0
, t1
);
2292 case OPC_VR54XX_MULHIU
:
2293 gen_helper_mulhiu(t0
, t0
, t1
);
2296 case OPC_VR54XX_MULSHI
:
2297 gen_helper_mulshi(t0
, t0
, t1
);
2300 case OPC_VR54XX_MULSHIU
:
2301 gen_helper_mulshiu(t0
, t0
, t1
);
2304 case OPC_VR54XX_MACCHI
:
2305 gen_helper_macchi(t0
, t0
, t1
);
2308 case OPC_VR54XX_MACCHIU
:
2309 gen_helper_macchiu(t0
, t0
, t1
);
2312 case OPC_VR54XX_MSACHI
:
2313 gen_helper_msachi(t0
, t0
, t1
);
2316 case OPC_VR54XX_MSACHIU
:
2317 gen_helper_msachiu(t0
, t0
, t1
);
2321 MIPS_INVAL("mul vr54xx");
2322 generate_exception(ctx
, EXCP_RI
);
2325 gen_store_gpr(t0
, rd
);
2326 (void)opn
; /* avoid a compiler warning */
2327 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
2334 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
2337 const char *opn
= "CLx";
2345 t0
= tcg_temp_new();
2346 gen_load_gpr(t0
, rs
);
2349 gen_helper_clo(cpu_gpr
[rd
], t0
);
2353 gen_helper_clz(cpu_gpr
[rd
], t0
);
2356 #if defined(TARGET_MIPS64)
2358 gen_helper_dclo(cpu_gpr
[rd
], t0
);
2362 gen_helper_dclz(cpu_gpr
[rd
], t0
);
2367 (void)opn
; /* avoid a compiler warning */
2368 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
2372 /* Godson integer instructions */
2373 static void gen_loongson_integer (DisasContext
*ctx
, uint32_t opc
,
2374 int rd
, int rs
, int rt
)
2376 const char *opn
= "loongson";
2388 case OPC_MULTU_G_2E
:
2389 case OPC_MULTU_G_2F
:
2390 #if defined(TARGET_MIPS64)
2391 case OPC_DMULT_G_2E
:
2392 case OPC_DMULT_G_2F
:
2393 case OPC_DMULTU_G_2E
:
2394 case OPC_DMULTU_G_2F
:
2396 t0
= tcg_temp_new();
2397 t1
= tcg_temp_new();
2400 t0
= tcg_temp_local_new();
2401 t1
= tcg_temp_local_new();
2405 gen_load_gpr(t0
, rs
);
2406 gen_load_gpr(t1
, rt
);
2411 tcg_gen_mul_tl(cpu_gpr
[rd
], t0
, t1
);
2412 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
2415 case OPC_MULTU_G_2E
:
2416 case OPC_MULTU_G_2F
:
2417 tcg_gen_ext32u_tl(t0
, t0
);
2418 tcg_gen_ext32u_tl(t1
, t1
);
2419 tcg_gen_mul_tl(cpu_gpr
[rd
], t0
, t1
);
2420 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
2426 int l1
= gen_new_label();
2427 int l2
= gen_new_label();
2428 int l3
= gen_new_label();
2429 tcg_gen_ext32s_tl(t0
, t0
);
2430 tcg_gen_ext32s_tl(t1
, t1
);
2431 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
2432 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2435 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, INT_MIN
, l2
);
2436 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1, l2
);
2437 tcg_gen_mov_tl(cpu_gpr
[rd
], t0
);
2440 tcg_gen_div_tl(cpu_gpr
[rd
], t0
, t1
);
2441 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
2449 int l1
= gen_new_label();
2450 int l2
= gen_new_label();
2451 tcg_gen_ext32u_tl(t0
, t0
);
2452 tcg_gen_ext32u_tl(t1
, t1
);
2453 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
2454 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2457 tcg_gen_divu_tl(cpu_gpr
[rd
], t0
, t1
);
2458 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
2466 int l1
= gen_new_label();
2467 int l2
= gen_new_label();
2468 int l3
= gen_new_label();
2469 tcg_gen_ext32u_tl(t0
, t0
);
2470 tcg_gen_ext32u_tl(t1
, t1
);
2471 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2472 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, INT_MIN
, l2
);
2473 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1, l2
);
2475 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2478 tcg_gen_rem_tl(cpu_gpr
[rd
], t0
, t1
);
2479 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
2487 int l1
= gen_new_label();
2488 int l2
= gen_new_label();
2489 tcg_gen_ext32u_tl(t0
, t0
);
2490 tcg_gen_ext32u_tl(t1
, t1
);
2491 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
2492 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2495 tcg_gen_remu_tl(cpu_gpr
[rd
], t0
, t1
);
2496 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
2501 #if defined(TARGET_MIPS64)
2502 case OPC_DMULT_G_2E
:
2503 case OPC_DMULT_G_2F
:
2504 tcg_gen_mul_tl(cpu_gpr
[rd
], t0
, t1
);
2507 case OPC_DMULTU_G_2E
:
2508 case OPC_DMULTU_G_2F
:
2509 tcg_gen_mul_tl(cpu_gpr
[rd
], t0
, t1
);
2515 int l1
= gen_new_label();
2516 int l2
= gen_new_label();
2517 int l3
= gen_new_label();
2518 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
2519 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2522 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
2523 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
2524 tcg_gen_mov_tl(cpu_gpr
[rd
], t0
);
2527 tcg_gen_div_tl(cpu_gpr
[rd
], t0
, t1
);
2532 case OPC_DDIVU_G_2E
:
2533 case OPC_DDIVU_G_2F
:
2535 int l1
= gen_new_label();
2536 int l2
= gen_new_label();
2537 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
2538 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2541 tcg_gen_divu_tl(cpu_gpr
[rd
], t0
, t1
);
2549 int l1
= gen_new_label();
2550 int l2
= gen_new_label();
2551 int l3
= gen_new_label();
2552 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2553 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
2554 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
2556 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2559 tcg_gen_rem_tl(cpu_gpr
[rd
], t0
, t1
);
2564 case OPC_DMODU_G_2E
:
2565 case OPC_DMODU_G_2F
:
2567 int l1
= gen_new_label();
2568 int l2
= gen_new_label();
2569 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, 0, l1
);
2570 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
2573 tcg_gen_remu_tl(cpu_gpr
[rd
], t0
, t1
);
2581 (void)opn
; /* avoid a compiler warning */
2582 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
2588 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
2589 int rs
, int rt
, int16_t imm
)
2592 TCGv t0
= tcg_temp_new();
2593 TCGv t1
= tcg_temp_new();
2596 /* Load needed operands */
2604 /* Compare two registers */
2606 gen_load_gpr(t0
, rs
);
2607 gen_load_gpr(t1
, rt
);
2617 /* Compare register to immediate */
2618 if (rs
!= 0 || imm
!= 0) {
2619 gen_load_gpr(t0
, rs
);
2620 tcg_gen_movi_tl(t1
, (int32_t)imm
);
2627 case OPC_TEQ
: /* rs == rs */
2628 case OPC_TEQI
: /* r0 == 0 */
2629 case OPC_TGE
: /* rs >= rs */
2630 case OPC_TGEI
: /* r0 >= 0 */
2631 case OPC_TGEU
: /* rs >= rs unsigned */
2632 case OPC_TGEIU
: /* r0 >= 0 unsigned */
2634 generate_exception(ctx
, EXCP_TRAP
);
2636 case OPC_TLT
: /* rs < rs */
2637 case OPC_TLTI
: /* r0 < 0 */
2638 case OPC_TLTU
: /* rs < rs unsigned */
2639 case OPC_TLTIU
: /* r0 < 0 unsigned */
2640 case OPC_TNE
: /* rs != rs */
2641 case OPC_TNEI
: /* r0 != 0 */
2642 /* Never trap: treat as NOP. */
2646 int l1
= gen_new_label();
2651 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, t1
, l1
);
2655 tcg_gen_brcond_tl(TCG_COND_LT
, t0
, t1
, l1
);
2659 tcg_gen_brcond_tl(TCG_COND_LTU
, t0
, t1
, l1
);
2663 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
2667 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
2671 tcg_gen_brcond_tl(TCG_COND_EQ
, t0
, t1
, l1
);
2674 generate_exception(ctx
, EXCP_TRAP
);
2681 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
2683 TranslationBlock
*tb
;
2685 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
2686 likely(!ctx
->singlestep_enabled
)) {
2689 tcg_gen_exit_tb((long)tb
+ n
);
2692 if (ctx
->singlestep_enabled
) {
2693 save_cpu_state(ctx
, 0);
2694 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
2700 /* Branches (before delay slot) */
2701 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
2703 int rs
, int rt
, int32_t offset
)
2705 target_ulong btgt
= -1;
2707 int bcond_compute
= 0;
2708 TCGv t0
= tcg_temp_new();
2709 TCGv t1
= tcg_temp_new();
2711 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
2712 #ifdef MIPS_DEBUG_DISAS
2713 LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n", ctx
->pc
);
2715 generate_exception(ctx
, EXCP_RI
);
2719 /* Load needed operands */
2725 /* Compare two registers */
2727 gen_load_gpr(t0
, rs
);
2728 gen_load_gpr(t1
, rt
);
2731 btgt
= ctx
->pc
+ insn_bytes
+ offset
;
2747 /* Compare to zero */
2749 gen_load_gpr(t0
, rs
);
2752 btgt
= ctx
->pc
+ insn_bytes
+ offset
;
2759 /* Jump to immediate */
2760 btgt
= ((ctx
->pc
+ insn_bytes
) & (int32_t)0xF0000000) | (uint32_t)offset
;
2766 /* Jump to register */
2767 if (offset
!= 0 && offset
!= 16) {
2768 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2769 others are reserved. */
2770 MIPS_INVAL("jump hint");
2771 generate_exception(ctx
, EXCP_RI
);
2774 gen_load_gpr(btarget
, rs
);
2777 MIPS_INVAL("branch/jump");
2778 generate_exception(ctx
, EXCP_RI
);
2781 if (bcond_compute
== 0) {
2782 /* No condition to be computed */
2784 case OPC_BEQ
: /* rx == rx */
2785 case OPC_BEQL
: /* rx == rx likely */
2786 case OPC_BGEZ
: /* 0 >= 0 */
2787 case OPC_BGEZL
: /* 0 >= 0 likely */
2788 case OPC_BLEZ
: /* 0 <= 0 */
2789 case OPC_BLEZL
: /* 0 <= 0 likely */
2791 ctx
->hflags
|= MIPS_HFLAG_B
;
2792 MIPS_DEBUG("balways");
2795 case OPC_BGEZAL
: /* 0 >= 0 */
2796 case OPC_BGEZALL
: /* 0 >= 0 likely */
2797 ctx
->hflags
|= (opc
== OPC_BGEZALS
2799 : MIPS_HFLAG_BDS32
);
2800 /* Always take and link */
2802 ctx
->hflags
|= MIPS_HFLAG_B
;
2803 MIPS_DEBUG("balways and link");
2805 case OPC_BNE
: /* rx != rx */
2806 case OPC_BGTZ
: /* 0 > 0 */
2807 case OPC_BLTZ
: /* 0 < 0 */
2809 MIPS_DEBUG("bnever (NOP)");
2812 case OPC_BLTZAL
: /* 0 < 0 */
2813 ctx
->hflags
|= (opc
== OPC_BLTZALS
2815 : MIPS_HFLAG_BDS32
);
2816 /* Handle as an unconditional branch to get correct delay
2819 btgt
= ctx
->pc
+ (opc
== OPC_BLTZALS
? 6 : 8);
2820 ctx
->hflags
|= MIPS_HFLAG_B
;
2821 MIPS_DEBUG("bnever and link");
2823 case OPC_BLTZALL
: /* 0 < 0 likely */
2824 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 8);
2825 /* Skip the instruction in the delay slot */
2826 MIPS_DEBUG("bnever, link and skip");
2829 case OPC_BNEL
: /* rx != rx likely */
2830 case OPC_BGTZL
: /* 0 > 0 likely */
2831 case OPC_BLTZL
: /* 0 < 0 likely */
2832 /* Skip the instruction in the delay slot */
2833 MIPS_DEBUG("bnever and skip");
2837 ctx
->hflags
|= MIPS_HFLAG_B
;
2838 MIPS_DEBUG("j " TARGET_FMT_lx
, btgt
);
2842 ctx
->hflags
|= MIPS_HFLAG_BX
;
2847 ctx
->hflags
|= MIPS_HFLAG_B
;
2848 ctx
->hflags
|= ((opc
== OPC_JALS
|| opc
== OPC_JALXS
)
2850 : MIPS_HFLAG_BDS32
);
2851 MIPS_DEBUG("jal " TARGET_FMT_lx
, btgt
);
2854 ctx
->hflags
|= MIPS_HFLAG_BR
;
2855 if (insn_bytes
== 4)
2856 ctx
->hflags
|= MIPS_HFLAG_BDS32
;
2857 MIPS_DEBUG("jr %s", regnames
[rs
]);
2863 ctx
->hflags
|= MIPS_HFLAG_BR
;
2864 ctx
->hflags
|= (opc
== OPC_JALRS
2866 : MIPS_HFLAG_BDS32
);
2867 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
2870 MIPS_INVAL("branch/jump");
2871 generate_exception(ctx
, EXCP_RI
);
2877 tcg_gen_setcond_tl(TCG_COND_EQ
, bcond
, t0
, t1
);
2878 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
2879 regnames
[rs
], regnames
[rt
], btgt
);
2882 tcg_gen_setcond_tl(TCG_COND_EQ
, bcond
, t0
, t1
);
2883 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
2884 regnames
[rs
], regnames
[rt
], btgt
);
2887 tcg_gen_setcond_tl(TCG_COND_NE
, bcond
, t0
, t1
);
2888 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
2889 regnames
[rs
], regnames
[rt
], btgt
);
2892 tcg_gen_setcond_tl(TCG_COND_NE
, bcond
, t0
, t1
);
2893 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
2894 regnames
[rs
], regnames
[rt
], btgt
);
2897 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
2898 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2901 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
2902 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2906 ctx
->hflags
|= (opc
== OPC_BGEZALS
2908 : MIPS_HFLAG_BDS32
);
2909 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
2910 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2914 tcg_gen_setcondi_tl(TCG_COND_GE
, bcond
, t0
, 0);
2916 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2919 tcg_gen_setcondi_tl(TCG_COND_GT
, bcond
, t0
, 0);
2920 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2923 tcg_gen_setcondi_tl(TCG_COND_GT
, bcond
, t0
, 0);
2924 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2927 tcg_gen_setcondi_tl(TCG_COND_LE
, bcond
, t0
, 0);
2928 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2931 tcg_gen_setcondi_tl(TCG_COND_LE
, bcond
, t0
, 0);
2932 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2935 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
2936 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2939 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
2940 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2944 ctx
->hflags
|= (opc
== OPC_BLTZALS
2946 : MIPS_HFLAG_BDS32
);
2947 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
2949 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2951 ctx
->hflags
|= MIPS_HFLAG_BC
;
2954 tcg_gen_setcondi_tl(TCG_COND_LT
, bcond
, t0
, 0);
2956 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2958 ctx
->hflags
|= MIPS_HFLAG_BL
;
2961 MIPS_INVAL("conditional branch/jump");
2962 generate_exception(ctx
, EXCP_RI
);
2966 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
2967 blink
, ctx
->hflags
, btgt
);
2969 ctx
->btarget
= btgt
;
2971 int post_delay
= insn_bytes
;
2972 int lowbit
= !!(ctx
->hflags
& MIPS_HFLAG_M16
);
2974 if (opc
!= OPC_JALRC
)
2975 post_delay
+= ((ctx
->hflags
& MIPS_HFLAG_BDS16
) ? 2 : 4);
2977 tcg_gen_movi_tl(cpu_gpr
[blink
], ctx
->pc
+ post_delay
+ lowbit
);
2981 if (insn_bytes
== 2)
2982 ctx
->hflags
|= MIPS_HFLAG_B16
;
2987 /* special3 bitfield operations */
2988 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
2989 int rs
, int lsb
, int msb
)
2991 TCGv t0
= tcg_temp_new();
2992 TCGv t1
= tcg_temp_new();
2995 gen_load_gpr(t1
, rs
);
3000 tcg_gen_shri_tl(t0
, t1
, lsb
);
3002 tcg_gen_andi_tl(t0
, t0
, (1 << (msb
+ 1)) - 1);
3004 tcg_gen_ext32s_tl(t0
, t0
);
3007 #if defined(TARGET_MIPS64)
3009 tcg_gen_shri_tl(t0
, t1
, lsb
);
3011 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1 + 32)) - 1);
3015 tcg_gen_shri_tl(t0
, t1
, lsb
+ 32);
3016 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
3019 tcg_gen_shri_tl(t0
, t1
, lsb
);
3020 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
3026 mask
= ((msb
- lsb
+ 1 < 32) ? ((1 << (msb
- lsb
+ 1)) - 1) : ~0) << lsb
;
3027 gen_load_gpr(t0
, rt
);
3028 tcg_gen_andi_tl(t0
, t0
, ~mask
);
3029 tcg_gen_shli_tl(t1
, t1
, lsb
);
3030 tcg_gen_andi_tl(t1
, t1
, mask
);
3031 tcg_gen_or_tl(t0
, t0
, t1
);
3032 tcg_gen_ext32s_tl(t0
, t0
);
3034 #if defined(TARGET_MIPS64)
3038 mask
= ((msb
- lsb
+ 1 + 32 < 64) ? ((1ULL << (msb
- lsb
+ 1 + 32)) - 1) : ~0ULL) << lsb
;
3039 gen_load_gpr(t0
, rt
);
3040 tcg_gen_andi_tl(t0
, t0
, ~mask
);
3041 tcg_gen_shli_tl(t1
, t1
, lsb
);
3042 tcg_gen_andi_tl(t1
, t1
, mask
);
3043 tcg_gen_or_tl(t0
, t0
, t1
);
3048 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << (lsb
+ 32);
3049 gen_load_gpr(t0
, rt
);
3050 tcg_gen_andi_tl(t0
, t0
, ~mask
);
3051 tcg_gen_shli_tl(t1
, t1
, lsb
+ 32);
3052 tcg_gen_andi_tl(t1
, t1
, mask
);
3053 tcg_gen_or_tl(t0
, t0
, t1
);
3058 gen_load_gpr(t0
, rt
);
3059 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
3060 gen_load_gpr(t0
, rt
);
3061 tcg_gen_andi_tl(t0
, t0
, ~mask
);
3062 tcg_gen_shli_tl(t1
, t1
, lsb
);
3063 tcg_gen_andi_tl(t1
, t1
, mask
);
3064 tcg_gen_or_tl(t0
, t0
, t1
);
3069 MIPS_INVAL("bitops");
3070 generate_exception(ctx
, EXCP_RI
);
3075 gen_store_gpr(t0
, rt
);
3080 static void gen_bshfl (DisasContext
*ctx
, uint32_t op2
, int rt
, int rd
)
3085 /* If no destination, treat it as a NOP. */
3090 t0
= tcg_temp_new();
3091 gen_load_gpr(t0
, rt
);
3095 TCGv t1
= tcg_temp_new();
3097 tcg_gen_shri_tl(t1
, t0
, 8);
3098 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF);
3099 tcg_gen_shli_tl(t0
, t0
, 8);
3100 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF);
3101 tcg_gen_or_tl(t0
, t0
, t1
);
3103 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
3107 tcg_gen_ext8s_tl(cpu_gpr
[rd
], t0
);
3110 tcg_gen_ext16s_tl(cpu_gpr
[rd
], t0
);
3112 #if defined(TARGET_MIPS64)
3115 TCGv t1
= tcg_temp_new();
3117 tcg_gen_shri_tl(t1
, t0
, 8);
3118 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF00FF00FFULL
);
3119 tcg_gen_shli_tl(t0
, t0
, 8);
3120 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF00FF00FFULL
);
3121 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
3127 TCGv t1
= tcg_temp_new();
3129 tcg_gen_shri_tl(t1
, t0
, 16);
3130 tcg_gen_andi_tl(t1
, t1
, 0x0000FFFF0000FFFFULL
);
3131 tcg_gen_shli_tl(t0
, t0
, 16);
3132 tcg_gen_andi_tl(t0
, t0
, ~0x0000FFFF0000FFFFULL
);
3133 tcg_gen_or_tl(t0
, t0
, t1
);
3134 tcg_gen_shri_tl(t1
, t0
, 32);
3135 tcg_gen_shli_tl(t0
, t0
, 32);
3136 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
3142 MIPS_INVAL("bsfhl");
3143 generate_exception(ctx
, EXCP_RI
);
3150 #ifndef CONFIG_USER_ONLY
3151 /* CP0 (MMU and control) */
3152 static inline void gen_mfc0_load32 (TCGv arg
, target_ulong off
)
3154 TCGv_i32 t0
= tcg_temp_new_i32();
3156 tcg_gen_ld_i32(t0
, cpu_env
, off
);
3157 tcg_gen_ext_i32_tl(arg
, t0
);
3158 tcg_temp_free_i32(t0
);
3161 static inline void gen_mfc0_load64 (TCGv arg
, target_ulong off
)
3163 tcg_gen_ld_tl(arg
, cpu_env
, off
);
3164 tcg_gen_ext32s_tl(arg
, arg
);
3167 static inline void gen_mtc0_store32 (TCGv arg
, target_ulong off
)
3169 TCGv_i32 t0
= tcg_temp_new_i32();
3171 tcg_gen_trunc_tl_i32(t0
, arg
);
3172 tcg_gen_st_i32(t0
, cpu_env
, off
);
3173 tcg_temp_free_i32(t0
);
3176 static inline void gen_mtc0_store64 (TCGv arg
, target_ulong off
)
3178 tcg_gen_ext32s_tl(arg
, arg
);
3179 tcg_gen_st_tl(arg
, cpu_env
, off
);
3182 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
3184 const char *rn
= "invalid";
3187 check_insn(env
, ctx
, ISA_MIPS32
);
3193 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Index
));
3197 check_insn(env
, ctx
, ASE_MT
);
3198 gen_helper_mfc0_mvpcontrol(arg
);
3202 check_insn(env
, ctx
, ASE_MT
);
3203 gen_helper_mfc0_mvpconf0(arg
);
3207 check_insn(env
, ctx
, ASE_MT
);
3208 gen_helper_mfc0_mvpconf1(arg
);
3218 gen_helper_mfc0_random(arg
);
3222 check_insn(env
, ctx
, ASE_MT
);
3223 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEControl
));
3227 check_insn(env
, ctx
, ASE_MT
);
3228 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf0
));
3232 check_insn(env
, ctx
, ASE_MT
);
3233 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf1
));
3237 check_insn(env
, ctx
, ASE_MT
);
3238 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_YQMask
));
3242 check_insn(env
, ctx
, ASE_MT
);
3243 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_VPESchedule
));
3247 check_insn(env
, ctx
, ASE_MT
);
3248 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_VPEScheFBack
));
3249 rn
= "VPEScheFBack";
3252 check_insn(env
, ctx
, ASE_MT
);
3253 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEOpt
));
3263 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
3264 tcg_gen_ext32s_tl(arg
, arg
);
3268 check_insn(env
, ctx
, ASE_MT
);
3269 gen_helper_mfc0_tcstatus(arg
);
3273 check_insn(env
, ctx
, ASE_MT
);
3274 gen_helper_mfc0_tcbind(arg
);
3278 check_insn(env
, ctx
, ASE_MT
);
3279 gen_helper_mfc0_tcrestart(arg
);
3283 check_insn(env
, ctx
, ASE_MT
);
3284 gen_helper_mfc0_tchalt(arg
);
3288 check_insn(env
, ctx
, ASE_MT
);
3289 gen_helper_mfc0_tccontext(arg
);
3293 check_insn(env
, ctx
, ASE_MT
);
3294 gen_helper_mfc0_tcschedule(arg
);
3298 check_insn(env
, ctx
, ASE_MT
);
3299 gen_helper_mfc0_tcschefback(arg
);
3309 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
3310 tcg_gen_ext32s_tl(arg
, arg
);
3320 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_Context
));
3321 tcg_gen_ext32s_tl(arg
, arg
);
3325 // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
3326 rn
= "ContextConfig";
3335 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageMask
));
3339 check_insn(env
, ctx
, ISA_MIPS32R2
);
3340 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageGrain
));
3350 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Wired
));
3354 check_insn(env
, ctx
, ISA_MIPS32R2
);
3355 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf0
));
3359 check_insn(env
, ctx
, ISA_MIPS32R2
);
3360 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf1
));
3364 check_insn(env
, ctx
, ISA_MIPS32R2
);
3365 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf2
));
3369 check_insn(env
, ctx
, ISA_MIPS32R2
);
3370 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf3
));
3374 check_insn(env
, ctx
, ISA_MIPS32R2
);
3375 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf4
));
3385 check_insn(env
, ctx
, ISA_MIPS32R2
);
3386 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_HWREna
));
3396 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
3397 tcg_gen_ext32s_tl(arg
, arg
);
3407 /* Mark as an IO operation because we read the time. */
3410 gen_helper_mfc0_count(arg
);
3413 ctx
->bstate
= BS_STOP
;
3417 /* 6,7 are implementation dependent */
3425 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
3426 tcg_gen_ext32s_tl(arg
, arg
);
3436 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Compare
));
3439 /* 6,7 are implementation dependent */
3447 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Status
));
3451 check_insn(env
, ctx
, ISA_MIPS32R2
);
3452 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_IntCtl
));
3456 check_insn(env
, ctx
, ISA_MIPS32R2
);
3457 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSCtl
));
3461 check_insn(env
, ctx
, ISA_MIPS32R2
);
3462 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSMap
));
3472 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Cause
));
3482 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
3483 tcg_gen_ext32s_tl(arg
, arg
);
3493 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PRid
));
3497 check_insn(env
, ctx
, ISA_MIPS32R2
);
3498 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_EBase
));
3508 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config0
));
3512 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config1
));
3516 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config2
));
3520 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config3
));
3523 /* 4,5 are reserved */
3524 /* 6,7 are implementation dependent */
3526 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config6
));
3530 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config7
));
3540 gen_helper_mfc0_lladdr(arg
);
3550 gen_helper_1i(mfc0_watchlo
, arg
, sel
);
3560 gen_helper_1i(mfc0_watchhi
, arg
, sel
);
3570 #if defined(TARGET_MIPS64)
3571 check_insn(env
, ctx
, ISA_MIPS3
);
3572 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
3573 tcg_gen_ext32s_tl(arg
, arg
);
3582 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3585 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Framemask
));
3593 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3594 rn
= "'Diagnostic"; /* implementation dependent */
3599 gen_helper_mfc0_debug(arg
); /* EJTAG support */
3603 // gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
3604 rn
= "TraceControl";
3607 // gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
3608 rn
= "TraceControl2";
3611 // gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
3612 rn
= "UserTraceData";
3615 // gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
3626 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
3627 tcg_gen_ext32s_tl(arg
, arg
);
3637 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Performance0
));
3638 rn
= "Performance0";
3641 // gen_helper_mfc0_performance1(arg);
3642 rn
= "Performance1";
3645 // gen_helper_mfc0_performance2(arg);
3646 rn
= "Performance2";
3649 // gen_helper_mfc0_performance3(arg);
3650 rn
= "Performance3";
3653 // gen_helper_mfc0_performance4(arg);
3654 rn
= "Performance4";
3657 // gen_helper_mfc0_performance5(arg);
3658 rn
= "Performance5";
3661 // gen_helper_mfc0_performance6(arg);
3662 rn
= "Performance6";
3665 // gen_helper_mfc0_performance7(arg);
3666 rn
= "Performance7";
3673 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3679 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3692 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagLo
));
3699 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataLo
));
3712 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagHi
));
3719 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataHi
));
3729 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
3730 tcg_gen_ext32s_tl(arg
, arg
);
3741 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DESAVE
));
3751 (void)rn
; /* avoid a compiler warning */
3752 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3756 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3757 generate_exception(ctx
, EXCP_RI
);
3760 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
3762 const char *rn
= "invalid";
3765 check_insn(env
, ctx
, ISA_MIPS32
);
3774 gen_helper_mtc0_index(arg
);
3778 check_insn(env
, ctx
, ASE_MT
);
3779 gen_helper_mtc0_mvpcontrol(arg
);
3783 check_insn(env
, ctx
, ASE_MT
);
3788 check_insn(env
, ctx
, ASE_MT
);
3803 check_insn(env
, ctx
, ASE_MT
);
3804 gen_helper_mtc0_vpecontrol(arg
);
3808 check_insn(env
, ctx
, ASE_MT
);
3809 gen_helper_mtc0_vpeconf0(arg
);
3813 check_insn(env
, ctx
, ASE_MT
);
3814 gen_helper_mtc0_vpeconf1(arg
);
3818 check_insn(env
, ctx
, ASE_MT
);
3819 gen_helper_mtc0_yqmask(arg
);
3823 check_insn(env
, ctx
, ASE_MT
);
3824 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_VPESchedule
));
3828 check_insn(env
, ctx
, ASE_MT
);
3829 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_VPEScheFBack
));
3830 rn
= "VPEScheFBack";
3833 check_insn(env
, ctx
, ASE_MT
);
3834 gen_helper_mtc0_vpeopt(arg
);
3844 gen_helper_mtc0_entrylo0(arg
);
3848 check_insn(env
, ctx
, ASE_MT
);
3849 gen_helper_mtc0_tcstatus(arg
);
3853 check_insn(env
, ctx
, ASE_MT
);
3854 gen_helper_mtc0_tcbind(arg
);
3858 check_insn(env
, ctx
, ASE_MT
);
3859 gen_helper_mtc0_tcrestart(arg
);
3863 check_insn(env
, ctx
, ASE_MT
);
3864 gen_helper_mtc0_tchalt(arg
);
3868 check_insn(env
, ctx
, ASE_MT
);
3869 gen_helper_mtc0_tccontext(arg
);
3873 check_insn(env
, ctx
, ASE_MT
);
3874 gen_helper_mtc0_tcschedule(arg
);
3878 check_insn(env
, ctx
, ASE_MT
);
3879 gen_helper_mtc0_tcschefback(arg
);
3889 gen_helper_mtc0_entrylo1(arg
);
3899 gen_helper_mtc0_context(arg
);
3903 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
3904 rn
= "ContextConfig";
3913 gen_helper_mtc0_pagemask(arg
);
3917 check_insn(env
, ctx
, ISA_MIPS32R2
);
3918 gen_helper_mtc0_pagegrain(arg
);
3928 gen_helper_mtc0_wired(arg
);
3932 check_insn(env
, ctx
, ISA_MIPS32R2
);
3933 gen_helper_mtc0_srsconf0(arg
);
3937 check_insn(env
, ctx
, ISA_MIPS32R2
);
3938 gen_helper_mtc0_srsconf1(arg
);
3942 check_insn(env
, ctx
, ISA_MIPS32R2
);
3943 gen_helper_mtc0_srsconf2(arg
);
3947 check_insn(env
, ctx
, ISA_MIPS32R2
);
3948 gen_helper_mtc0_srsconf3(arg
);
3952 check_insn(env
, ctx
, ISA_MIPS32R2
);
3953 gen_helper_mtc0_srsconf4(arg
);
3963 check_insn(env
, ctx
, ISA_MIPS32R2
);
3964 gen_helper_mtc0_hwrena(arg
);
3978 gen_helper_mtc0_count(arg
);
3981 /* 6,7 are implementation dependent */
3989 gen_helper_mtc0_entryhi(arg
);
3999 gen_helper_mtc0_compare(arg
);
4002 /* 6,7 are implementation dependent */
4010 save_cpu_state(ctx
, 1);
4011 gen_helper_mtc0_status(arg
);
4012 /* BS_STOP isn't good enough here, hflags may have changed. */
4013 gen_save_pc(ctx
->pc
+ 4);
4014 ctx
->bstate
= BS_EXCP
;
4018 check_insn(env
, ctx
, ISA_MIPS32R2
);
4019 gen_helper_mtc0_intctl(arg
);
4020 /* Stop translation as we may have switched the execution mode */
4021 ctx
->bstate
= BS_STOP
;
4025 check_insn(env
, ctx
, ISA_MIPS32R2
);
4026 gen_helper_mtc0_srsctl(arg
);
4027 /* Stop translation as we may have switched the execution mode */
4028 ctx
->bstate
= BS_STOP
;
4032 check_insn(env
, ctx
, ISA_MIPS32R2
);
4033 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_SRSMap
));
4034 /* Stop translation as we may have switched the execution mode */
4035 ctx
->bstate
= BS_STOP
;
4045 save_cpu_state(ctx
, 1);
4046 gen_helper_mtc0_cause(arg
);
4056 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_EPC
));
4070 check_insn(env
, ctx
, ISA_MIPS32R2
);
4071 gen_helper_mtc0_ebase(arg
);
4081 gen_helper_mtc0_config0(arg
);
4083 /* Stop translation as we may have switched the execution mode */
4084 ctx
->bstate
= BS_STOP
;
4087 /* ignored, read only */
4091 gen_helper_mtc0_config2(arg
);
4093 /* Stop translation as we may have switched the execution mode */
4094 ctx
->bstate
= BS_STOP
;
4097 /* ignored, read only */
4100 /* 4,5 are reserved */
4101 /* 6,7 are implementation dependent */
4111 rn
= "Invalid config selector";
4118 gen_helper_mtc0_lladdr(arg
);
4128 gen_helper_1i(mtc0_watchlo
, arg
, sel
);
4138 gen_helper_1i(mtc0_watchhi
, arg
, sel
);
4148 #if defined(TARGET_MIPS64)
4149 check_insn(env
, ctx
, ISA_MIPS3
);
4150 gen_helper_mtc0_xcontext(arg
);
4159 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4162 gen_helper_mtc0_framemask(arg
);
4171 rn
= "Diagnostic"; /* implementation dependent */
4176 gen_helper_mtc0_debug(arg
); /* EJTAG support */
4177 /* BS_STOP isn't good enough here, hflags may have changed. */
4178 gen_save_pc(ctx
->pc
+ 4);
4179 ctx
->bstate
= BS_EXCP
;
4183 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
4184 rn
= "TraceControl";
4185 /* Stop translation as we may have switched the execution mode */
4186 ctx
->bstate
= BS_STOP
;
4189 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
4190 rn
= "TraceControl2";
4191 /* Stop translation as we may have switched the execution mode */
4192 ctx
->bstate
= BS_STOP
;
4195 /* Stop translation as we may have switched the execution mode */
4196 ctx
->bstate
= BS_STOP
;
4197 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
4198 rn
= "UserTraceData";
4199 /* Stop translation as we may have switched the execution mode */
4200 ctx
->bstate
= BS_STOP
;
4203 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
4204 /* Stop translation as we may have switched the execution mode */
4205 ctx
->bstate
= BS_STOP
;
4216 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_DEPC
));
4226 gen_helper_mtc0_performance0(arg
);
4227 rn
= "Performance0";
4230 // gen_helper_mtc0_performance1(arg);
4231 rn
= "Performance1";
4234 // gen_helper_mtc0_performance2(arg);
4235 rn
= "Performance2";
4238 // gen_helper_mtc0_performance3(arg);
4239 rn
= "Performance3";
4242 // gen_helper_mtc0_performance4(arg);
4243 rn
= "Performance4";
4246 // gen_helper_mtc0_performance5(arg);
4247 rn
= "Performance5";
4250 // gen_helper_mtc0_performance6(arg);
4251 rn
= "Performance6";
4254 // gen_helper_mtc0_performance7(arg);
4255 rn
= "Performance7";
4281 gen_helper_mtc0_taglo(arg
);
4288 gen_helper_mtc0_datalo(arg
);
4301 gen_helper_mtc0_taghi(arg
);
4308 gen_helper_mtc0_datahi(arg
);
4319 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_ErrorEPC
));
4330 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_DESAVE
));
4336 /* Stop translation as we may have switched the execution mode */
4337 ctx
->bstate
= BS_STOP
;
4342 (void)rn
; /* avoid a compiler warning */
4343 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4344 /* For simplicity assume that all writes can cause interrupts. */
4347 ctx
->bstate
= BS_STOP
;
4352 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4353 generate_exception(ctx
, EXCP_RI
);
4356 #if defined(TARGET_MIPS64)
4357 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
4359 const char *rn
= "invalid";
4362 check_insn(env
, ctx
, ISA_MIPS64
);
4368 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Index
));
4372 check_insn(env
, ctx
, ASE_MT
);
4373 gen_helper_mfc0_mvpcontrol(arg
);
4377 check_insn(env
, ctx
, ASE_MT
);
4378 gen_helper_mfc0_mvpconf0(arg
);
4382 check_insn(env
, ctx
, ASE_MT
);
4383 gen_helper_mfc0_mvpconf1(arg
);
4393 gen_helper_mfc0_random(arg
);
4397 check_insn(env
, ctx
, ASE_MT
);
4398 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEControl
));
4402 check_insn(env
, ctx
, ASE_MT
);
4403 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf0
));
4407 check_insn(env
, ctx
, ASE_MT
);
4408 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf1
));
4412 check_insn(env
, ctx
, ASE_MT
);
4413 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_YQMask
));
4417 check_insn(env
, ctx
, ASE_MT
);
4418 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4422 check_insn(env
, ctx
, ASE_MT
);
4423 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4424 rn
= "VPEScheFBack";
4427 check_insn(env
, ctx
, ASE_MT
);
4428 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEOpt
));
4438 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
4442 check_insn(env
, ctx
, ASE_MT
);
4443 gen_helper_mfc0_tcstatus(arg
);
4447 check_insn(env
, ctx
, ASE_MT
);
4448 gen_helper_mfc0_tcbind(arg
);
4452 check_insn(env
, ctx
, ASE_MT
);
4453 gen_helper_dmfc0_tcrestart(arg
);
4457 check_insn(env
, ctx
, ASE_MT
);
4458 gen_helper_dmfc0_tchalt(arg
);
4462 check_insn(env
, ctx
, ASE_MT
);
4463 gen_helper_dmfc0_tccontext(arg
);
4467 check_insn(env
, ctx
, ASE_MT
);
4468 gen_helper_dmfc0_tcschedule(arg
);
4472 check_insn(env
, ctx
, ASE_MT
);
4473 gen_helper_dmfc0_tcschefback(arg
);
4483 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
4493 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_Context
));
4497 // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
4498 rn
= "ContextConfig";
4507 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageMask
));
4511 check_insn(env
, ctx
, ISA_MIPS32R2
);
4512 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageGrain
));
4522 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Wired
));
4526 check_insn(env
, ctx
, ISA_MIPS32R2
);
4527 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf0
));
4531 check_insn(env
, ctx
, ISA_MIPS32R2
);
4532 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf1
));
4536 check_insn(env
, ctx
, ISA_MIPS32R2
);
4537 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf2
));
4541 check_insn(env
, ctx
, ISA_MIPS32R2
);
4542 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf3
));
4546 check_insn(env
, ctx
, ISA_MIPS32R2
);
4547 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf4
));
4557 check_insn(env
, ctx
, ISA_MIPS32R2
);
4558 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_HWREna
));
4568 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
4578 /* Mark as an IO operation because we read the time. */
4581 gen_helper_mfc0_count(arg
);
4584 ctx
->bstate
= BS_STOP
;
4588 /* 6,7 are implementation dependent */
4596 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
4606 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Compare
));
4609 /* 6,7 are implementation dependent */
4617 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Status
));
4621 check_insn(env
, ctx
, ISA_MIPS32R2
);
4622 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_IntCtl
));
4626 check_insn(env
, ctx
, ISA_MIPS32R2
);
4627 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSCtl
));
4631 check_insn(env
, ctx
, ISA_MIPS32R2
);
4632 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSMap
));
4642 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Cause
));
4652 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4662 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PRid
));
4666 check_insn(env
, ctx
, ISA_MIPS32R2
);
4667 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_EBase
));
4677 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config0
));
4681 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config1
));
4685 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config2
));
4689 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config3
));
4692 /* 6,7 are implementation dependent */
4694 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config6
));
4698 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config7
));
4708 gen_helper_dmfc0_lladdr(arg
);
4718 gen_helper_1i(dmfc0_watchlo
, arg
, sel
);
4728 gen_helper_1i(mfc0_watchhi
, arg
, sel
);
4738 check_insn(env
, ctx
, ISA_MIPS3
);
4739 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
4747 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4750 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Framemask
));
4758 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4759 rn
= "'Diagnostic"; /* implementation dependent */
4764 gen_helper_mfc0_debug(arg
); /* EJTAG support */
4768 // gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */
4769 rn
= "TraceControl";
4772 // gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */
4773 rn
= "TraceControl2";
4776 // gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */
4777 rn
= "UserTraceData";
4780 // gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */
4791 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
4801 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Performance0
));
4802 rn
= "Performance0";
4805 // gen_helper_dmfc0_performance1(arg);
4806 rn
= "Performance1";
4809 // gen_helper_dmfc0_performance2(arg);
4810 rn
= "Performance2";
4813 // gen_helper_dmfc0_performance3(arg);
4814 rn
= "Performance3";
4817 // gen_helper_dmfc0_performance4(arg);
4818 rn
= "Performance4";
4821 // gen_helper_dmfc0_performance5(arg);
4822 rn
= "Performance5";
4825 // gen_helper_dmfc0_performance6(arg);
4826 rn
= "Performance6";
4829 // gen_helper_dmfc0_performance7(arg);
4830 rn
= "Performance7";
4837 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4844 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4857 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagLo
));
4864 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataLo
));
4877 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagHi
));
4884 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataHi
));
4894 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
4905 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DESAVE
));
4915 (void)rn
; /* avoid a compiler warning */
4916 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4920 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4921 generate_exception(ctx
, EXCP_RI
);
4924 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
4926 const char *rn
= "invalid";
4929 check_insn(env
, ctx
, ISA_MIPS64
);
4938 gen_helper_mtc0_index(arg
);
4942 check_insn(env
, ctx
, ASE_MT
);
4943 gen_helper_mtc0_mvpcontrol(arg
);
4947 check_insn(env
, ctx
, ASE_MT
);
4952 check_insn(env
, ctx
, ASE_MT
);
4967 check_insn(env
, ctx
, ASE_MT
);
4968 gen_helper_mtc0_vpecontrol(arg
);
4972 check_insn(env
, ctx
, ASE_MT
);
4973 gen_helper_mtc0_vpeconf0(arg
);
4977 check_insn(env
, ctx
, ASE_MT
);
4978 gen_helper_mtc0_vpeconf1(arg
);
4982 check_insn(env
, ctx
, ASE_MT
);
4983 gen_helper_mtc0_yqmask(arg
);
4987 check_insn(env
, ctx
, ASE_MT
);
4988 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4992 check_insn(env
, ctx
, ASE_MT
);
4993 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4994 rn
= "VPEScheFBack";
4997 check_insn(env
, ctx
, ASE_MT
);
4998 gen_helper_mtc0_vpeopt(arg
);
5008 gen_helper_mtc0_entrylo0(arg
);
5012 check_insn(env
, ctx
, ASE_MT
);
5013 gen_helper_mtc0_tcstatus(arg
);
5017 check_insn(env
, ctx
, ASE_MT
);
5018 gen_helper_mtc0_tcbind(arg
);
5022 check_insn(env
, ctx
, ASE_MT
);
5023 gen_helper_mtc0_tcrestart(arg
);
5027 check_insn(env
, ctx
, ASE_MT
);
5028 gen_helper_mtc0_tchalt(arg
);
5032 check_insn(env
, ctx
, ASE_MT
);
5033 gen_helper_mtc0_tccontext(arg
);
5037 check_insn(env
, ctx
, ASE_MT
);
5038 gen_helper_mtc0_tcschedule(arg
);
5042 check_insn(env
, ctx
, ASE_MT
);
5043 gen_helper_mtc0_tcschefback(arg
);
5053 gen_helper_mtc0_entrylo1(arg
);
5063 gen_helper_mtc0_context(arg
);
5067 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
5068 rn
= "ContextConfig";
5077 gen_helper_mtc0_pagemask(arg
);
5081 check_insn(env
, ctx
, ISA_MIPS32R2
);
5082 gen_helper_mtc0_pagegrain(arg
);
5092 gen_helper_mtc0_wired(arg
);
5096 check_insn(env
, ctx
, ISA_MIPS32R2
);
5097 gen_helper_mtc0_srsconf0(arg
);
5101 check_insn(env
, ctx
, ISA_MIPS32R2
);
5102 gen_helper_mtc0_srsconf1(arg
);
5106 check_insn(env
, ctx
, ISA_MIPS32R2
);
5107 gen_helper_mtc0_srsconf2(arg
);
5111 check_insn(env
, ctx
, ISA_MIPS32R2
);
5112 gen_helper_mtc0_srsconf3(arg
);
5116 check_insn(env
, ctx
, ISA_MIPS32R2
);
5117 gen_helper_mtc0_srsconf4(arg
);
5127 check_insn(env
, ctx
, ISA_MIPS32R2
);
5128 gen_helper_mtc0_hwrena(arg
);
5142 gen_helper_mtc0_count(arg
);
5145 /* 6,7 are implementation dependent */
5149 /* Stop translation as we may have switched the execution mode */
5150 ctx
->bstate
= BS_STOP
;
5155 gen_helper_mtc0_entryhi(arg
);
5165 gen_helper_mtc0_compare(arg
);
5168 /* 6,7 are implementation dependent */
5172 /* Stop translation as we may have switched the execution mode */
5173 ctx
->bstate
= BS_STOP
;
5178 save_cpu_state(ctx
, 1);
5179 gen_helper_mtc0_status(arg
);
5180 /* BS_STOP isn't good enough here, hflags may have changed. */
5181 gen_save_pc(ctx
->pc
+ 4);
5182 ctx
->bstate
= BS_EXCP
;
5186 check_insn(env
, ctx
, ISA_MIPS32R2
);
5187 gen_helper_mtc0_intctl(arg
);
5188 /* Stop translation as we may have switched the execution mode */
5189 ctx
->bstate
= BS_STOP
;
5193 check_insn(env
, ctx
, ISA_MIPS32R2
);
5194 gen_helper_mtc0_srsctl(arg
);
5195 /* Stop translation as we may have switched the execution mode */
5196 ctx
->bstate
= BS_STOP
;
5200 check_insn(env
, ctx
, ISA_MIPS32R2
);
5201 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_SRSMap
));
5202 /* Stop translation as we may have switched the execution mode */
5203 ctx
->bstate
= BS_STOP
;
5213 save_cpu_state(ctx
, 1);
5214 /* Mark as an IO operation because we may trigger a software
5219 gen_helper_mtc0_cause(arg
);
5223 /* Stop translation as we may have triggered an intetrupt */
5224 ctx
->bstate
= BS_STOP
;
5234 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
5248 check_insn(env
, ctx
, ISA_MIPS32R2
);
5249 gen_helper_mtc0_ebase(arg
);
5259 gen_helper_mtc0_config0(arg
);
5261 /* Stop translation as we may have switched the execution mode */
5262 ctx
->bstate
= BS_STOP
;
5265 /* ignored, read only */
5269 gen_helper_mtc0_config2(arg
);
5271 /* Stop translation as we may have switched the execution mode */
5272 ctx
->bstate
= BS_STOP
;
5278 /* 6,7 are implementation dependent */
5280 rn
= "Invalid config selector";
5287 gen_helper_mtc0_lladdr(arg
);
5297 gen_helper_1i(mtc0_watchlo
, arg
, sel
);
5307 gen_helper_1i(mtc0_watchhi
, arg
, sel
);
5317 check_insn(env
, ctx
, ISA_MIPS3
);
5318 gen_helper_mtc0_xcontext(arg
);
5326 /* Officially reserved, but sel 0 is used for R1x000 framemask */
5329 gen_helper_mtc0_framemask(arg
);
5338 rn
= "Diagnostic"; /* implementation dependent */
5343 gen_helper_mtc0_debug(arg
); /* EJTAG support */
5344 /* BS_STOP isn't good enough here, hflags may have changed. */
5345 gen_save_pc(ctx
->pc
+ 4);
5346 ctx
->bstate
= BS_EXCP
;
5350 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
5351 /* Stop translation as we may have switched the execution mode */
5352 ctx
->bstate
= BS_STOP
;
5353 rn
= "TraceControl";
5356 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
5357 /* Stop translation as we may have switched the execution mode */
5358 ctx
->bstate
= BS_STOP
;
5359 rn
= "TraceControl2";
5362 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
5363 /* Stop translation as we may have switched the execution mode */
5364 ctx
->bstate
= BS_STOP
;
5365 rn
= "UserTraceData";
5368 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
5369 /* Stop translation as we may have switched the execution mode */
5370 ctx
->bstate
= BS_STOP
;
5381 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
5391 gen_helper_mtc0_performance0(arg
);
5392 rn
= "Performance0";
5395 // gen_helper_mtc0_performance1(arg);
5396 rn
= "Performance1";
5399 // gen_helper_mtc0_performance2(arg);
5400 rn
= "Performance2";
5403 // gen_helper_mtc0_performance3(arg);
5404 rn
= "Performance3";
5407 // gen_helper_mtc0_performance4(arg);
5408 rn
= "Performance4";
5411 // gen_helper_mtc0_performance5(arg);
5412 rn
= "Performance5";
5415 // gen_helper_mtc0_performance6(arg);
5416 rn
= "Performance6";
5419 // gen_helper_mtc0_performance7(arg);
5420 rn
= "Performance7";
5446 gen_helper_mtc0_taglo(arg
);
5453 gen_helper_mtc0_datalo(arg
);
5466 gen_helper_mtc0_taghi(arg
);
5473 gen_helper_mtc0_datahi(arg
);
5484 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
5495 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_DESAVE
));
5501 /* Stop translation as we may have switched the execution mode */
5502 ctx
->bstate
= BS_STOP
;
5507 (void)rn
; /* avoid a compiler warning */
5508 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5509 /* For simplicity assume that all writes can cause interrupts. */
5512 ctx
->bstate
= BS_STOP
;
5517 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5518 generate_exception(ctx
, EXCP_RI
);
5520 #endif /* TARGET_MIPS64 */
5522 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
, int rd
,
5523 int u
, int sel
, int h
)
5525 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5526 TCGv t0
= tcg_temp_local_new();
5528 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5529 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5530 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5531 tcg_gen_movi_tl(t0
, -1);
5532 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5533 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5534 tcg_gen_movi_tl(t0
, -1);
5540 gen_helper_mftc0_tcstatus(t0
);
5543 gen_helper_mftc0_tcbind(t0
);
5546 gen_helper_mftc0_tcrestart(t0
);
5549 gen_helper_mftc0_tchalt(t0
);
5552 gen_helper_mftc0_tccontext(t0
);
5555 gen_helper_mftc0_tcschedule(t0
);
5558 gen_helper_mftc0_tcschefback(t0
);
5561 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5568 gen_helper_mftc0_entryhi(t0
);
5571 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5577 gen_helper_mftc0_status(t0
);
5580 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5586 gen_helper_mftc0_debug(t0
);
5589 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5594 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5596 } else switch (sel
) {
5597 /* GPR registers. */
5599 gen_helper_1i(mftgpr
, t0
, rt
);
5601 /* Auxiliary CPU registers */
5605 gen_helper_1i(mftlo
, t0
, 0);
5608 gen_helper_1i(mfthi
, t0
, 0);
5611 gen_helper_1i(mftacx
, t0
, 0);
5614 gen_helper_1i(mftlo
, t0
, 1);
5617 gen_helper_1i(mfthi
, t0
, 1);
5620 gen_helper_1i(mftacx
, t0
, 1);
5623 gen_helper_1i(mftlo
, t0
, 2);
5626 gen_helper_1i(mfthi
, t0
, 2);
5629 gen_helper_1i(mftacx
, t0
, 2);
5632 gen_helper_1i(mftlo
, t0
, 3);
5635 gen_helper_1i(mfthi
, t0
, 3);
5638 gen_helper_1i(mftacx
, t0
, 3);
5641 gen_helper_mftdsp(t0
);
5647 /* Floating point (COP1). */
5649 /* XXX: For now we support only a single FPU context. */
5651 TCGv_i32 fp0
= tcg_temp_new_i32();
5653 gen_load_fpr32(fp0
, rt
);
5654 tcg_gen_ext_i32_tl(t0
, fp0
);
5655 tcg_temp_free_i32(fp0
);
5657 TCGv_i32 fp0
= tcg_temp_new_i32();
5659 gen_load_fpr32h(fp0
, rt
);
5660 tcg_gen_ext_i32_tl(t0
, fp0
);
5661 tcg_temp_free_i32(fp0
);
5665 /* XXX: For now we support only a single FPU context. */
5666 gen_helper_1i(cfc1
, t0
, rt
);
5668 /* COP2: Not implemented. */
5675 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
5676 gen_store_gpr(t0
, rd
);
5682 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
5683 generate_exception(ctx
, EXCP_RI
);
5686 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
, int rt
,
5687 int u
, int sel
, int h
)
5689 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5690 TCGv t0
= tcg_temp_local_new();
5692 gen_load_gpr(t0
, rt
);
5693 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5694 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5695 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5697 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5698 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5705 gen_helper_mttc0_tcstatus(t0
);
5708 gen_helper_mttc0_tcbind(t0
);
5711 gen_helper_mttc0_tcrestart(t0
);
5714 gen_helper_mttc0_tchalt(t0
);
5717 gen_helper_mttc0_tccontext(t0
);
5720 gen_helper_mttc0_tcschedule(t0
);
5723 gen_helper_mttc0_tcschefback(t0
);
5726 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5733 gen_helper_mttc0_entryhi(t0
);
5736 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5742 gen_helper_mttc0_status(t0
);
5745 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5751 gen_helper_mttc0_debug(t0
);
5754 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5759 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5761 } else switch (sel
) {
5762 /* GPR registers. */
5764 gen_helper_1i(mttgpr
, t0
, rd
);
5766 /* Auxiliary CPU registers */
5770 gen_helper_1i(mttlo
, t0
, 0);
5773 gen_helper_1i(mtthi
, t0
, 0);
5776 gen_helper_1i(mttacx
, t0
, 0);
5779 gen_helper_1i(mttlo
, t0
, 1);
5782 gen_helper_1i(mtthi
, t0
, 1);
5785 gen_helper_1i(mttacx
, t0
, 1);
5788 gen_helper_1i(mttlo
, t0
, 2);
5791 gen_helper_1i(mtthi
, t0
, 2);
5794 gen_helper_1i(mttacx
, t0
, 2);
5797 gen_helper_1i(mttlo
, t0
, 3);
5800 gen_helper_1i(mtthi
, t0
, 3);
5803 gen_helper_1i(mttacx
, t0
, 3);
5806 gen_helper_mttdsp(t0
);
5812 /* Floating point (COP1). */
5814 /* XXX: For now we support only a single FPU context. */
5816 TCGv_i32 fp0
= tcg_temp_new_i32();
5818 tcg_gen_trunc_tl_i32(fp0
, t0
);
5819 gen_store_fpr32(fp0
, rd
);
5820 tcg_temp_free_i32(fp0
);
5822 TCGv_i32 fp0
= tcg_temp_new_i32();
5824 tcg_gen_trunc_tl_i32(fp0
, t0
);
5825 gen_store_fpr32h(fp0
, rd
);
5826 tcg_temp_free_i32(fp0
);
5830 /* XXX: For now we support only a single FPU context. */
5831 gen_helper_1i(ctc1
, t0
, rd
);
5833 /* COP2: Not implemented. */
5840 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
5846 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
5847 generate_exception(ctx
, EXCP_RI
);
5850 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
5852 const char *opn
= "ldst";
5860 gen_mfc0(env
, ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
5865 TCGv t0
= tcg_temp_new();
5867 gen_load_gpr(t0
, rt
);
5868 gen_mtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5873 #if defined(TARGET_MIPS64)
5875 check_insn(env
, ctx
, ISA_MIPS3
);
5880 gen_dmfc0(env
, ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
5884 check_insn(env
, ctx
, ISA_MIPS3
);
5886 TCGv t0
= tcg_temp_new();
5888 gen_load_gpr(t0
, rt
);
5889 gen_dmtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5896 check_insn(env
, ctx
, ASE_MT
);
5901 gen_mftr(env
, ctx
, rt
, rd
, (ctx
->opcode
>> 5) & 1,
5902 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5906 check_insn(env
, ctx
, ASE_MT
);
5907 gen_mttr(env
, ctx
, rd
, rt
, (ctx
->opcode
>> 5) & 1,
5908 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5913 if (!env
->tlb
->helper_tlbwi
)
5919 if (!env
->tlb
->helper_tlbwr
)
5925 if (!env
->tlb
->helper_tlbp
)
5931 if (!env
->tlb
->helper_tlbr
)
5937 check_insn(env
, ctx
, ISA_MIPS2
);
5939 ctx
->bstate
= BS_EXCP
;
5943 check_insn(env
, ctx
, ISA_MIPS32
);
5944 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
5946 generate_exception(ctx
, EXCP_RI
);
5949 ctx
->bstate
= BS_EXCP
;
5954 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
5955 /* If we get an exception, we want to restart at next instruction */
5957 save_cpu_state(ctx
, 1);
5960 ctx
->bstate
= BS_EXCP
;
5965 generate_exception(ctx
, EXCP_RI
);
5968 (void)opn
; /* avoid a compiler warning */
5969 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
5971 #endif /* !CONFIG_USER_ONLY */
5973 /* CP1 Branches (before delay slot) */
5974 static void gen_compute_branch1 (CPUState
*env
, DisasContext
*ctx
, uint32_t op
,
5975 int32_t cc
, int32_t offset
)
5977 target_ulong btarget
;
5978 const char *opn
= "cp1 cond branch";
5979 TCGv_i32 t0
= tcg_temp_new_i32();
5982 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
5984 btarget
= ctx
->pc
+ 4 + offset
;
5988 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5989 tcg_gen_not_i32(t0
, t0
);
5990 tcg_gen_andi_i32(t0
, t0
, 1);
5991 tcg_gen_extu_i32_tl(bcond
, t0
);
5995 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5996 tcg_gen_not_i32(t0
, t0
);
5997 tcg_gen_andi_i32(t0
, t0
, 1);
5998 tcg_gen_extu_i32_tl(bcond
, t0
);
6002 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
6003 tcg_gen_andi_i32(t0
, t0
, 1);
6004 tcg_gen_extu_i32_tl(bcond
, t0
);
6008 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
6009 tcg_gen_andi_i32(t0
, t0
, 1);
6010 tcg_gen_extu_i32_tl(bcond
, t0
);
6013 ctx
->hflags
|= MIPS_HFLAG_BL
;
6017 TCGv_i32 t1
= tcg_temp_new_i32();
6018 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
6019 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
6020 tcg_gen_nor_i32(t0
, t0
, t1
);
6021 tcg_temp_free_i32(t1
);
6022 tcg_gen_andi_i32(t0
, t0
, 1);
6023 tcg_gen_extu_i32_tl(bcond
, t0
);
6029 TCGv_i32 t1
= tcg_temp_new_i32();
6030 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
6031 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
6032 tcg_gen_or_i32(t0
, t0
, t1
);
6033 tcg_temp_free_i32(t1
);
6034 tcg_gen_andi_i32(t0
, t0
, 1);
6035 tcg_gen_extu_i32_tl(bcond
, t0
);
6041 TCGv_i32 t1
= tcg_temp_new_i32();
6042 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
6043 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
6044 tcg_gen_or_i32(t0
, t0
, t1
);
6045 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
6046 tcg_gen_or_i32(t0
, t0
, t1
);
6047 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
6048 tcg_gen_nor_i32(t0
, t0
, t1
);
6049 tcg_temp_free_i32(t1
);
6050 tcg_gen_andi_i32(t0
, t0
, 1);
6051 tcg_gen_extu_i32_tl(bcond
, t0
);
6057 TCGv_i32 t1
= tcg_temp_new_i32();
6058 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
6059 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
6060 tcg_gen_or_i32(t0
, t0
, t1
);
6061 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
6062 tcg_gen_or_i32(t0
, t0
, t1
);
6063 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
6064 tcg_gen_or_i32(t0
, t0
, t1
);
6065 tcg_temp_free_i32(t1
);
6066 tcg_gen_andi_i32(t0
, t0
, 1);
6067 tcg_gen_extu_i32_tl(bcond
, t0
);
6071 ctx
->hflags
|= MIPS_HFLAG_BC
;
6075 generate_exception (ctx
, EXCP_RI
);
6078 (void)opn
; /* avoid a compiler warning */
6079 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
6080 ctx
->hflags
, btarget
);
6081 ctx
->btarget
= btarget
;
6084 tcg_temp_free_i32(t0
);
6087 /* Coprocessor 1 (FPU) */
6089 #define FOP(func, fmt) (((fmt) << 21) | (func))
6092 OPC_ADD_S
= FOP(0, FMT_S
),
6093 OPC_SUB_S
= FOP(1, FMT_S
),
6094 OPC_MUL_S
= FOP(2, FMT_S
),
6095 OPC_DIV_S
= FOP(3, FMT_S
),
6096 OPC_SQRT_S
= FOP(4, FMT_S
),
6097 OPC_ABS_S
= FOP(5, FMT_S
),
6098 OPC_MOV_S
= FOP(6, FMT_S
),
6099 OPC_NEG_S
= FOP(7, FMT_S
),
6100 OPC_ROUND_L_S
= FOP(8, FMT_S
),
6101 OPC_TRUNC_L_S
= FOP(9, FMT_S
),
6102 OPC_CEIL_L_S
= FOP(10, FMT_S
),
6103 OPC_FLOOR_L_S
= FOP(11, FMT_S
),
6104 OPC_ROUND_W_S
= FOP(12, FMT_S
),
6105 OPC_TRUNC_W_S
= FOP(13, FMT_S
),
6106 OPC_CEIL_W_S
= FOP(14, FMT_S
),
6107 OPC_FLOOR_W_S
= FOP(15, FMT_S
),
6108 OPC_MOVCF_S
= FOP(17, FMT_S
),
6109 OPC_MOVZ_S
= FOP(18, FMT_S
),
6110 OPC_MOVN_S
= FOP(19, FMT_S
),
6111 OPC_RECIP_S
= FOP(21, FMT_S
),
6112 OPC_RSQRT_S
= FOP(22, FMT_S
),
6113 OPC_RECIP2_S
= FOP(28, FMT_S
),
6114 OPC_RECIP1_S
= FOP(29, FMT_S
),
6115 OPC_RSQRT1_S
= FOP(30, FMT_S
),
6116 OPC_RSQRT2_S
= FOP(31, FMT_S
),
6117 OPC_CVT_D_S
= FOP(33, FMT_S
),
6118 OPC_CVT_W_S
= FOP(36, FMT_S
),
6119 OPC_CVT_L_S
= FOP(37, FMT_S
),
6120 OPC_CVT_PS_S
= FOP(38, FMT_S
),
6121 OPC_CMP_F_S
= FOP (48, FMT_S
),
6122 OPC_CMP_UN_S
= FOP (49, FMT_S
),
6123 OPC_CMP_EQ_S
= FOP (50, FMT_S
),
6124 OPC_CMP_UEQ_S
= FOP (51, FMT_S
),
6125 OPC_CMP_OLT_S
= FOP (52, FMT_S
),
6126 OPC_CMP_ULT_S
= FOP (53, FMT_S
),
6127 OPC_CMP_OLE_S
= FOP (54, FMT_S
),
6128 OPC_CMP_ULE_S
= FOP (55, FMT_S
),
6129 OPC_CMP_SF_S
= FOP (56, FMT_S
),
6130 OPC_CMP_NGLE_S
= FOP (57, FMT_S
),
6131 OPC_CMP_SEQ_S
= FOP (58, FMT_S
),
6132 OPC_CMP_NGL_S
= FOP (59, FMT_S
),
6133 OPC_CMP_LT_S
= FOP (60, FMT_S
),
6134 OPC_CMP_NGE_S
= FOP (61, FMT_S
),
6135 OPC_CMP_LE_S
= FOP (62, FMT_S
),
6136 OPC_CMP_NGT_S
= FOP (63, FMT_S
),
6138 OPC_ADD_D
= FOP(0, FMT_D
),
6139 OPC_SUB_D
= FOP(1, FMT_D
),
6140 OPC_MUL_D
= FOP(2, FMT_D
),
6141 OPC_DIV_D
= FOP(3, FMT_D
),
6142 OPC_SQRT_D
= FOP(4, FMT_D
),
6143 OPC_ABS_D
= FOP(5, FMT_D
),
6144 OPC_MOV_D
= FOP(6, FMT_D
),
6145 OPC_NEG_D
= FOP(7, FMT_D
),
6146 OPC_ROUND_L_D
= FOP(8, FMT_D
),
6147 OPC_TRUNC_L_D
= FOP(9, FMT_D
),
6148 OPC_CEIL_L_D
= FOP(10, FMT_D
),
6149 OPC_FLOOR_L_D
= FOP(11, FMT_D
),
6150 OPC_ROUND_W_D
= FOP(12, FMT_D
),
6151 OPC_TRUNC_W_D
= FOP(13, FMT_D
),
6152 OPC_CEIL_W_D
= FOP(14, FMT_D
),
6153 OPC_FLOOR_W_D
= FOP(15, FMT_D
),
6154 OPC_MOVCF_D
= FOP(17, FMT_D
),
6155 OPC_MOVZ_D
= FOP(18, FMT_D
),
6156 OPC_MOVN_D
= FOP(19, FMT_D
),
6157 OPC_RECIP_D
= FOP(21, FMT_D
),
6158 OPC_RSQRT_D
= FOP(22, FMT_D
),
6159 OPC_RECIP2_D
= FOP(28, FMT_D
),
6160 OPC_RECIP1_D
= FOP(29, FMT_D
),
6161 OPC_RSQRT1_D
= FOP(30, FMT_D
),
6162 OPC_RSQRT2_D
= FOP(31, FMT_D
),
6163 OPC_CVT_S_D
= FOP(32, FMT_D
),
6164 OPC_CVT_W_D
= FOP(36, FMT_D
),
6165 OPC_CVT_L_D
= FOP(37, FMT_D
),
6166 OPC_CMP_F_D
= FOP (48, FMT_D
),
6167 OPC_CMP_UN_D
= FOP (49, FMT_D
),
6168 OPC_CMP_EQ_D
= FOP (50, FMT_D
),
6169 OPC_CMP_UEQ_D
= FOP (51, FMT_D
),
6170 OPC_CMP_OLT_D
= FOP (52, FMT_D
),
6171 OPC_CMP_ULT_D
= FOP (53, FMT_D
),
6172 OPC_CMP_OLE_D
= FOP (54, FMT_D
),
6173 OPC_CMP_ULE_D
= FOP (55, FMT_D
),
6174 OPC_CMP_SF_D
= FOP (56, FMT_D
),
6175 OPC_CMP_NGLE_D
= FOP (57, FMT_D
),
6176 OPC_CMP_SEQ_D
= FOP (58, FMT_D
),
6177 OPC_CMP_NGL_D
= FOP (59, FMT_D
),
6178 OPC_CMP_LT_D
= FOP (60, FMT_D
),
6179 OPC_CMP_NGE_D
= FOP (61, FMT_D
),
6180 OPC_CMP_LE_D
= FOP (62, FMT_D
),
6181 OPC_CMP_NGT_D
= FOP (63, FMT_D
),
6183 OPC_CVT_S_W
= FOP(32, FMT_W
),
6184 OPC_CVT_D_W
= FOP(33, FMT_W
),
6185 OPC_CVT_S_L
= FOP(32, FMT_L
),
6186 OPC_CVT_D_L
= FOP(33, FMT_L
),
6187 OPC_CVT_PS_PW
= FOP(38, FMT_W
),
6189 OPC_ADD_PS
= FOP(0, FMT_PS
),
6190 OPC_SUB_PS
= FOP(1, FMT_PS
),
6191 OPC_MUL_PS
= FOP(2, FMT_PS
),
6192 OPC_DIV_PS
= FOP(3, FMT_PS
),
6193 OPC_ABS_PS
= FOP(5, FMT_PS
),
6194 OPC_MOV_PS
= FOP(6, FMT_PS
),
6195 OPC_NEG_PS
= FOP(7, FMT_PS
),
6196 OPC_MOVCF_PS
= FOP(17, FMT_PS
),
6197 OPC_MOVZ_PS
= FOP(18, FMT_PS
),
6198 OPC_MOVN_PS
= FOP(19, FMT_PS
),
6199 OPC_ADDR_PS
= FOP(24, FMT_PS
),
6200 OPC_MULR_PS
= FOP(26, FMT_PS
),
6201 OPC_RECIP2_PS
= FOP(28, FMT_PS
),
6202 OPC_RECIP1_PS
= FOP(29, FMT_PS
),
6203 OPC_RSQRT1_PS
= FOP(30, FMT_PS
),
6204 OPC_RSQRT2_PS
= FOP(31, FMT_PS
),
6206 OPC_CVT_S_PU
= FOP(32, FMT_PS
),
6207 OPC_CVT_PW_PS
= FOP(36, FMT_PS
),
6208 OPC_CVT_S_PL
= FOP(40, FMT_PS
),
6209 OPC_PLL_PS
= FOP(44, FMT_PS
),
6210 OPC_PLU_PS
= FOP(45, FMT_PS
),
6211 OPC_PUL_PS
= FOP(46, FMT_PS
),
6212 OPC_PUU_PS
= FOP(47, FMT_PS
),
6213 OPC_CMP_F_PS
= FOP (48, FMT_PS
),
6214 OPC_CMP_UN_PS
= FOP (49, FMT_PS
),
6215 OPC_CMP_EQ_PS
= FOP (50, FMT_PS
),
6216 OPC_CMP_UEQ_PS
= FOP (51, FMT_PS
),
6217 OPC_CMP_OLT_PS
= FOP (52, FMT_PS
),
6218 OPC_CMP_ULT_PS
= FOP (53, FMT_PS
),
6219 OPC_CMP_OLE_PS
= FOP (54, FMT_PS
),
6220 OPC_CMP_ULE_PS
= FOP (55, FMT_PS
),
6221 OPC_CMP_SF_PS
= FOP (56, FMT_PS
),
6222 OPC_CMP_NGLE_PS
= FOP (57, FMT_PS
),
6223 OPC_CMP_SEQ_PS
= FOP (58, FMT_PS
),
6224 OPC_CMP_NGL_PS
= FOP (59, FMT_PS
),
6225 OPC_CMP_LT_PS
= FOP (60, FMT_PS
),
6226 OPC_CMP_NGE_PS
= FOP (61, FMT_PS
),
6227 OPC_CMP_LE_PS
= FOP (62, FMT_PS
),
6228 OPC_CMP_NGT_PS
= FOP (63, FMT_PS
),
6231 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
6233 const char *opn
= "cp1 move";
6234 TCGv t0
= tcg_temp_new();
6239 TCGv_i32 fp0
= tcg_temp_new_i32();
6241 gen_load_fpr32(fp0
, fs
);
6242 tcg_gen_ext_i32_tl(t0
, fp0
);
6243 tcg_temp_free_i32(fp0
);
6245 gen_store_gpr(t0
, rt
);
6249 gen_load_gpr(t0
, rt
);
6251 TCGv_i32 fp0
= tcg_temp_new_i32();
6253 tcg_gen_trunc_tl_i32(fp0
, t0
);
6254 gen_store_fpr32(fp0
, fs
);
6255 tcg_temp_free_i32(fp0
);
6260 gen_helper_1i(cfc1
, t0
, fs
);
6261 gen_store_gpr(t0
, rt
);
6265 gen_load_gpr(t0
, rt
);
6266 gen_helper_1i(ctc1
, t0
, fs
);
6269 #if defined(TARGET_MIPS64)
6271 gen_load_fpr64(ctx
, t0
, fs
);
6272 gen_store_gpr(t0
, rt
);
6276 gen_load_gpr(t0
, rt
);
6277 gen_store_fpr64(ctx
, t0
, fs
);
6283 TCGv_i32 fp0
= tcg_temp_new_i32();
6285 gen_load_fpr32h(fp0
, fs
);
6286 tcg_gen_ext_i32_tl(t0
, fp0
);
6287 tcg_temp_free_i32(fp0
);
6289 gen_store_gpr(t0
, rt
);
6293 gen_load_gpr(t0
, rt
);
6295 TCGv_i32 fp0
= tcg_temp_new_i32();
6297 tcg_gen_trunc_tl_i32(fp0
, t0
);
6298 gen_store_fpr32h(fp0
, fs
);
6299 tcg_temp_free_i32(fp0
);
6305 generate_exception (ctx
, EXCP_RI
);
6308 (void)opn
; /* avoid a compiler warning */
6309 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
6315 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
6331 l1
= gen_new_label();
6332 t0
= tcg_temp_new_i32();
6333 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
6334 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
6335 tcg_temp_free_i32(t0
);
6337 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
6339 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
6344 static inline void gen_movcf_s (int fs
, int fd
, int cc
, int tf
)
6347 TCGv_i32 t0
= tcg_temp_new_i32();
6348 int l1
= gen_new_label();
6355 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
6356 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
6357 gen_load_fpr32(t0
, fs
);
6358 gen_store_fpr32(t0
, fd
);
6360 tcg_temp_free_i32(t0
);
6363 static inline void gen_movcf_d (DisasContext
*ctx
, int fs
, int fd
, int cc
, int tf
)
6366 TCGv_i32 t0
= tcg_temp_new_i32();
6368 int l1
= gen_new_label();
6375 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
6376 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
6377 tcg_temp_free_i32(t0
);
6378 fp0
= tcg_temp_new_i64();
6379 gen_load_fpr64(ctx
, fp0
, fs
);
6380 gen_store_fpr64(ctx
, fp0
, fd
);
6381 tcg_temp_free_i64(fp0
);
6385 static inline void gen_movcf_ps (int fs
, int fd
, int cc
, int tf
)
6388 TCGv_i32 t0
= tcg_temp_new_i32();
6389 int l1
= gen_new_label();
6390 int l2
= gen_new_label();
6397 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
6398 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
6399 gen_load_fpr32(t0
, fs
);
6400 gen_store_fpr32(t0
, fd
);
6403 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
+1));
6404 tcg_gen_brcondi_i32(cond
, t0
, 0, l2
);
6405 gen_load_fpr32h(t0
, fs
);
6406 gen_store_fpr32h(t0
, fd
);
6407 tcg_temp_free_i32(t0
);
6412 static void gen_farith (DisasContext
*ctx
, enum fopcode op1
,
6413 int ft
, int fs
, int fd
, int cc
)
6415 const char *opn
= "farith";
6416 const char *condnames
[] = {
6434 const char *condnames_abs
[] = {
6452 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
6453 uint32_t func
= ctx
->opcode
& 0x3f;
6458 TCGv_i32 fp0
= tcg_temp_new_i32();
6459 TCGv_i32 fp1
= tcg_temp_new_i32();
6461 gen_load_fpr32(fp0
, fs
);
6462 gen_load_fpr32(fp1
, ft
);
6463 gen_helper_float_add_s(fp0
, fp0
, fp1
);
6464 tcg_temp_free_i32(fp1
);
6465 gen_store_fpr32(fp0
, fd
);
6466 tcg_temp_free_i32(fp0
);
6473 TCGv_i32 fp0
= tcg_temp_new_i32();
6474 TCGv_i32 fp1
= tcg_temp_new_i32();
6476 gen_load_fpr32(fp0
, fs
);
6477 gen_load_fpr32(fp1
, ft
);
6478 gen_helper_float_sub_s(fp0
, fp0
, fp1
);
6479 tcg_temp_free_i32(fp1
);
6480 gen_store_fpr32(fp0
, fd
);
6481 tcg_temp_free_i32(fp0
);
6488 TCGv_i32 fp0
= tcg_temp_new_i32();
6489 TCGv_i32 fp1
= tcg_temp_new_i32();
6491 gen_load_fpr32(fp0
, fs
);
6492 gen_load_fpr32(fp1
, ft
);
6493 gen_helper_float_mul_s(fp0
, fp0
, fp1
);
6494 tcg_temp_free_i32(fp1
);
6495 gen_store_fpr32(fp0
, fd
);
6496 tcg_temp_free_i32(fp0
);
6503 TCGv_i32 fp0
= tcg_temp_new_i32();
6504 TCGv_i32 fp1
= tcg_temp_new_i32();
6506 gen_load_fpr32(fp0
, fs
);
6507 gen_load_fpr32(fp1
, ft
);
6508 gen_helper_float_div_s(fp0
, fp0
, fp1
);
6509 tcg_temp_free_i32(fp1
);
6510 gen_store_fpr32(fp0
, fd
);
6511 tcg_temp_free_i32(fp0
);
6518 TCGv_i32 fp0
= tcg_temp_new_i32();
6520 gen_load_fpr32(fp0
, fs
);
6521 gen_helper_float_sqrt_s(fp0
, fp0
);
6522 gen_store_fpr32(fp0
, fd
);
6523 tcg_temp_free_i32(fp0
);
6529 TCGv_i32 fp0
= tcg_temp_new_i32();
6531 gen_load_fpr32(fp0
, fs
);
6532 gen_helper_float_abs_s(fp0
, fp0
);
6533 gen_store_fpr32(fp0
, fd
);
6534 tcg_temp_free_i32(fp0
);
6540 TCGv_i32 fp0
= tcg_temp_new_i32();
6542 gen_load_fpr32(fp0
, fs
);
6543 gen_store_fpr32(fp0
, fd
);
6544 tcg_temp_free_i32(fp0
);
6550 TCGv_i32 fp0
= tcg_temp_new_i32();
6552 gen_load_fpr32(fp0
, fs
);
6553 gen_helper_float_chs_s(fp0
, fp0
);
6554 gen_store_fpr32(fp0
, fd
);
6555 tcg_temp_free_i32(fp0
);
6560 check_cp1_64bitmode(ctx
);
6562 TCGv_i32 fp32
= tcg_temp_new_i32();
6563 TCGv_i64 fp64
= tcg_temp_new_i64();
6565 gen_load_fpr32(fp32
, fs
);
6566 gen_helper_float_roundl_s(fp64
, fp32
);
6567 tcg_temp_free_i32(fp32
);
6568 gen_store_fpr64(ctx
, fp64
, fd
);
6569 tcg_temp_free_i64(fp64
);
6574 check_cp1_64bitmode(ctx
);
6576 TCGv_i32 fp32
= tcg_temp_new_i32();
6577 TCGv_i64 fp64
= tcg_temp_new_i64();
6579 gen_load_fpr32(fp32
, fs
);
6580 gen_helper_float_truncl_s(fp64
, fp32
);
6581 tcg_temp_free_i32(fp32
);
6582 gen_store_fpr64(ctx
, fp64
, fd
);
6583 tcg_temp_free_i64(fp64
);
6588 check_cp1_64bitmode(ctx
);
6590 TCGv_i32 fp32
= tcg_temp_new_i32();
6591 TCGv_i64 fp64
= tcg_temp_new_i64();
6593 gen_load_fpr32(fp32
, fs
);
6594 gen_helper_float_ceill_s(fp64
, fp32
);
6595 tcg_temp_free_i32(fp32
);
6596 gen_store_fpr64(ctx
, fp64
, fd
);
6597 tcg_temp_free_i64(fp64
);
6602 check_cp1_64bitmode(ctx
);
6604 TCGv_i32 fp32
= tcg_temp_new_i32();
6605 TCGv_i64 fp64
= tcg_temp_new_i64();
6607 gen_load_fpr32(fp32
, fs
);
6608 gen_helper_float_floorl_s(fp64
, fp32
);
6609 tcg_temp_free_i32(fp32
);
6610 gen_store_fpr64(ctx
, fp64
, fd
);
6611 tcg_temp_free_i64(fp64
);
6617 TCGv_i32 fp0
= tcg_temp_new_i32();
6619 gen_load_fpr32(fp0
, fs
);
6620 gen_helper_float_roundw_s(fp0
, fp0
);
6621 gen_store_fpr32(fp0
, fd
);
6622 tcg_temp_free_i32(fp0
);
6628 TCGv_i32 fp0
= tcg_temp_new_i32();
6630 gen_load_fpr32(fp0
, fs
);
6631 gen_helper_float_truncw_s(fp0
, fp0
);
6632 gen_store_fpr32(fp0
, fd
);
6633 tcg_temp_free_i32(fp0
);
6639 TCGv_i32 fp0
= tcg_temp_new_i32();
6641 gen_load_fpr32(fp0
, fs
);
6642 gen_helper_float_ceilw_s(fp0
, fp0
);
6643 gen_store_fpr32(fp0
, fd
);
6644 tcg_temp_free_i32(fp0
);
6650 TCGv_i32 fp0
= tcg_temp_new_i32();
6652 gen_load_fpr32(fp0
, fs
);
6653 gen_helper_float_floorw_s(fp0
, fp0
);
6654 gen_store_fpr32(fp0
, fd
);
6655 tcg_temp_free_i32(fp0
);
6660 gen_movcf_s(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6665 int l1
= gen_new_label();
6669 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6671 fp0
= tcg_temp_new_i32();
6672 gen_load_fpr32(fp0
, fs
);
6673 gen_store_fpr32(fp0
, fd
);
6674 tcg_temp_free_i32(fp0
);
6681 int l1
= gen_new_label();
6685 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
6686 fp0
= tcg_temp_new_i32();
6687 gen_load_fpr32(fp0
, fs
);
6688 gen_store_fpr32(fp0
, fd
);
6689 tcg_temp_free_i32(fp0
);
6698 TCGv_i32 fp0
= tcg_temp_new_i32();
6700 gen_load_fpr32(fp0
, fs
);
6701 gen_helper_float_recip_s(fp0
, fp0
);
6702 gen_store_fpr32(fp0
, fd
);
6703 tcg_temp_free_i32(fp0
);
6710 TCGv_i32 fp0
= tcg_temp_new_i32();
6712 gen_load_fpr32(fp0
, fs
);
6713 gen_helper_float_rsqrt_s(fp0
, fp0
);
6714 gen_store_fpr32(fp0
, fd
);
6715 tcg_temp_free_i32(fp0
);
6720 check_cp1_64bitmode(ctx
);
6722 TCGv_i32 fp0
= tcg_temp_new_i32();
6723 TCGv_i32 fp1
= tcg_temp_new_i32();
6725 gen_load_fpr32(fp0
, fs
);
6726 gen_load_fpr32(fp1
, fd
);
6727 gen_helper_float_recip2_s(fp0
, fp0
, fp1
);
6728 tcg_temp_free_i32(fp1
);
6729 gen_store_fpr32(fp0
, fd
);
6730 tcg_temp_free_i32(fp0
);
6735 check_cp1_64bitmode(ctx
);
6737 TCGv_i32 fp0
= tcg_temp_new_i32();
6739 gen_load_fpr32(fp0
, fs
);
6740 gen_helper_float_recip1_s(fp0
, fp0
);
6741 gen_store_fpr32(fp0
, fd
);
6742 tcg_temp_free_i32(fp0
);
6747 check_cp1_64bitmode(ctx
);
6749 TCGv_i32 fp0
= tcg_temp_new_i32();
6751 gen_load_fpr32(fp0
, fs
);
6752 gen_helper_float_rsqrt1_s(fp0
, fp0
);
6753 gen_store_fpr32(fp0
, fd
);
6754 tcg_temp_free_i32(fp0
);
6759 check_cp1_64bitmode(ctx
);
6761 TCGv_i32 fp0
= tcg_temp_new_i32();
6762 TCGv_i32 fp1
= tcg_temp_new_i32();
6764 gen_load_fpr32(fp0
, fs
);
6765 gen_load_fpr32(fp1
, ft
);
6766 gen_helper_float_rsqrt2_s(fp0
, fp0
, fp1
);
6767 tcg_temp_free_i32(fp1
);
6768 gen_store_fpr32(fp0
, fd
);
6769 tcg_temp_free_i32(fp0
);
6774 check_cp1_registers(ctx
, fd
);
6776 TCGv_i32 fp32
= tcg_temp_new_i32();
6777 TCGv_i64 fp64
= tcg_temp_new_i64();
6779 gen_load_fpr32(fp32
, fs
);
6780 gen_helper_float_cvtd_s(fp64
, fp32
);
6781 tcg_temp_free_i32(fp32
);
6782 gen_store_fpr64(ctx
, fp64
, fd
);
6783 tcg_temp_free_i64(fp64
);
6789 TCGv_i32 fp0
= tcg_temp_new_i32();
6791 gen_load_fpr32(fp0
, fs
);
6792 gen_helper_float_cvtw_s(fp0
, fp0
);
6793 gen_store_fpr32(fp0
, fd
);
6794 tcg_temp_free_i32(fp0
);
6799 check_cp1_64bitmode(ctx
);
6801 TCGv_i32 fp32
= tcg_temp_new_i32();
6802 TCGv_i64 fp64
= tcg_temp_new_i64();
6804 gen_load_fpr32(fp32
, fs
);
6805 gen_helper_float_cvtl_s(fp64
, fp32
);
6806 tcg_temp_free_i32(fp32
);
6807 gen_store_fpr64(ctx
, fp64
, fd
);
6808 tcg_temp_free_i64(fp64
);
6813 check_cp1_64bitmode(ctx
);
6815 TCGv_i64 fp64
= tcg_temp_new_i64();
6816 TCGv_i32 fp32_0
= tcg_temp_new_i32();
6817 TCGv_i32 fp32_1
= tcg_temp_new_i32();
6819 gen_load_fpr32(fp32_0
, fs
);
6820 gen_load_fpr32(fp32_1
, ft
);
6821 tcg_gen_concat_i32_i64(fp64
, fp32_0
, fp32_1
);
6822 tcg_temp_free_i32(fp32_1
);
6823 tcg_temp_free_i32(fp32_0
);
6824 gen_store_fpr64(ctx
, fp64
, fd
);
6825 tcg_temp_free_i64(fp64
);
6838 case OPC_CMP_NGLE_S
:
6845 if (ctx
->opcode
& (1 << 6)) {
6846 gen_cmpabs_s(ctx
, func
-48, ft
, fs
, cc
);
6847 opn
= condnames_abs
[func
-48];
6849 gen_cmp_s(ctx
, func
-48, ft
, fs
, cc
);
6850 opn
= condnames
[func
-48];
6854 check_cp1_registers(ctx
, fs
| ft
| fd
);
6856 TCGv_i64 fp0
= tcg_temp_new_i64();
6857 TCGv_i64 fp1
= tcg_temp_new_i64();
6859 gen_load_fpr64(ctx
, fp0
, fs
);
6860 gen_load_fpr64(ctx
, fp1
, ft
);
6861 gen_helper_float_add_d(fp0
, fp0
, fp1
);
6862 tcg_temp_free_i64(fp1
);
6863 gen_store_fpr64(ctx
, fp0
, fd
);
6864 tcg_temp_free_i64(fp0
);
6870 check_cp1_registers(ctx
, fs
| ft
| fd
);
6872 TCGv_i64 fp0
= tcg_temp_new_i64();
6873 TCGv_i64 fp1
= tcg_temp_new_i64();
6875 gen_load_fpr64(ctx
, fp0
, fs
);
6876 gen_load_fpr64(ctx
, fp1
, ft
);
6877 gen_helper_float_sub_d(fp0
, fp0
, fp1
);
6878 tcg_temp_free_i64(fp1
);
6879 gen_store_fpr64(ctx
, fp0
, fd
);
6880 tcg_temp_free_i64(fp0
);
6886 check_cp1_registers(ctx
, fs
| ft
| fd
);
6888 TCGv_i64 fp0
= tcg_temp_new_i64();
6889 TCGv_i64 fp1
= tcg_temp_new_i64();
6891 gen_load_fpr64(ctx
, fp0
, fs
);
6892 gen_load_fpr64(ctx
, fp1
, ft
);
6893 gen_helper_float_mul_d(fp0
, fp0
, fp1
);
6894 tcg_temp_free_i64(fp1
);
6895 gen_store_fpr64(ctx
, fp0
, fd
);
6896 tcg_temp_free_i64(fp0
);
6902 check_cp1_registers(ctx
, fs
| ft
| fd
);
6904 TCGv_i64 fp0
= tcg_temp_new_i64();
6905 TCGv_i64 fp1
= tcg_temp_new_i64();
6907 gen_load_fpr64(ctx
, fp0
, fs
);
6908 gen_load_fpr64(ctx
, fp1
, ft
);
6909 gen_helper_float_div_d(fp0
, fp0
, fp1
);
6910 tcg_temp_free_i64(fp1
);
6911 gen_store_fpr64(ctx
, fp0
, fd
);
6912 tcg_temp_free_i64(fp0
);
6918 check_cp1_registers(ctx
, fs
| fd
);
6920 TCGv_i64 fp0
= tcg_temp_new_i64();
6922 gen_load_fpr64(ctx
, fp0
, fs
);
6923 gen_helper_float_sqrt_d(fp0
, fp0
);
6924 gen_store_fpr64(ctx
, fp0
, fd
);
6925 tcg_temp_free_i64(fp0
);
6930 check_cp1_registers(ctx
, fs
| fd
);
6932 TCGv_i64 fp0
= tcg_temp_new_i64();
6934 gen_load_fpr64(ctx
, fp0
, fs
);
6935 gen_helper_float_abs_d(fp0
, fp0
);
6936 gen_store_fpr64(ctx
, fp0
, fd
);
6937 tcg_temp_free_i64(fp0
);
6942 check_cp1_registers(ctx
, fs
| fd
);
6944 TCGv_i64 fp0
= tcg_temp_new_i64();
6946 gen_load_fpr64(ctx
, fp0
, fs
);
6947 gen_store_fpr64(ctx
, fp0
, fd
);
6948 tcg_temp_free_i64(fp0
);
6953 check_cp1_registers(ctx
, fs
| fd
);
6955 TCGv_i64 fp0
= tcg_temp_new_i64();
6957 gen_load_fpr64(ctx
, fp0
, fs
);
6958 gen_helper_float_chs_d(fp0
, fp0
);
6959 gen_store_fpr64(ctx
, fp0
, fd
);
6960 tcg_temp_free_i64(fp0
);
6965 check_cp1_64bitmode(ctx
);
6967 TCGv_i64 fp0
= tcg_temp_new_i64();
6969 gen_load_fpr64(ctx
, fp0
, fs
);
6970 gen_helper_float_roundl_d(fp0
, fp0
);
6971 gen_store_fpr64(ctx
, fp0
, fd
);
6972 tcg_temp_free_i64(fp0
);
6977 check_cp1_64bitmode(ctx
);
6979 TCGv_i64 fp0
= tcg_temp_new_i64();
6981 gen_load_fpr64(ctx
, fp0
, fs
);
6982 gen_helper_float_truncl_d(fp0
, fp0
);
6983 gen_store_fpr64(ctx
, fp0
, fd
);
6984 tcg_temp_free_i64(fp0
);
6989 check_cp1_64bitmode(ctx
);
6991 TCGv_i64 fp0
= tcg_temp_new_i64();
6993 gen_load_fpr64(ctx
, fp0
, fs
);
6994 gen_helper_float_ceill_d(fp0
, fp0
);
6995 gen_store_fpr64(ctx
, fp0
, fd
);
6996 tcg_temp_free_i64(fp0
);
7001 check_cp1_64bitmode(ctx
);
7003 TCGv_i64 fp0
= tcg_temp_new_i64();
7005 gen_load_fpr64(ctx
, fp0
, fs
);
7006 gen_helper_float_floorl_d(fp0
, fp0
);
7007 gen_store_fpr64(ctx
, fp0
, fd
);
7008 tcg_temp_free_i64(fp0
);
7013 check_cp1_registers(ctx
, fs
);
7015 TCGv_i32 fp32
= tcg_temp_new_i32();
7016 TCGv_i64 fp64
= tcg_temp_new_i64();
7018 gen_load_fpr64(ctx
, fp64
, fs
);
7019 gen_helper_float_roundw_d(fp32
, fp64
);
7020 tcg_temp_free_i64(fp64
);
7021 gen_store_fpr32(fp32
, fd
);
7022 tcg_temp_free_i32(fp32
);
7027 check_cp1_registers(ctx
, fs
);
7029 TCGv_i32 fp32
= tcg_temp_new_i32();
7030 TCGv_i64 fp64
= tcg_temp_new_i64();
7032 gen_load_fpr64(ctx
, fp64
, fs
);
7033 gen_helper_float_truncw_d(fp32
, fp64
);
7034 tcg_temp_free_i64(fp64
);
7035 gen_store_fpr32(fp32
, fd
);
7036 tcg_temp_free_i32(fp32
);
7041 check_cp1_registers(ctx
, fs
);
7043 TCGv_i32 fp32
= tcg_temp_new_i32();
7044 TCGv_i64 fp64
= tcg_temp_new_i64();
7046 gen_load_fpr64(ctx
, fp64
, fs
);
7047 gen_helper_float_ceilw_d(fp32
, fp64
);
7048 tcg_temp_free_i64(fp64
);
7049 gen_store_fpr32(fp32
, fd
);
7050 tcg_temp_free_i32(fp32
);
7055 check_cp1_registers(ctx
, fs
);
7057 TCGv_i32 fp32
= tcg_temp_new_i32();
7058 TCGv_i64 fp64
= tcg_temp_new_i64();
7060 gen_load_fpr64(ctx
, fp64
, fs
);
7061 gen_helper_float_floorw_d(fp32
, fp64
);
7062 tcg_temp_free_i64(fp64
);
7063 gen_store_fpr32(fp32
, fd
);
7064 tcg_temp_free_i32(fp32
);
7069 gen_movcf_d(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
7074 int l1
= gen_new_label();
7078 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
7080 fp0
= tcg_temp_new_i64();
7081 gen_load_fpr64(ctx
, fp0
, fs
);
7082 gen_store_fpr64(ctx
, fp0
, fd
);
7083 tcg_temp_free_i64(fp0
);
7090 int l1
= gen_new_label();
7094 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
7095 fp0
= tcg_temp_new_i64();
7096 gen_load_fpr64(ctx
, fp0
, fs
);
7097 gen_store_fpr64(ctx
, fp0
, fd
);
7098 tcg_temp_free_i64(fp0
);
7105 check_cp1_64bitmode(ctx
);
7107 TCGv_i64 fp0
= tcg_temp_new_i64();
7109 gen_load_fpr64(ctx
, fp0
, fs
);
7110 gen_helper_float_recip_d(fp0
, fp0
);
7111 gen_store_fpr64(ctx
, fp0
, fd
);
7112 tcg_temp_free_i64(fp0
);
7117 check_cp1_64bitmode(ctx
);
7119 TCGv_i64 fp0
= tcg_temp_new_i64();
7121 gen_load_fpr64(ctx
, fp0
, fs
);
7122 gen_helper_float_rsqrt_d(fp0
, fp0
);
7123 gen_store_fpr64(ctx
, fp0
, fd
);
7124 tcg_temp_free_i64(fp0
);
7129 check_cp1_64bitmode(ctx
);
7131 TCGv_i64 fp0
= tcg_temp_new_i64();
7132 TCGv_i64 fp1
= tcg_temp_new_i64();
7134 gen_load_fpr64(ctx
, fp0
, fs
);
7135 gen_load_fpr64(ctx
, fp1
, ft
);
7136 gen_helper_float_recip2_d(fp0
, fp0
, fp1
);
7137 tcg_temp_free_i64(fp1
);
7138 gen_store_fpr64(ctx
, fp0
, fd
);
7139 tcg_temp_free_i64(fp0
);
7144 check_cp1_64bitmode(ctx
);
7146 TCGv_i64 fp0
= tcg_temp_new_i64();
7148 gen_load_fpr64(ctx
, fp0
, fs
);
7149 gen_helper_float_recip1_d(fp0
, fp0
);
7150 gen_store_fpr64(ctx
, fp0
, fd
);
7151 tcg_temp_free_i64(fp0
);
7156 check_cp1_64bitmode(ctx
);
7158 TCGv_i64 fp0
= tcg_temp_new_i64();
7160 gen_load_fpr64(ctx
, fp0
, fs
);
7161 gen_helper_float_rsqrt1_d(fp0
, fp0
);
7162 gen_store_fpr64(ctx
, fp0
, fd
);
7163 tcg_temp_free_i64(fp0
);
7168 check_cp1_64bitmode(ctx
);
7170 TCGv_i64 fp0
= tcg_temp_new_i64();
7171 TCGv_i64 fp1
= tcg_temp_new_i64();
7173 gen_load_fpr64(ctx
, fp0
, fs
);
7174 gen_load_fpr64(ctx
, fp1
, ft
);
7175 gen_helper_float_rsqrt2_d(fp0
, fp0
, fp1
);
7176 tcg_temp_free_i64(fp1
);
7177 gen_store_fpr64(ctx
, fp0
, fd
);
7178 tcg_temp_free_i64(fp0
);
7191 case OPC_CMP_NGLE_D
:
7198 if (ctx
->opcode
& (1 << 6)) {
7199 gen_cmpabs_d(ctx
, func
-48, ft
, fs
, cc
);
7200 opn
= condnames_abs
[func
-48];
7202 gen_cmp_d(ctx
, func
-48, ft
, fs
, cc
);
7203 opn
= condnames
[func
-48];
7207 check_cp1_registers(ctx
, fs
);
7209 TCGv_i32 fp32
= tcg_temp_new_i32();
7210 TCGv_i64 fp64
= tcg_temp_new_i64();
7212 gen_load_fpr64(ctx
, fp64
, fs
);
7213 gen_helper_float_cvts_d(fp32
, fp64
);
7214 tcg_temp_free_i64(fp64
);
7215 gen_store_fpr32(fp32
, fd
);
7216 tcg_temp_free_i32(fp32
);
7221 check_cp1_registers(ctx
, fs
);
7223 TCGv_i32 fp32
= tcg_temp_new_i32();
7224 TCGv_i64 fp64
= tcg_temp_new_i64();
7226 gen_load_fpr64(ctx
, fp64
, fs
);
7227 gen_helper_float_cvtw_d(fp32
, fp64
);
7228 tcg_temp_free_i64(fp64
);
7229 gen_store_fpr32(fp32
, fd
);
7230 tcg_temp_free_i32(fp32
);
7235 check_cp1_64bitmode(ctx
);
7237 TCGv_i64 fp0
= tcg_temp_new_i64();
7239 gen_load_fpr64(ctx
, fp0
, fs
);
7240 gen_helper_float_cvtl_d(fp0
, fp0
);
7241 gen_store_fpr64(ctx
, fp0
, fd
);
7242 tcg_temp_free_i64(fp0
);
7248 TCGv_i32 fp0
= tcg_temp_new_i32();
7250 gen_load_fpr32(fp0
, fs
);
7251 gen_helper_float_cvts_w(fp0
, fp0
);
7252 gen_store_fpr32(fp0
, fd
);
7253 tcg_temp_free_i32(fp0
);
7258 check_cp1_registers(ctx
, fd
);
7260 TCGv_i32 fp32
= tcg_temp_new_i32();
7261 TCGv_i64 fp64
= tcg_temp_new_i64();
7263 gen_load_fpr32(fp32
, fs
);
7264 gen_helper_float_cvtd_w(fp64
, fp32
);
7265 tcg_temp_free_i32(fp32
);
7266 gen_store_fpr64(ctx
, fp64
, fd
);
7267 tcg_temp_free_i64(fp64
);
7272 check_cp1_64bitmode(ctx
);
7274 TCGv_i32 fp32
= tcg_temp_new_i32();
7275 TCGv_i64 fp64
= tcg_temp_new_i64();
7277 gen_load_fpr64(ctx
, fp64
, fs
);
7278 gen_helper_float_cvts_l(fp32
, fp64
);
7279 tcg_temp_free_i64(fp64
);
7280 gen_store_fpr32(fp32
, fd
);
7281 tcg_temp_free_i32(fp32
);
7286 check_cp1_64bitmode(ctx
);
7288 TCGv_i64 fp0
= tcg_temp_new_i64();
7290 gen_load_fpr64(ctx
, fp0
, fs
);
7291 gen_helper_float_cvtd_l(fp0
, fp0
);
7292 gen_store_fpr64(ctx
, fp0
, fd
);
7293 tcg_temp_free_i64(fp0
);
7298 check_cp1_64bitmode(ctx
);
7300 TCGv_i64 fp0
= tcg_temp_new_i64();
7302 gen_load_fpr64(ctx
, fp0
, fs
);
7303 gen_helper_float_cvtps_pw(fp0
, fp0
);
7304 gen_store_fpr64(ctx
, fp0
, fd
);
7305 tcg_temp_free_i64(fp0
);
7310 check_cp1_64bitmode(ctx
);
7312 TCGv_i64 fp0
= tcg_temp_new_i64();
7313 TCGv_i64 fp1
= tcg_temp_new_i64();
7315 gen_load_fpr64(ctx
, fp0
, fs
);
7316 gen_load_fpr64(ctx
, fp1
, ft
);
7317 gen_helper_float_add_ps(fp0
, fp0
, fp1
);
7318 tcg_temp_free_i64(fp1
);
7319 gen_store_fpr64(ctx
, fp0
, fd
);
7320 tcg_temp_free_i64(fp0
);
7325 check_cp1_64bitmode(ctx
);
7327 TCGv_i64 fp0
= tcg_temp_new_i64();
7328 TCGv_i64 fp1
= tcg_temp_new_i64();
7330 gen_load_fpr64(ctx
, fp0
, fs
);
7331 gen_load_fpr64(ctx
, fp1
, ft
);
7332 gen_helper_float_sub_ps(fp0
, fp0
, fp1
);
7333 tcg_temp_free_i64(fp1
);
7334 gen_store_fpr64(ctx
, fp0
, fd
);
7335 tcg_temp_free_i64(fp0
);
7340 check_cp1_64bitmode(ctx
);
7342 TCGv_i64 fp0
= tcg_temp_new_i64();
7343 TCGv_i64 fp1
= tcg_temp_new_i64();
7345 gen_load_fpr64(ctx
, fp0
, fs
);
7346 gen_load_fpr64(ctx
, fp1
, ft
);
7347 gen_helper_float_mul_ps(fp0
, fp0
, fp1
);
7348 tcg_temp_free_i64(fp1
);
7349 gen_store_fpr64(ctx
, fp0
, fd
);
7350 tcg_temp_free_i64(fp0
);
7355 check_cp1_64bitmode(ctx
);
7357 TCGv_i64 fp0
= tcg_temp_new_i64();
7359 gen_load_fpr64(ctx
, fp0
, fs
);
7360 gen_helper_float_abs_ps(fp0
, fp0
);
7361 gen_store_fpr64(ctx
, fp0
, fd
);
7362 tcg_temp_free_i64(fp0
);
7367 check_cp1_64bitmode(ctx
);
7369 TCGv_i64 fp0
= tcg_temp_new_i64();
7371 gen_load_fpr64(ctx
, fp0
, fs
);
7372 gen_store_fpr64(ctx
, fp0
, fd
);
7373 tcg_temp_free_i64(fp0
);
7378 check_cp1_64bitmode(ctx
);
7380 TCGv_i64 fp0
= tcg_temp_new_i64();
7382 gen_load_fpr64(ctx
, fp0
, fs
);
7383 gen_helper_float_chs_ps(fp0
, fp0
);
7384 gen_store_fpr64(ctx
, fp0
, fd
);
7385 tcg_temp_free_i64(fp0
);
7390 check_cp1_64bitmode(ctx
);
7391 gen_movcf_ps(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
7395 check_cp1_64bitmode(ctx
);
7397 int l1
= gen_new_label();
7401 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
7402 fp0
= tcg_temp_new_i64();
7403 gen_load_fpr64(ctx
, fp0
, fs
);
7404 gen_store_fpr64(ctx
, fp0
, fd
);
7405 tcg_temp_free_i64(fp0
);
7411 check_cp1_64bitmode(ctx
);
7413 int l1
= gen_new_label();
7417 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
7418 fp0
= tcg_temp_new_i64();
7419 gen_load_fpr64(ctx
, fp0
, fs
);
7420 gen_store_fpr64(ctx
, fp0
, fd
);
7421 tcg_temp_free_i64(fp0
);
7428 check_cp1_64bitmode(ctx
);
7430 TCGv_i64 fp0
= tcg_temp_new_i64();
7431 TCGv_i64 fp1
= tcg_temp_new_i64();
7433 gen_load_fpr64(ctx
, fp0
, ft
);
7434 gen_load_fpr64(ctx
, fp1
, fs
);
7435 gen_helper_float_addr_ps(fp0
, fp0
, fp1
);
7436 tcg_temp_free_i64(fp1
);
7437 gen_store_fpr64(ctx
, fp0
, fd
);
7438 tcg_temp_free_i64(fp0
);
7443 check_cp1_64bitmode(ctx
);
7445 TCGv_i64 fp0
= tcg_temp_new_i64();
7446 TCGv_i64 fp1
= tcg_temp_new_i64();
7448 gen_load_fpr64(ctx
, fp0
, ft
);
7449 gen_load_fpr64(ctx
, fp1
, fs
);
7450 gen_helper_float_mulr_ps(fp0
, fp0
, fp1
);
7451 tcg_temp_free_i64(fp1
);
7452 gen_store_fpr64(ctx
, fp0
, fd
);
7453 tcg_temp_free_i64(fp0
);
7458 check_cp1_64bitmode(ctx
);
7460 TCGv_i64 fp0
= tcg_temp_new_i64();
7461 TCGv_i64 fp1
= tcg_temp_new_i64();
7463 gen_load_fpr64(ctx
, fp0
, fs
);
7464 gen_load_fpr64(ctx
, fp1
, fd
);
7465 gen_helper_float_recip2_ps(fp0
, fp0
, fp1
);
7466 tcg_temp_free_i64(fp1
);
7467 gen_store_fpr64(ctx
, fp0
, fd
);
7468 tcg_temp_free_i64(fp0
);
7473 check_cp1_64bitmode(ctx
);
7475 TCGv_i64 fp0
= tcg_temp_new_i64();
7477 gen_load_fpr64(ctx
, fp0
, fs
);
7478 gen_helper_float_recip1_ps(fp0
, fp0
);
7479 gen_store_fpr64(ctx
, fp0
, fd
);
7480 tcg_temp_free_i64(fp0
);
7485 check_cp1_64bitmode(ctx
);
7487 TCGv_i64 fp0
= tcg_temp_new_i64();
7489 gen_load_fpr64(ctx
, fp0
, fs
);
7490 gen_helper_float_rsqrt1_ps(fp0
, fp0
);
7491 gen_store_fpr64(ctx
, fp0
, fd
);
7492 tcg_temp_free_i64(fp0
);
7497 check_cp1_64bitmode(ctx
);
7499 TCGv_i64 fp0
= tcg_temp_new_i64();
7500 TCGv_i64 fp1
= tcg_temp_new_i64();
7502 gen_load_fpr64(ctx
, fp0
, fs
);
7503 gen_load_fpr64(ctx
, fp1
, ft
);
7504 gen_helper_float_rsqrt2_ps(fp0
, fp0
, fp1
);
7505 tcg_temp_free_i64(fp1
);
7506 gen_store_fpr64(ctx
, fp0
, fd
);
7507 tcg_temp_free_i64(fp0
);
7512 check_cp1_64bitmode(ctx
);
7514 TCGv_i32 fp0
= tcg_temp_new_i32();
7516 gen_load_fpr32h(fp0
, fs
);
7517 gen_helper_float_cvts_pu(fp0
, fp0
);
7518 gen_store_fpr32(fp0
, fd
);
7519 tcg_temp_free_i32(fp0
);
7524 check_cp1_64bitmode(ctx
);
7526 TCGv_i64 fp0
= tcg_temp_new_i64();
7528 gen_load_fpr64(ctx
, fp0
, fs
);
7529 gen_helper_float_cvtpw_ps(fp0
, fp0
);
7530 gen_store_fpr64(ctx
, fp0
, fd
);
7531 tcg_temp_free_i64(fp0
);
7536 check_cp1_64bitmode(ctx
);
7538 TCGv_i32 fp0
= tcg_temp_new_i32();
7540 gen_load_fpr32(fp0
, fs
);
7541 gen_helper_float_cvts_pl(fp0
, fp0
);
7542 gen_store_fpr32(fp0
, fd
);
7543 tcg_temp_free_i32(fp0
);
7548 check_cp1_64bitmode(ctx
);
7550 TCGv_i32 fp0
= tcg_temp_new_i32();
7551 TCGv_i32 fp1
= tcg_temp_new_i32();
7553 gen_load_fpr32(fp0
, fs
);
7554 gen_load_fpr32(fp1
, ft
);
7555 gen_store_fpr32h(fp0
, fd
);
7556 gen_store_fpr32(fp1
, fd
);
7557 tcg_temp_free_i32(fp0
);
7558 tcg_temp_free_i32(fp1
);
7563 check_cp1_64bitmode(ctx
);
7565 TCGv_i32 fp0
= tcg_temp_new_i32();
7566 TCGv_i32 fp1
= tcg_temp_new_i32();
7568 gen_load_fpr32(fp0
, fs
);
7569 gen_load_fpr32h(fp1
, ft
);
7570 gen_store_fpr32(fp1
, fd
);
7571 gen_store_fpr32h(fp0
, fd
);
7572 tcg_temp_free_i32(fp0
);
7573 tcg_temp_free_i32(fp1
);
7578 check_cp1_64bitmode(ctx
);
7580 TCGv_i32 fp0
= tcg_temp_new_i32();
7581 TCGv_i32 fp1
= tcg_temp_new_i32();
7583 gen_load_fpr32h(fp0
, fs
);
7584 gen_load_fpr32(fp1
, ft
);
7585 gen_store_fpr32(fp1
, fd
);
7586 gen_store_fpr32h(fp0
, fd
);
7587 tcg_temp_free_i32(fp0
);
7588 tcg_temp_free_i32(fp1
);
7593 check_cp1_64bitmode(ctx
);
7595 TCGv_i32 fp0
= tcg_temp_new_i32();
7596 TCGv_i32 fp1
= tcg_temp_new_i32();
7598 gen_load_fpr32h(fp0
, fs
);
7599 gen_load_fpr32h(fp1
, ft
);
7600 gen_store_fpr32(fp1
, fd
);
7601 gen_store_fpr32h(fp0
, fd
);
7602 tcg_temp_free_i32(fp0
);
7603 tcg_temp_free_i32(fp1
);
7610 case OPC_CMP_UEQ_PS
:
7611 case OPC_CMP_OLT_PS
:
7612 case OPC_CMP_ULT_PS
:
7613 case OPC_CMP_OLE_PS
:
7614 case OPC_CMP_ULE_PS
:
7616 case OPC_CMP_NGLE_PS
:
7617 case OPC_CMP_SEQ_PS
:
7618 case OPC_CMP_NGL_PS
:
7620 case OPC_CMP_NGE_PS
:
7622 case OPC_CMP_NGT_PS
:
7623 if (ctx
->opcode
& (1 << 6)) {
7624 gen_cmpabs_ps(ctx
, func
-48, ft
, fs
, cc
);
7625 opn
= condnames_abs
[func
-48];
7627 gen_cmp_ps(ctx
, func
-48, ft
, fs
, cc
);
7628 opn
= condnames
[func
-48];
7633 generate_exception (ctx
, EXCP_RI
);
7636 (void)opn
; /* avoid a compiler warning */
7639 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
7642 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
7645 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
7650 /* Coprocessor 3 (FPU) */
7651 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
7652 int fd
, int fs
, int base
, int index
)
7654 const char *opn
= "extended float load/store";
7656 TCGv t0
= tcg_temp_new();
7659 gen_load_gpr(t0
, index
);
7660 } else if (index
== 0) {
7661 gen_load_gpr(t0
, base
);
7663 gen_load_gpr(t0
, index
);
7664 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], t0
);
7666 /* Don't do NOP if destination is zero: we must perform the actual
7668 save_cpu_state(ctx
, 0);
7673 TCGv_i32 fp0
= tcg_temp_new_i32();
7675 tcg_gen_qemu_ld32s(t0
, t0
, ctx
->mem_idx
);
7676 tcg_gen_trunc_tl_i32(fp0
, t0
);
7677 gen_store_fpr32(fp0
, fd
);
7678 tcg_temp_free_i32(fp0
);
7684 check_cp1_registers(ctx
, fd
);
7686 TCGv_i64 fp0
= tcg_temp_new_i64();
7688 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7689 gen_store_fpr64(ctx
, fp0
, fd
);
7690 tcg_temp_free_i64(fp0
);
7695 check_cp1_64bitmode(ctx
);
7696 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7698 TCGv_i64 fp0
= tcg_temp_new_i64();
7700 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7701 gen_store_fpr64(ctx
, fp0
, fd
);
7702 tcg_temp_free_i64(fp0
);
7709 TCGv_i32 fp0
= tcg_temp_new_i32();
7710 TCGv t1
= tcg_temp_new();
7712 gen_load_fpr32(fp0
, fs
);
7713 tcg_gen_extu_i32_tl(t1
, fp0
);
7714 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
7715 tcg_temp_free_i32(fp0
);
7723 check_cp1_registers(ctx
, fs
);
7725 TCGv_i64 fp0
= tcg_temp_new_i64();
7727 gen_load_fpr64(ctx
, fp0
, fs
);
7728 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7729 tcg_temp_free_i64(fp0
);
7735 check_cp1_64bitmode(ctx
);
7736 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7738 TCGv_i64 fp0
= tcg_temp_new_i64();
7740 gen_load_fpr64(ctx
, fp0
, fs
);
7741 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7742 tcg_temp_free_i64(fp0
);
7749 (void)opn
; (void)store
; /* avoid compiler warnings */
7750 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
7751 regnames
[index
], regnames
[base
]);
7754 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
7755 int fd
, int fr
, int fs
, int ft
)
7757 const char *opn
= "flt3_arith";
7761 check_cp1_64bitmode(ctx
);
7763 TCGv t0
= tcg_temp_local_new();
7764 TCGv_i32 fp
= tcg_temp_new_i32();
7765 TCGv_i32 fph
= tcg_temp_new_i32();
7766 int l1
= gen_new_label();
7767 int l2
= gen_new_label();
7769 gen_load_gpr(t0
, fr
);
7770 tcg_gen_andi_tl(t0
, t0
, 0x7);
7772 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
7773 gen_load_fpr32(fp
, fs
);
7774 gen_load_fpr32h(fph
, fs
);
7775 gen_store_fpr32(fp
, fd
);
7776 gen_store_fpr32h(fph
, fd
);
7779 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 4, l2
);
7781 #ifdef TARGET_WORDS_BIGENDIAN
7782 gen_load_fpr32(fp
, fs
);
7783 gen_load_fpr32h(fph
, ft
);
7784 gen_store_fpr32h(fp
, fd
);
7785 gen_store_fpr32(fph
, fd
);
7787 gen_load_fpr32h(fph
, fs
);
7788 gen_load_fpr32(fp
, ft
);
7789 gen_store_fpr32(fph
, fd
);
7790 gen_store_fpr32h(fp
, fd
);
7793 tcg_temp_free_i32(fp
);
7794 tcg_temp_free_i32(fph
);
7801 TCGv_i32 fp0
= tcg_temp_new_i32();
7802 TCGv_i32 fp1
= tcg_temp_new_i32();
7803 TCGv_i32 fp2
= tcg_temp_new_i32();
7805 gen_load_fpr32(fp0
, fs
);
7806 gen_load_fpr32(fp1
, ft
);
7807 gen_load_fpr32(fp2
, fr
);
7808 gen_helper_float_muladd_s(fp2
, fp0
, fp1
, fp2
);
7809 tcg_temp_free_i32(fp0
);
7810 tcg_temp_free_i32(fp1
);
7811 gen_store_fpr32(fp2
, fd
);
7812 tcg_temp_free_i32(fp2
);
7818 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7820 TCGv_i64 fp0
= tcg_temp_new_i64();
7821 TCGv_i64 fp1
= tcg_temp_new_i64();
7822 TCGv_i64 fp2
= tcg_temp_new_i64();
7824 gen_load_fpr64(ctx
, fp0
, fs
);
7825 gen_load_fpr64(ctx
, fp1
, ft
);
7826 gen_load_fpr64(ctx
, fp2
, fr
);
7827 gen_helper_float_muladd_d(fp2
, fp0
, fp1
, fp2
);
7828 tcg_temp_free_i64(fp0
);
7829 tcg_temp_free_i64(fp1
);
7830 gen_store_fpr64(ctx
, fp2
, fd
);
7831 tcg_temp_free_i64(fp2
);
7836 check_cp1_64bitmode(ctx
);
7838 TCGv_i64 fp0
= tcg_temp_new_i64();
7839 TCGv_i64 fp1
= tcg_temp_new_i64();
7840 TCGv_i64 fp2
= tcg_temp_new_i64();
7842 gen_load_fpr64(ctx
, fp0
, fs
);
7843 gen_load_fpr64(ctx
, fp1
, ft
);
7844 gen_load_fpr64(ctx
, fp2
, fr
);
7845 gen_helper_float_muladd_ps(fp2
, fp0
, fp1
, fp2
);
7846 tcg_temp_free_i64(fp0
);
7847 tcg_temp_free_i64(fp1
);
7848 gen_store_fpr64(ctx
, fp2
, fd
);
7849 tcg_temp_free_i64(fp2
);
7856 TCGv_i32 fp0
= tcg_temp_new_i32();
7857 TCGv_i32 fp1
= tcg_temp_new_i32();
7858 TCGv_i32 fp2
= tcg_temp_new_i32();
7860 gen_load_fpr32(fp0
, fs
);
7861 gen_load_fpr32(fp1
, ft
);
7862 gen_load_fpr32(fp2
, fr
);
7863 gen_helper_float_mulsub_s(fp2
, fp0
, fp1
, fp2
);
7864 tcg_temp_free_i32(fp0
);
7865 tcg_temp_free_i32(fp1
);
7866 gen_store_fpr32(fp2
, fd
);
7867 tcg_temp_free_i32(fp2
);
7873 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7875 TCGv_i64 fp0
= tcg_temp_new_i64();
7876 TCGv_i64 fp1
= tcg_temp_new_i64();
7877 TCGv_i64 fp2
= tcg_temp_new_i64();
7879 gen_load_fpr64(ctx
, fp0
, fs
);
7880 gen_load_fpr64(ctx
, fp1
, ft
);
7881 gen_load_fpr64(ctx
, fp2
, fr
);
7882 gen_helper_float_mulsub_d(fp2
, fp0
, fp1
, fp2
);
7883 tcg_temp_free_i64(fp0
);
7884 tcg_temp_free_i64(fp1
);
7885 gen_store_fpr64(ctx
, fp2
, fd
);
7886 tcg_temp_free_i64(fp2
);
7891 check_cp1_64bitmode(ctx
);
7893 TCGv_i64 fp0
= tcg_temp_new_i64();
7894 TCGv_i64 fp1
= tcg_temp_new_i64();
7895 TCGv_i64 fp2
= tcg_temp_new_i64();
7897 gen_load_fpr64(ctx
, fp0
, fs
);
7898 gen_load_fpr64(ctx
, fp1
, ft
);
7899 gen_load_fpr64(ctx
, fp2
, fr
);
7900 gen_helper_float_mulsub_ps(fp2
, fp0
, fp1
, fp2
);
7901 tcg_temp_free_i64(fp0
);
7902 tcg_temp_free_i64(fp1
);
7903 gen_store_fpr64(ctx
, fp2
, fd
);
7904 tcg_temp_free_i64(fp2
);
7911 TCGv_i32 fp0
= tcg_temp_new_i32();
7912 TCGv_i32 fp1
= tcg_temp_new_i32();
7913 TCGv_i32 fp2
= tcg_temp_new_i32();
7915 gen_load_fpr32(fp0
, fs
);
7916 gen_load_fpr32(fp1
, ft
);
7917 gen_load_fpr32(fp2
, fr
);
7918 gen_helper_float_nmuladd_s(fp2
, fp0
, fp1
, fp2
);
7919 tcg_temp_free_i32(fp0
);
7920 tcg_temp_free_i32(fp1
);
7921 gen_store_fpr32(fp2
, fd
);
7922 tcg_temp_free_i32(fp2
);
7928 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7930 TCGv_i64 fp0
= tcg_temp_new_i64();
7931 TCGv_i64 fp1
= tcg_temp_new_i64();
7932 TCGv_i64 fp2
= tcg_temp_new_i64();
7934 gen_load_fpr64(ctx
, fp0
, fs
);
7935 gen_load_fpr64(ctx
, fp1
, ft
);
7936 gen_load_fpr64(ctx
, fp2
, fr
);
7937 gen_helper_float_nmuladd_d(fp2
, fp0
, fp1
, fp2
);
7938 tcg_temp_free_i64(fp0
);
7939 tcg_temp_free_i64(fp1
);
7940 gen_store_fpr64(ctx
, fp2
, fd
);
7941 tcg_temp_free_i64(fp2
);
7946 check_cp1_64bitmode(ctx
);
7948 TCGv_i64 fp0
= tcg_temp_new_i64();
7949 TCGv_i64 fp1
= tcg_temp_new_i64();
7950 TCGv_i64 fp2
= tcg_temp_new_i64();
7952 gen_load_fpr64(ctx
, fp0
, fs
);
7953 gen_load_fpr64(ctx
, fp1
, ft
);
7954 gen_load_fpr64(ctx
, fp2
, fr
);
7955 gen_helper_float_nmuladd_ps(fp2
, fp0
, fp1
, fp2
);
7956 tcg_temp_free_i64(fp0
);
7957 tcg_temp_free_i64(fp1
);
7958 gen_store_fpr64(ctx
, fp2
, fd
);
7959 tcg_temp_free_i64(fp2
);
7966 TCGv_i32 fp0
= tcg_temp_new_i32();
7967 TCGv_i32 fp1
= tcg_temp_new_i32();
7968 TCGv_i32 fp2
= tcg_temp_new_i32();
7970 gen_load_fpr32(fp0
, fs
);
7971 gen_load_fpr32(fp1
, ft
);
7972 gen_load_fpr32(fp2
, fr
);
7973 gen_helper_float_nmulsub_s(fp2
, fp0
, fp1
, fp2
);
7974 tcg_temp_free_i32(fp0
);
7975 tcg_temp_free_i32(fp1
);
7976 gen_store_fpr32(fp2
, fd
);
7977 tcg_temp_free_i32(fp2
);
7983 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7985 TCGv_i64 fp0
= tcg_temp_new_i64();
7986 TCGv_i64 fp1
= tcg_temp_new_i64();
7987 TCGv_i64 fp2
= tcg_temp_new_i64();
7989 gen_load_fpr64(ctx
, fp0
, fs
);
7990 gen_load_fpr64(ctx
, fp1
, ft
);
7991 gen_load_fpr64(ctx
, fp2
, fr
);
7992 gen_helper_float_nmulsub_d(fp2
, fp0
, fp1
, fp2
);
7993 tcg_temp_free_i64(fp0
);
7994 tcg_temp_free_i64(fp1
);
7995 gen_store_fpr64(ctx
, fp2
, fd
);
7996 tcg_temp_free_i64(fp2
);
8001 check_cp1_64bitmode(ctx
);
8003 TCGv_i64 fp0
= tcg_temp_new_i64();
8004 TCGv_i64 fp1
= tcg_temp_new_i64();
8005 TCGv_i64 fp2
= tcg_temp_new_i64();
8007 gen_load_fpr64(ctx
, fp0
, fs
);
8008 gen_load_fpr64(ctx
, fp1
, ft
);
8009 gen_load_fpr64(ctx
, fp2
, fr
);
8010 gen_helper_float_nmulsub_ps(fp2
, fp0
, fp1
, fp2
);
8011 tcg_temp_free_i64(fp0
);
8012 tcg_temp_free_i64(fp1
);
8013 gen_store_fpr64(ctx
, fp2
, fd
);
8014 tcg_temp_free_i64(fp2
);
8020 generate_exception (ctx
, EXCP_RI
);
8023 (void)opn
; /* avoid a compiler warning */
8024 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
8025 fregnames
[fs
], fregnames
[ft
]);
8029 gen_rdhwr (CPUState
*env
, DisasContext
*ctx
, int rt
, int rd
)
8033 check_insn(env
, ctx
, ISA_MIPS32R2
);
8034 t0
= tcg_temp_new();
8038 save_cpu_state(ctx
, 1);
8039 gen_helper_rdhwr_cpunum(t0
);
8040 gen_store_gpr(t0
, rt
);
8043 save_cpu_state(ctx
, 1);
8044 gen_helper_rdhwr_synci_step(t0
);
8045 gen_store_gpr(t0
, rt
);
8048 save_cpu_state(ctx
, 1);
8049 gen_helper_rdhwr_cc(t0
);
8050 gen_store_gpr(t0
, rt
);
8053 save_cpu_state(ctx
, 1);
8054 gen_helper_rdhwr_ccres(t0
);
8055 gen_store_gpr(t0
, rt
);
8058 #if defined(CONFIG_USER_ONLY)
8059 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, tls_value
));
8060 gen_store_gpr(t0
, rt
);
8063 /* XXX: Some CPUs implement this in hardware.
8064 Not supported yet. */
8066 default: /* Invalid */
8067 MIPS_INVAL("rdhwr");
8068 generate_exception(ctx
, EXCP_RI
);
8074 static void handle_delay_slot (CPUState
*env
, DisasContext
*ctx
,
8077 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
8078 int proc_hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
8079 /* Branches completion */
8080 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
8081 ctx
->bstate
= BS_BRANCH
;
8082 save_cpu_state(ctx
, 0);
8083 /* FIXME: Need to clear can_do_io. */
8084 switch (proc_hflags
& MIPS_HFLAG_BMASK_BASE
) {
8086 /* unconditional branch */
8087 MIPS_DEBUG("unconditional branch");
8088 if (proc_hflags
& MIPS_HFLAG_BX
) {
8089 tcg_gen_xori_i32(hflags
, hflags
, MIPS_HFLAG_M16
);
8091 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8094 /* blikely taken case */
8095 MIPS_DEBUG("blikely branch taken");
8096 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8099 /* Conditional branch */
8100 MIPS_DEBUG("conditional branch");
8102 int l1
= gen_new_label();
8104 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
8105 gen_goto_tb(ctx
, 1, ctx
->pc
+ insn_bytes
);
8107 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8111 /* unconditional branch to register */
8112 MIPS_DEBUG("branch to register");
8113 if (env
->insn_flags
& (ASE_MIPS16
| ASE_MICROMIPS
)) {
8114 TCGv t0
= tcg_temp_new();
8115 TCGv_i32 t1
= tcg_temp_new_i32();
8117 tcg_gen_andi_tl(t0
, btarget
, 0x1);
8118 tcg_gen_trunc_tl_i32(t1
, t0
);
8120 tcg_gen_andi_i32(hflags
, hflags
, ~(uint32_t)MIPS_HFLAG_M16
);
8121 tcg_gen_shli_i32(t1
, t1
, MIPS_HFLAG_M16_SHIFT
);
8122 tcg_gen_or_i32(hflags
, hflags
, t1
);
8123 tcg_temp_free_i32(t1
);
8125 tcg_gen_andi_tl(cpu_PC
, btarget
, ~(target_ulong
)0x1);
8127 tcg_gen_mov_tl(cpu_PC
, btarget
);
8129 if (ctx
->singlestep_enabled
) {
8130 save_cpu_state(ctx
, 0);
8131 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
8136 MIPS_DEBUG("unknown branch");
8142 /* ISA extensions (ASEs) */
8143 /* MIPS16 extension to MIPS32 */
8145 /* MIPS16 major opcodes */
8147 M16_OPC_ADDIUSP
= 0x00,
8148 M16_OPC_ADDIUPC
= 0x01,
8151 M16_OPC_BEQZ
= 0x04,
8152 M16_OPC_BNEQZ
= 0x05,
8153 M16_OPC_SHIFT
= 0x06,
8155 M16_OPC_RRIA
= 0x08,
8156 M16_OPC_ADDIU8
= 0x09,
8157 M16_OPC_SLTI
= 0x0a,
8158 M16_OPC_SLTIU
= 0x0b,
8161 M16_OPC_CMPI
= 0x0e,
8165 M16_OPC_LWSP
= 0x12,
8169 M16_OPC_LWPC
= 0x16,
8173 M16_OPC_SWSP
= 0x1a,
8177 M16_OPC_EXTEND
= 0x1e,
8181 /* I8 funct field */
8200 /* RR funct field */
8234 /* I64 funct field */
8246 /* RR ry field for CNVT */
8248 RR_RY_CNVT_ZEB
= 0x0,
8249 RR_RY_CNVT_ZEH
= 0x1,
8250 RR_RY_CNVT_ZEW
= 0x2,
8251 RR_RY_CNVT_SEB
= 0x4,
8252 RR_RY_CNVT_SEH
= 0x5,
8253 RR_RY_CNVT_SEW
= 0x6,
8256 static int xlat (int r
)
8258 static int map
[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
8263 static void gen_mips16_save (DisasContext
*ctx
,
8264 int xsregs
, int aregs
,
8265 int do_ra
, int do_s0
, int do_s1
,
8268 TCGv t0
= tcg_temp_new();
8269 TCGv t1
= tcg_temp_new();
8299 generate_exception(ctx
, EXCP_RI
);
8305 gen_base_offset_addr(ctx
, t0
, 29, 12);
8306 gen_load_gpr(t1
, 7);
8307 op_st_sw(t1
, t0
, ctx
);
8310 gen_base_offset_addr(ctx
, t0
, 29, 8);
8311 gen_load_gpr(t1
, 6);
8312 op_st_sw(t1
, t0
, ctx
);
8315 gen_base_offset_addr(ctx
, t0
, 29, 4);
8316 gen_load_gpr(t1
, 5);
8317 op_st_sw(t1
, t0
, ctx
);
8320 gen_base_offset_addr(ctx
, t0
, 29, 0);
8321 gen_load_gpr(t1
, 4);
8322 op_st_sw(t1
, t0
, ctx
);
8325 gen_load_gpr(t0
, 29);
8327 #define DECR_AND_STORE(reg) do { \
8328 tcg_gen_subi_tl(t0, t0, 4); \
8329 gen_load_gpr(t1, reg); \
8330 op_st_sw(t1, t0, ctx); \
8394 generate_exception(ctx
, EXCP_RI
);
8410 #undef DECR_AND_STORE
8412 tcg_gen_subi_tl(cpu_gpr
[29], cpu_gpr
[29], framesize
);
8417 static void gen_mips16_restore (DisasContext
*ctx
,
8418 int xsregs
, int aregs
,
8419 int do_ra
, int do_s0
, int do_s1
,
8423 TCGv t0
= tcg_temp_new();
8424 TCGv t1
= tcg_temp_new();
8426 tcg_gen_addi_tl(t0
, cpu_gpr
[29], framesize
);
8428 #define DECR_AND_LOAD(reg) do { \
8429 tcg_gen_subi_tl(t0, t0, 4); \
8430 op_ld_lw(t1, t0, ctx); \
8431 gen_store_gpr(t1, reg); \
8495 generate_exception(ctx
, EXCP_RI
);
8511 #undef DECR_AND_LOAD
8513 tcg_gen_addi_tl(cpu_gpr
[29], cpu_gpr
[29], framesize
);
8518 static void gen_addiupc (DisasContext
*ctx
, int rx
, int imm
,
8519 int is_64_bit
, int extended
)
8523 if (extended
&& (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
8524 generate_exception(ctx
, EXCP_RI
);
8528 t0
= tcg_temp_new();
8530 tcg_gen_movi_tl(t0
, pc_relative_pc(ctx
));
8531 tcg_gen_addi_tl(cpu_gpr
[rx
], t0
, imm
);
8533 tcg_gen_ext32s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
8539 #if defined(TARGET_MIPS64)
8540 static void decode_i64_mips16 (CPUState
*env
, DisasContext
*ctx
,
8541 int ry
, int funct
, int16_t offset
,
8547 offset
= extended
? offset
: offset
<< 3;
8548 gen_ld(env
, ctx
, OPC_LD
, ry
, 29, offset
);
8552 offset
= extended
? offset
: offset
<< 3;
8553 gen_st(ctx
, OPC_SD
, ry
, 29, offset
);
8557 offset
= extended
? offset
: (ctx
->opcode
& 0xff) << 3;
8558 gen_st(ctx
, OPC_SD
, 31, 29, offset
);
8562 offset
= extended
? offset
: ((int8_t)ctx
->opcode
) << 3;
8563 gen_arith_imm(env
, ctx
, OPC_DADDIU
, 29, 29, offset
);
8566 if (extended
&& (ctx
->hflags
& MIPS_HFLAG_BMASK
)) {
8567 generate_exception(ctx
, EXCP_RI
);
8569 offset
= extended
? offset
: offset
<< 3;
8570 gen_ld(env
, ctx
, OPC_LDPC
, ry
, 0, offset
);
8575 offset
= extended
? offset
: ((int8_t)(offset
<< 3)) >> 3;
8576 gen_arith_imm(env
, ctx
, OPC_DADDIU
, ry
, ry
, offset
);
8580 offset
= extended
? offset
: offset
<< 2;
8581 gen_addiupc(ctx
, ry
, offset
, 1, extended
);
8585 offset
= extended
? offset
: offset
<< 2;
8586 gen_arith_imm(env
, ctx
, OPC_DADDIU
, ry
, 29, offset
);
8592 static int decode_extended_mips16_opc (CPUState
*env
, DisasContext
*ctx
,
8595 int extend
= lduw_code(ctx
->pc
+ 2);
8596 int op
, rx
, ry
, funct
, sa
;
8597 int16_t imm
, offset
;
8599 ctx
->opcode
= (ctx
->opcode
<< 16) | extend
;
8600 op
= (ctx
->opcode
>> 11) & 0x1f;
8601 sa
= (ctx
->opcode
>> 22) & 0x1f;
8602 funct
= (ctx
->opcode
>> 8) & 0x7;
8603 rx
= xlat((ctx
->opcode
>> 8) & 0x7);
8604 ry
= xlat((ctx
->opcode
>> 5) & 0x7);
8605 offset
= imm
= (int16_t) (((ctx
->opcode
>> 16) & 0x1f) << 11
8606 | ((ctx
->opcode
>> 21) & 0x3f) << 5
8607 | (ctx
->opcode
& 0x1f));
8609 /* The extended opcodes cleverly reuse the opcodes from their 16-bit
8612 case M16_OPC_ADDIUSP
:
8613 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, 29, imm
);
8615 case M16_OPC_ADDIUPC
:
8616 gen_addiupc(ctx
, rx
, imm
, 0, 1);
8619 gen_compute_branch(ctx
, OPC_BEQ
, 4, 0, 0, offset
<< 1);
8620 /* No delay slot, so just process as a normal instruction */
8623 gen_compute_branch(ctx
, OPC_BEQ
, 4, rx
, 0, offset
<< 1);
8624 /* No delay slot, so just process as a normal instruction */
8627 gen_compute_branch(ctx
, OPC_BNE
, 4, rx
, 0, offset
<< 1);
8628 /* No delay slot, so just process as a normal instruction */
8631 switch (ctx
->opcode
& 0x3) {
8633 gen_shift_imm(env
, ctx
, OPC_SLL
, rx
, ry
, sa
);
8636 #if defined(TARGET_MIPS64)
8638 gen_shift_imm(env
, ctx
, OPC_DSLL
, rx
, ry
, sa
);
8640 generate_exception(ctx
, EXCP_RI
);
8644 gen_shift_imm(env
, ctx
, OPC_SRL
, rx
, ry
, sa
);
8647 gen_shift_imm(env
, ctx
, OPC_SRA
, rx
, ry
, sa
);
8651 #if defined(TARGET_MIPS64)
8654 gen_ld(env
, ctx
, OPC_LD
, ry
, rx
, offset
);
8658 imm
= ctx
->opcode
& 0xf;
8659 imm
= imm
| ((ctx
->opcode
>> 20) & 0x7f) << 4;
8660 imm
= imm
| ((ctx
->opcode
>> 16) & 0xf) << 11;
8661 imm
= (int16_t) (imm
<< 1) >> 1;
8662 if ((ctx
->opcode
>> 4) & 0x1) {
8663 #if defined(TARGET_MIPS64)
8665 gen_arith_imm(env
, ctx
, OPC_DADDIU
, ry
, rx
, imm
);
8667 generate_exception(ctx
, EXCP_RI
);
8670 gen_arith_imm(env
, ctx
, OPC_ADDIU
, ry
, rx
, imm
);
8673 case M16_OPC_ADDIU8
:
8674 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, rx
, imm
);
8677 gen_slt_imm(env
, OPC_SLTI
, 24, rx
, imm
);
8680 gen_slt_imm(env
, OPC_SLTIU
, 24, rx
, imm
);
8685 gen_compute_branch(ctx
, OPC_BEQ
, 4, 24, 0, offset
<< 1);
8688 gen_compute_branch(ctx
, OPC_BNE
, 4, 24, 0, offset
<< 1);
8691 gen_st(ctx
, OPC_SW
, 31, 29, imm
);
8694 gen_arith_imm(env
, ctx
, OPC_ADDIU
, 29, 29, imm
);
8698 int xsregs
= (ctx
->opcode
>> 24) & 0x7;
8699 int aregs
= (ctx
->opcode
>> 16) & 0xf;
8700 int do_ra
= (ctx
->opcode
>> 6) & 0x1;
8701 int do_s0
= (ctx
->opcode
>> 5) & 0x1;
8702 int do_s1
= (ctx
->opcode
>> 4) & 0x1;
8703 int framesize
= (((ctx
->opcode
>> 20) & 0xf) << 4
8704 | (ctx
->opcode
& 0xf)) << 3;
8706 if (ctx
->opcode
& (1 << 7)) {
8707 gen_mips16_save(ctx
, xsregs
, aregs
,
8708 do_ra
, do_s0
, do_s1
,
8711 gen_mips16_restore(ctx
, xsregs
, aregs
,
8712 do_ra
, do_s0
, do_s1
,
8718 generate_exception(ctx
, EXCP_RI
);
8723 tcg_gen_movi_tl(cpu_gpr
[rx
], (uint16_t) imm
);
8726 tcg_gen_xori_tl(cpu_gpr
[24], cpu_gpr
[rx
], (uint16_t) imm
);
8728 #if defined(TARGET_MIPS64)
8730 gen_st(ctx
, OPC_SD
, ry
, rx
, offset
);
8734 gen_ld(env
, ctx
, OPC_LB
, ry
, rx
, offset
);
8737 gen_ld(env
, ctx
, OPC_LH
, ry
, rx
, offset
);
8740 gen_ld(env
, ctx
, OPC_LW
, rx
, 29, offset
);
8743 gen_ld(env
, ctx
, OPC_LW
, ry
, rx
, offset
);
8746 gen_ld(env
, ctx
, OPC_LBU
, ry
, rx
, offset
);
8749 gen_ld(env
, ctx
, OPC_LHU
, ry
, rx
, offset
);
8752 gen_ld(env
, ctx
, OPC_LWPC
, rx
, 0, offset
);
8754 #if defined(TARGET_MIPS64)
8756 gen_ld(env
, ctx
, OPC_LWU
, ry
, rx
, offset
);
8760 gen_st(ctx
, OPC_SB
, ry
, rx
, offset
);
8763 gen_st(ctx
, OPC_SH
, ry
, rx
, offset
);
8766 gen_st(ctx
, OPC_SW
, rx
, 29, offset
);
8769 gen_st(ctx
, OPC_SW
, ry
, rx
, offset
);
8771 #if defined(TARGET_MIPS64)
8773 decode_i64_mips16(env
, ctx
, ry
, funct
, offset
, 1);
8777 generate_exception(ctx
, EXCP_RI
);
8784 static int decode_mips16_opc (CPUState
*env
, DisasContext
*ctx
,
8789 int op
, cnvt_op
, op1
, offset
;
8793 op
= (ctx
->opcode
>> 11) & 0x1f;
8794 sa
= (ctx
->opcode
>> 2) & 0x7;
8795 sa
= sa
== 0 ? 8 : sa
;
8796 rx
= xlat((ctx
->opcode
>> 8) & 0x7);
8797 cnvt_op
= (ctx
->opcode
>> 5) & 0x7;
8798 ry
= xlat((ctx
->opcode
>> 5) & 0x7);
8799 op1
= offset
= ctx
->opcode
& 0x1f;
8804 case M16_OPC_ADDIUSP
:
8806 int16_t imm
= ((uint8_t) ctx
->opcode
) << 2;
8808 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, 29, imm
);
8811 case M16_OPC_ADDIUPC
:
8812 gen_addiupc(ctx
, rx
, ((uint8_t) ctx
->opcode
) << 2, 0, 0);
8815 offset
= (ctx
->opcode
& 0x7ff) << 1;
8816 offset
= (int16_t)(offset
<< 4) >> 4;
8817 gen_compute_branch(ctx
, OPC_BEQ
, 2, 0, 0, offset
);
8818 /* No delay slot, so just process as a normal instruction */
8821 offset
= lduw_code(ctx
->pc
+ 2);
8822 offset
= (((ctx
->opcode
& 0x1f) << 21)
8823 | ((ctx
->opcode
>> 5) & 0x1f) << 16
8825 op
= ((ctx
->opcode
>> 10) & 0x1) ? OPC_JALXS
: OPC_JALS
;
8826 gen_compute_branch(ctx
, op
, 4, rx
, ry
, offset
);
8831 gen_compute_branch(ctx
, OPC_BEQ
, 2, rx
, 0, ((int8_t)ctx
->opcode
) << 1);
8832 /* No delay slot, so just process as a normal instruction */
8835 gen_compute_branch(ctx
, OPC_BNE
, 2, rx
, 0, ((int8_t)ctx
->opcode
) << 1);
8836 /* No delay slot, so just process as a normal instruction */
8839 switch (ctx
->opcode
& 0x3) {
8841 gen_shift_imm(env
, ctx
, OPC_SLL
, rx
, ry
, sa
);
8844 #if defined(TARGET_MIPS64)
8846 gen_shift_imm(env
, ctx
, OPC_DSLL
, rx
, ry
, sa
);
8848 generate_exception(ctx
, EXCP_RI
);
8852 gen_shift_imm(env
, ctx
, OPC_SRL
, rx
, ry
, sa
);
8855 gen_shift_imm(env
, ctx
, OPC_SRA
, rx
, ry
, sa
);
8859 #if defined(TARGET_MIPS64)
8862 gen_ld(env
, ctx
, OPC_LD
, ry
, rx
, offset
<< 3);
8867 int16_t imm
= (int8_t)((ctx
->opcode
& 0xf) << 4) >> 4;
8869 if ((ctx
->opcode
>> 4) & 1) {
8870 #if defined(TARGET_MIPS64)
8872 gen_arith_imm(env
, ctx
, OPC_DADDIU
, ry
, rx
, imm
);
8874 generate_exception(ctx
, EXCP_RI
);
8877 gen_arith_imm(env
, ctx
, OPC_ADDIU
, ry
, rx
, imm
);
8881 case M16_OPC_ADDIU8
:
8883 int16_t imm
= (int8_t) ctx
->opcode
;
8885 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, rx
, imm
);
8890 int16_t imm
= (uint8_t) ctx
->opcode
;
8892 gen_slt_imm(env
, OPC_SLTI
, 24, rx
, imm
);
8897 int16_t imm
= (uint8_t) ctx
->opcode
;
8899 gen_slt_imm(env
, OPC_SLTIU
, 24, rx
, imm
);
8906 funct
= (ctx
->opcode
>> 8) & 0x7;
8909 gen_compute_branch(ctx
, OPC_BEQ
, 2, 24, 0,
8910 ((int8_t)ctx
->opcode
) << 1);
8913 gen_compute_branch(ctx
, OPC_BNE
, 2, 24, 0,
8914 ((int8_t)ctx
->opcode
) << 1);
8917 gen_st(ctx
, OPC_SW
, 31, 29, (ctx
->opcode
& 0xff) << 2);
8920 gen_arith_imm(env
, ctx
, OPC_ADDIU
, 29, 29,
8921 ((int8_t)ctx
->opcode
) << 3);
8925 int do_ra
= ctx
->opcode
& (1 << 6);
8926 int do_s0
= ctx
->opcode
& (1 << 5);
8927 int do_s1
= ctx
->opcode
& (1 << 4);
8928 int framesize
= ctx
->opcode
& 0xf;
8930 if (framesize
== 0) {
8933 framesize
= framesize
<< 3;
8936 if (ctx
->opcode
& (1 << 7)) {
8937 gen_mips16_save(ctx
, 0, 0,
8938 do_ra
, do_s0
, do_s1
, framesize
);
8940 gen_mips16_restore(ctx
, 0, 0,
8941 do_ra
, do_s0
, do_s1
, framesize
);
8947 int rz
= xlat(ctx
->opcode
& 0x7);
8949 reg32
= (((ctx
->opcode
>> 3) & 0x3) << 3) |
8950 ((ctx
->opcode
>> 5) & 0x7);
8951 gen_arith(env
, ctx
, OPC_ADDU
, reg32
, rz
, 0);
8955 reg32
= ctx
->opcode
& 0x1f;
8956 gen_arith(env
, ctx
, OPC_ADDU
, ry
, reg32
, 0);
8959 generate_exception(ctx
, EXCP_RI
);
8966 int16_t imm
= (uint8_t) ctx
->opcode
;
8968 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rx
, 0, imm
);
8973 int16_t imm
= (uint8_t) ctx
->opcode
;
8975 gen_logic_imm(env
, OPC_XORI
, 24, rx
, imm
);
8978 #if defined(TARGET_MIPS64)
8981 gen_st(ctx
, OPC_SD
, ry
, rx
, offset
<< 3);
8985 gen_ld(env
, ctx
, OPC_LB
, ry
, rx
, offset
);
8988 gen_ld(env
, ctx
, OPC_LH
, ry
, rx
, offset
<< 1);
8991 gen_ld(env
, ctx
, OPC_LW
, rx
, 29, ((uint8_t)ctx
->opcode
) << 2);
8994 gen_ld(env
, ctx
, OPC_LW
, ry
, rx
, offset
<< 2);
8997 gen_ld(env
, ctx
, OPC_LBU
, ry
, rx
, offset
);
9000 gen_ld(env
, ctx
, OPC_LHU
, ry
, rx
, offset
<< 1);
9003 gen_ld(env
, ctx
, OPC_LWPC
, rx
, 0, ((uint8_t)ctx
->opcode
) << 2);
9005 #if defined (TARGET_MIPS64)
9008 gen_ld(env
, ctx
, OPC_LWU
, ry
, rx
, offset
<< 2);
9012 gen_st(ctx
, OPC_SB
, ry
, rx
, offset
);
9015 gen_st(ctx
, OPC_SH
, ry
, rx
, offset
<< 1);
9018 gen_st(ctx
, OPC_SW
, rx
, 29, ((uint8_t)ctx
->opcode
) << 2);
9021 gen_st(ctx
, OPC_SW
, ry
, rx
, offset
<< 2);
9025 int rz
= xlat((ctx
->opcode
>> 2) & 0x7);
9028 switch (ctx
->opcode
& 0x3) {
9030 mips32_op
= OPC_ADDU
;
9033 mips32_op
= OPC_SUBU
;
9035 #if defined(TARGET_MIPS64)
9037 mips32_op
= OPC_DADDU
;
9041 mips32_op
= OPC_DSUBU
;
9046 generate_exception(ctx
, EXCP_RI
);
9050 gen_arith(env
, ctx
, mips32_op
, rz
, rx
, ry
);
9059 int nd
= (ctx
->opcode
>> 7) & 0x1;
9060 int link
= (ctx
->opcode
>> 6) & 0x1;
9061 int ra
= (ctx
->opcode
>> 5) & 0x1;
9064 op
= nd
? OPC_JALRC
: OPC_JALRS
;
9069 gen_compute_branch(ctx
, op
, 2, ra
? 31 : rx
, 31, 0);
9076 /* XXX: not clear which exception should be raised
9077 * when in debug mode...
9079 check_insn(env
, ctx
, ISA_MIPS32
);
9080 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
9081 generate_exception(ctx
, EXCP_DBp
);
9083 generate_exception(ctx
, EXCP_DBp
);
9087 gen_slt(env
, OPC_SLT
, 24, rx
, ry
);
9090 gen_slt(env
, OPC_SLTU
, 24, rx
, ry
);
9093 generate_exception(ctx
, EXCP_BREAK
);
9096 gen_shift(env
, ctx
, OPC_SLLV
, ry
, rx
, ry
);
9099 gen_shift(env
, ctx
, OPC_SRLV
, ry
, rx
, ry
);
9102 gen_shift(env
, ctx
, OPC_SRAV
, ry
, rx
, ry
);
9104 #if defined (TARGET_MIPS64)
9107 gen_shift_imm(env
, ctx
, OPC_DSRL
, ry
, ry
, sa
);
9111 gen_logic(env
, OPC_XOR
, 24, rx
, ry
);
9114 gen_arith(env
, ctx
, OPC_SUBU
, rx
, 0, ry
);
9117 gen_logic(env
, OPC_AND
, rx
, rx
, ry
);
9120 gen_logic(env
, OPC_OR
, rx
, rx
, ry
);
9123 gen_logic(env
, OPC_XOR
, rx
, rx
, ry
);
9126 gen_logic(env
, OPC_NOR
, rx
, ry
, 0);
9129 gen_HILO(ctx
, OPC_MFHI
, rx
);
9133 case RR_RY_CNVT_ZEB
:
9134 tcg_gen_ext8u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
9136 case RR_RY_CNVT_ZEH
:
9137 tcg_gen_ext16u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
9139 case RR_RY_CNVT_SEB
:
9140 tcg_gen_ext8s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
9142 case RR_RY_CNVT_SEH
:
9143 tcg_gen_ext16s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
9145 #if defined (TARGET_MIPS64)
9146 case RR_RY_CNVT_ZEW
:
9148 tcg_gen_ext32u_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
9150 case RR_RY_CNVT_SEW
:
9152 tcg_gen_ext32s_tl(cpu_gpr
[rx
], cpu_gpr
[rx
]);
9156 generate_exception(ctx
, EXCP_RI
);
9161 gen_HILO(ctx
, OPC_MFLO
, rx
);
9163 #if defined (TARGET_MIPS64)
9166 gen_shift_imm(env
, ctx
, OPC_DSRA
, ry
, ry
, sa
);
9170 gen_shift(env
, ctx
, OPC_DSLLV
, ry
, rx
, ry
);
9174 gen_shift(env
, ctx
, OPC_DSRLV
, ry
, rx
, ry
);
9178 gen_shift(env
, ctx
, OPC_DSRAV
, ry
, rx
, ry
);
9182 gen_muldiv(ctx
, OPC_MULT
, rx
, ry
);
9185 gen_muldiv(ctx
, OPC_MULTU
, rx
, ry
);
9188 gen_muldiv(ctx
, OPC_DIV
, rx
, ry
);
9191 gen_muldiv(ctx
, OPC_DIVU
, rx
, ry
);
9193 #if defined (TARGET_MIPS64)
9196 gen_muldiv(ctx
, OPC_DMULT
, rx
, ry
);
9200 gen_muldiv(ctx
, OPC_DMULTU
, rx
, ry
);
9204 gen_muldiv(ctx
, OPC_DDIV
, rx
, ry
);
9208 gen_muldiv(ctx
, OPC_DDIVU
, rx
, ry
);
9212 generate_exception(ctx
, EXCP_RI
);
9216 case M16_OPC_EXTEND
:
9217 decode_extended_mips16_opc(env
, ctx
, is_branch
);
9220 #if defined(TARGET_MIPS64)
9222 funct
= (ctx
->opcode
>> 8) & 0x7;
9223 decode_i64_mips16(env
, ctx
, ry
, funct
, offset
, 0);
9227 generate_exception(ctx
, EXCP_RI
);
9234 /* microMIPS extension to MIPS32 */
9236 /* microMIPS32 major opcodes */
9275 /* 0x20 is reserved */
9285 /* 0x28 and 0x29 are reserved */
9295 /* 0x30 and 0x31 are reserved */
9305 /* 0x38 and 0x39 are reserved */
9316 /* POOL32A encoding of minor opcode field */
9319 /* These opcodes are distinguished only by bits 9..6; those bits are
9320 * what are recorded below. */
9346 /* The following can be distinguished by their lower 6 bits. */
9352 /* POOL32AXF encoding of minor opcode field extension */
9366 /* bits 13..12 for 0x01 */
9372 /* bits 13..12 for 0x2a */
9378 /* bits 13..12 for 0x32 */
9382 /* bits 15..12 for 0x2c */
9398 /* bits 15..12 for 0x34 */
9406 /* bits 15..12 for 0x3c */
9408 JR
= 0x0, /* alias */
9413 /* bits 15..12 for 0x05 */
9417 /* bits 15..12 for 0x0d */
9427 /* bits 15..12 for 0x15 */
9433 /* bits 15..12 for 0x1d */
9437 /* bits 15..12 for 0x2d */
9442 /* bits 15..12 for 0x35 */
9449 /* POOL32B encoding of minor opcode field (bits 15..12) */
9465 /* POOL32C encoding of minor opcode field (bits 15..12) */
9473 /* 0xa is reserved */
9480 /* 0x6 is reserved */
9486 /* POOL32F encoding of minor opcode field (bits 5..0) */
9489 /* These are the bit 7..6 values */
9500 /* These are the bit 8..6 values */
9544 CABS_COND_FMT
= 0x1c, /* MIPS3D */
9548 /* POOL32Fxf encoding of minor opcode extension field */
9586 /* POOL32I encoding of minor opcode field (bits 25..21) */
9611 /* These overlap and are distinguished by bit16 of the instruction */
9620 /* POOL16A encoding of minor opcode field */
9627 /* POOL16B encoding of minor opcode field */
9634 /* POOL16C encoding of minor opcode field */
9654 /* POOL16D encoding of minor opcode field */
9661 /* POOL16E encoding of minor opcode field */
9668 static int mmreg (int r
)
9670 static const int map
[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
9675 /* Used for 16-bit store instructions. */
9676 static int mmreg2 (int r
)
9678 static const int map
[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
9683 #define uMIPS_RD(op) ((op >> 7) & 0x7)
9684 #define uMIPS_RS(op) ((op >> 4) & 0x7)
9685 #define uMIPS_RS2(op) uMIPS_RS(op)
9686 #define uMIPS_RS1(op) ((op >> 1) & 0x7)
9687 #define uMIPS_RD5(op) ((op >> 5) & 0x1f)
9688 #define uMIPS_RS5(op) (op & 0x1f)
9690 /* Signed immediate */
9691 #define SIMM(op, start, width) \
9692 ((int32_t)(((op >> start) & ((~0U) >> (32-width))) \
9695 /* Zero-extended immediate */
9696 #define ZIMM(op, start, width) ((op >> start) & ((~0U) >> (32-width)))
9698 static void gen_addiur1sp (CPUState
*env
, DisasContext
*ctx
)
9700 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
9702 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rd
, 29, ((ctx
->opcode
>> 1) & 0x3f) << 2);
9705 static void gen_addiur2 (CPUState
*env
, DisasContext
*ctx
)
9707 static const int decoded_imm
[] = { 1, 4, 8, 12, 16, 20, 24, -1 };
9708 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
9709 int rs
= mmreg(uMIPS_RS(ctx
->opcode
));
9711 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rd
, rs
, decoded_imm
[ZIMM(ctx
->opcode
, 1, 3)]);
9714 static void gen_addiusp (CPUState
*env
, DisasContext
*ctx
)
9716 int encoded
= ZIMM(ctx
->opcode
, 1, 9);
9720 decoded
= 256 + encoded
;
9721 } else if (encoded
<= 255) {
9723 } else if (encoded
<= 509) {
9724 decoded
= encoded
- 512;
9726 decoded
= encoded
- 768;
9729 gen_arith_imm(env
, ctx
, OPC_ADDIU
, 29, 29, decoded
<< 2);
9732 static void gen_addius5 (CPUState
*env
, DisasContext
*ctx
)
9734 int imm
= SIMM(ctx
->opcode
, 1, 4);
9735 int rd
= (ctx
->opcode
>> 5) & 0x1f;
9737 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rd
, rd
, imm
);
9740 static void gen_andi16 (CPUState
*env
, DisasContext
*ctx
)
9742 static const int decoded_imm
[] = { 128, 1, 2, 3, 4, 7, 8, 15, 16,
9743 31, 32, 63, 64, 255, 32768, 65535 };
9744 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
9745 int rs
= mmreg(uMIPS_RS(ctx
->opcode
));
9746 int encoded
= ZIMM(ctx
->opcode
, 0, 4);
9748 gen_logic_imm(env
, OPC_ANDI
, rd
, rs
, decoded_imm
[encoded
]);
9751 static void gen_ldst_multiple (DisasContext
*ctx
, uint32_t opc
, int reglist
,
9752 int base
, int16_t offset
)
9757 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
9758 generate_exception(ctx
, EXCP_RI
);
9762 t0
= tcg_temp_new();
9764 gen_base_offset_addr(ctx
, t0
, base
, offset
);
9766 t1
= tcg_const_tl(reglist
);
9767 t2
= tcg_const_i32(ctx
->mem_idx
);
9769 save_cpu_state(ctx
, 1);
9772 gen_helper_lwm(t0
, t1
, t2
);
9775 gen_helper_swm(t0
, t1
, t2
);
9777 #ifdef TARGET_MIPS64
9779 gen_helper_ldm(t0
, t1
, t2
);
9782 gen_helper_sdm(t0
, t1
, t2
);
9786 MIPS_DEBUG("%s, %x, %d(%s)", opn
, reglist
, offset
, regnames
[base
]);
9789 tcg_temp_free_i32(t2
);
9793 static void gen_pool16c_insn (CPUState
*env
, DisasContext
*ctx
, int *is_branch
)
9795 int rd
= mmreg((ctx
->opcode
>> 3) & 0x7);
9796 int rs
= mmreg(ctx
->opcode
& 0x7);
9799 switch (((ctx
->opcode
) >> 4) & 0x3f) {
9804 gen_logic(env
, OPC_NOR
, rd
, rs
, 0);
9810 gen_logic(env
, OPC_XOR
, rd
, rd
, rs
);
9816 gen_logic(env
, OPC_AND
, rd
, rd
, rs
);
9822 gen_logic(env
, OPC_OR
, rd
, rd
, rs
);
9829 static const int lwm_convert
[] = { 0x11, 0x12, 0x13, 0x14 };
9830 int offset
= ZIMM(ctx
->opcode
, 0, 4);
9832 gen_ldst_multiple(ctx
, LWM32
, lwm_convert
[(ctx
->opcode
>> 4) & 0x3],
9841 static const int swm_convert
[] = { 0x11, 0x12, 0x13, 0x14 };
9842 int offset
= ZIMM(ctx
->opcode
, 0, 4);
9844 gen_ldst_multiple(ctx
, SWM32
, swm_convert
[(ctx
->opcode
>> 4) & 0x3],
9851 int reg
= ctx
->opcode
& 0x1f;
9853 gen_compute_branch(ctx
, OPC_JR
, 2, reg
, 0, 0);
9860 int reg
= ctx
->opcode
& 0x1f;
9862 gen_compute_branch(ctx
, OPC_JR
, 2, reg
, 0, 0);
9863 /* Let normal delay slot handling in our caller take us
9864 to the branch target. */
9876 int reg
= ctx
->opcode
& 0x1f;
9878 gen_compute_branch(ctx
, opc
, 2, reg
, 31, 0);
9884 gen_HILO(ctx
, OPC_MFHI
, uMIPS_RS5(ctx
->opcode
));
9888 gen_HILO(ctx
, OPC_MFLO
, uMIPS_RS5(ctx
->opcode
));
9891 generate_exception(ctx
, EXCP_BREAK
);
9894 /* XXX: not clear which exception should be raised
9895 * when in debug mode...
9897 check_insn(env
, ctx
, ISA_MIPS32
);
9898 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
9899 generate_exception(ctx
, EXCP_DBp
);
9901 generate_exception(ctx
, EXCP_DBp
);
9907 int imm
= ZIMM(ctx
->opcode
, 0, 5);
9909 gen_compute_branch(ctx
, OPC_JR
, 2, 31, 0, 0);
9910 gen_arith_imm(env
, ctx
, OPC_ADDIU
, 29, 29, imm
<< 2);
9911 /* Let normal delay slot handling in our caller take us
9912 to the branch target. */
9916 generate_exception(ctx
, EXCP_RI
);
9921 static void gen_ldxs (DisasContext
*ctx
, int base
, int index
, int rd
)
9923 TCGv t0
= tcg_temp_new();
9924 TCGv t1
= tcg_temp_new();
9926 gen_load_gpr(t0
, base
);
9929 gen_load_gpr(t1
, index
);
9930 tcg_gen_shli_tl(t1
, t1
, 2);
9931 gen_op_addr_add(ctx
, t0
, t1
, t0
);
9934 save_cpu_state(ctx
, 0);
9935 op_ld_lw(t1
, t0
, ctx
);
9936 gen_store_gpr(t1
, rd
);
9942 static void gen_ldst_pair (DisasContext
*ctx
, uint32_t opc
, int rd
,
9943 int base
, int16_t offset
)
9945 const char *opn
= "ldst_pair";
9948 if (ctx
->hflags
& MIPS_HFLAG_BMASK
|| rd
== 31 || rd
== base
) {
9949 generate_exception(ctx
, EXCP_RI
);
9953 t0
= tcg_temp_new();
9954 t1
= tcg_temp_new();
9956 gen_base_offset_addr(ctx
, t0
, base
, offset
);
9960 save_cpu_state(ctx
, 0);
9961 op_ld_lw(t1
, t0
, ctx
);
9962 gen_store_gpr(t1
, rd
);
9963 tcg_gen_movi_tl(t1
, 4);
9964 gen_op_addr_add(ctx
, t0
, t0
, t1
);
9965 op_ld_lw(t1
, t0
, ctx
);
9966 gen_store_gpr(t1
, rd
+1);
9970 save_cpu_state(ctx
, 1);
9971 gen_load_gpr(t1
, rd
);
9972 op_st_sw(t1
, t0
, ctx
);
9973 tcg_gen_movi_tl(t1
, 4);
9974 gen_op_addr_add(ctx
, t0
, t0
, t1
);
9975 gen_load_gpr(t1
, rd
+1);
9976 op_st_sw(t1
, t0
, ctx
);
9979 #ifdef TARGET_MIPS64
9981 save_cpu_state(ctx
, 0);
9982 op_ld_ld(t1
, t0
, ctx
);
9983 gen_store_gpr(t1
, rd
);
9984 tcg_gen_movi_tl(t1
, 8);
9985 gen_op_addr_add(ctx
, t0
, t0
, t1
);
9986 op_ld_ld(t1
, t0
, ctx
);
9987 gen_store_gpr(t1
, rd
+1);
9991 save_cpu_state(ctx
, 1);
9992 gen_load_gpr(t1
, rd
);
9993 op_st_sd(t1
, t0
, ctx
);
9994 tcg_gen_movi_tl(t1
, 8);
9995 gen_op_addr_add(ctx
, t0
, t0
, t1
);
9996 gen_load_gpr(t1
, rd
+1);
9997 op_st_sd(t1
, t0
, ctx
);
10002 (void)opn
; /* avoid a compiler warning */
10003 MIPS_DEBUG("%s, %s, %d(%s)", opn
, regnames
[rd
], offset
, regnames
[base
]);
10008 static void gen_pool32axf (CPUState
*env
, DisasContext
*ctx
, int rt
, int rs
,
10011 int extension
= (ctx
->opcode
>> 6) & 0x3f;
10012 int minor
= (ctx
->opcode
>> 12) & 0xf;
10013 uint32_t mips32_op
;
10015 switch (extension
) {
10017 mips32_op
= OPC_TEQ
;
10020 mips32_op
= OPC_TGE
;
10023 mips32_op
= OPC_TGEU
;
10026 mips32_op
= OPC_TLT
;
10029 mips32_op
= OPC_TLTU
;
10032 mips32_op
= OPC_TNE
;
10034 gen_trap(ctx
, mips32_op
, rs
, rt
, -1);
10036 #ifndef CONFIG_USER_ONLY
10040 /* Treat as NOP. */
10043 gen_mfc0(env
, ctx
, cpu_gpr
[rt
], rs
, (ctx
->opcode
>> 11) & 0x7);
10048 TCGv t0
= tcg_temp_new();
10050 gen_load_gpr(t0
, rt
);
10051 gen_mtc0(env
, ctx
, t0
, rs
, (ctx
->opcode
>> 11) & 0x7);
10059 gen_bshfl(ctx
, OPC_SEB
, rs
, rt
);
10062 gen_bshfl(ctx
, OPC_SEH
, rs
, rt
);
10065 mips32_op
= OPC_CLO
;
10068 mips32_op
= OPC_CLZ
;
10070 check_insn(env
, ctx
, ISA_MIPS32
);
10071 gen_cl(ctx
, mips32_op
, rt
, rs
);
10074 gen_rdhwr(env
, ctx
, rt
, rs
);
10077 gen_bshfl(ctx
, OPC_WSBH
, rs
, rt
);
10080 mips32_op
= OPC_MULT
;
10083 mips32_op
= OPC_MULTU
;
10086 mips32_op
= OPC_DIV
;
10089 mips32_op
= OPC_DIVU
;
10092 mips32_op
= OPC_MADD
;
10095 mips32_op
= OPC_MADDU
;
10098 mips32_op
= OPC_MSUB
;
10101 mips32_op
= OPC_MSUBU
;
10103 check_insn(env
, ctx
, ISA_MIPS32
);
10104 gen_muldiv(ctx
, mips32_op
, rs
, rt
);
10107 goto pool32axf_invalid
;
10118 generate_exception_err(ctx
, EXCP_CpU
, 2);
10121 goto pool32axf_invalid
;
10128 gen_compute_branch (ctx
, OPC_JALR
, 4, rs
, rt
, 0);
10133 gen_compute_branch (ctx
, OPC_JALRS
, 4, rs
, rt
, 0);
10137 goto pool32axf_invalid
;
10143 check_insn(env
, ctx
, ISA_MIPS32R2
);
10144 gen_load_srsgpr(rt
, rs
);
10147 check_insn(env
, ctx
, ISA_MIPS32R2
);
10148 gen_store_srsgpr(rt
, rs
);
10151 goto pool32axf_invalid
;
10154 #ifndef CONFIG_USER_ONLY
10158 mips32_op
= OPC_TLBP
;
10161 mips32_op
= OPC_TLBR
;
10164 mips32_op
= OPC_TLBWI
;
10167 mips32_op
= OPC_TLBWR
;
10170 mips32_op
= OPC_WAIT
;
10173 mips32_op
= OPC_DERET
;
10176 mips32_op
= OPC_ERET
;
10178 gen_cp0(env
, ctx
, mips32_op
, rt
, rs
);
10181 goto pool32axf_invalid
;
10188 TCGv t0
= tcg_temp_new();
10190 save_cpu_state(ctx
, 1);
10192 gen_store_gpr(t0
, rs
);
10193 /* Stop translation as we may have switched the execution mode */
10194 ctx
->bstate
= BS_STOP
;
10200 TCGv t0
= tcg_temp_new();
10202 save_cpu_state(ctx
, 1);
10204 gen_store_gpr(t0
, rs
);
10205 /* Stop translation as we may have switched the execution mode */
10206 ctx
->bstate
= BS_STOP
;
10211 goto pool32axf_invalid
;
10221 generate_exception(ctx
, EXCP_SYSCALL
);
10222 ctx
->bstate
= BS_STOP
;
10225 check_insn(env
, ctx
, ISA_MIPS32
);
10226 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
10227 generate_exception(ctx
, EXCP_DBp
);
10229 generate_exception(ctx
, EXCP_DBp
);
10233 goto pool32axf_invalid
;
10239 gen_HILO(ctx
, OPC_MFHI
, rs
);
10242 gen_HILO(ctx
, OPC_MFLO
, rs
);
10245 gen_HILO(ctx
, OPC_MTHI
, rs
);
10248 gen_HILO(ctx
, OPC_MTLO
, rs
);
10251 goto pool32axf_invalid
;
10256 MIPS_INVAL("pool32axf");
10257 generate_exception(ctx
, EXCP_RI
);
10262 /* Values for microMIPS fmt field. Variable-width, depending on which
10263 formats the instruction supports. */
10282 static void gen_pool32fxf (CPUState
*env
, DisasContext
*ctx
, int rt
, int rs
)
10284 int extension
= (ctx
->opcode
>> 6) & 0x3ff;
10285 uint32_t mips32_op
;
10287 #define FLOAT_1BIT_FMT(opc, fmt) (fmt << 8) | opc
10288 #define FLOAT_2BIT_FMT(opc, fmt) (fmt << 7) | opc
10289 #define COND_FLOAT_MOV(opc, cond) (cond << 7) | opc
10291 switch (extension
) {
10292 case FLOAT_1BIT_FMT(CFC1
, 0):
10293 mips32_op
= OPC_CFC1
;
10295 case FLOAT_1BIT_FMT(CTC1
, 0):
10296 mips32_op
= OPC_CTC1
;
10298 case FLOAT_1BIT_FMT(MFC1
, 0):
10299 mips32_op
= OPC_MFC1
;
10301 case FLOAT_1BIT_FMT(MTC1
, 0):
10302 mips32_op
= OPC_MTC1
;
10304 case FLOAT_1BIT_FMT(MFHC1
, 0):
10305 mips32_op
= OPC_MFHC1
;
10307 case FLOAT_1BIT_FMT(MTHC1
, 0):
10308 mips32_op
= OPC_MTHC1
;
10310 gen_cp1(ctx
, mips32_op
, rt
, rs
);
10313 /* Reciprocal square root */
10314 case FLOAT_1BIT_FMT(RSQRT_FMT
, FMT_SD_S
):
10315 mips32_op
= OPC_RSQRT_S
;
10317 case FLOAT_1BIT_FMT(RSQRT_FMT
, FMT_SD_D
):
10318 mips32_op
= OPC_RSQRT_D
;
10322 case FLOAT_1BIT_FMT(SQRT_FMT
, FMT_SD_S
):
10323 mips32_op
= OPC_SQRT_S
;
10325 case FLOAT_1BIT_FMT(SQRT_FMT
, FMT_SD_D
):
10326 mips32_op
= OPC_SQRT_D
;
10330 case FLOAT_1BIT_FMT(RECIP_FMT
, FMT_SD_S
):
10331 mips32_op
= OPC_RECIP_S
;
10333 case FLOAT_1BIT_FMT(RECIP_FMT
, FMT_SD_D
):
10334 mips32_op
= OPC_RECIP_D
;
10338 case FLOAT_1BIT_FMT(FLOOR_L
, FMT_SD_S
):
10339 mips32_op
= OPC_FLOOR_L_S
;
10341 case FLOAT_1BIT_FMT(FLOOR_L
, FMT_SD_D
):
10342 mips32_op
= OPC_FLOOR_L_D
;
10344 case FLOAT_1BIT_FMT(FLOOR_W
, FMT_SD_S
):
10345 mips32_op
= OPC_FLOOR_W_S
;
10347 case FLOAT_1BIT_FMT(FLOOR_W
, FMT_SD_D
):
10348 mips32_op
= OPC_FLOOR_W_D
;
10352 case FLOAT_1BIT_FMT(CEIL_L
, FMT_SD_S
):
10353 mips32_op
= OPC_CEIL_L_S
;
10355 case FLOAT_1BIT_FMT(CEIL_L
, FMT_SD_D
):
10356 mips32_op
= OPC_CEIL_L_D
;
10358 case FLOAT_1BIT_FMT(CEIL_W
, FMT_SD_S
):
10359 mips32_op
= OPC_CEIL_W_S
;
10361 case FLOAT_1BIT_FMT(CEIL_W
, FMT_SD_D
):
10362 mips32_op
= OPC_CEIL_W_D
;
10366 case FLOAT_1BIT_FMT(TRUNC_L
, FMT_SD_S
):
10367 mips32_op
= OPC_TRUNC_L_S
;
10369 case FLOAT_1BIT_FMT(TRUNC_L
, FMT_SD_D
):
10370 mips32_op
= OPC_TRUNC_L_D
;
10372 case FLOAT_1BIT_FMT(TRUNC_W
, FMT_SD_S
):
10373 mips32_op
= OPC_TRUNC_W_S
;
10375 case FLOAT_1BIT_FMT(TRUNC_W
, FMT_SD_D
):
10376 mips32_op
= OPC_TRUNC_W_D
;
10380 case FLOAT_1BIT_FMT(ROUND_L
, FMT_SD_S
):
10381 mips32_op
= OPC_ROUND_L_S
;
10383 case FLOAT_1BIT_FMT(ROUND_L
, FMT_SD_D
):
10384 mips32_op
= OPC_ROUND_L_D
;
10386 case FLOAT_1BIT_FMT(ROUND_W
, FMT_SD_S
):
10387 mips32_op
= OPC_ROUND_W_S
;
10389 case FLOAT_1BIT_FMT(ROUND_W
, FMT_SD_D
):
10390 mips32_op
= OPC_ROUND_W_D
;
10393 /* Integer to floating-point conversion */
10394 case FLOAT_1BIT_FMT(CVT_L
, FMT_SD_S
):
10395 mips32_op
= OPC_CVT_L_S
;
10397 case FLOAT_1BIT_FMT(CVT_L
, FMT_SD_D
):
10398 mips32_op
= OPC_CVT_L_D
;
10400 case FLOAT_1BIT_FMT(CVT_W
, FMT_SD_S
):
10401 mips32_op
= OPC_CVT_W_S
;
10403 case FLOAT_1BIT_FMT(CVT_W
, FMT_SD_D
):
10404 mips32_op
= OPC_CVT_W_D
;
10407 /* Paired-foo conversions */
10408 case FLOAT_1BIT_FMT(CVT_S_PL
, 0):
10409 mips32_op
= OPC_CVT_S_PL
;
10411 case FLOAT_1BIT_FMT(CVT_S_PU
, 0):
10412 mips32_op
= OPC_CVT_S_PU
;
10414 case FLOAT_1BIT_FMT(CVT_PW_PS
, 0):
10415 mips32_op
= OPC_CVT_PW_PS
;
10417 case FLOAT_1BIT_FMT(CVT_PS_PW
, 0):
10418 mips32_op
= OPC_CVT_PS_PW
;
10421 /* Floating-point moves */
10422 case FLOAT_2BIT_FMT(MOV_FMT
, FMT_SDPS_S
):
10423 mips32_op
= OPC_MOV_S
;
10425 case FLOAT_2BIT_FMT(MOV_FMT
, FMT_SDPS_D
):
10426 mips32_op
= OPC_MOV_D
;
10428 case FLOAT_2BIT_FMT(MOV_FMT
, FMT_SDPS_PS
):
10429 mips32_op
= OPC_MOV_PS
;
10432 /* Absolute value */
10433 case FLOAT_2BIT_FMT(ABS_FMT
, FMT_SDPS_S
):
10434 mips32_op
= OPC_ABS_S
;
10436 case FLOAT_2BIT_FMT(ABS_FMT
, FMT_SDPS_D
):
10437 mips32_op
= OPC_ABS_D
;
10439 case FLOAT_2BIT_FMT(ABS_FMT
, FMT_SDPS_PS
):
10440 mips32_op
= OPC_ABS_PS
;
10444 case FLOAT_2BIT_FMT(NEG_FMT
, FMT_SDPS_S
):
10445 mips32_op
= OPC_NEG_S
;
10447 case FLOAT_2BIT_FMT(NEG_FMT
, FMT_SDPS_D
):
10448 mips32_op
= OPC_NEG_D
;
10450 case FLOAT_2BIT_FMT(NEG_FMT
, FMT_SDPS_PS
):
10451 mips32_op
= OPC_NEG_PS
;
10454 /* Reciprocal square root step */
10455 case FLOAT_2BIT_FMT(RSQRT1_FMT
, FMT_SDPS_S
):
10456 mips32_op
= OPC_RSQRT1_S
;
10458 case FLOAT_2BIT_FMT(RSQRT1_FMT
, FMT_SDPS_D
):
10459 mips32_op
= OPC_RSQRT1_D
;
10461 case FLOAT_2BIT_FMT(RSQRT1_FMT
, FMT_SDPS_PS
):
10462 mips32_op
= OPC_RSQRT1_PS
;
10465 /* Reciprocal step */
10466 case FLOAT_2BIT_FMT(RECIP1_FMT
, FMT_SDPS_S
):
10467 mips32_op
= OPC_RECIP1_S
;
10469 case FLOAT_2BIT_FMT(RECIP1_FMT
, FMT_SDPS_D
):
10470 mips32_op
= OPC_RECIP1_S
;
10472 case FLOAT_2BIT_FMT(RECIP1_FMT
, FMT_SDPS_PS
):
10473 mips32_op
= OPC_RECIP1_PS
;
10476 /* Conversions from double */
10477 case FLOAT_2BIT_FMT(CVT_D
, FMT_SWL_S
):
10478 mips32_op
= OPC_CVT_D_S
;
10480 case FLOAT_2BIT_FMT(CVT_D
, FMT_SWL_W
):
10481 mips32_op
= OPC_CVT_D_W
;
10483 case FLOAT_2BIT_FMT(CVT_D
, FMT_SWL_L
):
10484 mips32_op
= OPC_CVT_D_L
;
10487 /* Conversions from single */
10488 case FLOAT_2BIT_FMT(CVT_S
, FMT_DWL_D
):
10489 mips32_op
= OPC_CVT_S_D
;
10491 case FLOAT_2BIT_FMT(CVT_S
, FMT_DWL_W
):
10492 mips32_op
= OPC_CVT_S_W
;
10494 case FLOAT_2BIT_FMT(CVT_S
, FMT_DWL_L
):
10495 mips32_op
= OPC_CVT_S_L
;
10497 gen_farith(ctx
, mips32_op
, -1, rs
, rt
, 0);
10500 /* Conditional moves on floating-point codes */
10501 case COND_FLOAT_MOV(MOVT
, 0):
10502 case COND_FLOAT_MOV(MOVT
, 1):
10503 case COND_FLOAT_MOV(MOVT
, 2):
10504 case COND_FLOAT_MOV(MOVT
, 3):
10505 case COND_FLOAT_MOV(MOVT
, 4):
10506 case COND_FLOAT_MOV(MOVT
, 5):
10507 case COND_FLOAT_MOV(MOVT
, 6):
10508 case COND_FLOAT_MOV(MOVT
, 7):
10509 gen_movci(ctx
, rt
, rs
, (ctx
->opcode
>> 13) & 0x7, 1);
10511 case COND_FLOAT_MOV(MOVF
, 0):
10512 case COND_FLOAT_MOV(MOVF
, 1):
10513 case COND_FLOAT_MOV(MOVF
, 2):
10514 case COND_FLOAT_MOV(MOVF
, 3):
10515 case COND_FLOAT_MOV(MOVF
, 4):
10516 case COND_FLOAT_MOV(MOVF
, 5):
10517 case COND_FLOAT_MOV(MOVF
, 6):
10518 case COND_FLOAT_MOV(MOVF
, 7):
10519 gen_movci(ctx
, rt
, rs
, (ctx
->opcode
>> 13) & 0x7, 0);
10522 MIPS_INVAL("pool32fxf");
10523 generate_exception(ctx
, EXCP_RI
);
10528 static void decode_micromips32_opc (CPUState
*env
, DisasContext
*ctx
,
10529 uint16_t insn_hw1
, int *is_branch
)
10533 int rt
, rs
, rd
, rr
;
10535 uint32_t op
, minor
, mips32_op
;
10536 uint32_t cond
, fmt
, cc
;
10538 insn
= lduw_code(ctx
->pc
+ 2);
10539 ctx
->opcode
= (ctx
->opcode
<< 16) | insn
;
10541 rt
= (ctx
->opcode
>> 21) & 0x1f;
10542 rs
= (ctx
->opcode
>> 16) & 0x1f;
10543 rd
= (ctx
->opcode
>> 11) & 0x1f;
10544 rr
= (ctx
->opcode
>> 6) & 0x1f;
10545 imm
= (int16_t) ctx
->opcode
;
10547 op
= (ctx
->opcode
>> 26) & 0x3f;
10550 minor
= ctx
->opcode
& 0x3f;
10553 minor
= (ctx
->opcode
>> 6) & 0xf;
10556 mips32_op
= OPC_SLL
;
10559 mips32_op
= OPC_SRA
;
10562 mips32_op
= OPC_SRL
;
10565 mips32_op
= OPC_ROTR
;
10567 gen_shift_imm(env
, ctx
, mips32_op
, rt
, rs
, rd
);
10570 goto pool32a_invalid
;
10574 minor
= (ctx
->opcode
>> 6) & 0xf;
10578 mips32_op
= OPC_ADD
;
10581 mips32_op
= OPC_ADDU
;
10584 mips32_op
= OPC_SUB
;
10587 mips32_op
= OPC_SUBU
;
10590 mips32_op
= OPC_MUL
;
10592 gen_arith(env
, ctx
, mips32_op
, rd
, rs
, rt
);
10596 mips32_op
= OPC_SLLV
;
10599 mips32_op
= OPC_SRLV
;
10602 mips32_op
= OPC_SRAV
;
10605 mips32_op
= OPC_ROTRV
;
10607 gen_shift(env
, ctx
, mips32_op
, rd
, rs
, rt
);
10609 /* Logical operations */
10611 mips32_op
= OPC_AND
;
10614 mips32_op
= OPC_OR
;
10617 mips32_op
= OPC_NOR
;
10620 mips32_op
= OPC_XOR
;
10622 gen_logic(env
, mips32_op
, rd
, rs
, rt
);
10624 /* Set less than */
10626 mips32_op
= OPC_SLT
;
10629 mips32_op
= OPC_SLTU
;
10631 gen_slt(env
, mips32_op
, rd
, rs
, rt
);
10634 goto pool32a_invalid
;
10638 minor
= (ctx
->opcode
>> 6) & 0xf;
10640 /* Conditional moves */
10642 mips32_op
= OPC_MOVN
;
10645 mips32_op
= OPC_MOVZ
;
10647 gen_cond_move(env
, mips32_op
, rd
, rs
, rt
);
10650 gen_ldxs(ctx
, rs
, rt
, rd
);
10653 goto pool32a_invalid
;
10657 gen_bitops(ctx
, OPC_INS
, rt
, rs
, rr
, rd
);
10660 gen_bitops(ctx
, OPC_EXT
, rt
, rs
, rr
, rd
);
10663 gen_pool32axf(env
, ctx
, rt
, rs
, is_branch
);
10666 generate_exception(ctx
, EXCP_BREAK
);
10670 MIPS_INVAL("pool32a");
10671 generate_exception(ctx
, EXCP_RI
);
10676 minor
= (ctx
->opcode
>> 12) & 0xf;
10679 /* Treat as no-op. */
10683 /* COP2: Not implemented. */
10684 generate_exception_err(ctx
, EXCP_CpU
, 2);
10688 #ifdef TARGET_MIPS64
10692 gen_ldst_pair(ctx
, minor
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
10696 #ifdef TARGET_MIPS64
10700 gen_ldst_multiple(ctx
, minor
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
10703 MIPS_INVAL("pool32b");
10704 generate_exception(ctx
, EXCP_RI
);
10709 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
10710 minor
= ctx
->opcode
& 0x3f;
10711 check_cp1_enabled(ctx
);
10714 mips32_op
= OPC_ALNV_PS
;
10717 mips32_op
= OPC_MADD_S
;
10720 mips32_op
= OPC_MADD_D
;
10723 mips32_op
= OPC_MADD_PS
;
10726 mips32_op
= OPC_MSUB_S
;
10729 mips32_op
= OPC_MSUB_D
;
10732 mips32_op
= OPC_MSUB_PS
;
10735 mips32_op
= OPC_NMADD_S
;
10738 mips32_op
= OPC_NMADD_D
;
10741 mips32_op
= OPC_NMADD_PS
;
10744 mips32_op
= OPC_NMSUB_S
;
10747 mips32_op
= OPC_NMSUB_D
;
10750 mips32_op
= OPC_NMSUB_PS
;
10752 gen_flt3_arith(ctx
, mips32_op
, rd
, rr
, rs
, rt
);
10754 case CABS_COND_FMT
:
10755 cond
= (ctx
->opcode
>> 6) & 0xf;
10756 cc
= (ctx
->opcode
>> 13) & 0x7;
10757 fmt
= (ctx
->opcode
>> 10) & 0x3;
10760 gen_cmpabs_s(ctx
, cond
, rt
, rs
, cc
);
10763 gen_cmpabs_d(ctx
, cond
, rt
, rs
, cc
);
10766 gen_cmpabs_ps(ctx
, cond
, rt
, rs
, cc
);
10769 goto pool32f_invalid
;
10773 cond
= (ctx
->opcode
>> 6) & 0xf;
10774 cc
= (ctx
->opcode
>> 13) & 0x7;
10775 fmt
= (ctx
->opcode
>> 10) & 0x3;
10778 gen_cmp_s(ctx
, cond
, rt
, rs
, cc
);
10781 gen_cmp_d(ctx
, cond
, rt
, rs
, cc
);
10784 gen_cmp_ps(ctx
, cond
, rt
, rs
, cc
);
10787 goto pool32f_invalid
;
10791 gen_pool32fxf(env
, ctx
, rt
, rs
);
10795 switch ((ctx
->opcode
>> 6) & 0x7) {
10797 mips32_op
= OPC_PLL_PS
;
10800 mips32_op
= OPC_PLU_PS
;
10803 mips32_op
= OPC_PUL_PS
;
10806 mips32_op
= OPC_PUU_PS
;
10809 mips32_op
= OPC_CVT_PS_S
;
10811 gen_farith(ctx
, mips32_op
, rt
, rs
, rd
, 0);
10814 goto pool32f_invalid
;
10819 switch ((ctx
->opcode
>> 6) & 0x7) {
10821 mips32_op
= OPC_LWXC1
;
10824 mips32_op
= OPC_SWXC1
;
10827 mips32_op
= OPC_LDXC1
;
10830 mips32_op
= OPC_SDXC1
;
10833 mips32_op
= OPC_LUXC1
;
10836 mips32_op
= OPC_SUXC1
;
10838 gen_flt3_ldst(ctx
, mips32_op
, rd
, rd
, rt
, rs
);
10841 goto pool32f_invalid
;
10846 fmt
= (ctx
->opcode
>> 9) & 0x3;
10847 switch ((ctx
->opcode
>> 6) & 0x7) {
10851 mips32_op
= OPC_RSQRT2_S
;
10854 mips32_op
= OPC_RSQRT2_D
;
10857 mips32_op
= OPC_RSQRT2_PS
;
10860 goto pool32f_invalid
;
10866 mips32_op
= OPC_RECIP2_S
;
10869 mips32_op
= OPC_RECIP2_D
;
10872 mips32_op
= OPC_RECIP2_PS
;
10875 goto pool32f_invalid
;
10879 mips32_op
= OPC_ADDR_PS
;
10882 mips32_op
= OPC_MULR_PS
;
10884 gen_farith(ctx
, mips32_op
, rt
, rs
, rd
, 0);
10887 goto pool32f_invalid
;
10891 /* MOV[FT].fmt and PREFX */
10892 cc
= (ctx
->opcode
>> 13) & 0x7;
10893 fmt
= (ctx
->opcode
>> 9) & 0x3;
10894 switch ((ctx
->opcode
>> 6) & 0x7) {
10898 gen_movcf_s(rs
, rt
, cc
, 0);
10901 gen_movcf_d(ctx
, rs
, rt
, cc
, 0);
10904 gen_movcf_ps(rs
, rt
, cc
, 0);
10907 goto pool32f_invalid
;
10913 gen_movcf_s(rs
, rt
, cc
, 1);
10916 gen_movcf_d(ctx
, rs
, rt
, cc
, 1);
10919 gen_movcf_ps(rs
, rt
, cc
, 1);
10922 goto pool32f_invalid
;
10928 goto pool32f_invalid
;
10931 #define FINSN_3ARG_SDPS(prfx) \
10932 switch ((ctx->opcode >> 8) & 0x3) { \
10934 mips32_op = OPC_##prfx##_S; \
10937 mips32_op = OPC_##prfx##_D; \
10939 case FMT_SDPS_PS: \
10940 mips32_op = OPC_##prfx##_PS; \
10943 goto pool32f_invalid; \
10946 /* regular FP ops */
10947 switch ((ctx
->opcode
>> 6) & 0x3) {
10949 FINSN_3ARG_SDPS(ADD
);
10952 FINSN_3ARG_SDPS(SUB
);
10955 FINSN_3ARG_SDPS(MUL
);
10958 fmt
= (ctx
->opcode
>> 8) & 0x3;
10960 mips32_op
= OPC_DIV_D
;
10961 } else if (fmt
== 0) {
10962 mips32_op
= OPC_DIV_S
;
10964 goto pool32f_invalid
;
10968 goto pool32f_invalid
;
10973 switch ((ctx
->opcode
>> 6) & 0x3) {
10975 FINSN_3ARG_SDPS(MOVN
);
10978 FINSN_3ARG_SDPS(MOVZ
);
10981 goto pool32f_invalid
;
10985 gen_farith(ctx
, mips32_op
, rt
, rs
, rd
, 0);
10989 MIPS_INVAL("pool32f");
10990 generate_exception(ctx
, EXCP_RI
);
10994 generate_exception_err(ctx
, EXCP_CpU
, 1);
10998 minor
= (ctx
->opcode
>> 21) & 0x1f;
11001 mips32_op
= OPC_BLTZ
;
11004 mips32_op
= OPC_BLTZAL
;
11007 mips32_op
= OPC_BLTZALS
;
11010 mips32_op
= OPC_BGEZ
;
11013 mips32_op
= OPC_BGEZAL
;
11016 mips32_op
= OPC_BGEZALS
;
11019 mips32_op
= OPC_BLEZ
;
11022 mips32_op
= OPC_BGTZ
;
11024 gen_compute_branch(ctx
, mips32_op
, 4, rs
, -1, imm
<< 1);
11030 mips32_op
= OPC_TLTI
;
11033 mips32_op
= OPC_TGEI
;
11036 mips32_op
= OPC_TLTIU
;
11039 mips32_op
= OPC_TGEIU
;
11042 mips32_op
= OPC_TNEI
;
11045 mips32_op
= OPC_TEQI
;
11047 gen_trap(ctx
, mips32_op
, rs
, -1, imm
);
11052 gen_compute_branch(ctx
, minor
== BNEZC
? OPC_BNE
: OPC_BEQ
,
11053 4, rs
, 0, imm
<< 1);
11054 /* Compact branches don't have a delay slot, so just let
11055 the normal delay slot handling take us to the branch
11059 gen_logic_imm(env
, OPC_LUI
, rs
, -1, imm
);
11065 /* COP2: Not implemented. */
11066 generate_exception_err(ctx
, EXCP_CpU
, 2);
11069 mips32_op
= (ctx
->opcode
& (1 << 16)) ? OPC_BC1FANY2
: OPC_BC1F
;
11072 mips32_op
= (ctx
->opcode
& (1 << 16)) ? OPC_BC1TANY2
: OPC_BC1T
;
11075 mips32_op
= OPC_BC1FANY4
;
11078 mips32_op
= OPC_BC1TANY4
;
11081 check_insn(env
, ctx
, ASE_MIPS3D
);
11084 gen_compute_branch1(env
, ctx
, mips32_op
,
11085 (ctx
->opcode
>> 18) & 0x7, imm
<< 1);
11090 /* MIPS DSP: not implemented */
11093 MIPS_INVAL("pool32i");
11094 generate_exception(ctx
, EXCP_RI
);
11099 minor
= (ctx
->opcode
>> 12) & 0xf;
11102 mips32_op
= OPC_LWL
;
11105 mips32_op
= OPC_SWL
;
11108 mips32_op
= OPC_LWR
;
11111 mips32_op
= OPC_SWR
;
11113 #if defined(TARGET_MIPS64)
11115 mips32_op
= OPC_LDL
;
11118 mips32_op
= OPC_SDL
;
11121 mips32_op
= OPC_LDR
;
11124 mips32_op
= OPC_SDR
;
11127 mips32_op
= OPC_LWU
;
11130 mips32_op
= OPC_LLD
;
11134 mips32_op
= OPC_LL
;
11137 gen_ld(env
, ctx
, mips32_op
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
11140 gen_st(ctx
, mips32_op
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
11143 gen_st_cond(ctx
, OPC_SC
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
11145 #if defined(TARGET_MIPS64)
11147 gen_st_cond(ctx
, OPC_SCD
, rt
, rs
, SIMM(ctx
->opcode
, 0, 12));
11151 /* Treat as no-op */
11154 MIPS_INVAL("pool32c");
11155 generate_exception(ctx
, EXCP_RI
);
11160 mips32_op
= OPC_ADDI
;
11163 mips32_op
= OPC_ADDIU
;
11165 gen_arith_imm(env
, ctx
, mips32_op
, rt
, rs
, imm
);
11168 /* Logical operations */
11170 mips32_op
= OPC_ORI
;
11173 mips32_op
= OPC_XORI
;
11176 mips32_op
= OPC_ANDI
;
11178 gen_logic_imm(env
, mips32_op
, rt
, rs
, imm
);
11181 /* Set less than immediate */
11183 mips32_op
= OPC_SLTI
;
11186 mips32_op
= OPC_SLTIU
;
11188 gen_slt_imm(env
, mips32_op
, rt
, rs
, imm
);
11191 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
11192 gen_compute_branch(ctx
, OPC_JALX
, 4, rt
, rs
, offset
);
11196 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 1;
11197 gen_compute_branch(ctx
, OPC_JALS
, 4, rt
, rs
, offset
);
11201 gen_compute_branch(ctx
, OPC_BEQ
, 4, rt
, rs
, imm
<< 1);
11205 gen_compute_branch(ctx
, OPC_BNE
, 4, rt
, rs
, imm
<< 1);
11209 gen_compute_branch(ctx
, OPC_J
, 4, rt
, rs
,
11210 (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 1);
11214 gen_compute_branch(ctx
, OPC_JAL
, 4, rt
, rs
,
11215 (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 1);
11218 /* Floating point (COP1) */
11220 mips32_op
= OPC_LWC1
;
11223 mips32_op
= OPC_LDC1
;
11226 mips32_op
= OPC_SWC1
;
11229 mips32_op
= OPC_SDC1
;
11231 gen_cop1_ldst(env
, ctx
, mips32_op
, rt
, rs
, imm
);
11235 int reg
= mmreg(ZIMM(ctx
->opcode
, 23, 3));
11236 int offset
= SIMM(ctx
->opcode
, 0, 23) << 2;
11238 gen_addiupc(ctx
, reg
, offset
, 0, 0);
11241 /* Loads and stores */
11243 mips32_op
= OPC_LB
;
11246 mips32_op
= OPC_LBU
;
11249 mips32_op
= OPC_LH
;
11252 mips32_op
= OPC_LHU
;
11255 mips32_op
= OPC_LW
;
11257 #ifdef TARGET_MIPS64
11259 mips32_op
= OPC_LD
;
11262 mips32_op
= OPC_SD
;
11266 mips32_op
= OPC_SB
;
11269 mips32_op
= OPC_SH
;
11272 mips32_op
= OPC_SW
;
11275 gen_ld(env
, ctx
, mips32_op
, rt
, rs
, imm
);
11278 gen_st(ctx
, mips32_op
, rt
, rs
, imm
);
11281 generate_exception(ctx
, EXCP_RI
);
11286 static int decode_micromips_opc (CPUState
*env
, DisasContext
*ctx
, int *is_branch
)
11290 /* make sure instructions are on a halfword boundary */
11291 if (ctx
->pc
& 0x1) {
11292 env
->CP0_BadVAddr
= ctx
->pc
;
11293 generate_exception(ctx
, EXCP_AdEL
);
11294 ctx
->bstate
= BS_STOP
;
11298 op
= (ctx
->opcode
>> 10) & 0x3f;
11299 /* Enforce properly-sized instructions in a delay slot */
11300 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
11301 int bits
= ctx
->hflags
& MIPS_HFLAG_BMASK_EXT
;
11335 case POOL48A
: /* ??? */
11340 if (bits
& MIPS_HFLAG_BDS16
) {
11341 generate_exception(ctx
, EXCP_RI
);
11342 /* Just stop translation; the user is confused. */
11343 ctx
->bstate
= BS_STOP
;
11368 if (bits
& MIPS_HFLAG_BDS32
) {
11369 generate_exception(ctx
, EXCP_RI
);
11370 /* Just stop translation; the user is confused. */
11371 ctx
->bstate
= BS_STOP
;
11382 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
11383 int rs1
= mmreg(uMIPS_RS1(ctx
->opcode
));
11384 int rs2
= mmreg(uMIPS_RS2(ctx
->opcode
));
11387 switch (ctx
->opcode
& 0x1) {
11396 gen_arith(env
, ctx
, opc
, rd
, rs1
, rs2
);
11401 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
11402 int rs
= mmreg(uMIPS_RS(ctx
->opcode
));
11403 int amount
= (ctx
->opcode
>> 1) & 0x7;
11405 amount
= amount
== 0 ? 8 : amount
;
11407 switch (ctx
->opcode
& 0x1) {
11416 gen_shift_imm(env
, ctx
, opc
, rd
, rs
, amount
);
11420 gen_pool16c_insn(env
, ctx
, is_branch
);
11424 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
11425 int rb
= 28; /* GP */
11426 int16_t offset
= SIMM(ctx
->opcode
, 0, 7) << 2;
11428 gen_ld(env
, ctx
, OPC_LW
, rd
, rb
, offset
);
11432 if (ctx
->opcode
& 1) {
11433 generate_exception(ctx
, EXCP_RI
);
11436 int enc_dest
= uMIPS_RD(ctx
->opcode
);
11437 int enc_rt
= uMIPS_RS2(ctx
->opcode
);
11438 int enc_rs
= uMIPS_RS1(ctx
->opcode
);
11439 int rd
, rs
, re
, rt
;
11440 static const int rd_enc
[] = { 5, 5, 6, 4, 4, 4, 4, 4 };
11441 static const int re_enc
[] = { 6, 7, 7, 21, 22, 5, 6, 7 };
11442 static const int rs_rt_enc
[] = { 0, 17, 2, 3, 16, 18, 19, 20 };
11444 rd
= rd_enc
[enc_dest
];
11445 re
= re_enc
[enc_dest
];
11446 rs
= rs_rt_enc
[enc_rs
];
11447 rt
= rs_rt_enc
[enc_rt
];
11449 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rd
, rs
, 0);
11450 gen_arith_imm(env
, ctx
, OPC_ADDIU
, re
, rt
, 0);
11455 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
11456 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
11457 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4);
11458 offset
= (offset
== 0xf ? -1 : offset
);
11460 gen_ld(env
, ctx
, OPC_LBU
, rd
, rb
, offset
);
11465 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
11466 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
11467 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 1;
11469 gen_ld(env
, ctx
, OPC_LHU
, rd
, rb
, offset
);
11474 int rd
= (ctx
->opcode
>> 5) & 0x1f;
11475 int rb
= 29; /* SP */
11476 int16_t offset
= ZIMM(ctx
->opcode
, 0, 5) << 2;
11478 gen_ld(env
, ctx
, OPC_LW
, rd
, rb
, offset
);
11483 int rd
= mmreg(uMIPS_RD(ctx
->opcode
));
11484 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
11485 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 2;
11487 gen_ld(env
, ctx
, OPC_LW
, rd
, rb
, offset
);
11492 int rd
= mmreg2(uMIPS_RD(ctx
->opcode
));
11493 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
11494 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4);
11496 gen_st(ctx
, OPC_SB
, rd
, rb
, offset
);
11501 int rd
= mmreg2(uMIPS_RD(ctx
->opcode
));
11502 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
11503 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 1;
11505 gen_st(ctx
, OPC_SH
, rd
, rb
, offset
);
11510 int rd
= (ctx
->opcode
>> 5) & 0x1f;
11511 int rb
= 29; /* SP */
11512 int16_t offset
= ZIMM(ctx
->opcode
, 0, 5) << 2;
11514 gen_st(ctx
, OPC_SW
, rd
, rb
, offset
);
11519 int rd
= mmreg2(uMIPS_RD(ctx
->opcode
));
11520 int rb
= mmreg(uMIPS_RS(ctx
->opcode
));
11521 int16_t offset
= ZIMM(ctx
->opcode
, 0, 4) << 2;
11523 gen_st(ctx
, OPC_SW
, rd
, rb
, offset
);
11528 int rd
= uMIPS_RD5(ctx
->opcode
);
11529 int rs
= uMIPS_RS5(ctx
->opcode
);
11531 gen_arith_imm(env
, ctx
, OPC_ADDIU
, rd
, rs
, 0);
11535 gen_andi16(env
, ctx
);
11538 switch (ctx
->opcode
& 0x1) {
11540 gen_addius5(env
, ctx
);
11543 gen_addiusp(env
, ctx
);
11548 switch (ctx
->opcode
& 0x1) {
11550 gen_addiur2(env
, ctx
);
11553 gen_addiur1sp(env
, ctx
);
11558 gen_compute_branch(ctx
, OPC_BEQ
, 2, 0, 0,
11559 SIMM(ctx
->opcode
, 0, 10) << 1);
11564 gen_compute_branch(ctx
, op
== BNEZ16
? OPC_BNE
: OPC_BEQ
, 2,
11565 mmreg(uMIPS_RD(ctx
->opcode
)),
11566 0, SIMM(ctx
->opcode
, 0, 7) << 1);
11571 int reg
= mmreg(uMIPS_RD(ctx
->opcode
));
11572 int imm
= ZIMM(ctx
->opcode
, 0, 7);
11574 imm
= (imm
== 0x7f ? -1 : imm
);
11575 tcg_gen_movi_tl(cpu_gpr
[reg
], imm
);
11585 generate_exception(ctx
, EXCP_RI
);
11588 decode_micromips32_opc (env
, ctx
, op
, is_branch
);
11595 /* SmartMIPS extension to MIPS32 */
11597 #if defined(TARGET_MIPS64)
11599 /* MDMX extension to MIPS64 */
11603 static void decode_opc (CPUState
*env
, DisasContext
*ctx
, int *is_branch
)
11606 int rs
, rt
, rd
, sa
;
11607 uint32_t op
, op1
, op2
;
11610 /* make sure instructions are on a word boundary */
11611 if (ctx
->pc
& 0x3) {
11612 env
->CP0_BadVAddr
= ctx
->pc
;
11613 generate_exception(ctx
, EXCP_AdEL
);
11617 /* Handle blikely not taken case */
11618 if ((ctx
->hflags
& MIPS_HFLAG_BMASK_BASE
) == MIPS_HFLAG_BL
) {
11619 int l1
= gen_new_label();
11621 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
11622 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
11623 tcg_gen_movi_i32(hflags
, ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
11624 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
11628 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)))
11629 tcg_gen_debug_insn_start(ctx
->pc
);
11631 op
= MASK_OP_MAJOR(ctx
->opcode
);
11632 rs
= (ctx
->opcode
>> 21) & 0x1f;
11633 rt
= (ctx
->opcode
>> 16) & 0x1f;
11634 rd
= (ctx
->opcode
>> 11) & 0x1f;
11635 sa
= (ctx
->opcode
>> 6) & 0x1f;
11636 imm
= (int16_t)ctx
->opcode
;
11639 op1
= MASK_SPECIAL(ctx
->opcode
);
11641 case OPC_SLL
: /* Shift with immediate */
11643 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
11646 switch ((ctx
->opcode
>> 21) & 0x1f) {
11648 /* rotr is decoded as srl on non-R2 CPUs */
11649 if (env
->insn_flags
& ISA_MIPS32R2
) {
11654 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
11657 generate_exception(ctx
, EXCP_RI
);
11661 case OPC_MOVN
: /* Conditional move */
11663 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
|
11664 INSN_LOONGSON2E
| INSN_LOONGSON2F
);
11665 gen_cond_move(env
, op1
, rd
, rs
, rt
);
11667 case OPC_ADD
... OPC_SUBU
:
11668 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
11670 case OPC_SLLV
: /* Shifts */
11672 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
11675 switch ((ctx
->opcode
>> 6) & 0x1f) {
11677 /* rotrv is decoded as srlv on non-R2 CPUs */
11678 if (env
->insn_flags
& ISA_MIPS32R2
) {
11683 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
11686 generate_exception(ctx
, EXCP_RI
);
11690 case OPC_SLT
: /* Set on less than */
11692 gen_slt(env
, op1
, rd
, rs
, rt
);
11694 case OPC_AND
: /* Logic*/
11698 gen_logic(env
, op1
, rd
, rs
, rt
);
11700 case OPC_MULT
... OPC_DIVU
:
11702 check_insn(env
, ctx
, INSN_VR54XX
);
11703 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
11704 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
11706 gen_muldiv(ctx
, op1
, rs
, rt
);
11708 case OPC_JR
... OPC_JALR
:
11709 gen_compute_branch(ctx
, op1
, 4, rs
, rd
, sa
);
11712 case OPC_TGE
... OPC_TEQ
: /* Traps */
11714 gen_trap(ctx
, op1
, rs
, rt
, -1);
11716 case OPC_MFHI
: /* Move from HI/LO */
11718 gen_HILO(ctx
, op1
, rd
);
11721 case OPC_MTLO
: /* Move to HI/LO */
11722 gen_HILO(ctx
, op1
, rs
);
11724 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
11725 #ifdef MIPS_STRICT_STANDARD
11726 MIPS_INVAL("PMON / selsl");
11727 generate_exception(ctx
, EXCP_RI
);
11729 gen_helper_0i(pmon
, sa
);
11733 generate_exception(ctx
, EXCP_SYSCALL
);
11734 ctx
->bstate
= BS_STOP
;
11737 generate_exception(ctx
, EXCP_BREAK
);
11740 #ifdef MIPS_STRICT_STANDARD
11741 MIPS_INVAL("SPIM");
11742 generate_exception(ctx
, EXCP_RI
);
11744 /* Implemented as RI exception for now. */
11745 MIPS_INVAL("spim (unofficial)");
11746 generate_exception(ctx
, EXCP_RI
);
11750 /* Treat as NOP. */
11754 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
11755 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
11756 check_cp1_enabled(ctx
);
11757 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
11758 (ctx
->opcode
>> 16) & 1);
11760 generate_exception_err(ctx
, EXCP_CpU
, 1);
11764 #if defined(TARGET_MIPS64)
11765 /* MIPS64 specific opcodes */
11770 check_insn(env
, ctx
, ISA_MIPS3
);
11771 check_mips_64(ctx
);
11772 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
11775 switch ((ctx
->opcode
>> 21) & 0x1f) {
11777 /* drotr is decoded as dsrl on non-R2 CPUs */
11778 if (env
->insn_flags
& ISA_MIPS32R2
) {
11783 check_insn(env
, ctx
, ISA_MIPS3
);
11784 check_mips_64(ctx
);
11785 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
11788 generate_exception(ctx
, EXCP_RI
);
11793 switch ((ctx
->opcode
>> 21) & 0x1f) {
11795 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
11796 if (env
->insn_flags
& ISA_MIPS32R2
) {
11801 check_insn(env
, ctx
, ISA_MIPS3
);
11802 check_mips_64(ctx
);
11803 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
11806 generate_exception(ctx
, EXCP_RI
);
11810 case OPC_DADD
... OPC_DSUBU
:
11811 check_insn(env
, ctx
, ISA_MIPS3
);
11812 check_mips_64(ctx
);
11813 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
11817 check_insn(env
, ctx
, ISA_MIPS3
);
11818 check_mips_64(ctx
);
11819 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
11822 switch ((ctx
->opcode
>> 6) & 0x1f) {
11824 /* drotrv is decoded as dsrlv on non-R2 CPUs */
11825 if (env
->insn_flags
& ISA_MIPS32R2
) {
11830 check_insn(env
, ctx
, ISA_MIPS3
);
11831 check_mips_64(ctx
);
11832 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
11835 generate_exception(ctx
, EXCP_RI
);
11839 case OPC_DMULT
... OPC_DDIVU
:
11840 check_insn(env
, ctx
, ISA_MIPS3
);
11841 check_mips_64(ctx
);
11842 gen_muldiv(ctx
, op1
, rs
, rt
);
11845 default: /* Invalid */
11846 MIPS_INVAL("special");
11847 generate_exception(ctx
, EXCP_RI
);
11852 op1
= MASK_SPECIAL2(ctx
->opcode
);
11854 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
11855 case OPC_MSUB
... OPC_MSUBU
:
11856 check_insn(env
, ctx
, ISA_MIPS32
);
11857 gen_muldiv(ctx
, op1
, rs
, rt
);
11860 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
11864 check_insn(env
, ctx
, ISA_MIPS32
);
11865 gen_cl(ctx
, op1
, rd
, rs
);
11868 /* XXX: not clear which exception should be raised
11869 * when in debug mode...
11871 check_insn(env
, ctx
, ISA_MIPS32
);
11872 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
11873 generate_exception(ctx
, EXCP_DBp
);
11875 generate_exception(ctx
, EXCP_DBp
);
11877 /* Treat as NOP. */
11880 case OPC_DIVU_G_2F
:
11881 case OPC_MULT_G_2F
:
11882 case OPC_MULTU_G_2F
:
11884 case OPC_MODU_G_2F
:
11885 check_insn(env
, ctx
, INSN_LOONGSON2F
);
11886 gen_loongson_integer(ctx
, op1
, rd
, rs
, rt
);
11888 #if defined(TARGET_MIPS64)
11891 check_insn(env
, ctx
, ISA_MIPS64
);
11892 check_mips_64(ctx
);
11893 gen_cl(ctx
, op1
, rd
, rs
);
11895 case OPC_DMULT_G_2F
:
11896 case OPC_DMULTU_G_2F
:
11897 case OPC_DDIV_G_2F
:
11898 case OPC_DDIVU_G_2F
:
11899 case OPC_DMOD_G_2F
:
11900 case OPC_DMODU_G_2F
:
11901 check_insn(env
, ctx
, INSN_LOONGSON2F
);
11902 gen_loongson_integer(ctx
, op1
, rd
, rs
, rt
);
11905 default: /* Invalid */
11906 MIPS_INVAL("special2");
11907 generate_exception(ctx
, EXCP_RI
);
11912 op1
= MASK_SPECIAL3(ctx
->opcode
);
11916 check_insn(env
, ctx
, ISA_MIPS32R2
);
11917 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
11920 check_insn(env
, ctx
, ISA_MIPS32R2
);
11921 op2
= MASK_BSHFL(ctx
->opcode
);
11922 gen_bshfl(ctx
, op2
, rt
, rd
);
11925 gen_rdhwr(env
, ctx
, rt
, rd
);
11928 check_insn(env
, ctx
, ASE_MT
);
11930 TCGv t0
= tcg_temp_new();
11931 TCGv t1
= tcg_temp_new();
11933 gen_load_gpr(t0
, rt
);
11934 gen_load_gpr(t1
, rs
);
11935 gen_helper_fork(t0
, t1
);
11941 check_insn(env
, ctx
, ASE_MT
);
11943 TCGv t0
= tcg_temp_new();
11945 save_cpu_state(ctx
, 1);
11946 gen_load_gpr(t0
, rs
);
11947 gen_helper_yield(t0
, t0
);
11948 gen_store_gpr(t0
, rd
);
11952 case OPC_DIV_G_2E
... OPC_DIVU_G_2E
:
11953 case OPC_MULT_G_2E
... OPC_MULTU_G_2E
:
11954 case OPC_MOD_G_2E
... OPC_MODU_G_2E
:
11955 check_insn(env
, ctx
, INSN_LOONGSON2E
);
11956 gen_loongson_integer(ctx
, op1
, rd
, rs
, rt
);
11958 #if defined(TARGET_MIPS64)
11959 case OPC_DEXTM
... OPC_DEXT
:
11960 case OPC_DINSM
... OPC_DINS
:
11961 check_insn(env
, ctx
, ISA_MIPS64R2
);
11962 check_mips_64(ctx
);
11963 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
11966 check_insn(env
, ctx
, ISA_MIPS64R2
);
11967 check_mips_64(ctx
);
11968 op2
= MASK_DBSHFL(ctx
->opcode
);
11969 gen_bshfl(ctx
, op2
, rt
, rd
);
11971 case OPC_DDIV_G_2E
... OPC_DDIVU_G_2E
:
11972 case OPC_DMULT_G_2E
... OPC_DMULTU_G_2E
:
11973 case OPC_DMOD_G_2E
... OPC_DMODU_G_2E
:
11974 check_insn(env
, ctx
, INSN_LOONGSON2E
);
11975 gen_loongson_integer(ctx
, op1
, rd
, rs
, rt
);
11978 default: /* Invalid */
11979 MIPS_INVAL("special3");
11980 generate_exception(ctx
, EXCP_RI
);
11985 op1
= MASK_REGIMM(ctx
->opcode
);
11987 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
11988 case OPC_BLTZAL
... OPC_BGEZALL
:
11989 gen_compute_branch(ctx
, op1
, 4, rs
, -1, imm
<< 2);
11992 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
11994 gen_trap(ctx
, op1
, rs
, -1, imm
);
11997 check_insn(env
, ctx
, ISA_MIPS32R2
);
11998 /* Treat as NOP. */
12000 default: /* Invalid */
12001 MIPS_INVAL("regimm");
12002 generate_exception(ctx
, EXCP_RI
);
12007 check_cp0_enabled(ctx
);
12008 op1
= MASK_CP0(ctx
->opcode
);
12014 #if defined(TARGET_MIPS64)
12018 #ifndef CONFIG_USER_ONLY
12019 gen_cp0(env
, ctx
, op1
, rt
, rd
);
12020 #endif /* !CONFIG_USER_ONLY */
12022 case OPC_C0_FIRST
... OPC_C0_LAST
:
12023 #ifndef CONFIG_USER_ONLY
12024 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
12025 #endif /* !CONFIG_USER_ONLY */
12028 #ifndef CONFIG_USER_ONLY
12030 TCGv t0
= tcg_temp_new();
12032 op2
= MASK_MFMC0(ctx
->opcode
);
12035 check_insn(env
, ctx
, ASE_MT
);
12036 gen_helper_dmt(t0
);
12037 gen_store_gpr(t0
, rt
);
12040 check_insn(env
, ctx
, ASE_MT
);
12041 gen_helper_emt(t0
);
12042 gen_store_gpr(t0
, rt
);
12045 check_insn(env
, ctx
, ASE_MT
);
12046 gen_helper_dvpe(t0
);
12047 gen_store_gpr(t0
, rt
);
12050 check_insn(env
, ctx
, ASE_MT
);
12051 gen_helper_evpe(t0
);
12052 gen_store_gpr(t0
, rt
);
12055 check_insn(env
, ctx
, ISA_MIPS32R2
);
12056 save_cpu_state(ctx
, 1);
12058 gen_store_gpr(t0
, rt
);
12059 /* Stop translation as we may have switched the execution mode */
12060 ctx
->bstate
= BS_STOP
;
12063 check_insn(env
, ctx
, ISA_MIPS32R2
);
12064 save_cpu_state(ctx
, 1);
12066 gen_store_gpr(t0
, rt
);
12067 /* Stop translation as we may have switched the execution mode */
12068 ctx
->bstate
= BS_STOP
;
12070 default: /* Invalid */
12071 MIPS_INVAL("mfmc0");
12072 generate_exception(ctx
, EXCP_RI
);
12077 #endif /* !CONFIG_USER_ONLY */
12080 check_insn(env
, ctx
, ISA_MIPS32R2
);
12081 gen_load_srsgpr(rt
, rd
);
12084 check_insn(env
, ctx
, ISA_MIPS32R2
);
12085 gen_store_srsgpr(rt
, rd
);
12089 generate_exception(ctx
, EXCP_RI
);
12093 case OPC_ADDI
: /* Arithmetic with immediate opcode */
12095 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
12097 case OPC_SLTI
: /* Set on less than with immediate opcode */
12099 gen_slt_imm(env
, op
, rt
, rs
, imm
);
12101 case OPC_ANDI
: /* Arithmetic with immediate opcode */
12105 gen_logic_imm(env
, op
, rt
, rs
, imm
);
12107 case OPC_J
... OPC_JAL
: /* Jump */
12108 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
12109 gen_compute_branch(ctx
, op
, 4, rs
, rt
, offset
);
12112 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
12113 case OPC_BEQL
... OPC_BGTZL
:
12114 gen_compute_branch(ctx
, op
, 4, rs
, rt
, imm
<< 2);
12117 case OPC_LB
... OPC_LWR
: /* Load and stores */
12119 gen_ld(env
, ctx
, op
, rt
, rs
, imm
);
12121 case OPC_SB
... OPC_SW
:
12123 gen_st(ctx
, op
, rt
, rs
, imm
);
12126 gen_st_cond(ctx
, op
, rt
, rs
, imm
);
12129 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
12130 /* Treat as NOP. */
12133 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
12134 /* Treat as NOP. */
12137 /* Floating point (COP1). */
12142 gen_cop1_ldst(env
, ctx
, op
, rt
, rs
, imm
);
12146 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
12147 check_cp1_enabled(ctx
);
12148 op1
= MASK_CP1(ctx
->opcode
);
12152 check_insn(env
, ctx
, ISA_MIPS32R2
);
12157 gen_cp1(ctx
, op1
, rt
, rd
);
12159 #if defined(TARGET_MIPS64)
12162 check_insn(env
, ctx
, ISA_MIPS3
);
12163 gen_cp1(ctx
, op1
, rt
, rd
);
12169 check_insn(env
, ctx
, ASE_MIPS3D
);
12172 gen_compute_branch1(env
, ctx
, MASK_BC1(ctx
->opcode
),
12173 (rt
>> 2) & 0x7, imm
<< 2);
12181 gen_farith(ctx
, ctx
->opcode
& FOP(0x3f, 0x1f), rt
, rd
, sa
,
12186 generate_exception (ctx
, EXCP_RI
);
12190 generate_exception_err(ctx
, EXCP_CpU
, 1);
12200 /* COP2: Not implemented. */
12201 generate_exception_err(ctx
, EXCP_CpU
, 2);
12205 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
12206 check_cp1_enabled(ctx
);
12207 op1
= MASK_CP3(ctx
->opcode
);
12215 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
12218 /* Treat as NOP. */
12233 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
12237 generate_exception (ctx
, EXCP_RI
);
12241 generate_exception_err(ctx
, EXCP_CpU
, 1);
12245 #if defined(TARGET_MIPS64)
12246 /* MIPS64 opcodes */
12248 case OPC_LDL
... OPC_LDR
:
12251 check_insn(env
, ctx
, ISA_MIPS3
);
12252 check_mips_64(ctx
);
12253 gen_ld(env
, ctx
, op
, rt
, rs
, imm
);
12255 case OPC_SDL
... OPC_SDR
:
12257 check_insn(env
, ctx
, ISA_MIPS3
);
12258 check_mips_64(ctx
);
12259 gen_st(ctx
, op
, rt
, rs
, imm
);
12262 check_insn(env
, ctx
, ISA_MIPS3
);
12263 check_mips_64(ctx
);
12264 gen_st_cond(ctx
, op
, rt
, rs
, imm
);
12268 check_insn(env
, ctx
, ISA_MIPS3
);
12269 check_mips_64(ctx
);
12270 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
12274 check_insn(env
, ctx
, ASE_MIPS16
| ASE_MICROMIPS
);
12275 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
12276 gen_compute_branch(ctx
, op
, 4, rs
, rt
, offset
);
12280 check_insn(env
, ctx
, ASE_MDMX
);
12281 /* MDMX: Not implemented. */
12282 default: /* Invalid */
12283 MIPS_INVAL("major opcode");
12284 generate_exception(ctx
, EXCP_RI
);
12290 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
12294 target_ulong pc_start
;
12295 uint16_t *gen_opc_end
;
12304 qemu_log("search pc %d\n", search_pc
);
12307 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
12310 ctx
.singlestep_enabled
= env
->singlestep_enabled
;
12312 ctx
.bstate
= BS_NONE
;
12313 /* Restore delay slot state from the tb context. */
12314 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
12315 restore_cpu_state(env
, &ctx
);
12316 #ifdef CONFIG_USER_ONLY
12317 ctx
.mem_idx
= MIPS_HFLAG_UM
;
12319 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
12322 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
12323 if (max_insns
== 0)
12324 max_insns
= CF_COUNT_MASK
;
12325 LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb
, ctx
.mem_idx
, ctx
.hflags
);
12326 gen_icount_start();
12327 while (ctx
.bstate
== BS_NONE
) {
12328 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
12329 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
12330 if (bp
->pc
== ctx
.pc
) {
12331 save_cpu_state(&ctx
, 1);
12332 ctx
.bstate
= BS_BRANCH
;
12333 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
12334 /* Include the breakpoint location or the tb won't
12335 * be flushed when it must be. */
12337 goto done_generating
;
12343 j
= gen_opc_ptr
- gen_opc_buf
;
12347 gen_opc_instr_start
[lj
++] = 0;
12349 gen_opc_pc
[lj
] = ctx
.pc
;
12350 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
12351 gen_opc_instr_start
[lj
] = 1;
12352 gen_opc_icount
[lj
] = num_insns
;
12354 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
12358 if (!(ctx
.hflags
& MIPS_HFLAG_M16
)) {
12359 ctx
.opcode
= ldl_code(ctx
.pc
);
12361 decode_opc(env
, &ctx
, &is_branch
);
12362 } else if (env
->insn_flags
& ASE_MICROMIPS
) {
12363 ctx
.opcode
= lduw_code(ctx
.pc
);
12364 insn_bytes
= decode_micromips_opc(env
, &ctx
, &is_branch
);
12365 } else if (env
->insn_flags
& ASE_MIPS16
) {
12366 ctx
.opcode
= lduw_code(ctx
.pc
);
12367 insn_bytes
= decode_mips16_opc(env
, &ctx
, &is_branch
);
12369 generate_exception(&ctx
, EXCP_RI
);
12370 ctx
.bstate
= BS_STOP
;
12374 handle_delay_slot(env
, &ctx
, insn_bytes
);
12376 ctx
.pc
+= insn_bytes
;
12380 /* Execute a branch and its delay slot as a single instruction.
12381 This is what GDB expects and is consistent with what the
12382 hardware does (e.g. if a delay slot instruction faults, the
12383 reported PC is the PC of the branch). */
12384 if (env
->singlestep_enabled
&& (ctx
.hflags
& MIPS_HFLAG_BMASK
) == 0)
12387 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
12390 if (gen_opc_ptr
>= gen_opc_end
)
12393 if (num_insns
>= max_insns
)
12399 if (tb
->cflags
& CF_LAST_IO
)
12401 if (env
->singlestep_enabled
&& ctx
.bstate
!= BS_BRANCH
) {
12402 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
12403 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
12405 switch (ctx
.bstate
) {
12407 gen_goto_tb(&ctx
, 0, ctx
.pc
);
12410 save_cpu_state(&ctx
, 0);
12411 gen_goto_tb(&ctx
, 0, ctx
.pc
);
12414 tcg_gen_exit_tb(0);
12422 gen_icount_end(tb
, num_insns
);
12423 *gen_opc_ptr
= INDEX_op_end
;
12425 j
= gen_opc_ptr
- gen_opc_buf
;
12428 gen_opc_instr_start
[lj
++] = 0;
12430 tb
->size
= ctx
.pc
- pc_start
;
12431 tb
->icount
= num_insns
;
12435 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
12436 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
12437 log_target_disas(pc_start
, ctx
.pc
- pc_start
, 0);
12443 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
12445 gen_intermediate_code_internal(env
, tb
, 0);
12448 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
12450 gen_intermediate_code_internal(env
, tb
, 1);
12453 static void fpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function fpu_fprintf
,
12457 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
12459 #define printfpr(fp) \
12462 fpu_fprintf(f, "w:%08x d:%016" PRIx64 \
12463 " fd:%13g fs:%13g psu: %13g\n", \
12464 (fp)->w[FP_ENDIAN_IDX], (fp)->d, \
12465 (double)(fp)->fd, \
12466 (double)(fp)->fs[FP_ENDIAN_IDX], \
12467 (double)(fp)->fs[!FP_ENDIAN_IDX]); \
12470 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
12471 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
12472 fpu_fprintf(f, "w:%08x d:%016" PRIx64 \
12473 " fd:%13g fs:%13g psu:%13g\n", \
12474 tmp.w[FP_ENDIAN_IDX], tmp.d, \
12476 (double)tmp.fs[FP_ENDIAN_IDX], \
12477 (double)tmp.fs[!FP_ENDIAN_IDX]); \
12482 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
12483 env
->active_fpu
.fcr0
, env
->active_fpu
.fcr31
, is_fpu64
,
12484 get_float_exception_flags(&env
->active_fpu
.fp_status
));
12485 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
12486 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
12487 printfpr(&env
->active_fpu
.fpr
[i
]);
12493 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
12494 /* Debug help: The architecture requires 32bit code to maintain proper
12495 sign-extended values on 64bit machines. */
12497 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
12500 cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
12501 fprintf_function cpu_fprintf
,
12506 if (!SIGN_EXT_P(env
->active_tc
.PC
))
12507 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->active_tc
.PC
);
12508 if (!SIGN_EXT_P(env
->active_tc
.HI
[0]))
12509 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->active_tc
.HI
[0]);
12510 if (!SIGN_EXT_P(env
->active_tc
.LO
[0]))
12511 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->active_tc
.LO
[0]);
12512 if (!SIGN_EXT_P(env
->btarget
))
12513 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
12515 for (i
= 0; i
< 32; i
++) {
12516 if (!SIGN_EXT_P(env
->active_tc
.gpr
[i
]))
12517 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->active_tc
.gpr
[i
]);
12520 if (!SIGN_EXT_P(env
->CP0_EPC
))
12521 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
12522 if (!SIGN_EXT_P(env
->lladdr
))
12523 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->lladdr
);
12527 void cpu_dump_state (CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
12532 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
12533 " LO=0x" TARGET_FMT_lx
" ds %04x "
12534 TARGET_FMT_lx
" " TARGET_FMT_ld
"\n",
12535 env
->active_tc
.PC
, env
->active_tc
.HI
[0], env
->active_tc
.LO
[0],
12536 env
->hflags
, env
->btarget
, env
->bcond
);
12537 for (i
= 0; i
< 32; i
++) {
12539 cpu_fprintf(f
, "GPR%02d:", i
);
12540 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->active_tc
.gpr
[i
]);
12542 cpu_fprintf(f
, "\n");
12545 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
12546 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
12547 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
12548 env
->CP0_Config0
, env
->CP0_Config1
, env
->lladdr
);
12549 if (env
->hflags
& MIPS_HFLAG_FPU
)
12550 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
12551 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
12552 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
12556 static void mips_tcg_init(void)
12561 /* Initialize various static tables. */
12565 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
12566 TCGV_UNUSED(cpu_gpr
[0]);
12567 for (i
= 1; i
< 32; i
++)
12568 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
12569 offsetof(CPUState
, active_tc
.gpr
[i
]),
12571 cpu_PC
= tcg_global_mem_new(TCG_AREG0
,
12572 offsetof(CPUState
, active_tc
.PC
), "PC");
12573 for (i
= 0; i
< MIPS_DSP_ACC
; i
++) {
12574 cpu_HI
[i
] = tcg_global_mem_new(TCG_AREG0
,
12575 offsetof(CPUState
, active_tc
.HI
[i
]),
12577 cpu_LO
[i
] = tcg_global_mem_new(TCG_AREG0
,
12578 offsetof(CPUState
, active_tc
.LO
[i
]),
12580 cpu_ACX
[i
] = tcg_global_mem_new(TCG_AREG0
,
12581 offsetof(CPUState
, active_tc
.ACX
[i
]),
12584 cpu_dspctrl
= tcg_global_mem_new(TCG_AREG0
,
12585 offsetof(CPUState
, active_tc
.DSPControl
),
12587 bcond
= tcg_global_mem_new(TCG_AREG0
,
12588 offsetof(CPUState
, bcond
), "bcond");
12589 btarget
= tcg_global_mem_new(TCG_AREG0
,
12590 offsetof(CPUState
, btarget
), "btarget");
12591 hflags
= tcg_global_mem_new_i32(TCG_AREG0
,
12592 offsetof(CPUState
, hflags
), "hflags");
12594 fpu_fcr0
= tcg_global_mem_new_i32(TCG_AREG0
,
12595 offsetof(CPUState
, active_fpu
.fcr0
),
12597 fpu_fcr31
= tcg_global_mem_new_i32(TCG_AREG0
,
12598 offsetof(CPUState
, active_fpu
.fcr31
),
12601 /* register helpers */
12602 #define GEN_HELPER 2
12603 #include "helper.h"
12608 #include "translate_init.c"
12610 CPUMIPSState
*cpu_mips_init (const char *cpu_model
)
12613 const mips_def_t
*def
;
12615 def
= cpu_mips_find_by_name(cpu_model
);
12618 env
= qemu_mallocz(sizeof(CPUMIPSState
));
12619 env
->cpu_model
= def
;
12620 env
->cpu_model_str
= cpu_model
;
12622 cpu_exec_init(env
);
12623 #ifndef CONFIG_USER_ONLY
12624 mmu_init(env
, def
);
12626 fpu_init(env
, def
);
12627 mvp_init(env
, def
);
12630 qemu_init_vcpu(env
);
12634 void cpu_reset (CPUMIPSState
*env
)
12636 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
12637 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
12638 log_cpu_state(env
, 0);
12641 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
12644 /* Reset registers to their default values */
12645 env
->CP0_PRid
= env
->cpu_model
->CP0_PRid
;
12646 env
->CP0_Config0
= env
->cpu_model
->CP0_Config0
;
12647 #ifdef TARGET_WORDS_BIGENDIAN
12648 env
->CP0_Config0
|= (1 << CP0C0_BE
);
12650 env
->CP0_Config1
= env
->cpu_model
->CP0_Config1
;
12651 env
->CP0_Config2
= env
->cpu_model
->CP0_Config2
;
12652 env
->CP0_Config3
= env
->cpu_model
->CP0_Config3
;
12653 env
->CP0_Config6
= env
->cpu_model
->CP0_Config6
;
12654 env
->CP0_Config7
= env
->cpu_model
->CP0_Config7
;
12655 env
->CP0_LLAddr_rw_bitmask
= env
->cpu_model
->CP0_LLAddr_rw_bitmask
12656 << env
->cpu_model
->CP0_LLAddr_shift
;
12657 env
->CP0_LLAddr_shift
= env
->cpu_model
->CP0_LLAddr_shift
;
12658 env
->SYNCI_Step
= env
->cpu_model
->SYNCI_Step
;
12659 env
->CCRes
= env
->cpu_model
->CCRes
;
12660 env
->CP0_Status_rw_bitmask
= env
->cpu_model
->CP0_Status_rw_bitmask
;
12661 env
->CP0_TCStatus_rw_bitmask
= env
->cpu_model
->CP0_TCStatus_rw_bitmask
;
12662 env
->CP0_SRSCtl
= env
->cpu_model
->CP0_SRSCtl
;
12663 env
->current_tc
= 0;
12664 env
->SEGBITS
= env
->cpu_model
->SEGBITS
;
12665 env
->SEGMask
= (target_ulong
)((1ULL << env
->cpu_model
->SEGBITS
) - 1);
12666 #if defined(TARGET_MIPS64)
12667 if (env
->cpu_model
->insn_flags
& ISA_MIPS3
) {
12668 env
->SEGMask
|= 3ULL << 62;
12671 env
->PABITS
= env
->cpu_model
->PABITS
;
12672 env
->PAMask
= (target_ulong
)((1ULL << env
->cpu_model
->PABITS
) - 1);
12673 env
->CP0_SRSConf0_rw_bitmask
= env
->cpu_model
->CP0_SRSConf0_rw_bitmask
;
12674 env
->CP0_SRSConf0
= env
->cpu_model
->CP0_SRSConf0
;
12675 env
->CP0_SRSConf1_rw_bitmask
= env
->cpu_model
->CP0_SRSConf1_rw_bitmask
;
12676 env
->CP0_SRSConf1
= env
->cpu_model
->CP0_SRSConf1
;
12677 env
->CP0_SRSConf2_rw_bitmask
= env
->cpu_model
->CP0_SRSConf2_rw_bitmask
;
12678 env
->CP0_SRSConf2
= env
->cpu_model
->CP0_SRSConf2
;
12679 env
->CP0_SRSConf3_rw_bitmask
= env
->cpu_model
->CP0_SRSConf3_rw_bitmask
;
12680 env
->CP0_SRSConf3
= env
->cpu_model
->CP0_SRSConf3
;
12681 env
->CP0_SRSConf4_rw_bitmask
= env
->cpu_model
->CP0_SRSConf4_rw_bitmask
;
12682 env
->CP0_SRSConf4
= env
->cpu_model
->CP0_SRSConf4
;
12683 env
->insn_flags
= env
->cpu_model
->insn_flags
;
12685 #if defined(CONFIG_USER_ONLY)
12686 env
->hflags
= MIPS_HFLAG_UM
;
12687 /* Enable access to the SYNCI_Step register. */
12688 env
->CP0_HWREna
|= (1 << 1);
12689 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
12690 env
->hflags
|= MIPS_HFLAG_FPU
;
12692 #ifdef TARGET_MIPS64
12693 if (env
->active_fpu
.fcr0
& (1 << FCR0_F64
)) {
12694 env
->hflags
|= MIPS_HFLAG_F64
;
12698 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
12699 /* If the exception was raised from a delay slot,
12700 come back to the jump. */
12701 env
->CP0_ErrorEPC
= env
->active_tc
.PC
- 4;
12703 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
12705 env
->active_tc
.PC
= (int32_t)0xBFC00000;
12706 env
->CP0_Random
= env
->tlb
->nb_tlb
- 1;
12707 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
12708 env
->CP0_Wired
= 0;
12709 env
->CP0_EBase
= 0x80000000 | (env
->cpu_index
& 0x3FF);
12710 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
12711 /* vectored interrupts not implemented, timer on int 7,
12712 no performance counters. */
12713 env
->CP0_IntCtl
= 0xe0000000;
12717 for (i
= 0; i
< 7; i
++) {
12718 env
->CP0_WatchLo
[i
] = 0;
12719 env
->CP0_WatchHi
[i
] = 0x80000000;
12721 env
->CP0_WatchLo
[7] = 0;
12722 env
->CP0_WatchHi
[7] = 0;
12724 /* Count register increments in debug mode, EJTAG version 1 */
12725 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
12726 env
->hflags
= MIPS_HFLAG_CP0
;
12728 #if defined(TARGET_MIPS64)
12729 if (env
->cpu_model
->insn_flags
& ISA_MIPS3
) {
12730 env
->hflags
|= MIPS_HFLAG_64
;
12733 env
->exception_index
= EXCP_NONE
;
12736 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
12737 unsigned long searched_pc
, int pc_pos
, void *puc
)
12739 env
->active_tc
.PC
= gen_opc_pc
[pc_pos
];
12740 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
12741 env
->hflags
|= gen_opc_hflags
[pc_pos
];