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win32: Add missing function setenv
[qemu/lumag.git] / hw / sun4m.c
bloba1373d4072f518a48512afc79e7bd77d53261bf6
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "esp.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
41 #include "loader.h"
42 #include "elf.h"
43
44 //#define DEBUG_IRQ
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #ifdef DEBUG_IRQ
75 #define DPRINTF(fmt, ...) \
76 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
77 #else
78 #define DPRINTF(fmt, ...)
79 #endif
80
81 #define KERNEL_LOAD_ADDR 0x00004000
82 #define CMDLINE_ADDR 0x007ff000
83 #define INITRD_LOAD_ADDR 0x00800000
84 #define PROM_SIZE_MAX (1024 * 1024)
85 #define PROM_VADDR 0xffd00000
86 #define PROM_FILENAME "openbios-sparc32"
87 #define CFG_ADDR 0xd00000510ULL
88 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
89
90 #define MAX_CPUS 16
91 #define MAX_PILS 16
92 #define MAX_VSIMMS 4
93
94 #define ESCC_CLOCK 4915200
95
96 struct sun4m_hwdef {
97 target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
98 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
99 target_phys_addr_t serial_base, fd_base;
100 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
101 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
102 target_phys_addr_t bpp_base, dbri_base, sx_base;
103 struct {
104 target_phys_addr_t reg_base, vram_base;
105 } vsimm[MAX_VSIMMS];
106 target_phys_addr_t ecc_base;
107 uint32_t ecc_version;
108 uint8_t nvram_machine_id;
109 uint16_t machine_id;
110 uint32_t iommu_version;
111 uint64_t max_mem;
112 const char * const default_cpu_model;
113 };
114
115 #define MAX_IOUNITS 5
116
117 struct sun4d_hwdef {
118 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
119 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
120 target_phys_addr_t serial_base;
121 target_phys_addr_t espdma_base, esp_base;
122 target_phys_addr_t ledma_base, le_base;
123 target_phys_addr_t tcx_base;
124 target_phys_addr_t sbi_base;
125 uint8_t nvram_machine_id;
126 uint16_t machine_id;
127 uint32_t iounit_version;
128 uint64_t max_mem;
129 const char * const default_cpu_model;
130 };
131
132 struct sun4c_hwdef {
133 target_phys_addr_t iommu_base, slavio_base;
134 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
135 target_phys_addr_t serial_base, fd_base;
136 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
137 target_phys_addr_t tcx_base, aux1_base;
138 uint8_t nvram_machine_id;
139 uint16_t machine_id;
140 uint32_t iommu_version;
141 uint64_t max_mem;
142 const char * const default_cpu_model;
143 };
144
145 int DMA_get_channel_mode (int nchan)
146 {
147 return 0;
148 }
149 int DMA_read_memory (int nchan, void *buf, int pos, int size)
150 {
151 return 0;
152 }
153 int DMA_write_memory (int nchan, void *buf, int pos, int size)
154 {
155 return 0;
156 }
157 void DMA_hold_DREQ (int nchan) {}
158 void DMA_release_DREQ (int nchan) {}
159 void DMA_schedule(int nchan) {}
160
161 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
162 {
163 }
164
165 void DMA_register_channel (int nchan,
166 DMA_transfer_handler transfer_handler,
167 void *opaque)
168 {
169 }
170
171 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
172 {
173 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
174 return 0;
175 }
176
177 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
178 const char *cmdline, const char *boot_devices,
179 ram_addr_t RAM_size, uint32_t kernel_size,
180 int width, int height, int depth,
181 int nvram_machine_id, const char *arch)
182 {
183 unsigned int i;
184 uint32_t start, end;
185 uint8_t image[0x1ff0];
186 struct OpenBIOS_nvpart_v1 *part_header;
187
188 memset(image, '\0', sizeof(image));
189
190 start = 0;
191
192 // OpenBIOS nvram variables
193 // Variable partition
194 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
195 part_header->signature = OPENBIOS_PART_SYSTEM;
196 pstrcpy(part_header->name, sizeof(part_header->name), "system");
197
198 end = start + sizeof(struct OpenBIOS_nvpart_v1);
199 for (i = 0; i < nb_prom_envs; i++)
200 end = OpenBIOS_set_var(image, end, prom_envs[i]);
201
202 // End marker
203 image[end++] = '\0';
204
205 end = start + ((end - start + 15) & ~15);
206 OpenBIOS_finish_partition(part_header, end - start);
207
208 // free partition
209 start = end;
210 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
211 part_header->signature = OPENBIOS_PART_FREE;
212 pstrcpy(part_header->name, sizeof(part_header->name), "free");
213
214 end = 0x1fd0;
215 OpenBIOS_finish_partition(part_header, end - start);
216
217 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
218 nvram_machine_id);
219
220 for (i = 0; i < sizeof(image); i++)
221 m48t59_write(nvram, i, image[i]);
222 }
223
224 static DeviceState *slavio_intctl;
225
226 void pic_info(Monitor *mon)
227 {
228 if (slavio_intctl)
229 slavio_pic_info(mon, slavio_intctl);
230 }
231
232 void irq_info(Monitor *mon)
233 {
234 if (slavio_intctl)
235 slavio_irq_info(mon, slavio_intctl);
236 }
237
238 void cpu_check_irqs(CPUState *env)
239 {
240 if (env->pil_in && (env->interrupt_index == 0 ||
241 (env->interrupt_index & ~15) == TT_EXTINT)) {
242 unsigned int i;
243
244 for (i = 15; i > 0; i--) {
245 if (env->pil_in & (1 << i)) {
246 int old_interrupt = env->interrupt_index;
247
248 env->interrupt_index = TT_EXTINT | i;
249 if (old_interrupt != env->interrupt_index) {
250 DPRINTF("Set CPU IRQ %d\n", i);
251 cpu_interrupt(env, CPU_INTERRUPT_HARD);
252 }
253 break;
254 }
255 }
256 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
257 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
258 env->interrupt_index = 0;
259 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
260 }
261 }
262
263 static void cpu_set_irq(void *opaque, int irq, int level)
264 {
265 CPUState *env = opaque;
266
267 if (level) {
268 DPRINTF("Raise CPU IRQ %d\n", irq);
269 env->halted = 0;
270 env->pil_in |= 1 << irq;
271 cpu_check_irqs(env);
272 } else {
273 DPRINTF("Lower CPU IRQ %d\n", irq);
274 env->pil_in &= ~(1 << irq);
275 cpu_check_irqs(env);
276 }
277 }
278
279 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
280 {
281 }
282
283 static void main_cpu_reset(void *opaque)
284 {
285 CPUState *env = opaque;
286
287 cpu_reset(env);
288 env->halted = 0;
289 }
290
291 static void secondary_cpu_reset(void *opaque)
292 {
293 CPUState *env = opaque;
294
295 cpu_reset(env);
296 env->halted = 1;
297 }
298
299 static void cpu_halt_signal(void *opaque, int irq, int level)
300 {
301 if (level && cpu_single_env)
302 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
303 }
304
305 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
306 {
307 return addr - 0xf0000000ULL;
308 }
309
310 static unsigned long sun4m_load_kernel(const char *kernel_filename,
311 const char *initrd_filename,
312 ram_addr_t RAM_size)
313 {
314 int linux_boot;
315 unsigned int i;
316 long initrd_size, kernel_size;
317 uint8_t *ptr;
318
319 linux_boot = (kernel_filename != NULL);
320
321 kernel_size = 0;
322 if (linux_boot) {
323 int bswap_needed;
324
325 #ifdef BSWAP_NEEDED
326 bswap_needed = 1;
327 #else
328 bswap_needed = 0;
329 #endif
330 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
331 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
332 if (kernel_size < 0)
333 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
334 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
335 TARGET_PAGE_SIZE);
336 if (kernel_size < 0)
337 kernel_size = load_image_targphys(kernel_filename,
338 KERNEL_LOAD_ADDR,
339 RAM_size - KERNEL_LOAD_ADDR);
340 if (kernel_size < 0) {
341 fprintf(stderr, "qemu: could not load kernel '%s'\n",
342 kernel_filename);
343 exit(1);
344 }
345
346 /* load initrd */
347 initrd_size = 0;
348 if (initrd_filename) {
349 initrd_size = load_image_targphys(initrd_filename,
350 INITRD_LOAD_ADDR,
351 RAM_size - INITRD_LOAD_ADDR);
352 if (initrd_size < 0) {
353 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
354 initrd_filename);
355 exit(1);
356 }
357 }
358 if (initrd_size > 0) {
359 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
360 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
361 if (ldl_p(ptr) == 0x48647253) { // HdrS
362 stl_p(ptr + 16, INITRD_LOAD_ADDR);
363 stl_p(ptr + 20, initrd_size);
364 break;
365 }
366 }
367 }
368 }
369 return kernel_size;
370 }
371
372 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
373 {
374 DeviceState *dev;
375 SysBusDevice *s;
376
377 dev = qdev_create(NULL, "iommu");
378 qdev_prop_set_uint32(dev, "version", version);
379 qdev_init_nofail(dev);
380 s = sysbus_from_qdev(dev);
381 sysbus_connect_irq(s, 0, irq);
382 sysbus_mmio_map(s, 0, addr);
383
384 return s;
385 }
386
387 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
388 void *iommu, qemu_irq *dev_irq)
389 {
390 DeviceState *dev;
391 SysBusDevice *s;
392
393 dev = qdev_create(NULL, "sparc32_dma");
394 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
395 qdev_init_nofail(dev);
396 s = sysbus_from_qdev(dev);
397 sysbus_connect_irq(s, 0, parent_irq);
398 *dev_irq = qdev_get_gpio_in(dev, 0);
399 sysbus_mmio_map(s, 0, daddr);
400
401 return s;
402 }
403
404 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
405 void *dma_opaque, qemu_irq irq)
406 {
407 DeviceState *dev;
408 SysBusDevice *s;
409 qemu_irq reset;
410
411 qemu_check_nic_model(&nd_table[0], "lance");
412
413 dev = qdev_create(NULL, "lance");
414 qdev_set_nic_properties(dev, nd);
415 qdev_prop_set_ptr(dev, "dma", dma_opaque);
416 qdev_init_nofail(dev);
417 s = sysbus_from_qdev(dev);
418 sysbus_mmio_map(s, 0, leaddr);
419 sysbus_connect_irq(s, 0, irq);
420 reset = qdev_get_gpio_in(dev, 0);
421 qdev_connect_gpio_out(dma_opaque, 0, reset);
422 }
423
424 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
425 target_phys_addr_t addrg,
426 qemu_irq **parent_irq)
427 {
428 DeviceState *dev;
429 SysBusDevice *s;
430 unsigned int i, j;
431
432 dev = qdev_create(NULL, "slavio_intctl");
433 qdev_init_nofail(dev);
434
435 s = sysbus_from_qdev(dev);
436
437 for (i = 0; i < MAX_CPUS; i++) {
438 for (j = 0; j < MAX_PILS; j++) {
439 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
440 }
441 }
442 sysbus_mmio_map(s, 0, addrg);
443 for (i = 0; i < MAX_CPUS; i++) {
444 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
445 }
446
447 return dev;
448 }
449
450 #define SYS_TIMER_OFFSET 0x10000ULL
451 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
452
453 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
454 qemu_irq *cpu_irqs, unsigned int num_cpus)
455 {
456 DeviceState *dev;
457 SysBusDevice *s;
458 unsigned int i;
459
460 dev = qdev_create(NULL, "slavio_timer");
461 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
462 qdev_init_nofail(dev);
463 s = sysbus_from_qdev(dev);
464 sysbus_connect_irq(s, 0, master_irq);
465 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
466
467 for (i = 0; i < MAX_CPUS; i++) {
468 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
469 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
470 }
471 }
472
473 #define MISC_LEDS 0x01600000
474 #define MISC_CFG 0x01800000
475 #define MISC_DIAG 0x01a00000
476 #define MISC_MDM 0x01b00000
477 #define MISC_SYS 0x01f00000
478
479 static void slavio_misc_init(target_phys_addr_t base,
480 target_phys_addr_t aux1_base,
481 target_phys_addr_t aux2_base, qemu_irq irq,
482 qemu_irq fdc_tc)
483 {
484 DeviceState *dev;
485 SysBusDevice *s;
486
487 dev = qdev_create(NULL, "slavio_misc");
488 qdev_init_nofail(dev);
489 s = sysbus_from_qdev(dev);
490 if (base) {
491 /* 8 bit registers */
492 /* Slavio control */
493 sysbus_mmio_map(s, 0, base + MISC_CFG);
494 /* Diagnostics */
495 sysbus_mmio_map(s, 1, base + MISC_DIAG);
496 /* Modem control */
497 sysbus_mmio_map(s, 2, base + MISC_MDM);
498 /* 16 bit registers */
499 /* ss600mp diag LEDs */
500 sysbus_mmio_map(s, 3, base + MISC_LEDS);
501 /* 32 bit registers */
502 /* System control */
503 sysbus_mmio_map(s, 4, base + MISC_SYS);
504 }
505 if (aux1_base) {
506 /* AUX 1 (Misc System Functions) */
507 sysbus_mmio_map(s, 5, aux1_base);
508 }
509 if (aux2_base) {
510 /* AUX 2 (Software Powerdown Control) */
511 sysbus_mmio_map(s, 6, aux2_base);
512 }
513 sysbus_connect_irq(s, 0, irq);
514 sysbus_connect_irq(s, 1, fdc_tc);
515 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
516 }
517
518 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
519 {
520 DeviceState *dev;
521 SysBusDevice *s;
522
523 dev = qdev_create(NULL, "eccmemctl");
524 qdev_prop_set_uint32(dev, "version", version);
525 qdev_init_nofail(dev);
526 s = sysbus_from_qdev(dev);
527 sysbus_connect_irq(s, 0, irq);
528 sysbus_mmio_map(s, 0, base);
529 if (version == 0) { // SS-600MP only
530 sysbus_mmio_map(s, 1, base + 0x1000);
531 }
532 }
533
534 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
535 {
536 DeviceState *dev;
537 SysBusDevice *s;
538
539 dev = qdev_create(NULL, "apc");
540 qdev_init_nofail(dev);
541 s = sysbus_from_qdev(dev);
542 /* Power management (APC) XXX: not a Slavio device */
543 sysbus_mmio_map(s, 0, power_base);
544 sysbus_connect_irq(s, 0, cpu_halt);
545 }
546
547 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
548 int height, int depth)
549 {
550 DeviceState *dev;
551 SysBusDevice *s;
552
553 dev = qdev_create(NULL, "SUNW,tcx");
554 qdev_prop_set_taddr(dev, "addr", addr);
555 qdev_prop_set_uint32(dev, "vram_size", vram_size);
556 qdev_prop_set_uint16(dev, "width", width);
557 qdev_prop_set_uint16(dev, "height", height);
558 qdev_prop_set_uint16(dev, "depth", depth);
559 qdev_init_nofail(dev);
560 s = sysbus_from_qdev(dev);
561 /* 8-bit plane */
562 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
563 /* DAC */
564 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
565 /* TEC (dummy) */
566 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
567 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
568 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
569 if (depth == 24) {
570 /* 24-bit plane */
571 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
572 /* Control plane */
573 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
574 } else {
575 /* THC 8 bit (dummy) */
576 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
577 }
578 }
579
580 /* NCR89C100/MACIO Internal ID register */
581 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
582
583 static void idreg_init(target_phys_addr_t addr)
584 {
585 DeviceState *dev;
586 SysBusDevice *s;
587
588 dev = qdev_create(NULL, "macio_idreg");
589 qdev_init_nofail(dev);
590 s = sysbus_from_qdev(dev);
591
592 sysbus_mmio_map(s, 0, addr);
593 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
594 }
595
596 static int idreg_init1(SysBusDevice *dev)
597 {
598 ram_addr_t idreg_offset;
599
600 idreg_offset = qemu_ram_alloc(NULL, "sun4m.idreg", sizeof(idreg_data));
601 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
602 return 0;
603 }
604
605 static SysBusDeviceInfo idreg_info = {
606 .init = idreg_init1,
607 .qdev.name = "macio_idreg",
608 .qdev.size = sizeof(SysBusDevice),
609 };
610
611 static void idreg_register_devices(void)
612 {
613 sysbus_register_withprop(&idreg_info);
614 }
615
616 device_init(idreg_register_devices);
617
618 /* SS-5 TCX AFX register */
619 static void afx_init(target_phys_addr_t addr)
620 {
621 DeviceState *dev;
622 SysBusDevice *s;
623
624 dev = qdev_create(NULL, "tcx_afx");
625 qdev_init_nofail(dev);
626 s = sysbus_from_qdev(dev);
627
628 sysbus_mmio_map(s, 0, addr);
629 }
630
631 static int afx_init1(SysBusDevice *dev)
632 {
633 ram_addr_t afx_offset;
634
635 afx_offset = qemu_ram_alloc(NULL, "sun4m.afx", 4);
636 sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);
637 return 0;
638 }
639
640 static SysBusDeviceInfo afx_info = {
641 .init = afx_init1,
642 .qdev.name = "tcx_afx",
643 .qdev.size = sizeof(SysBusDevice),
644 };
645
646 static void afx_register_devices(void)
647 {
648 sysbus_register_withprop(&afx_info);
649 }
650
651 device_init(afx_register_devices);
652
653 /* Boot PROM (OpenBIOS) */
654 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
655 {
656 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
657 return addr + *base_addr - PROM_VADDR;
658 }
659
660 static void prom_init(target_phys_addr_t addr, const char *bios_name)
661 {
662 DeviceState *dev;
663 SysBusDevice *s;
664 char *filename;
665 int ret;
666
667 dev = qdev_create(NULL, "openprom");
668 qdev_init_nofail(dev);
669 s = sysbus_from_qdev(dev);
670
671 sysbus_mmio_map(s, 0, addr);
672
673 /* load boot prom */
674 if (bios_name == NULL) {
675 bios_name = PROM_FILENAME;
676 }
677 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
678 if (filename) {
679 ret = load_elf(filename, translate_prom_address, &addr, NULL,
680 NULL, NULL, 1, ELF_MACHINE, 0);
681 if (ret < 0 || ret > PROM_SIZE_MAX) {
682 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
683 }
684 qemu_free(filename);
685 } else {
686 ret = -1;
687 }
688 if (ret < 0 || ret > PROM_SIZE_MAX) {
689 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
690 exit(1);
691 }
692 }
693
694 static int prom_init1(SysBusDevice *dev)
695 {
696 ram_addr_t prom_offset;
697
698 prom_offset = qemu_ram_alloc(NULL, "sun4m.prom", PROM_SIZE_MAX);
699 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
700 return 0;
701 }
702
703 static SysBusDeviceInfo prom_info = {
704 .init = prom_init1,
705 .qdev.name = "openprom",
706 .qdev.size = sizeof(SysBusDevice),
707 .qdev.props = (Property[]) {
708 {/* end of property list */}
709 }
710 };
711
712 static void prom_register_devices(void)
713 {
714 sysbus_register_withprop(&prom_info);
715 }
716
717 device_init(prom_register_devices);
718
719 typedef struct RamDevice
720 {
721 SysBusDevice busdev;
722 uint64_t size;
723 } RamDevice;
724
725 /* System RAM */
726 static int ram_init1(SysBusDevice *dev)
727 {
728 ram_addr_t RAM_size, ram_offset;
729 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
730
731 RAM_size = d->size;
732
733 ram_offset = qemu_ram_alloc(NULL, "sun4m.ram", RAM_size);
734 sysbus_init_mmio(dev, RAM_size, ram_offset);
735 return 0;
736 }
737
738 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
739 uint64_t max_mem)
740 {
741 DeviceState *dev;
742 SysBusDevice *s;
743 RamDevice *d;
744
745 /* allocate RAM */
746 if ((uint64_t)RAM_size > max_mem) {
747 fprintf(stderr,
748 "qemu: Too much memory for this machine: %d, maximum %d\n",
749 (unsigned int)(RAM_size / (1024 * 1024)),
750 (unsigned int)(max_mem / (1024 * 1024)));
751 exit(1);
752 }
753 dev = qdev_create(NULL, "memory");
754 s = sysbus_from_qdev(dev);
755
756 d = FROM_SYSBUS(RamDevice, s);
757 d->size = RAM_size;
758 qdev_init_nofail(dev);
759
760 sysbus_mmio_map(s, 0, addr);
761 }
762
763 static SysBusDeviceInfo ram_info = {
764 .init = ram_init1,
765 .qdev.name = "memory",
766 .qdev.size = sizeof(RamDevice),
767 .qdev.props = (Property[]) {
768 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
769 DEFINE_PROP_END_OF_LIST(),
770 }
771 };
772
773 static void ram_register_devices(void)
774 {
775 sysbus_register_withprop(&ram_info);
776 }
777
778 device_init(ram_register_devices);
779
780 static void cpu_devinit(const char *cpu_model, unsigned int id,
781 uint64_t prom_addr, qemu_irq **cpu_irqs)
782 {
783 CPUState *env;
784
785 env = cpu_init(cpu_model);
786 if (!env) {
787 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
788 exit(1);
789 }
790
791 cpu_sparc_set_id(env, id);
792 if (id == 0) {
793 qemu_register_reset(main_cpu_reset, env);
794 } else {
795 qemu_register_reset(secondary_cpu_reset, env);
796 env->halted = 1;
797 }
798 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
799 env->prom_addr = prom_addr;
800 }
801
802 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
803 const char *boot_device,
804 const char *kernel_filename,
805 const char *kernel_cmdline,
806 const char *initrd_filename, const char *cpu_model)
807 {
808 unsigned int i;
809 void *iommu, *espdma, *ledma, *nvram;
810 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
811 espdma_irq, ledma_irq;
812 qemu_irq esp_reset;
813 qemu_irq fdc_tc;
814 qemu_irq *cpu_halt;
815 unsigned long kernel_size;
816 DriveInfo *fd[MAX_FD];
817 void *fw_cfg;
818 unsigned int num_vsimms;
819
820 /* init CPUs */
821 if (!cpu_model)
822 cpu_model = hwdef->default_cpu_model;
823
824 for(i = 0; i < smp_cpus; i++) {
825 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
826 }
827
828 for (i = smp_cpus; i < MAX_CPUS; i++)
829 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
830
831
832 /* set up devices */
833 ram_init(0, RAM_size, hwdef->max_mem);
834 /* models without ECC don't trap when missing ram is accessed */
835 if (!hwdef->ecc_base) {
836 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
837 }
838
839 prom_init(hwdef->slavio_base, bios_name);
840
841 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
842 hwdef->intctl_base + 0x10000ULL,
843 cpu_irqs);
844
845 for (i = 0; i < 32; i++) {
846 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
847 }
848 for (i = 0; i < MAX_CPUS; i++) {
849 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
850 }
851
852 if (hwdef->idreg_base) {
853 idreg_init(hwdef->idreg_base);
854 }
855
856 if (hwdef->afx_base) {
857 afx_init(hwdef->afx_base);
858 }
859
860 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
861 slavio_irq[30]);
862
863 if (hwdef->iommu_pad_base) {
864 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
865 Software shouldn't use aliased addresses, neither should it crash
866 when does. Using empty_slot instead of aliasing can help with
867 debugging such accesses */
868 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
869 }
870
871 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
872 iommu, &espdma_irq);
873
874 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
875 slavio_irq[16], iommu, &ledma_irq);
876
877 if (graphic_depth != 8 && graphic_depth != 24) {
878 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
879 exit (1);
880 }
881 num_vsimms = 0;
882 if (num_vsimms == 0) {
883 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
884 graphic_depth);
885 }
886
887 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
888 /* vsimm registers probed by OBP */
889 if (hwdef->vsimm[i].reg_base) {
890 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
891 }
892 }
893
894 if (hwdef->sx_base) {
895 empty_slot_init(hwdef->sx_base, 0x2000);
896 }
897
898 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
899
900 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
901
902 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
903
904 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
905 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
906 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
907 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
908 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
909 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
910
911 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
912 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
913 slavio_irq[30], fdc_tc);
914
915 if (hwdef->apc_base) {
916 apc_init(hwdef->apc_base, cpu_halt[0]);
917 }
918
919 if (hwdef->fd_base) {
920 /* there is zero or one floppy drive */
921 memset(fd, 0, sizeof(fd));
922 fd[0] = drive_get(IF_FLOPPY, 0, 0);
923 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
924 &fdc_tc);
925 }
926
927 if (drive_get_max_bus(IF_SCSI) > 0) {
928 fprintf(stderr, "qemu: too many SCSI bus\n");
929 exit(1);
930 }
931
932 esp_reset = qdev_get_gpio_in(espdma, 0);
933 esp_init(hwdef->esp_base, 2,
934 espdma_memory_read, espdma_memory_write,
935 espdma, espdma_irq, &esp_reset);
936
937
938 if (hwdef->cs_base) {
939 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
940 slavio_irq[5]);
941 }
942
943 if (hwdef->dbri_base) {
944 /* ISDN chip with attached CS4215 audio codec */
945 /* prom space */
946 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
947 /* reg space */
948 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
949 }
950
951 if (hwdef->bpp_base) {
952 /* parallel port */
953 empty_slot_init(hwdef->bpp_base, 0x20);
954 }
955
956 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
957 RAM_size);
958
959 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
960 boot_device, RAM_size, kernel_size, graphic_width,
961 graphic_height, graphic_depth, hwdef->nvram_machine_id,
962 "Sun4m");
963
964 if (hwdef->ecc_base)
965 ecc_init(hwdef->ecc_base, slavio_irq[28],
966 hwdef->ecc_version);
967
968 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
969 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
970 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
971 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
972 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
973 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
974 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
975 if (kernel_cmdline) {
976 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
977 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
978 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
979 (uint8_t*)strdup(kernel_cmdline),
980 strlen(kernel_cmdline) + 1);
981 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
982 strlen(kernel_cmdline) + 1);
983 } else {
984 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
985 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
986 }
987 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
988 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
989 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
990 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
991 }
992
993 enum {
994 ss2_id = 0,
995 ss5_id = 32,
996 vger_id,
997 lx_id,
998 ss4_id,
999 scls_id,
1000 sbook_id,
1001 ss10_id = 64,
1002 ss20_id,
1003 ss600mp_id,
1004 ss1000_id = 96,
1005 ss2000_id,
1006 };
1007
1008 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1009 /* SS-5 */
1010 {
1011 .iommu_base = 0x10000000,
1012 .iommu_pad_base = 0x10004000,
1013 .iommu_pad_len = 0x0fffb000,
1014 .tcx_base = 0x50000000,
1015 .cs_base = 0x6c000000,
1016 .slavio_base = 0x70000000,
1017 .ms_kb_base = 0x71000000,
1018 .serial_base = 0x71100000,
1019 .nvram_base = 0x71200000,
1020 .fd_base = 0x71400000,
1021 .counter_base = 0x71d00000,
1022 .intctl_base = 0x71e00000,
1023 .idreg_base = 0x78000000,
1024 .dma_base = 0x78400000,
1025 .esp_base = 0x78800000,
1026 .le_base = 0x78c00000,
1027 .apc_base = 0x6a000000,
1028 .afx_base = 0x6e000000,
1029 .aux1_base = 0x71900000,
1030 .aux2_base = 0x71910000,
1031 .nvram_machine_id = 0x80,
1032 .machine_id = ss5_id,
1033 .iommu_version = 0x05000000,
1034 .max_mem = 0x10000000,
1035 .default_cpu_model = "Fujitsu MB86904",
1036 },
1037 /* SS-10 */
1038 {
1039 .iommu_base = 0xfe0000000ULL,
1040 .tcx_base = 0xe20000000ULL,
1041 .slavio_base = 0xff0000000ULL,
1042 .ms_kb_base = 0xff1000000ULL,
1043 .serial_base = 0xff1100000ULL,
1044 .nvram_base = 0xff1200000ULL,
1045 .fd_base = 0xff1700000ULL,
1046 .counter_base = 0xff1300000ULL,
1047 .intctl_base = 0xff1400000ULL,
1048 .idreg_base = 0xef0000000ULL,
1049 .dma_base = 0xef0400000ULL,
1050 .esp_base = 0xef0800000ULL,
1051 .le_base = 0xef0c00000ULL,
1052 .apc_base = 0xefa000000ULL, // XXX should not exist
1053 .aux1_base = 0xff1800000ULL,
1054 .aux2_base = 0xff1a01000ULL,
1055 .ecc_base = 0xf00000000ULL,
1056 .ecc_version = 0x10000000, // version 0, implementation 1
1057 .nvram_machine_id = 0x72,
1058 .machine_id = ss10_id,
1059 .iommu_version = 0x03000000,
1060 .max_mem = 0xf00000000ULL,
1061 .default_cpu_model = "TI SuperSparc II",
1062 },
1063 /* SS-600MP */
1064 {
1065 .iommu_base = 0xfe0000000ULL,
1066 .tcx_base = 0xe20000000ULL,
1067 .slavio_base = 0xff0000000ULL,
1068 .ms_kb_base = 0xff1000000ULL,
1069 .serial_base = 0xff1100000ULL,
1070 .nvram_base = 0xff1200000ULL,
1071 .counter_base = 0xff1300000ULL,
1072 .intctl_base = 0xff1400000ULL,
1073 .dma_base = 0xef0081000ULL,
1074 .esp_base = 0xef0080000ULL,
1075 .le_base = 0xef0060000ULL,
1076 .apc_base = 0xefa000000ULL, // XXX should not exist
1077 .aux1_base = 0xff1800000ULL,
1078 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1079 .ecc_base = 0xf00000000ULL,
1080 .ecc_version = 0x00000000, // version 0, implementation 0
1081 .nvram_machine_id = 0x71,
1082 .machine_id = ss600mp_id,
1083 .iommu_version = 0x01000000,
1084 .max_mem = 0xf00000000ULL,
1085 .default_cpu_model = "TI SuperSparc II",
1086 },
1087 /* SS-20 */
1088 {
1089 .iommu_base = 0xfe0000000ULL,
1090 .tcx_base = 0xe20000000ULL,
1091 .slavio_base = 0xff0000000ULL,
1092 .ms_kb_base = 0xff1000000ULL,
1093 .serial_base = 0xff1100000ULL,
1094 .nvram_base = 0xff1200000ULL,
1095 .fd_base = 0xff1700000ULL,
1096 .counter_base = 0xff1300000ULL,
1097 .intctl_base = 0xff1400000ULL,
1098 .idreg_base = 0xef0000000ULL,
1099 .dma_base = 0xef0400000ULL,
1100 .esp_base = 0xef0800000ULL,
1101 .le_base = 0xef0c00000ULL,
1102 .bpp_base = 0xef4800000ULL,
1103 .apc_base = 0xefa000000ULL, // XXX should not exist
1104 .aux1_base = 0xff1800000ULL,
1105 .aux2_base = 0xff1a01000ULL,
1106 .dbri_base = 0xee0000000ULL,
1107 .sx_base = 0xf80000000ULL,
1108 .vsimm = {
1109 {
1110 .reg_base = 0x9c000000ULL,
1111 .vram_base = 0xfc000000ULL
1112 }, {
1113 .reg_base = 0x90000000ULL,
1114 .vram_base = 0xf0000000ULL
1115 }, {
1116 .reg_base = 0x94000000ULL
1117 }, {
1118 .reg_base = 0x98000000ULL
1119 }
1120 },
1121 .ecc_base = 0xf00000000ULL,
1122 .ecc_version = 0x20000000, // version 0, implementation 2
1123 .nvram_machine_id = 0x72,
1124 .machine_id = ss20_id,
1125 .iommu_version = 0x13000000,
1126 .max_mem = 0xf00000000ULL,
1127 .default_cpu_model = "TI SuperSparc II",
1128 },
1129 /* Voyager */
1130 {
1131 .iommu_base = 0x10000000,
1132 .tcx_base = 0x50000000,
1133 .slavio_base = 0x70000000,
1134 .ms_kb_base = 0x71000000,
1135 .serial_base = 0x71100000,
1136 .nvram_base = 0x71200000,
1137 .fd_base = 0x71400000,
1138 .counter_base = 0x71d00000,
1139 .intctl_base = 0x71e00000,
1140 .idreg_base = 0x78000000,
1141 .dma_base = 0x78400000,
1142 .esp_base = 0x78800000,
1143 .le_base = 0x78c00000,
1144 .apc_base = 0x71300000, // pmc
1145 .aux1_base = 0x71900000,
1146 .aux2_base = 0x71910000,
1147 .nvram_machine_id = 0x80,
1148 .machine_id = vger_id,
1149 .iommu_version = 0x05000000,
1150 .max_mem = 0x10000000,
1151 .default_cpu_model = "Fujitsu MB86904",
1152 },
1153 /* LX */
1154 {
1155 .iommu_base = 0x10000000,
1156 .iommu_pad_base = 0x10004000,
1157 .iommu_pad_len = 0x0fffb000,
1158 .tcx_base = 0x50000000,
1159 .slavio_base = 0x70000000,
1160 .ms_kb_base = 0x71000000,
1161 .serial_base = 0x71100000,
1162 .nvram_base = 0x71200000,
1163 .fd_base = 0x71400000,
1164 .counter_base = 0x71d00000,
1165 .intctl_base = 0x71e00000,
1166 .idreg_base = 0x78000000,
1167 .dma_base = 0x78400000,
1168 .esp_base = 0x78800000,
1169 .le_base = 0x78c00000,
1170 .aux1_base = 0x71900000,
1171 .aux2_base = 0x71910000,
1172 .nvram_machine_id = 0x80,
1173 .machine_id = lx_id,
1174 .iommu_version = 0x04000000,
1175 .max_mem = 0x10000000,
1176 .default_cpu_model = "TI MicroSparc I",
1177 },
1178 /* SS-4 */
1179 {
1180 .iommu_base = 0x10000000,
1181 .tcx_base = 0x50000000,
1182 .cs_base = 0x6c000000,
1183 .slavio_base = 0x70000000,
1184 .ms_kb_base = 0x71000000,
1185 .serial_base = 0x71100000,
1186 .nvram_base = 0x71200000,
1187 .fd_base = 0x71400000,
1188 .counter_base = 0x71d00000,
1189 .intctl_base = 0x71e00000,
1190 .idreg_base = 0x78000000,
1191 .dma_base = 0x78400000,
1192 .esp_base = 0x78800000,
1193 .le_base = 0x78c00000,
1194 .apc_base = 0x6a000000,
1195 .aux1_base = 0x71900000,
1196 .aux2_base = 0x71910000,
1197 .nvram_machine_id = 0x80,
1198 .machine_id = ss4_id,
1199 .iommu_version = 0x05000000,
1200 .max_mem = 0x10000000,
1201 .default_cpu_model = "Fujitsu MB86904",
1202 },
1203 /* SPARCClassic */
1204 {
1205 .iommu_base = 0x10000000,
1206 .tcx_base = 0x50000000,
1207 .slavio_base = 0x70000000,
1208 .ms_kb_base = 0x71000000,
1209 .serial_base = 0x71100000,
1210 .nvram_base = 0x71200000,
1211 .fd_base = 0x71400000,
1212 .counter_base = 0x71d00000,
1213 .intctl_base = 0x71e00000,
1214 .idreg_base = 0x78000000,
1215 .dma_base = 0x78400000,
1216 .esp_base = 0x78800000,
1217 .le_base = 0x78c00000,
1218 .apc_base = 0x6a000000,
1219 .aux1_base = 0x71900000,
1220 .aux2_base = 0x71910000,
1221 .nvram_machine_id = 0x80,
1222 .machine_id = scls_id,
1223 .iommu_version = 0x05000000,
1224 .max_mem = 0x10000000,
1225 .default_cpu_model = "TI MicroSparc I",
1226 },
1227 /* SPARCbook */
1228 {
1229 .iommu_base = 0x10000000,
1230 .tcx_base = 0x50000000, // XXX
1231 .slavio_base = 0x70000000,
1232 .ms_kb_base = 0x71000000,
1233 .serial_base = 0x71100000,
1234 .nvram_base = 0x71200000,
1235 .fd_base = 0x71400000,
1236 .counter_base = 0x71d00000,
1237 .intctl_base = 0x71e00000,
1238 .idreg_base = 0x78000000,
1239 .dma_base = 0x78400000,
1240 .esp_base = 0x78800000,
1241 .le_base = 0x78c00000,
1242 .apc_base = 0x6a000000,
1243 .aux1_base = 0x71900000,
1244 .aux2_base = 0x71910000,
1245 .nvram_machine_id = 0x80,
1246 .machine_id = sbook_id,
1247 .iommu_version = 0x05000000,
1248 .max_mem = 0x10000000,
1249 .default_cpu_model = "TI MicroSparc I",
1250 },
1251 };
1252
1253 /* SPARCstation 5 hardware initialisation */
1254 static void ss5_init(ram_addr_t RAM_size,
1255 const char *boot_device,
1256 const char *kernel_filename, const char *kernel_cmdline,
1257 const char *initrd_filename, const char *cpu_model)
1258 {
1259 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1260 kernel_cmdline, initrd_filename, cpu_model);
1261 }
1262
1263 /* SPARCstation 10 hardware initialisation */
1264 static void ss10_init(ram_addr_t RAM_size,
1265 const char *boot_device,
1266 const char *kernel_filename, const char *kernel_cmdline,
1267 const char *initrd_filename, const char *cpu_model)
1268 {
1269 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1270 kernel_cmdline, initrd_filename, cpu_model);
1271 }
1272
1273 /* SPARCserver 600MP hardware initialisation */
1274 static void ss600mp_init(ram_addr_t RAM_size,
1275 const char *boot_device,
1276 const char *kernel_filename,
1277 const char *kernel_cmdline,
1278 const char *initrd_filename, const char *cpu_model)
1279 {
1280 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1281 kernel_cmdline, initrd_filename, cpu_model);
1282 }
1283
1284 /* SPARCstation 20 hardware initialisation */
1285 static void ss20_init(ram_addr_t RAM_size,
1286 const char *boot_device,
1287 const char *kernel_filename, const char *kernel_cmdline,
1288 const char *initrd_filename, const char *cpu_model)
1289 {
1290 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1291 kernel_cmdline, initrd_filename, cpu_model);
1292 }
1293
1294 /* SPARCstation Voyager hardware initialisation */
1295 static void vger_init(ram_addr_t RAM_size,
1296 const char *boot_device,
1297 const char *kernel_filename, const char *kernel_cmdline,
1298 const char *initrd_filename, const char *cpu_model)
1299 {
1300 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1301 kernel_cmdline, initrd_filename, cpu_model);
1302 }
1303
1304 /* SPARCstation LX hardware initialisation */
1305 static void ss_lx_init(ram_addr_t RAM_size,
1306 const char *boot_device,
1307 const char *kernel_filename, const char *kernel_cmdline,
1308 const char *initrd_filename, const char *cpu_model)
1309 {
1310 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1311 kernel_cmdline, initrd_filename, cpu_model);
1312 }
1313
1314 /* SPARCstation 4 hardware initialisation */
1315 static void ss4_init(ram_addr_t RAM_size,
1316 const char *boot_device,
1317 const char *kernel_filename, const char *kernel_cmdline,
1318 const char *initrd_filename, const char *cpu_model)
1319 {
1320 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1321 kernel_cmdline, initrd_filename, cpu_model);
1322 }
1323
1324 /* SPARCClassic hardware initialisation */
1325 static void scls_init(ram_addr_t RAM_size,
1326 const char *boot_device,
1327 const char *kernel_filename, const char *kernel_cmdline,
1328 const char *initrd_filename, const char *cpu_model)
1329 {
1330 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1331 kernel_cmdline, initrd_filename, cpu_model);
1332 }
1333
1334 /* SPARCbook hardware initialisation */
1335 static void sbook_init(ram_addr_t RAM_size,
1336 const char *boot_device,
1337 const char *kernel_filename, const char *kernel_cmdline,
1338 const char *initrd_filename, const char *cpu_model)
1339 {
1340 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1341 kernel_cmdline, initrd_filename, cpu_model);
1342 }
1343
1344 static QEMUMachine ss5_machine = {
1345 .name = "SS-5",
1346 .desc = "Sun4m platform, SPARCstation 5",
1347 .init = ss5_init,
1348 .use_scsi = 1,
1349 .is_default = 1,
1350 };
1351
1352 static QEMUMachine ss10_machine = {
1353 .name = "SS-10",
1354 .desc = "Sun4m platform, SPARCstation 10",
1355 .init = ss10_init,
1356 .use_scsi = 1,
1357 .max_cpus = 4,
1358 };
1359
1360 static QEMUMachine ss600mp_machine = {
1361 .name = "SS-600MP",
1362 .desc = "Sun4m platform, SPARCserver 600MP",
1363 .init = ss600mp_init,
1364 .use_scsi = 1,
1365 .max_cpus = 4,
1366 };
1367
1368 static QEMUMachine ss20_machine = {
1369 .name = "SS-20",
1370 .desc = "Sun4m platform, SPARCstation 20",
1371 .init = ss20_init,
1372 .use_scsi = 1,
1373 .max_cpus = 4,
1374 };
1375
1376 static QEMUMachine voyager_machine = {
1377 .name = "Voyager",
1378 .desc = "Sun4m platform, SPARCstation Voyager",
1379 .init = vger_init,
1380 .use_scsi = 1,
1381 };
1382
1383 static QEMUMachine ss_lx_machine = {
1384 .name = "LX",
1385 .desc = "Sun4m platform, SPARCstation LX",
1386 .init = ss_lx_init,
1387 .use_scsi = 1,
1388 };
1389
1390 static QEMUMachine ss4_machine = {
1391 .name = "SS-4",
1392 .desc = "Sun4m platform, SPARCstation 4",
1393 .init = ss4_init,
1394 .use_scsi = 1,
1395 };
1396
1397 static QEMUMachine scls_machine = {
1398 .name = "SPARCClassic",
1399 .desc = "Sun4m platform, SPARCClassic",
1400 .init = scls_init,
1401 .use_scsi = 1,
1402 };
1403
1404 static QEMUMachine sbook_machine = {
1405 .name = "SPARCbook",
1406 .desc = "Sun4m platform, SPARCbook",
1407 .init = sbook_init,
1408 .use_scsi = 1,
1409 };
1410
1411 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1412 /* SS-1000 */
1413 {
1414 .iounit_bases = {
1415 0xfe0200000ULL,
1416 0xfe1200000ULL,
1417 0xfe2200000ULL,
1418 0xfe3200000ULL,
1419 -1,
1420 },
1421 .tcx_base = 0x820000000ULL,
1422 .slavio_base = 0xf00000000ULL,
1423 .ms_kb_base = 0xf00240000ULL,
1424 .serial_base = 0xf00200000ULL,
1425 .nvram_base = 0xf00280000ULL,
1426 .counter_base = 0xf00300000ULL,
1427 .espdma_base = 0x800081000ULL,
1428 .esp_base = 0x800080000ULL,
1429 .ledma_base = 0x800040000ULL,
1430 .le_base = 0x800060000ULL,
1431 .sbi_base = 0xf02800000ULL,
1432 .nvram_machine_id = 0x80,
1433 .machine_id = ss1000_id,
1434 .iounit_version = 0x03000000,
1435 .max_mem = 0xf00000000ULL,
1436 .default_cpu_model = "TI SuperSparc II",
1437 },
1438 /* SS-2000 */
1439 {
1440 .iounit_bases = {
1441 0xfe0200000ULL,
1442 0xfe1200000ULL,
1443 0xfe2200000ULL,
1444 0xfe3200000ULL,
1445 0xfe4200000ULL,
1446 },
1447 .tcx_base = 0x820000000ULL,
1448 .slavio_base = 0xf00000000ULL,
1449 .ms_kb_base = 0xf00240000ULL,
1450 .serial_base = 0xf00200000ULL,
1451 .nvram_base = 0xf00280000ULL,
1452 .counter_base = 0xf00300000ULL,
1453 .espdma_base = 0x800081000ULL,
1454 .esp_base = 0x800080000ULL,
1455 .ledma_base = 0x800040000ULL,
1456 .le_base = 0x800060000ULL,
1457 .sbi_base = 0xf02800000ULL,
1458 .nvram_machine_id = 0x80,
1459 .machine_id = ss2000_id,
1460 .iounit_version = 0x03000000,
1461 .max_mem = 0xf00000000ULL,
1462 .default_cpu_model = "TI SuperSparc II",
1463 },
1464 };
1465
1466 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1467 {
1468 DeviceState *dev;
1469 SysBusDevice *s;
1470 unsigned int i;
1471
1472 dev = qdev_create(NULL, "sbi");
1473 qdev_init_nofail(dev);
1474
1475 s = sysbus_from_qdev(dev);
1476
1477 for (i = 0; i < MAX_CPUS; i++) {
1478 sysbus_connect_irq(s, i, *parent_irq[i]);
1479 }
1480
1481 sysbus_mmio_map(s, 0, addr);
1482
1483 return dev;
1484 }
1485
1486 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1487 const char *boot_device,
1488 const char *kernel_filename,
1489 const char *kernel_cmdline,
1490 const char *initrd_filename, const char *cpu_model)
1491 {
1492 unsigned int i;
1493 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1494 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1495 espdma_irq, ledma_irq;
1496 qemu_irq esp_reset;
1497 unsigned long kernel_size;
1498 void *fw_cfg;
1499 DeviceState *dev;
1500
1501 /* init CPUs */
1502 if (!cpu_model)
1503 cpu_model = hwdef->default_cpu_model;
1504
1505 for(i = 0; i < smp_cpus; i++) {
1506 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1507 }
1508
1509 for (i = smp_cpus; i < MAX_CPUS; i++)
1510 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1511
1512 /* set up devices */
1513 ram_init(0, RAM_size, hwdef->max_mem);
1514
1515 prom_init(hwdef->slavio_base, bios_name);
1516
1517 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1518
1519 for (i = 0; i < 32; i++) {
1520 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1521 }
1522 for (i = 0; i < MAX_CPUS; i++) {
1523 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1524 }
1525
1526 for (i = 0; i < MAX_IOUNITS; i++)
1527 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1528 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1529 hwdef->iounit_version,
1530 sbi_irq[0]);
1531
1532 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1533 iounits[0], &espdma_irq);
1534
1535 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1536 iounits[0], &ledma_irq);
1537
1538 if (graphic_depth != 8 && graphic_depth != 24) {
1539 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1540 exit (1);
1541 }
1542 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1543 graphic_depth);
1544
1545 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1546
1547 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1548
1549 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1550
1551 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1552 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1553 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1554 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1555 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1556 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1557
1558 if (drive_get_max_bus(IF_SCSI) > 0) {
1559 fprintf(stderr, "qemu: too many SCSI bus\n");
1560 exit(1);
1561 }
1562
1563 esp_reset = qdev_get_gpio_in(espdma, 0);
1564 esp_init(hwdef->esp_base, 2,
1565 espdma_memory_read, espdma_memory_write,
1566 espdma, espdma_irq, &esp_reset);
1567
1568 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1569 RAM_size);
1570
1571 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1572 boot_device, RAM_size, kernel_size, graphic_width,
1573 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1574 "Sun4d");
1575
1576 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1577 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1578 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1579 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1580 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1581 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1582 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1583 if (kernel_cmdline) {
1584 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1585 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1586 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1587 (uint8_t*)strdup(kernel_cmdline),
1588 strlen(kernel_cmdline) + 1);
1589 } else {
1590 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1591 }
1592 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1593 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1594 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1595 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1596 }
1597
1598 /* SPARCserver 1000 hardware initialisation */
1599 static void ss1000_init(ram_addr_t RAM_size,
1600 const char *boot_device,
1601 const char *kernel_filename, const char *kernel_cmdline,
1602 const char *initrd_filename, const char *cpu_model)
1603 {
1604 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1605 kernel_cmdline, initrd_filename, cpu_model);
1606 }
1607
1608 /* SPARCcenter 2000 hardware initialisation */
1609 static void ss2000_init(ram_addr_t RAM_size,
1610 const char *boot_device,
1611 const char *kernel_filename, const char *kernel_cmdline,
1612 const char *initrd_filename, const char *cpu_model)
1613 {
1614 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1615 kernel_cmdline, initrd_filename, cpu_model);
1616 }
1617
1618 static QEMUMachine ss1000_machine = {
1619 .name = "SS-1000",
1620 .desc = "Sun4d platform, SPARCserver 1000",
1621 .init = ss1000_init,
1622 .use_scsi = 1,
1623 .max_cpus = 8,
1624 };
1625
1626 static QEMUMachine ss2000_machine = {
1627 .name = "SS-2000",
1628 .desc = "Sun4d platform, SPARCcenter 2000",
1629 .init = ss2000_init,
1630 .use_scsi = 1,
1631 .max_cpus = 20,
1632 };
1633
1634 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1635 /* SS-2 */
1636 {
1637 .iommu_base = 0xf8000000,
1638 .tcx_base = 0xfe000000,
1639 .slavio_base = 0xf6000000,
1640 .intctl_base = 0xf5000000,
1641 .counter_base = 0xf3000000,
1642 .ms_kb_base = 0xf0000000,
1643 .serial_base = 0xf1000000,
1644 .nvram_base = 0xf2000000,
1645 .fd_base = 0xf7200000,
1646 .dma_base = 0xf8400000,
1647 .esp_base = 0xf8800000,
1648 .le_base = 0xf8c00000,
1649 .aux1_base = 0xf7400003,
1650 .nvram_machine_id = 0x55,
1651 .machine_id = ss2_id,
1652 .max_mem = 0x10000000,
1653 .default_cpu_model = "Cypress CY7C601",
1654 },
1655 };
1656
1657 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1658 qemu_irq *parent_irq)
1659 {
1660 DeviceState *dev;
1661 SysBusDevice *s;
1662 unsigned int i;
1663
1664 dev = qdev_create(NULL, "sun4c_intctl");
1665 qdev_init_nofail(dev);
1666
1667 s = sysbus_from_qdev(dev);
1668
1669 for (i = 0; i < MAX_PILS; i++) {
1670 sysbus_connect_irq(s, i, parent_irq[i]);
1671 }
1672 sysbus_mmio_map(s, 0, addr);
1673
1674 return dev;
1675 }
1676
1677 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1678 const char *boot_device,
1679 const char *kernel_filename,
1680 const char *kernel_cmdline,
1681 const char *initrd_filename, const char *cpu_model)
1682 {
1683 void *iommu, *espdma, *ledma, *nvram;
1684 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1685 qemu_irq esp_reset;
1686 qemu_irq fdc_tc;
1687 unsigned long kernel_size;
1688 DriveInfo *fd[MAX_FD];
1689 void *fw_cfg;
1690 DeviceState *dev;
1691 unsigned int i;
1692
1693 /* init CPU */
1694 if (!cpu_model)
1695 cpu_model = hwdef->default_cpu_model;
1696
1697 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1698
1699 /* set up devices */
1700 ram_init(0, RAM_size, hwdef->max_mem);
1701
1702 prom_init(hwdef->slavio_base, bios_name);
1703
1704 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1705
1706 for (i = 0; i < 8; i++) {
1707 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1708 }
1709
1710 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1711 slavio_irq[1]);
1712
1713 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1714 iommu, &espdma_irq);
1715
1716 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1717 slavio_irq[3], iommu, &ledma_irq);
1718
1719 if (graphic_depth != 8 && graphic_depth != 24) {
1720 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1721 exit (1);
1722 }
1723 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1724 graphic_depth);
1725
1726 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1727
1728 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1729
1730 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1731 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1732 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1733 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1734 escc_init(hwdef->serial_base, slavio_irq[1],
1735 slavio_irq[1], serial_hds[0], serial_hds[1],
1736 ESCC_CLOCK, 1);
1737
1738 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1739
1740 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1741 /* there is zero or one floppy drive */
1742 memset(fd, 0, sizeof(fd));
1743 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1744 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1745 &fdc_tc);
1746 }
1747
1748 if (drive_get_max_bus(IF_SCSI) > 0) {
1749 fprintf(stderr, "qemu: too many SCSI bus\n");
1750 exit(1);
1751 }
1752
1753 esp_reset = qdev_get_gpio_in(espdma, 0);
1754 esp_init(hwdef->esp_base, 2,
1755 espdma_memory_read, espdma_memory_write,
1756 espdma, espdma_irq, &esp_reset);
1757
1758 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1759 RAM_size);
1760
1761 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1762 boot_device, RAM_size, kernel_size, graphic_width,
1763 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1764 "Sun4c");
1765
1766 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1767 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1768 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1769 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1770 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1771 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1772 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1773 if (kernel_cmdline) {
1774 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1775 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1776 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1777 (uint8_t*)strdup(kernel_cmdline),
1778 strlen(kernel_cmdline) + 1);
1779 } else {
1780 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1781 }
1782 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1783 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1784 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1785 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1786 }
1787
1788 /* SPARCstation 2 hardware initialisation */
1789 static void ss2_init(ram_addr_t RAM_size,
1790 const char *boot_device,
1791 const char *kernel_filename, const char *kernel_cmdline,
1792 const char *initrd_filename, const char *cpu_model)
1793 {
1794 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1795 kernel_cmdline, initrd_filename, cpu_model);
1796 }
1797
1798 static QEMUMachine ss2_machine = {
1799 .name = "SS-2",
1800 .desc = "Sun4c platform, SPARCstation 2",
1801 .init = ss2_init,
1802 .use_scsi = 1,
1803 };
1804
1805 static void ss2_machine_init(void)
1806 {
1807 qemu_register_machine(&ss5_machine);
1808 qemu_register_machine(&ss10_machine);
1809 qemu_register_machine(&ss600mp_machine);
1810 qemu_register_machine(&ss20_machine);
1811 qemu_register_machine(&voyager_machine);
1812 qemu_register_machine(&ss_lx_machine);
1813 qemu_register_machine(&ss4_machine);
1814 qemu_register_machine(&scls_machine);
1815 qemu_register_machine(&sbook_machine);
1816 qemu_register_machine(&ss1000_machine);
1817 qemu_register_machine(&ss2000_machine);
1818 qemu_register_machine(&ss2_machine);
1819 }
1820
1821 machine_init(ss2_machine_init);
various patches