hw/slavio_intctl.c

   1 /*
   2  * QEMU Sparc SLAVIO interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sun4m.h"
  26 #include "monitor.h"
  27 #include "sysbus.h"
  28
  29 //#define DEBUG_IRQ_COUNT
  30 //#define DEBUG_IRQ
  31
  32 #ifdef DEBUG_IRQ
  33 #define DPRINTF(fmt, ...)                                       \
  34     do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
  35 #else
  36 #define DPRINTF(fmt, ...)
  37 #endif
  38
  39 /*
  40  * Registers of interrupt controller in sun4m.
  41  *
  42  * This is the interrupt controller part of chip STP2001 (Slave I/O), also
  43  * produced as NCR89C105. See
  44  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  45  *
  46  * There is a system master controller and one for each cpu.
  47  *
  48  */
  49
  50 #define MAX_CPUS 16
  51 #define MAX_PILS 16
  52
  53 struct SLAVIO_INTCTLState;
  54
  55 typedef struct SLAVIO_CPUINTCTLState {
  56     uint32_t intreg_pending;
  57     struct SLAVIO_INTCTLState *master;
  58     uint32_t cpu;
  59     uint32_t irl_out;
  60 } SLAVIO_CPUINTCTLState;
  61
  62 typedef struct SLAVIO_INTCTLState {
  63     SysBusDevice busdev;
  64     uint32_t intregm_pending;
  65     uint32_t intregm_disabled;
  66     uint32_t target_cpu;
  67 #ifdef DEBUG_IRQ_COUNT
  68     uint64_t irq_count[32];
  69 #endif
  70     qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS];
  71     SLAVIO_CPUINTCTLState slaves[MAX_CPUS];
  72 } SLAVIO_INTCTLState;
  73
  74 #define INTCTL_MAXADDR 0xf
  75 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  76 #define INTCTLM_SIZE 0x14
  77 #define MASTER_IRQ_MASK ~0x0fa2007f
  78 #define MASTER_DISABLE 0x80000000
  79 #define CPU_SOFTIRQ_MASK 0xfffe0000
  80 #define CPU_IRQ_INT15_IN (1 << 15)
  81 #define CPU_IRQ_TIMER_IN (1 << 14)
  82
  83 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
  84
  85 // per-cpu interrupt controller
  86 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
  87 {
  88     SLAVIO_CPUINTCTLState *s = opaque;
  89     uint32_t saddr, ret;
  90
  91     saddr = addr >> 2;
  92     switch (saddr) {
  93     case 0:
  94         ret = s->intreg_pending;
  95         break;
  96     default:
  97         ret = 0;
  98         break;
  99     }
 100     DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);
 101
 102     return ret;
 103 }
 104
 105 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
 106                                      uint32_t val)
 107 {
 108     SLAVIO_CPUINTCTLState *s = opaque;
 109     uint32_t saddr;
 110
 111     saddr = addr >> 2;
 112     DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
 113     switch (saddr) {
 114     case 1: // clear pending softints
 115         val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN;
 116         s->intreg_pending &= ~val;
 117         slavio_check_interrupts(s->master, 1);
 118         DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
 119                 s->intreg_pending);
 120         break;
 121     case 2: // set softint
 122         val &= CPU_SOFTIRQ_MASK;
 123         s->intreg_pending |= val;
 124         slavio_check_interrupts(s->master, 1);
 125         DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
 126                 s->intreg_pending);
 127         break;
 128     default:
 129         break;
 130     }
 131 }
 132
 133 static CPUReadMemoryFunc * const slavio_intctl_mem_read[3] = {
 134     NULL,
 135     NULL,
 136     slavio_intctl_mem_readl,
 137 };
 138
 139 static CPUWriteMemoryFunc * const slavio_intctl_mem_write[3] = {
 140     NULL,
 141     NULL,
 142     slavio_intctl_mem_writel,
 143 };
 144
 145 // master system interrupt controller
 146 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
 147 {
 148     SLAVIO_INTCTLState *s = opaque;
 149     uint32_t saddr, ret;
 150
 151     saddr = addr >> 2;
 152     switch (saddr) {
 153     case 0:
 154         ret = s->intregm_pending & ~MASTER_DISABLE;
 155         break;
 156     case 1:
 157         ret = s->intregm_disabled & MASTER_IRQ_MASK;
 158         break;
 159     case 4:
 160         ret = s->target_cpu;
 161         break;
 162     default:
 163         ret = 0;
 164         break;
 165     }
 166     DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
 167
 168     return ret;
 169 }
 170
 171 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
 172                                       uint32_t val)
 173 {
 174     SLAVIO_INTCTLState *s = opaque;
 175     uint32_t saddr;
 176
 177     saddr = addr >> 2;
 178     DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
 179     switch (saddr) {
 180     case 2: // clear (enable)
 181         // Force clear unused bits
 182         val &= MASTER_IRQ_MASK;
 183         s->intregm_disabled &= ~val;
 184         DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
 185                 s->intregm_disabled);
 186         slavio_check_interrupts(s, 1);
 187         break;
 188     case 3: // set (disable; doesn't affect pending)
 189         // Force clear unused bits
 190         val &= MASTER_IRQ_MASK;
 191         s->intregm_disabled |= val;
 192         slavio_check_interrupts(s, 1);
 193         DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
 194                 s->intregm_disabled);
 195         break;
 196     case 4:
 197         s->target_cpu = val & (MAX_CPUS - 1);
 198         slavio_check_interrupts(s, 1);
 199         DPRINTF("Set master irq cpu %d\n", s->target_cpu);
 200         break;
 201     default:
 202         break;
 203     }
 204 }
 205
 206 static CPUReadMemoryFunc * const slavio_intctlm_mem_read[3] = {
 207     NULL,
 208     NULL,
 209     slavio_intctlm_mem_readl,
 210 };
 211
 212 static CPUWriteMemoryFunc * const slavio_intctlm_mem_write[3] = {
 213     NULL,
 214     NULL,
 215     slavio_intctlm_mem_writel,
 216 };
 217
 218 void slavio_pic_info(Monitor *mon, DeviceState *dev)
 219 {
 220     SysBusDevice *sd;
 221     SLAVIO_INTCTLState *s;
 222     int i;
 223
 224     sd = sysbus_from_qdev(dev);
 225     s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
 226     for (i = 0; i < MAX_CPUS; i++) {
 227         monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
 228                        s->slaves[i].intreg_pending);
 229     }
 230     monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
 231                    s->intregm_pending, s->intregm_disabled);
 232 }
 233
 234 void slavio_irq_info(Monitor *mon, DeviceState *dev)
 235 {
 236 #ifndef DEBUG_IRQ_COUNT
 237     monitor_printf(mon, "irq statistic code not compiled.\n");
 238 #else
 239     SysBusDevice *sd;
 240     SLAVIO_INTCTLState *s;
 241     int i;
 242     int64_t count;
 243
 244     sd = sysbus_from_qdev(dev);
 245     s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
 246     monitor_printf(mon, "IRQ statistics:\n");
 247     for (i = 0; i < 32; i++) {
 248         count = s->irq_count[i];
 249         if (count > 0)
 250             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 251     }
 252 #endif
 253 }
 254
 255 static const uint32_t intbit_to_level[] = {
 256     2, 3, 5, 7, 9, 11, 13, 2,   3, 5, 7, 9, 11, 13, 12, 12,
 257     6, 13, 4, 10, 8, 9, 11, 0,  0, 0, 0, 15, 15, 15, 15, 0,
 258 };
 259
 260 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
 261 {
 262     uint32_t pending = s->intregm_pending, pil_pending;
 263     unsigned int i, j;
 264
 265     pending &= ~s->intregm_disabled;
 266
 267     DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
 268     for (i = 0; i < MAX_CPUS; i++) {
 269         pil_pending = 0;
 270
 271         /* If we are the current interrupt target, get hard interrupts */
 272         if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
 273             (i == s->target_cpu)) {
 274             for (j = 0; j < 32; j++) {
 275                 if ((pending & (1 << j)) && intbit_to_level[j]) {
 276                     pil_pending |= 1 << intbit_to_level[j];
 277                 }
 278             }
 279         }
 280
 281         /* Calculate current pending hard interrupts for display */
 282         s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN |
 283             CPU_IRQ_TIMER_IN;
 284         if (i == s->target_cpu) {
 285             for (j = 0; j < 32; j++) {
 286                 if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) {
 287                     s->slaves[i].intreg_pending |= 1 << intbit_to_level[j];
 288                 }
 289             }
 290         }
 291
 292         /* Level 15 and CPU timer interrupts are only masked when
 293            the MASTER_DISABLE bit is set */
 294         if (!(s->intregm_disabled & MASTER_DISABLE)) {
 295             pil_pending |= s->slaves[i].intreg_pending &
 296                 (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);
 297         }
 298
 299         /* Add soft interrupts */
 300         pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
 301
 302         if (set_irqs) {
 303             for (j = MAX_PILS; j > 0; j--) {
 304                 if (pil_pending & (1 << j)) {
 305                     if (!(s->slaves[i].irl_out & (1 << j))) {
 306                         qemu_irq_raise(s->cpu_irqs[i][j]);
 307                     }
 308                 } else {
 309                     if (s->slaves[i].irl_out & (1 << j)) {
 310                         qemu_irq_lower(s->cpu_irqs[i][j]);
 311                     }
 312                 }
 313             }
 314         }
 315         s->slaves[i].irl_out = pil_pending;
 316     }
 317 }
 318
 319 /*
 320  * "irq" here is the bit number in the system interrupt register to
 321  * separate serial and keyboard interrupts sharing a level.
 322  */
 323 static void slavio_set_irq(void *opaque, int irq, int level)
 324 {
 325     SLAVIO_INTCTLState *s = opaque;
 326     uint32_t mask = 1 << irq;
 327     uint32_t pil = intbit_to_level[irq];
 328     unsigned int i;
 329
 330     DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
 331             level);
 332     if (pil > 0) {
 333         if (level) {
 334 #ifdef DEBUG_IRQ_COUNT
 335             s->irq_count[pil]++;
 336 #endif
 337             s->intregm_pending |= mask;
 338             if (pil == 15) {
 339                 for (i = 0; i < MAX_CPUS; i++) {
 340                     s->slaves[i].intreg_pending |= 1 << pil;
 341                 }
 342             }
 343         } else {
 344             s->intregm_pending &= ~mask;
 345             if (pil == 15) {
 346                 for (i = 0; i < MAX_CPUS; i++) {
 347                     s->slaves[i].intreg_pending &= ~(1 << pil);
 348                 }
 349             }
 350         }
 351         slavio_check_interrupts(s, 1);
 352     }
 353 }
 354
 355 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
 356 {
 357     SLAVIO_INTCTLState *s = opaque;
 358
 359     DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
 360
 361     if (level) {
 362         s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN;
 363     } else {
 364         s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN;
 365     }
 366
 367     slavio_check_interrupts(s, 1);
 368 }
 369
 370 static void slavio_set_irq_all(void *opaque, int irq, int level)
 371 {
 372     if (irq < 32) {
 373         slavio_set_irq(opaque, irq, level);
 374     } else {
 375         slavio_set_timer_irq_cpu(opaque, irq - 32, level);
 376     }
 377 }
 378
 379 static int vmstate_intctl_post_load(void *opaque, int version_id)
 380 {
 381     SLAVIO_INTCTLState *s = opaque;
 382
 383     slavio_check_interrupts(s, 0);
 384     return 0;
 385 }
 386
 387 static const VMStateDescription vmstate_intctl_cpu = {
 388     .name ="slavio_intctl_cpu",
 389     .version_id = 1,
 390     .minimum_version_id = 1,
 391     .minimum_version_id_old = 1,
 392     .fields      = (VMStateField []) {
 393         VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState),
 394         VMSTATE_END_OF_LIST()
 395     }
 396 };
 397
 398 static const VMStateDescription vmstate_intctl = {
 399     .name ="slavio_intctl",
 400     .version_id = 1,
 401     .minimum_version_id = 1,
 402     .minimum_version_id_old = 1,
 403     .post_load = vmstate_intctl_post_load,
 404     .fields      = (VMStateField []) {
 405         VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1,
 406                              vmstate_intctl_cpu, SLAVIO_CPUINTCTLState),
 407         VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState),
 408         VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState),
 409         VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState),
 410         VMSTATE_END_OF_LIST()
 411     }
 412 };
 413
 414 static void slavio_intctl_reset(DeviceState *d)
 415 {
 416     SLAVIO_INTCTLState *s = container_of(d, SLAVIO_INTCTLState, busdev.qdev);
 417     int i;
 418
 419     for (i = 0; i < MAX_CPUS; i++) {
 420         s->slaves[i].intreg_pending = 0;
 421         s->slaves[i].irl_out = 0;
 422     }
 423     s->intregm_disabled = ~MASTER_IRQ_MASK;
 424     s->intregm_pending = 0;
 425     s->target_cpu = 0;
 426     slavio_check_interrupts(s, 0);
 427 }
 428
 429 static int slavio_intctl_init1(SysBusDevice *dev)
 430 {
 431     SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev);
 432     int io_memory;
 433     unsigned int i, j;
 434
 435     qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
 436     io_memory = cpu_register_io_memory(slavio_intctlm_mem_read,
 437                                        slavio_intctlm_mem_write, s);
 438     sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory);
 439
 440     for (i = 0; i < MAX_CPUS; i++) {
 441         for (j = 0; j < MAX_PILS; j++) {
 442             sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
 443         }
 444         io_memory = cpu_register_io_memory(slavio_intctl_mem_read,
 445                                            slavio_intctl_mem_write,
 446                                            &s->slaves[i]);
 447         sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
 448         s->slaves[i].cpu = i;
 449         s->slaves[i].master = s;
 450     }
 451
 452     return 0;
 453 }
 454
 455 static SysBusDeviceInfo slavio_intctl_info = {
 456     .init = slavio_intctl_init1,
 457     .qdev.name  = "slavio_intctl",
 458     .qdev.size  = sizeof(SLAVIO_INTCTLState),
 459     .qdev.vmsd  = &vmstate_intctl,
 460     .qdev.reset = slavio_intctl_reset,
 461 };
 462
 463 static void slavio_intctl_register_devices(void)
 464 {
 465     sysbus_register_withprop(&slavio_intctl_info);
 466 }
 467
 468 device_init(slavio_intctl_register_devices)