hw/r2d.c

   1 /*
   2  * Renesas SH7751R R2D-PLUS emulation
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Copyright (c) 2008 Paul Mundt
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw.h"
  27 #include "sh.h"
  28 #include "devices.h"
  29 #include "sysemu.h"
  30 #include "boards.h"
  31 #include "pci.h"
  32 #include "sh_pci.h"
  33 #include "net.h"
  34 #include "sh7750_regs.h"
  35 #include "ide.h"
  36 #include "loader.h"
  37
  38 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
  39 #define SDRAM_SIZE 0x04000000
  40
  41 #define SM501_VRAM_SIZE 0x800000
  42
  43 /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
  44 #define LINUX_LOAD_OFFSET 0x800000
  45
  46 #define PA_IRLMSK       0x00
  47 #define PA_POWOFF       0x30
  48 #define PA_VERREG       0x32
  49 #define PA_OUTPORT      0x36
  50
  51 typedef struct {
  52     uint16_t bcr;
  53     uint16_t irlmsk;
  54     uint16_t irlmon;
  55     uint16_t cfctl;
  56     uint16_t cfpow;
  57     uint16_t dispctl;
  58     uint16_t sdmpow;
  59     uint16_t rtcce;
  60     uint16_t pcicd;
  61     uint16_t voyagerrts;
  62     uint16_t cfrst;
  63     uint16_t admrts;
  64     uint16_t extrst;
  65     uint16_t cfcdintclr;
  66     uint16_t keyctlclr;
  67     uint16_t pad0;
  68     uint16_t pad1;
  69     uint16_t verreg;
  70     uint16_t inport;
  71     uint16_t outport;
  72     uint16_t bverreg;
  73
  74 /* output pin */
  75     qemu_irq irl;
  76 } r2d_fpga_t;
  77
  78 enum r2d_fpga_irq {
  79     PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
  80     SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
  81     NR_IRQS
  82 };
  83
  84 static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
  85     [CF_IDE]    = {  1, 1<<9 },
  86     [CF_CD]     = {  2, 1<<8 },
  87     [PCI_INTA]  = {  9, 1<<14 },
  88     [PCI_INTB]  = { 10, 1<<13 },
  89     [PCI_INTC]  = {  3, 1<<12 },
  90     [PCI_INTD]  = {  0, 1<<11 },
  91     [SM501]     = {  4, 1<<10 },
  92     [KEY]       = {  5, 1<<6 },
  93     [RTC_A]     = {  6, 1<<5 },
  94     [RTC_T]     = {  7, 1<<4 },
  95     [SDCARD]    = {  8, 1<<7 },
  96     [EXT]       = { 11, 1<<0 },
  97     [TP]        = { 12, 1<<15 },
  98 };
  99
 100 static void update_irl(r2d_fpga_t *fpga)
 101 {
 102     int i, irl = 15;
 103     for (i = 0; i < NR_IRQS; i++)
 104         if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
 105             if (irqtab[i].irl < irl)
 106                 irl = irqtab[i].irl;
 107     qemu_set_irq(fpga->irl, irl ^ 15);
 108 }
 109
 110 static void r2d_fpga_irq_set(void *opaque, int n, int level)
 111 {
 112     r2d_fpga_t *fpga = opaque;
 113     if (level)
 114         fpga->irlmon |= irqtab[n].msk;
 115     else
 116         fpga->irlmon &= ~irqtab[n].msk;
 117     update_irl(fpga);
 118 }
 119
 120 static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
 121 {
 122     r2d_fpga_t *s = opaque;
 123
 124     switch (addr) {
 125     case PA_IRLMSK:
 126         return s->irlmsk;
 127     case PA_OUTPORT:
 128         return s->outport;
 129     case PA_POWOFF:
 130         return 0x00;
 131     case PA_VERREG:
 132         return 0x10;
 133     }
 134
 135     return 0;
 136 }
 137
 138 static void
 139 r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
 140 {
 141     r2d_fpga_t *s = opaque;
 142
 143     switch (addr) {
 144     case PA_IRLMSK:
 145         s->irlmsk = value;
 146         update_irl(s);
 147         break;
 148     case PA_OUTPORT:
 149         s->outport = value;
 150         break;
 151     case PA_POWOFF:
 152         if (value & 1) {
 153             qemu_system_shutdown_request();
 154         }
 155         break;
 156     case PA_VERREG:
 157         /* Discard writes */
 158         break;
 159     }
 160 }
 161
 162 static CPUReadMemoryFunc * const r2d_fpga_readfn[] = {
 163     r2d_fpga_read,
 164     r2d_fpga_read,
 165     NULL,
 166 };
 167
 168 static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = {
 169     r2d_fpga_write,
 170     r2d_fpga_write,
 171     NULL,
 172 };
 173
 174 static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
 175 {
 176     int iomemtype;
 177     r2d_fpga_t *s;
 178
 179     s = qemu_mallocz(sizeof(r2d_fpga_t));
 180
 181     s->irl = irl;
 182
 183     iomemtype = cpu_register_io_memory(r2d_fpga_readfn,
 184                                        r2d_fpga_writefn, s);
 185     cpu_register_physical_memory(base, 0x40, iomemtype);
 186     return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
 187 }
 188
 189 static void r2d_pci_set_irq(void *opaque, int n, int l)
 190 {
 191     qemu_irq *p = opaque;
 192
 193     qemu_set_irq(p[n], l);
 194 }
 195
 196 static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
 197 {
 198     const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
 199     return intx[d->devfn >> 3];
 200 }
 201
 202 static void r2d_init(ram_addr_t ram_size,
 203               const char *boot_device,
 204               const char *kernel_filename, const char *kernel_cmdline,
 205               const char *initrd_filename, const char *cpu_model)
 206 {
 207     CPUState *env;
 208     struct SH7750State *s;
 209     ram_addr_t sdram_addr;
 210     qemu_irq *irq;
 211     PCIBus *pci;
 212     DriveInfo *dinfo;
 213     int i;
 214
 215     if (!cpu_model)
 216         cpu_model = "SH7751R";
 217
 218     env = cpu_init(cpu_model);
 219     if (!env) {
 220         fprintf(stderr, "Unable to find CPU definition\n");
 221         exit(1);
 222     }
 223
 224     /* Allocate memory space */
 225     sdram_addr = qemu_ram_alloc(SDRAM_SIZE);
 226     cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
 227     /* Register peripherals */
 228     s = sh7750_init(env);
 229     irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
 230     pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
 231
 232     sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]);
 233
 234     /* onboard CF (True IDE mode, Master only). */
 235     if ((dinfo = drive_get(IF_IDE, 0, 0)) != NULL)
 236         mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
 237                       dinfo, NULL);
 238
 239     /* NIC: rtl8139 on-board, and 2 slots. */
 240     for (i = 0; i < nb_nics; i++)
 241         pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL);
 242
 243     /* Todo: register on board registers */
 244     if (kernel_filename) {
 245       int kernel_size;
 246       /* initialization which should be done by firmware */
 247       stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
 248       stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
 249
 250       if (kernel_cmdline) {
 251           kernel_size = load_image_targphys(kernel_filename,
 252                                    SDRAM_BASE + LINUX_LOAD_OFFSET,
 253                                    SDRAM_SIZE - LINUX_LOAD_OFFSET);
 254           env->pc = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000;
 255           pstrcpy_targphys("cmdline", SDRAM_BASE + 0x10100, 256, kernel_cmdline);
 256       } else {
 257           kernel_size = load_image_targphys(kernel_filename, SDRAM_BASE, SDRAM_SIZE);
 258           env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */
 259       }
 260
 261       if (kernel_size < 0) {
 262         fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
 263         exit(1);
 264       }
 265     }
 266 }
 267
 268 static QEMUMachine r2d_machine = {
 269     .name = "r2d",
 270     .desc = "r2d-plus board",
 271     .init = r2d_init,
 272 };
 273
 274 static void r2d_machine_init(void)
 275 {
 276     qemu_register_machine(&r2d_machine);
 277 }
 278
 279 machine_init(r2d_machine_init);