2 * Alpha emulation cpu translation for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
27 #include "host-utils.h"
29 #include "qemu-common.h"
35 #undef ALPHA_DEBUG_DISAS
37 #ifdef ALPHA_DEBUG_DISAS
38 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 # define LOG_DISAS(...) do { } while (0)
43 typedef struct DisasContext DisasContext
;
47 #if !defined (CONFIG_USER_ONLY)
54 /* global register indexes */
55 static TCGv_ptr cpu_env
;
56 static TCGv cpu_ir
[31];
57 static TCGv cpu_fir
[31];
62 static char cpu_reg_names
[10*4+21*5 + 10*5+21*6];
64 #include "gen-icount.h"
66 static void alpha_translate_init(void)
70 static int done_init
= 0;
75 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
78 for (i
= 0; i
< 31; i
++) {
79 sprintf(p
, "ir%d", i
);
80 cpu_ir
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
81 offsetof(CPUState
, ir
[i
]), p
);
82 p
+= (i
< 10) ? 4 : 5;
84 sprintf(p
, "fir%d", i
);
85 cpu_fir
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
86 offsetof(CPUState
, fir
[i
]), p
);
87 p
+= (i
< 10) ? 5 : 6;
90 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
,
91 offsetof(CPUState
, pc
), "pc");
93 cpu_lock
= tcg_global_mem_new_i64(TCG_AREG0
,
94 offsetof(CPUState
, lock
), "lock");
96 /* register helpers */
103 static inline void gen_excp(DisasContext
*ctx
, int exception
, int error_code
)
107 tcg_gen_movi_i64(cpu_pc
, ctx
->pc
);
108 tmp1
= tcg_const_i32(exception
);
109 tmp2
= tcg_const_i32(error_code
);
110 gen_helper_excp(tmp1
, tmp2
);
111 tcg_temp_free_i32(tmp2
);
112 tcg_temp_free_i32(tmp1
);
115 static inline void gen_invalid(DisasContext
*ctx
)
117 gen_excp(ctx
, EXCP_OPCDEC
, 0);
120 static inline void gen_qemu_ldf(TCGv t0
, TCGv t1
, int flags
)
122 TCGv tmp
= tcg_temp_new();
123 TCGv_i32 tmp32
= tcg_temp_new_i32();
124 tcg_gen_qemu_ld32u(tmp
, t1
, flags
);
125 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
126 gen_helper_memory_to_f(t0
, tmp32
);
127 tcg_temp_free_i32(tmp32
);
131 static inline void gen_qemu_ldg(TCGv t0
, TCGv t1
, int flags
)
133 TCGv tmp
= tcg_temp_new();
134 tcg_gen_qemu_ld64(tmp
, t1
, flags
);
135 gen_helper_memory_to_g(t0
, tmp
);
139 static inline void gen_qemu_lds(TCGv t0
, TCGv t1
, int flags
)
141 TCGv tmp
= tcg_temp_new();
142 TCGv_i32 tmp32
= tcg_temp_new_i32();
143 tcg_gen_qemu_ld32u(tmp
, t1
, flags
);
144 tcg_gen_trunc_i64_i32(tmp32
, tmp
);
145 gen_helper_memory_to_s(t0
, tmp32
);
146 tcg_temp_free_i32(tmp32
);
150 static inline void gen_qemu_ldl_l(TCGv t0
, TCGv t1
, int flags
)
152 tcg_gen_mov_i64(cpu_lock
, t1
);
153 tcg_gen_qemu_ld32s(t0
, t1
, flags
);
156 static inline void gen_qemu_ldq_l(TCGv t0
, TCGv t1
, int flags
)
158 tcg_gen_mov_i64(cpu_lock
, t1
);
159 tcg_gen_qemu_ld64(t0
, t1
, flags
);
162 static inline void gen_load_mem(DisasContext
*ctx
,
163 void (*tcg_gen_qemu_load
)(TCGv t0
, TCGv t1
,
165 int ra
, int rb
, int32_t disp16
, int fp
,
170 if (unlikely(ra
== 31))
173 addr
= tcg_temp_new();
175 tcg_gen_addi_i64(addr
, cpu_ir
[rb
], disp16
);
177 tcg_gen_andi_i64(addr
, addr
, ~0x7);
181 tcg_gen_movi_i64(addr
, disp16
);
184 tcg_gen_qemu_load(cpu_fir
[ra
], addr
, ctx
->mem_idx
);
186 tcg_gen_qemu_load(cpu_ir
[ra
], addr
, ctx
->mem_idx
);
190 static inline void gen_qemu_stf(TCGv t0
, TCGv t1
, int flags
)
192 TCGv_i32 tmp32
= tcg_temp_new_i32();
193 TCGv tmp
= tcg_temp_new();
194 gen_helper_f_to_memory(tmp32
, t0
);
195 tcg_gen_extu_i32_i64(tmp
, tmp32
);
196 tcg_gen_qemu_st32(tmp
, t1
, flags
);
198 tcg_temp_free_i32(tmp32
);
201 static inline void gen_qemu_stg(TCGv t0
, TCGv t1
, int flags
)
203 TCGv tmp
= tcg_temp_new();
204 gen_helper_g_to_memory(tmp
, t0
);
205 tcg_gen_qemu_st64(tmp
, t1
, flags
);
209 static inline void gen_qemu_sts(TCGv t0
, TCGv t1
, int flags
)
211 TCGv_i32 tmp32
= tcg_temp_new_i32();
212 TCGv tmp
= tcg_temp_new();
213 gen_helper_s_to_memory(tmp32
, t0
);
214 tcg_gen_extu_i32_i64(tmp
, tmp32
);
215 tcg_gen_qemu_st32(tmp
, t1
, flags
);
217 tcg_temp_free_i32(tmp32
);
220 static inline void gen_qemu_stl_c(TCGv t0
, TCGv t1
, int flags
)
224 l1
= gen_new_label();
225 l2
= gen_new_label();
226 tcg_gen_brcond_i64(TCG_COND_NE
, cpu_lock
, t1
, l1
);
227 tcg_gen_qemu_st32(t0
, t1
, flags
);
228 tcg_gen_movi_i64(t0
, 1);
231 tcg_gen_movi_i64(t0
, 0);
233 tcg_gen_movi_i64(cpu_lock
, -1);
236 static inline void gen_qemu_stq_c(TCGv t0
, TCGv t1
, int flags
)
240 l1
= gen_new_label();
241 l2
= gen_new_label();
242 tcg_gen_brcond_i64(TCG_COND_NE
, cpu_lock
, t1
, l1
);
243 tcg_gen_qemu_st64(t0
, t1
, flags
);
244 tcg_gen_movi_i64(t0
, 1);
247 tcg_gen_movi_i64(t0
, 0);
249 tcg_gen_movi_i64(cpu_lock
, -1);
252 static inline void gen_store_mem(DisasContext
*ctx
,
253 void (*tcg_gen_qemu_store
)(TCGv t0
, TCGv t1
,
255 int ra
, int rb
, int32_t disp16
, int fp
,
256 int clear
, int local
)
260 addr
= tcg_temp_local_new();
262 addr
= tcg_temp_new();
264 tcg_gen_addi_i64(addr
, cpu_ir
[rb
], disp16
);
266 tcg_gen_andi_i64(addr
, addr
, ~0x7);
270 tcg_gen_movi_i64(addr
, disp16
);
274 tcg_gen_qemu_store(cpu_fir
[ra
], addr
, ctx
->mem_idx
);
276 tcg_gen_qemu_store(cpu_ir
[ra
], addr
, ctx
->mem_idx
);
280 zero
= tcg_const_local_i64(0);
282 zero
= tcg_const_i64(0);
283 tcg_gen_qemu_store(zero
, addr
, ctx
->mem_idx
);
289 static inline void gen_bcond(DisasContext
*ctx
, TCGCond cond
, int ra
,
290 int32_t disp
, int mask
)
294 l1
= gen_new_label();
295 l2
= gen_new_label();
296 if (likely(ra
!= 31)) {
298 TCGv tmp
= tcg_temp_new();
299 tcg_gen_andi_i64(tmp
, cpu_ir
[ra
], 1);
300 tcg_gen_brcondi_i64(cond
, tmp
, 0, l1
);
303 tcg_gen_brcondi_i64(cond
, cpu_ir
[ra
], 0, l1
);
305 /* Very uncommon case - Do not bother to optimize. */
306 TCGv tmp
= tcg_const_i64(0);
307 tcg_gen_brcondi_i64(cond
, tmp
, 0, l1
);
310 tcg_gen_movi_i64(cpu_pc
, ctx
->pc
);
313 tcg_gen_movi_i64(cpu_pc
, ctx
->pc
+ (int64_t)(disp
<< 2));
317 static inline void gen_fbcond(DisasContext
*ctx
, int opc
, int ra
, int32_t disp
)
323 l1
= gen_new_label();
324 l2
= gen_new_label();
326 tmp
= tcg_temp_new();
329 tmp
= tcg_const_i64(0);
333 case 0x31: /* FBEQ */
334 gen_helper_cmpfeq(tmp
, src
);
336 case 0x32: /* FBLT */
337 gen_helper_cmpflt(tmp
, src
);
339 case 0x33: /* FBLE */
340 gen_helper_cmpfle(tmp
, src
);
342 case 0x35: /* FBNE */
343 gen_helper_cmpfne(tmp
, src
);
345 case 0x36: /* FBGE */
346 gen_helper_cmpfge(tmp
, src
);
348 case 0x37: /* FBGT */
349 gen_helper_cmpfgt(tmp
, src
);
354 tcg_gen_brcondi_i64(TCG_COND_NE
, tmp
, 0, l1
);
355 tcg_gen_movi_i64(cpu_pc
, ctx
->pc
);
358 tcg_gen_movi_i64(cpu_pc
, ctx
->pc
+ (int64_t)(disp
<< 2));
362 static inline void gen_cmov(TCGCond inv_cond
, int ra
, int rb
, int rc
,
363 int islit
, uint8_t lit
, int mask
)
367 if (unlikely(rc
== 31))
370 l1
= gen_new_label();
374 TCGv tmp
= tcg_temp_new();
375 tcg_gen_andi_i64(tmp
, cpu_ir
[ra
], 1);
376 tcg_gen_brcondi_i64(inv_cond
, tmp
, 0, l1
);
379 tcg_gen_brcondi_i64(inv_cond
, cpu_ir
[ra
], 0, l1
);
381 /* Very uncommon case - Do not bother to optimize. */
382 TCGv tmp
= tcg_const_i64(0);
383 tcg_gen_brcondi_i64(inv_cond
, tmp
, 0, l1
);
388 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
390 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
394 #define FARITH2(name) \
395 static inline void glue(gen_f, name)(int rb, int rc) \
397 if (unlikely(rc == 31)) \
401 gen_helper_ ## name (cpu_fir[rc], cpu_fir[rb]); \
403 TCGv tmp = tcg_const_i64(0); \
404 gen_helper_ ## name (cpu_fir[rc], tmp); \
405 tcg_temp_free(tmp); \
426 #define FARITH3(name) \
427 static inline void glue(gen_f, name)(int ra, int rb, int rc) \
429 if (unlikely(rc == 31)) \
434 gen_helper_ ## name (cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]); \
436 TCGv tmp = tcg_const_i64(0); \
437 gen_helper_ ## name (cpu_fir[rc], cpu_fir[ra], tmp); \
438 tcg_temp_free(tmp); \
441 TCGv tmp = tcg_const_i64(0); \
443 gen_helper_ ## name (cpu_fir[rc], tmp, cpu_fir[rb]); \
445 gen_helper_ ## name (cpu_fir[rc], tmp, tmp); \
446 tcg_temp_free(tmp); \
477 #define FCMOV(name) \
478 static inline void glue(gen_f, name)(int ra, int rb, int rc) \
483 if (unlikely(rc == 31)) \
486 l1 = gen_new_label(); \
487 tmp = tcg_temp_new(); \
489 tmp = tcg_temp_new(); \
490 gen_helper_ ## name (tmp, cpu_fir[ra]); \
492 tmp = tcg_const_i64(0); \
493 gen_helper_ ## name (tmp, tmp); \
495 tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1); \
497 tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); \
499 tcg_gen_movi_i64(cpu_fir[rc], 0); \
509 /* Implement zapnot with an immediate operand, which expands to some
510 form of immediate AND. This is a basic building block in the
511 definition of many of the other byte manipulation instructions. */
512 static inline void gen_zapnoti(int ra
, int rc
, uint8_t lit
)
519 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
522 tcg_gen_ext8u_i64(cpu_ir
[rc
], cpu_ir
[ra
]);
525 tcg_gen_ext16u_i64(cpu_ir
[rc
], cpu_ir
[ra
]);
528 tcg_gen_ext32u_i64(cpu_ir
[rc
], cpu_ir
[ra
]);
531 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[ra
]);
534 for (mask
= i
= 0; i
< 8; ++i
) {
536 mask
|= 0xffull
<< (i
* 8);
538 tcg_gen_andi_i64 (cpu_ir
[rc
], cpu_ir
[ra
], mask
);
543 static inline void gen_zapnot(int ra
, int rb
, int rc
, int islit
, uint8_t lit
)
545 if (unlikely(rc
== 31))
547 else if (unlikely(ra
== 31))
548 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
550 gen_zapnoti(ra
, rc
, lit
);
552 gen_helper_zapnot (cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
555 static inline void gen_zap(int ra
, int rb
, int rc
, int islit
, uint8_t lit
)
557 if (unlikely(rc
== 31))
559 else if (unlikely(ra
== 31))
560 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
562 gen_zapnoti(ra
, rc
, ~lit
);
564 gen_helper_zap (cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
568 /* EXTWH, EXTWH, EXTLH, EXTQH */
569 static inline void gen_ext_h(int ra
, int rb
, int rc
, int islit
,
570 uint8_t lit
, uint8_t byte_mask
)
572 if (unlikely(rc
== 31))
574 else if (unlikely(ra
== 31))
575 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
578 lit
= (64 - (lit
& 7) * 8) & 0x3f;
579 tcg_gen_shli_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
581 TCGv tmp1
= tcg_temp_new();
582 tcg_gen_andi_i64(tmp1
, cpu_ir
[rb
], 7);
583 tcg_gen_shli_i64(tmp1
, tmp1
, 3);
584 tcg_gen_neg_i64(tmp1
, tmp1
);
585 tcg_gen_andi_i64(tmp1
, tmp1
, 0x3f);
586 tcg_gen_shl_i64(cpu_ir
[rc
], cpu_ir
[ra
], tmp1
);
589 gen_zapnoti(rc
, rc
, byte_mask
);
593 /* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */
594 static inline void gen_ext_l(int ra
, int rb
, int rc
, int islit
,
595 uint8_t lit
, uint8_t byte_mask
)
597 if (unlikely(rc
== 31))
599 else if (unlikely(ra
== 31))
600 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
603 tcg_gen_shri_i64(cpu_ir
[rc
], cpu_ir
[ra
], (lit
& 7) * 8);
605 TCGv tmp
= tcg_temp_new();
606 tcg_gen_andi_i64(tmp
, cpu_ir
[rb
], 7);
607 tcg_gen_shli_i64(tmp
, tmp
, 3);
608 tcg_gen_shr_i64(cpu_ir
[rc
], cpu_ir
[ra
], tmp
);
611 gen_zapnoti(rc
, rc
, byte_mask
);
615 /* Code to call arith3 helpers */
616 #define ARITH3(name) \
617 static inline void glue(gen_, name)(int ra, int rb, int rc, int islit,\
620 if (unlikely(rc == 31)) \
625 TCGv tmp = tcg_const_i64(lit); \
626 gen_helper_ ## name(cpu_ir[rc], cpu_ir[ra], tmp); \
627 tcg_temp_free(tmp); \
629 gen_helper_ ## name (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); \
631 TCGv tmp1 = tcg_const_i64(0); \
633 TCGv tmp2 = tcg_const_i64(lit); \
634 gen_helper_ ## name (cpu_ir[rc], tmp1, tmp2); \
635 tcg_temp_free(tmp2); \
637 gen_helper_ ## name (cpu_ir[rc], tmp1, cpu_ir[rb]); \
638 tcg_temp_free(tmp1); \
673 #define MVIOP2(name) \
674 static inline void glue(gen_, name)(int rb, int rc) \
676 if (unlikely(rc == 31)) \
678 if (unlikely(rb == 31)) \
679 tcg_gen_movi_i64(cpu_ir[rc], 0); \
681 gen_helper_ ## name (cpu_ir[rc], cpu_ir[rb]); \
688 static inline void gen_cmp(TCGCond cond
, int ra
, int rb
, int rc
, int islit
,
694 if (unlikely(rc
== 31))
697 l1
= gen_new_label();
698 l2
= gen_new_label();
701 tmp
= tcg_temp_new();
702 tcg_gen_mov_i64(tmp
, cpu_ir
[ra
]);
704 tmp
= tcg_const_i64(0);
706 tcg_gen_brcondi_i64(cond
, tmp
, lit
, l1
);
708 tcg_gen_brcond_i64(cond
, tmp
, cpu_ir
[rb
], l1
);
710 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
713 tcg_gen_movi_i64(cpu_ir
[rc
], 1);
717 static inline int translate_one(DisasContext
*ctx
, uint32_t insn
)
720 int32_t disp21
, disp16
, disp12
;
722 uint8_t opc
, ra
, rb
, rc
, sbz
, fpfn
, fn7
, fn2
, islit
, real_islit
;
726 /* Decode all instruction fields */
728 ra
= (insn
>> 21) & 0x1F;
729 rb
= (insn
>> 16) & 0x1F;
731 sbz
= (insn
>> 13) & 0x07;
732 real_islit
= islit
= (insn
>> 12) & 1;
733 if (rb
== 31 && !islit
) {
737 lit
= (insn
>> 13) & 0xFF;
738 palcode
= insn
& 0x03FFFFFF;
739 disp21
= ((int32_t)((insn
& 0x001FFFFF) << 11)) >> 11;
740 disp16
= (int16_t)(insn
& 0x0000FFFF);
741 disp12
= (int32_t)((insn
& 0x00000FFF) << 20) >> 20;
742 fn16
= insn
& 0x0000FFFF;
743 fn11
= (insn
>> 5) & 0x000007FF;
745 fn7
= (insn
>> 5) & 0x0000007F;
746 fn2
= (insn
>> 5) & 0x00000003;
748 LOG_DISAS("opc %02x ra %2d rb %2d rc %2d disp16 %6d\n",
749 opc
, ra
, rb
, rc
, disp16
);
754 if (palcode
>= 0x80 && palcode
< 0xC0) {
755 /* Unprivileged PAL call */
756 gen_excp(ctx
, EXCP_CALL_PAL
+ ((palcode
& 0x3F) << 6), 0);
757 #if !defined (CONFIG_USER_ONLY)
758 } else if (palcode
< 0x40) {
759 /* Privileged PAL code */
760 if (ctx
->mem_idx
& 1)
763 gen_excp(ctx
, EXCP_CALL_PALP
+ ((palcode
& 0x3F) << 6), 0);
766 /* Invalid PAL call */
794 if (likely(ra
!= 31)) {
796 tcg_gen_addi_i64(cpu_ir
[ra
], cpu_ir
[rb
], disp16
);
798 tcg_gen_movi_i64(cpu_ir
[ra
], disp16
);
803 if (likely(ra
!= 31)) {
805 tcg_gen_addi_i64(cpu_ir
[ra
], cpu_ir
[rb
], disp16
<< 16);
807 tcg_gen_movi_i64(cpu_ir
[ra
], disp16
<< 16);
812 if (!(ctx
->amask
& AMASK_BWX
))
814 gen_load_mem(ctx
, &tcg_gen_qemu_ld8u
, ra
, rb
, disp16
, 0, 0);
818 gen_load_mem(ctx
, &tcg_gen_qemu_ld64
, ra
, rb
, disp16
, 0, 1);
822 if (!(ctx
->amask
& AMASK_BWX
))
824 gen_load_mem(ctx
, &tcg_gen_qemu_ld16u
, ra
, rb
, disp16
, 0, 0);
828 gen_store_mem(ctx
, &tcg_gen_qemu_st16
, ra
, rb
, disp16
, 0, 0, 0);
832 gen_store_mem(ctx
, &tcg_gen_qemu_st8
, ra
, rb
, disp16
, 0, 0, 0);
836 gen_store_mem(ctx
, &tcg_gen_qemu_st64
, ra
, rb
, disp16
, 0, 1, 0);
842 if (likely(rc
!= 31)) {
845 tcg_gen_addi_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
846 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
848 tcg_gen_add_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
849 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
853 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
855 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
861 if (likely(rc
!= 31)) {
863 TCGv tmp
= tcg_temp_new();
864 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 2);
866 tcg_gen_addi_i64(tmp
, tmp
, lit
);
868 tcg_gen_add_i64(tmp
, tmp
, cpu_ir
[rb
]);
869 tcg_gen_ext32s_i64(cpu_ir
[rc
], tmp
);
873 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
875 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
881 if (likely(rc
!= 31)) {
884 tcg_gen_subi_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
886 tcg_gen_sub_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
887 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
890 tcg_gen_movi_i64(cpu_ir
[rc
], -lit
);
892 tcg_gen_neg_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
893 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
899 if (likely(rc
!= 31)) {
901 TCGv tmp
= tcg_temp_new();
902 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 2);
904 tcg_gen_subi_i64(tmp
, tmp
, lit
);
906 tcg_gen_sub_i64(tmp
, tmp
, cpu_ir
[rb
]);
907 tcg_gen_ext32s_i64(cpu_ir
[rc
], tmp
);
911 tcg_gen_movi_i64(cpu_ir
[rc
], -lit
);
913 tcg_gen_neg_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
914 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
921 gen_cmpbge(ra
, rb
, rc
, islit
, lit
);
925 if (likely(rc
!= 31)) {
927 TCGv tmp
= tcg_temp_new();
928 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 3);
930 tcg_gen_addi_i64(tmp
, tmp
, lit
);
932 tcg_gen_add_i64(tmp
, tmp
, cpu_ir
[rb
]);
933 tcg_gen_ext32s_i64(cpu_ir
[rc
], tmp
);
937 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
939 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
945 if (likely(rc
!= 31)) {
947 TCGv tmp
= tcg_temp_new();
948 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 3);
950 tcg_gen_subi_i64(tmp
, tmp
, lit
);
952 tcg_gen_sub_i64(tmp
, tmp
, cpu_ir
[rb
]);
953 tcg_gen_ext32s_i64(cpu_ir
[rc
], tmp
);
957 tcg_gen_movi_i64(cpu_ir
[rc
], -lit
);
959 tcg_gen_neg_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
960 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
967 gen_cmp(TCG_COND_LTU
, ra
, rb
, rc
, islit
, lit
);
971 if (likely(rc
!= 31)) {
974 tcg_gen_addi_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
976 tcg_gen_add_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
979 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
981 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
987 if (likely(rc
!= 31)) {
989 TCGv tmp
= tcg_temp_new();
990 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 2);
992 tcg_gen_addi_i64(cpu_ir
[rc
], tmp
, lit
);
994 tcg_gen_add_i64(cpu_ir
[rc
], tmp
, cpu_ir
[rb
]);
998 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
1000 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1006 if (likely(rc
!= 31)) {
1009 tcg_gen_subi_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
1011 tcg_gen_sub_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
1014 tcg_gen_movi_i64(cpu_ir
[rc
], -lit
);
1016 tcg_gen_neg_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1022 if (likely(rc
!= 31)) {
1024 TCGv tmp
= tcg_temp_new();
1025 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 2);
1027 tcg_gen_subi_i64(cpu_ir
[rc
], tmp
, lit
);
1029 tcg_gen_sub_i64(cpu_ir
[rc
], tmp
, cpu_ir
[rb
]);
1033 tcg_gen_movi_i64(cpu_ir
[rc
], -lit
);
1035 tcg_gen_neg_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1041 gen_cmp(TCG_COND_EQ
, ra
, rb
, rc
, islit
, lit
);
1045 if (likely(rc
!= 31)) {
1047 TCGv tmp
= tcg_temp_new();
1048 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 3);
1050 tcg_gen_addi_i64(cpu_ir
[rc
], tmp
, lit
);
1052 tcg_gen_add_i64(cpu_ir
[rc
], tmp
, cpu_ir
[rb
]);
1056 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
1058 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1064 if (likely(rc
!= 31)) {
1066 TCGv tmp
= tcg_temp_new();
1067 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 3);
1069 tcg_gen_subi_i64(cpu_ir
[rc
], tmp
, lit
);
1071 tcg_gen_sub_i64(cpu_ir
[rc
], tmp
, cpu_ir
[rb
]);
1075 tcg_gen_movi_i64(cpu_ir
[rc
], -lit
);
1077 tcg_gen_neg_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1083 gen_cmp(TCG_COND_LEU
, ra
, rb
, rc
, islit
, lit
);
1087 gen_addlv(ra
, rb
, rc
, islit
, lit
);
1091 gen_sublv(ra
, rb
, rc
, islit
, lit
);
1095 gen_cmp(TCG_COND_LT
, ra
, rb
, rc
, islit
, lit
);
1099 gen_addqv(ra
, rb
, rc
, islit
, lit
);
1103 gen_subqv(ra
, rb
, rc
, islit
, lit
);
1107 gen_cmp(TCG_COND_LE
, ra
, rb
, rc
, islit
, lit
);
1117 if (likely(rc
!= 31)) {
1119 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
1121 tcg_gen_andi_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
1123 tcg_gen_and_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
1128 if (likely(rc
!= 31)) {
1131 tcg_gen_andi_i64(cpu_ir
[rc
], cpu_ir
[ra
], ~lit
);
1133 tcg_gen_andc_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
1135 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
1140 gen_cmov(TCG_COND_EQ
, ra
, rb
, rc
, islit
, lit
, 1);
1144 gen_cmov(TCG_COND_NE
, ra
, rb
, rc
, islit
, lit
, 1);
1148 if (likely(rc
!= 31)) {
1151 tcg_gen_ori_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
1153 tcg_gen_or_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
1156 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
1158 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1164 gen_cmov(TCG_COND_NE
, ra
, rb
, rc
, islit
, lit
, 0);
1168 gen_cmov(TCG_COND_EQ
, ra
, rb
, rc
, islit
, lit
, 0);
1172 if (likely(rc
!= 31)) {
1175 tcg_gen_ori_i64(cpu_ir
[rc
], cpu_ir
[ra
], ~lit
);
1177 tcg_gen_orc_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
1180 tcg_gen_movi_i64(cpu_ir
[rc
], ~lit
);
1182 tcg_gen_not_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1188 if (likely(rc
!= 31)) {
1191 tcg_gen_xori_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
1193 tcg_gen_xor_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
1196 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
1198 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1204 gen_cmov(TCG_COND_GE
, ra
, rb
, rc
, islit
, lit
, 0);
1208 gen_cmov(TCG_COND_LT
, ra
, rb
, rc
, islit
, lit
, 0);
1212 if (likely(rc
!= 31)) {
1215 tcg_gen_xori_i64(cpu_ir
[rc
], cpu_ir
[ra
], ~lit
);
1217 tcg_gen_eqv_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
1220 tcg_gen_movi_i64(cpu_ir
[rc
], ~lit
);
1222 tcg_gen_not_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1228 if (likely(rc
!= 31)) {
1230 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
1232 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1233 switch (ctx
->env
->implver
) {
1235 /* EV4, EV45, LCA, LCA45 & EV5 */
1240 tcg_gen_andi_i64(cpu_ir
[rc
], cpu_ir
[rc
],
1241 ~(uint64_t)ctx
->amask
);
1248 gen_cmov(TCG_COND_GT
, ra
, rb
, rc
, islit
, lit
, 0);
1252 gen_cmov(TCG_COND_LE
, ra
, rb
, rc
, islit
, lit
, 0);
1257 tcg_gen_movi_i64(cpu_ir
[rc
], ctx
->env
->implver
);
1267 gen_mskbl(ra
, rb
, rc
, islit
, lit
);
1271 gen_ext_l(ra
, rb
, rc
, islit
, lit
, 0x01);
1275 gen_insbl(ra
, rb
, rc
, islit
, lit
);
1279 gen_mskwl(ra
, rb
, rc
, islit
, lit
);
1283 gen_ext_l(ra
, rb
, rc
, islit
, lit
, 0x03);
1287 gen_inswl(ra
, rb
, rc
, islit
, lit
);
1291 gen_mskll(ra
, rb
, rc
, islit
, lit
);
1295 gen_ext_l(ra
, rb
, rc
, islit
, lit
, 0x0f);
1299 gen_insll(ra
, rb
, rc
, islit
, lit
);
1303 gen_zap(ra
, rb
, rc
, islit
, lit
);
1307 gen_zapnot(ra
, rb
, rc
, islit
, lit
);
1311 gen_mskql(ra
, rb
, rc
, islit
, lit
);
1315 if (likely(rc
!= 31)) {
1318 tcg_gen_shri_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
& 0x3f);
1320 TCGv shift
= tcg_temp_new();
1321 tcg_gen_andi_i64(shift
, cpu_ir
[rb
], 0x3f);
1322 tcg_gen_shr_i64(cpu_ir
[rc
], cpu_ir
[ra
], shift
);
1323 tcg_temp_free(shift
);
1326 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
1331 gen_ext_l(ra
, rb
, rc
, islit
, lit
, 0xff);
1335 if (likely(rc
!= 31)) {
1338 tcg_gen_shli_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
& 0x3f);
1340 TCGv shift
= tcg_temp_new();
1341 tcg_gen_andi_i64(shift
, cpu_ir
[rb
], 0x3f);
1342 tcg_gen_shl_i64(cpu_ir
[rc
], cpu_ir
[ra
], shift
);
1343 tcg_temp_free(shift
);
1346 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
1351 gen_insql(ra
, rb
, rc
, islit
, lit
);
1355 if (likely(rc
!= 31)) {
1358 tcg_gen_sari_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
& 0x3f);
1360 TCGv shift
= tcg_temp_new();
1361 tcg_gen_andi_i64(shift
, cpu_ir
[rb
], 0x3f);
1362 tcg_gen_sar_i64(cpu_ir
[rc
], cpu_ir
[ra
], shift
);
1363 tcg_temp_free(shift
);
1366 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
1371 gen_mskwh(ra
, rb
, rc
, islit
, lit
);
1375 gen_inswh(ra
, rb
, rc
, islit
, lit
);
1379 gen_ext_h(ra
, rb
, rc
, islit
, lit
, 0x03);
1383 gen_msklh(ra
, rb
, rc
, islit
, lit
);
1387 gen_inslh(ra
, rb
, rc
, islit
, lit
);
1391 gen_ext_h(ra
, rb
, rc
, islit
, lit
, 0x0f);
1395 gen_mskqh(ra
, rb
, rc
, islit
, lit
);
1399 gen_insqh(ra
, rb
, rc
, islit
, lit
);
1403 gen_ext_h(ra
, rb
, rc
, islit
, lit
, 0xff);
1413 if (likely(rc
!= 31)) {
1415 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
1418 tcg_gen_muli_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
1420 tcg_gen_mul_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
1421 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
1427 if (likely(rc
!= 31)) {
1429 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
1431 tcg_gen_muli_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
1433 tcg_gen_mul_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
1438 gen_umulh(ra
, rb
, rc
, islit
, lit
);
1442 gen_mullv(ra
, rb
, rc
, islit
, lit
);
1446 gen_mulqv(ra
, rb
, rc
, islit
, lit
);
1453 switch (fpfn
) { /* f11 & 0x3F */
1456 if (!(ctx
->amask
& AMASK_FIX
))
1458 if (likely(rc
!= 31)) {
1460 TCGv_i32 tmp
= tcg_temp_new_i32();
1461 tcg_gen_trunc_i64_i32(tmp
, cpu_ir
[ra
]);
1462 gen_helper_memory_to_s(cpu_fir
[rc
], tmp
);
1463 tcg_temp_free_i32(tmp
);
1465 tcg_gen_movi_i64(cpu_fir
[rc
], 0);
1470 if (!(ctx
->amask
& AMASK_FIX
))
1476 if (!(ctx
->amask
& AMASK_FIX
))
1482 if (!(ctx
->amask
& AMASK_FIX
))
1484 if (likely(rc
!= 31)) {
1486 TCGv_i32 tmp
= tcg_temp_new_i32();
1487 tcg_gen_trunc_i64_i32(tmp
, cpu_ir
[ra
]);
1488 gen_helper_memory_to_f(cpu_fir
[rc
], tmp
);
1489 tcg_temp_free_i32(tmp
);
1491 tcg_gen_movi_i64(cpu_fir
[rc
], 0);
1496 if (!(ctx
->amask
& AMASK_FIX
))
1498 if (likely(rc
!= 31)) {
1500 tcg_gen_mov_i64(cpu_fir
[rc
], cpu_ir
[ra
]);
1502 tcg_gen_movi_i64(cpu_fir
[rc
], 0);
1507 if (!(ctx
->amask
& AMASK_FIX
))
1513 if (!(ctx
->amask
& AMASK_FIX
))
1522 /* VAX floating point */
1523 /* XXX: rounding mode and trap are ignored (!) */
1524 switch (fpfn
) { /* f11 & 0x3F */
1527 gen_faddf(ra
, rb
, rc
);
1531 gen_fsubf(ra
, rb
, rc
);
1535 gen_fmulf(ra
, rb
, rc
);
1539 gen_fdivf(ra
, rb
, rc
);
1551 gen_faddg(ra
, rb
, rc
);
1555 gen_fsubg(ra
, rb
, rc
);
1559 gen_fmulg(ra
, rb
, rc
);
1563 gen_fdivg(ra
, rb
, rc
);
1567 gen_fcmpgeq(ra
, rb
, rc
);
1571 gen_fcmpglt(ra
, rb
, rc
);
1575 gen_fcmpgle(ra
, rb
, rc
);
1606 /* IEEE floating-point */
1607 /* XXX: rounding mode and traps are ignored (!) */
1608 switch (fpfn
) { /* f11 & 0x3F */
1611 gen_fadds(ra
, rb
, rc
);
1615 gen_fsubs(ra
, rb
, rc
);
1619 gen_fmuls(ra
, rb
, rc
);
1623 gen_fdivs(ra
, rb
, rc
);
1627 gen_faddt(ra
, rb
, rc
);
1631 gen_fsubt(ra
, rb
, rc
);
1635 gen_fmult(ra
, rb
, rc
);
1639 gen_fdivt(ra
, rb
, rc
);
1643 gen_fcmptun(ra
, rb
, rc
);
1647 gen_fcmpteq(ra
, rb
, rc
);
1651 gen_fcmptlt(ra
, rb
, rc
);
1655 gen_fcmptle(ra
, rb
, rc
);
1658 /* XXX: incorrect */
1659 if (fn11
== 0x2AC || fn11
== 0x6AC) {
1690 if (likely(rc
!= 31)) {
1693 tcg_gen_mov_i64(cpu_fir
[rc
], cpu_fir
[ra
]);
1696 gen_fcpys(ra
, rb
, rc
);
1701 gen_fcpysn(ra
, rb
, rc
);
1705 gen_fcpyse(ra
, rb
, rc
);
1709 if (likely(ra
!= 31))
1710 gen_helper_store_fpcr(cpu_fir
[ra
]);
1712 TCGv tmp
= tcg_const_i64(0);
1713 gen_helper_store_fpcr(tmp
);
1719 if (likely(ra
!= 31))
1720 gen_helper_load_fpcr(cpu_fir
[ra
]);
1724 gen_fcmpfeq(ra
, rb
, rc
);
1728 gen_fcmpfne(ra
, rb
, rc
);
1732 gen_fcmpflt(ra
, rb
, rc
);
1736 gen_fcmpfge(ra
, rb
, rc
);
1740 gen_fcmpfle(ra
, rb
, rc
);
1744 gen_fcmpfgt(ra
, rb
, rc
);
1752 gen_fcvtqlv(rb
, rc
);
1756 gen_fcvtqlsv(rb
, rc
);
1763 switch ((uint16_t)disp16
) {
1766 /* No-op. Just exit from the current tb */
1771 /* No-op. Just exit from the current tb */
1793 gen_helper_load_pcc(cpu_ir
[ra
]);
1798 gen_helper_rc(cpu_ir
[ra
]);
1806 gen_helper_rs(cpu_ir
[ra
]);
1817 /* HW_MFPR (PALcode) */
1818 #if defined (CONFIG_USER_ONLY)
1824 TCGv tmp
= tcg_const_i32(insn
& 0xFF);
1825 gen_helper_mfpr(cpu_ir
[ra
], tmp
, cpu_ir
[ra
]);
1832 tcg_gen_andi_i64(cpu_pc
, cpu_ir
[rb
], ~3);
1834 tcg_gen_movi_i64(cpu_pc
, 0);
1836 tcg_gen_movi_i64(cpu_ir
[ra
], ctx
->pc
);
1837 /* Those four jumps only differ by the branch prediction hint */
1855 /* HW_LD (PALcode) */
1856 #if defined (CONFIG_USER_ONLY)
1862 TCGv addr
= tcg_temp_new();
1864 tcg_gen_addi_i64(addr
, cpu_ir
[rb
], disp12
);
1866 tcg_gen_movi_i64(addr
, disp12
);
1867 switch ((insn
>> 12) & 0xF) {
1869 /* Longword physical access (hw_ldl/p) */
1870 gen_helper_ldl_raw(cpu_ir
[ra
], addr
);
1873 /* Quadword physical access (hw_ldq/p) */
1874 gen_helper_ldq_raw(cpu_ir
[ra
], addr
);
1877 /* Longword physical access with lock (hw_ldl_l/p) */
1878 gen_helper_ldl_l_raw(cpu_ir
[ra
], addr
);
1881 /* Quadword physical access with lock (hw_ldq_l/p) */
1882 gen_helper_ldq_l_raw(cpu_ir
[ra
], addr
);
1885 /* Longword virtual PTE fetch (hw_ldl/v) */
1886 tcg_gen_qemu_ld32s(cpu_ir
[ra
], addr
, 0);
1889 /* Quadword virtual PTE fetch (hw_ldq/v) */
1890 tcg_gen_qemu_ld64(cpu_ir
[ra
], addr
, 0);
1893 /* Incpu_ir[ra]id */
1896 /* Incpu_ir[ra]id */
1899 /* Longword virtual access (hw_ldl) */
1900 gen_helper_st_virt_to_phys(addr
, addr
);
1901 gen_helper_ldl_raw(cpu_ir
[ra
], addr
);
1904 /* Quadword virtual access (hw_ldq) */
1905 gen_helper_st_virt_to_phys(addr
, addr
);
1906 gen_helper_ldq_raw(cpu_ir
[ra
], addr
);
1909 /* Longword virtual access with protection check (hw_ldl/w) */
1910 tcg_gen_qemu_ld32s(cpu_ir
[ra
], addr
, 0);
1913 /* Quadword virtual access with protection check (hw_ldq/w) */
1914 tcg_gen_qemu_ld64(cpu_ir
[ra
], addr
, 0);
1917 /* Longword virtual access with alt access mode (hw_ldl/a)*/
1918 gen_helper_set_alt_mode();
1919 gen_helper_st_virt_to_phys(addr
, addr
);
1920 gen_helper_ldl_raw(cpu_ir
[ra
], addr
);
1921 gen_helper_restore_mode();
1924 /* Quadword virtual access with alt access mode (hw_ldq/a) */
1925 gen_helper_set_alt_mode();
1926 gen_helper_st_virt_to_phys(addr
, addr
);
1927 gen_helper_ldq_raw(cpu_ir
[ra
], addr
);
1928 gen_helper_restore_mode();
1931 /* Longword virtual access with alternate access mode and
1932 * protection checks (hw_ldl/wa)
1934 gen_helper_set_alt_mode();
1935 gen_helper_ldl_data(cpu_ir
[ra
], addr
);
1936 gen_helper_restore_mode();
1939 /* Quadword virtual access with alternate access mode and
1940 * protection checks (hw_ldq/wa)
1942 gen_helper_set_alt_mode();
1943 gen_helper_ldq_data(cpu_ir
[ra
], addr
);
1944 gen_helper_restore_mode();
1947 tcg_temp_free(addr
);
1955 if (!(ctx
->amask
& AMASK_BWX
))
1957 if (likely(rc
!= 31)) {
1959 tcg_gen_movi_i64(cpu_ir
[rc
], (int64_t)((int8_t)lit
));
1961 tcg_gen_ext8s_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1966 if (!(ctx
->amask
& AMASK_BWX
))
1968 if (likely(rc
!= 31)) {
1970 tcg_gen_movi_i64(cpu_ir
[rc
], (int64_t)((int16_t)lit
));
1972 tcg_gen_ext16s_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1977 if (!(ctx
->amask
& AMASK_CIX
))
1979 if (likely(rc
!= 31)) {
1981 tcg_gen_movi_i64(cpu_ir
[rc
], ctpop64(lit
));
1983 gen_helper_ctpop(cpu_ir
[rc
], cpu_ir
[rb
]);
1988 if (!(ctx
->amask
& AMASK_MVI
))
1990 gen_perr(ra
, rb
, rc
, islit
, lit
);
1994 if (!(ctx
->amask
& AMASK_CIX
))
1996 if (likely(rc
!= 31)) {
1998 tcg_gen_movi_i64(cpu_ir
[rc
], clz64(lit
));
2000 gen_helper_ctlz(cpu_ir
[rc
], cpu_ir
[rb
]);
2005 if (!(ctx
->amask
& AMASK_CIX
))
2007 if (likely(rc
!= 31)) {
2009 tcg_gen_movi_i64(cpu_ir
[rc
], ctz64(lit
));
2011 gen_helper_cttz(cpu_ir
[rc
], cpu_ir
[rb
]);
2016 if (!(ctx
->amask
& AMASK_MVI
))
2018 if (real_islit
|| ra
!= 31)
2020 gen_unpkbw (rb
, rc
);
2024 if (!(ctx
->amask
& AMASK_MVI
))
2026 if (real_islit
|| ra
!= 31)
2028 gen_unpkbl (rb
, rc
);
2032 if (!(ctx
->amask
& AMASK_MVI
))
2034 if (real_islit
|| ra
!= 31)
2040 if (!(ctx
->amask
& AMASK_MVI
))
2042 if (real_islit
|| ra
!= 31)
2048 if (!(ctx
->amask
& AMASK_MVI
))
2050 gen_minsb8 (ra
, rb
, rc
, islit
, lit
);
2054 if (!(ctx
->amask
& AMASK_MVI
))
2056 gen_minsw4 (ra
, rb
, rc
, islit
, lit
);
2060 if (!(ctx
->amask
& AMASK_MVI
))
2062 gen_minub8 (ra
, rb
, rc
, islit
, lit
);
2066 if (!(ctx
->amask
& AMASK_MVI
))
2068 gen_minuw4 (ra
, rb
, rc
, islit
, lit
);
2072 if (!(ctx
->amask
& AMASK_MVI
))
2074 gen_maxub8 (ra
, rb
, rc
, islit
, lit
);
2078 if (!(ctx
->amask
& AMASK_MVI
))
2080 gen_maxuw4 (ra
, rb
, rc
, islit
, lit
);
2084 if (!(ctx
->amask
& AMASK_MVI
))
2086 gen_maxsb8 (ra
, rb
, rc
, islit
, lit
);
2090 if (!(ctx
->amask
& AMASK_MVI
))
2092 gen_maxsw4 (ra
, rb
, rc
, islit
, lit
);
2096 if (!(ctx
->amask
& AMASK_FIX
))
2098 if (likely(rc
!= 31)) {
2100 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_fir
[ra
]);
2102 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
2107 if (!(ctx
->amask
& AMASK_FIX
))
2110 TCGv_i32 tmp1
= tcg_temp_new_i32();
2112 gen_helper_s_to_memory(tmp1
, cpu_fir
[ra
]);
2114 TCGv tmp2
= tcg_const_i64(0);
2115 gen_helper_s_to_memory(tmp1
, tmp2
);
2116 tcg_temp_free(tmp2
);
2118 tcg_gen_ext_i32_i64(cpu_ir
[rc
], tmp1
);
2119 tcg_temp_free_i32(tmp1
);
2127 /* HW_MTPR (PALcode) */
2128 #if defined (CONFIG_USER_ONLY)
2134 TCGv tmp1
= tcg_const_i32(insn
& 0xFF);
2136 gen_helper_mtpr(tmp1
, cpu_ir
[ra
]);
2138 TCGv tmp2
= tcg_const_i64(0);
2139 gen_helper_mtpr(tmp1
, tmp2
);
2140 tcg_temp_free(tmp2
);
2142 tcg_temp_free(tmp1
);
2148 /* HW_REI (PALcode) */
2149 #if defined (CONFIG_USER_ONLY)
2156 gen_helper_hw_rei();
2161 tmp
= tcg_temp_new();
2162 tcg_gen_addi_i64(tmp
, cpu_ir
[rb
], (((int64_t)insn
<< 51) >> 51));
2164 tmp
= tcg_const_i64(((int64_t)insn
<< 51) >> 51);
2165 gen_helper_hw_ret(tmp
);
2172 /* HW_ST (PALcode) */
2173 #if defined (CONFIG_USER_ONLY)
2180 addr
= tcg_temp_new();
2182 tcg_gen_addi_i64(addr
, cpu_ir
[rb
], disp12
);
2184 tcg_gen_movi_i64(addr
, disp12
);
2188 val
= tcg_temp_new();
2189 tcg_gen_movi_i64(val
, 0);
2191 switch ((insn
>> 12) & 0xF) {
2193 /* Longword physical access */
2194 gen_helper_stl_raw(val
, addr
);
2197 /* Quadword physical access */
2198 gen_helper_stq_raw(val
, addr
);
2201 /* Longword physical access with lock */
2202 gen_helper_stl_c_raw(val
, val
, addr
);
2205 /* Quadword physical access with lock */
2206 gen_helper_stq_c_raw(val
, val
, addr
);
2209 /* Longword virtual access */
2210 gen_helper_st_virt_to_phys(addr
, addr
);
2211 gen_helper_stl_raw(val
, addr
);
2214 /* Quadword virtual access */
2215 gen_helper_st_virt_to_phys(addr
, addr
);
2216 gen_helper_stq_raw(val
, addr
);
2237 /* Longword virtual access with alternate access mode */
2238 gen_helper_set_alt_mode();
2239 gen_helper_st_virt_to_phys(addr
, addr
);
2240 gen_helper_stl_raw(val
, addr
);
2241 gen_helper_restore_mode();
2244 /* Quadword virtual access with alternate access mode */
2245 gen_helper_set_alt_mode();
2246 gen_helper_st_virt_to_phys(addr
, addr
);
2247 gen_helper_stl_raw(val
, addr
);
2248 gen_helper_restore_mode();
2259 tcg_temp_free(addr
);
2265 gen_load_mem(ctx
, &gen_qemu_ldf
, ra
, rb
, disp16
, 1, 0);
2269 gen_load_mem(ctx
, &gen_qemu_ldg
, ra
, rb
, disp16
, 1, 0);
2273 gen_load_mem(ctx
, &gen_qemu_lds
, ra
, rb
, disp16
, 1, 0);
2277 gen_load_mem(ctx
, &tcg_gen_qemu_ld64
, ra
, rb
, disp16
, 1, 0);
2281 gen_store_mem(ctx
, &gen_qemu_stf
, ra
, rb
, disp16
, 1, 0, 0);
2285 gen_store_mem(ctx
, &gen_qemu_stg
, ra
, rb
, disp16
, 1, 0, 0);
2289 gen_store_mem(ctx
, &gen_qemu_sts
, ra
, rb
, disp16
, 1, 0, 0);
2293 gen_store_mem(ctx
, &tcg_gen_qemu_st64
, ra
, rb
, disp16
, 1, 0, 0);
2297 gen_load_mem(ctx
, &tcg_gen_qemu_ld32s
, ra
, rb
, disp16
, 0, 0);
2301 gen_load_mem(ctx
, &tcg_gen_qemu_ld64
, ra
, rb
, disp16
, 0, 0);
2305 gen_load_mem(ctx
, &gen_qemu_ldl_l
, ra
, rb
, disp16
, 0, 0);
2309 gen_load_mem(ctx
, &gen_qemu_ldq_l
, ra
, rb
, disp16
, 0, 0);
2313 gen_store_mem(ctx
, &tcg_gen_qemu_st32
, ra
, rb
, disp16
, 0, 0, 0);
2317 gen_store_mem(ctx
, &tcg_gen_qemu_st64
, ra
, rb
, disp16
, 0, 0, 0);
2321 gen_store_mem(ctx
, &gen_qemu_stl_c
, ra
, rb
, disp16
, 0, 0, 1);
2325 gen_store_mem(ctx
, &gen_qemu_stq_c
, ra
, rb
, disp16
, 0, 0, 1);
2330 tcg_gen_movi_i64(cpu_ir
[ra
], ctx
->pc
);
2331 tcg_gen_movi_i64(cpu_pc
, ctx
->pc
+ (int64_t)(disp21
<< 2));
2334 case 0x31: /* FBEQ */
2335 case 0x32: /* FBLT */
2336 case 0x33: /* FBLE */
2337 gen_fbcond(ctx
, opc
, ra
, disp21
);
2343 tcg_gen_movi_i64(cpu_ir
[ra
], ctx
->pc
);
2344 tcg_gen_movi_i64(cpu_pc
, ctx
->pc
+ (int64_t)(disp21
<< 2));
2347 case 0x35: /* FBNE */
2348 case 0x36: /* FBGE */
2349 case 0x37: /* FBGT */
2350 gen_fbcond(ctx
, opc
, ra
, disp21
);
2355 gen_bcond(ctx
, TCG_COND_EQ
, ra
, disp21
, 1);
2360 gen_bcond(ctx
, TCG_COND_EQ
, ra
, disp21
, 0);
2365 gen_bcond(ctx
, TCG_COND_LT
, ra
, disp21
, 0);
2370 gen_bcond(ctx
, TCG_COND_LE
, ra
, disp21
, 0);
2375 gen_bcond(ctx
, TCG_COND_NE
, ra
, disp21
, 1);
2380 gen_bcond(ctx
, TCG_COND_NE
, ra
, disp21
, 0);
2385 gen_bcond(ctx
, TCG_COND_GE
, ra
, disp21
, 0);
2390 gen_bcond(ctx
, TCG_COND_GT
, ra
, disp21
, 0);
2402 static inline void gen_intermediate_code_internal(CPUState
*env
,
2403 TranslationBlock
*tb
,
2406 DisasContext ctx
, *ctxp
= &ctx
;
2407 target_ulong pc_start
;
2409 uint16_t *gen_opc_end
;
2417 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
2419 ctx
.amask
= env
->amask
;
2421 #if defined (CONFIG_USER_ONLY)
2424 ctx
.mem_idx
= ((env
->ps
>> 3) & 3);
2425 ctx
.pal_mode
= env
->ipr
[IPR_EXC_ADDR
] & 1;
2428 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
2430 max_insns
= CF_COUNT_MASK
;
2433 for (ret
= 0; ret
== 0;) {
2434 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
2435 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
2436 if (bp
->pc
== ctx
.pc
) {
2437 gen_excp(&ctx
, EXCP_DEBUG
, 0);
2443 j
= gen_opc_ptr
- gen_opc_buf
;
2447 gen_opc_instr_start
[lj
++] = 0;
2449 gen_opc_pc
[lj
] = ctx
.pc
;
2450 gen_opc_instr_start
[lj
] = 1;
2451 gen_opc_icount
[lj
] = num_insns
;
2453 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
2455 insn
= ldl_code(ctx
.pc
);
2458 ret
= translate_one(ctxp
, insn
);
2461 /* if we reach a page boundary or are single stepping, stop
2464 if (env
->singlestep_enabled
) {
2465 gen_excp(&ctx
, EXCP_DEBUG
, 0);
2469 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
2472 if (gen_opc_ptr
>= gen_opc_end
)
2475 if (num_insns
>= max_insns
)
2482 if (ret
!= 1 && ret
!= 3) {
2483 tcg_gen_movi_i64(cpu_pc
, ctx
.pc
);
2485 if (tb
->cflags
& CF_LAST_IO
)
2487 /* Generate the return instruction */
2489 gen_icount_end(tb
, num_insns
);
2490 *gen_opc_ptr
= INDEX_op_end
;
2492 j
= gen_opc_ptr
- gen_opc_buf
;
2495 gen_opc_instr_start
[lj
++] = 0;
2497 tb
->size
= ctx
.pc
- pc_start
;
2498 tb
->icount
= num_insns
;
2501 log_cpu_state_mask(CPU_LOG_TB_CPU
, env
, 0);
2502 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
2503 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
2504 log_target_disas(pc_start
, ctx
.pc
- pc_start
, 1);
2510 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
2512 gen_intermediate_code_internal(env
, tb
, 0);
2515 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
2517 gen_intermediate_code_internal(env
, tb
, 1);
2525 static const struct cpu_def_t cpu_defs
[] = {
2526 { "ev4", IMPLVER_2106x
, 0 },
2527 { "ev5", IMPLVER_21164
, 0 },
2528 { "ev56", IMPLVER_21164
, AMASK_BWX
},
2529 { "pca56", IMPLVER_21164
, AMASK_BWX
| AMASK_MVI
},
2530 { "ev6", IMPLVER_21264
, AMASK_BWX
| AMASK_FIX
| AMASK_MVI
| AMASK_TRAP
},
2531 { "ev67", IMPLVER_21264
, (AMASK_BWX
| AMASK_FIX
| AMASK_CIX
2532 | AMASK_MVI
| AMASK_TRAP
| AMASK_PREFETCH
), },
2533 { "ev68", IMPLVER_21264
, (AMASK_BWX
| AMASK_FIX
| AMASK_CIX
2534 | AMASK_MVI
| AMASK_TRAP
| AMASK_PREFETCH
), },
2535 { "21064", IMPLVER_2106x
, 0 },
2536 { "21164", IMPLVER_21164
, 0 },
2537 { "21164a", IMPLVER_21164
, AMASK_BWX
},
2538 { "21164pc", IMPLVER_21164
, AMASK_BWX
| AMASK_MVI
},
2539 { "21264", IMPLVER_21264
, AMASK_BWX
| AMASK_FIX
| AMASK_MVI
| AMASK_TRAP
},
2540 { "21264a", IMPLVER_21264
, (AMASK_BWX
| AMASK_FIX
| AMASK_CIX
2541 | AMASK_MVI
| AMASK_TRAP
| AMASK_PREFETCH
), }
2544 CPUAlphaState
* cpu_alpha_init (const char *cpu_model
)
2548 int implver
, amask
, i
, max
;
2550 env
= qemu_mallocz(sizeof(CPUAlphaState
));
2552 alpha_translate_init();
2555 /* Default to ev67; no reason not to emulate insns by default. */
2556 implver
= IMPLVER_21264
;
2557 amask
= (AMASK_BWX
| AMASK_FIX
| AMASK_CIX
| AMASK_MVI
2558 | AMASK_TRAP
| AMASK_PREFETCH
);
2560 max
= ARRAY_SIZE(cpu_defs
);
2561 for (i
= 0; i
< max
; i
++) {
2562 if (strcmp (cpu_model
, cpu_defs
[i
].name
) == 0) {
2563 implver
= cpu_defs
[i
].implver
;
2564 amask
= cpu_defs
[i
].amask
;
2568 env
->implver
= implver
;
2572 #if defined (CONFIG_USER_ONLY)
2576 /* Initialize IPR */
2577 hwpcb
= env
->ipr
[IPR_PCBB
];
2578 env
->ipr
[IPR_ASN
] = 0;
2579 env
->ipr
[IPR_ASTEN
] = 0;
2580 env
->ipr
[IPR_ASTSR
] = 0;
2581 env
->ipr
[IPR_DATFX
] = 0;
2583 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2584 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2585 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2586 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2587 env
->ipr
[IPR_FEN
] = 0;
2588 env
->ipr
[IPR_IPL
] = 31;
2589 env
->ipr
[IPR_MCES
] = 0;
2590 env
->ipr
[IPR_PERFMON
] = 0; /* Implementation specific */
2591 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2592 env
->ipr
[IPR_SISR
] = 0;
2593 env
->ipr
[IPR_VIRBND
] = -1ULL;
2595 qemu_init_vcpu(env
);
2599 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
2600 unsigned long searched_pc
, int pc_pos
, void *puc
)
2602 env
->pc
= gen_opc_pc
[pc_pos
];