exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef _EXEC_ALL_H_
  21 #define _EXEC_ALL_H_
  22
  23 #include "qemu-common.h"
  24
  25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  26 #define DEBUG_DISAS
  27
  28 /* Page tracking code uses ram addresses in system mode, and virtual
  29    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  30    type.  */
  31 #if defined(CONFIG_USER_ONLY)
  32 typedef abi_ulong tb_page_addr_t;
  33 #else
  34 typedef ram_addr_t tb_page_addr_t;
  35 #endif
  36
  37 /* is_jmp field values */
  38 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  39 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  40 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  42
  43 typedef struct TranslationBlock TranslationBlock;
  44
  45 /* XXX: make safe guess about sizes */
  46 #define MAX_OP_PER_INSTR 96
  47 /* A Call op needs up to 6 + 2N parameters (N = number of arguments).  */
  48 #define MAX_OPC_PARAM 10
  49 #define OPC_BUF_SIZE 640
  50 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  51
  52 /* Maximum size a TCG op can expand to.  This is complicated because a
  53    single op may require several host instructions and register reloads.
  54    For now take a wild guess at 192 bytes, which should allow at least
  55    a couple of fixup instructions per argument.  */
  56 #define TCG_MAX_OP_SIZE 192
  57
  58 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  59
  60 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  61 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  62 extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
  63
  64 #include "qemu-log.h"
  65
  66 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  67 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  68 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
  69                  unsigned long searched_pc, int pc_pos, void *puc);
  70
  71 unsigned long code_gen_max_block_size(void);
  72 void cpu_gen_init(void);
  73 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  74                  int *gen_code_size_ptr);
  75 int cpu_restore_state(struct TranslationBlock *tb,
  76                       CPUState *env, unsigned long searched_pc,
  77                       void *puc);
  78 int cpu_restore_state_copy(struct TranslationBlock *tb,
  79                            CPUState *env, unsigned long searched_pc,
  80                            void *puc);
  81 void cpu_resume_from_signal(CPUState *env1, void *puc);
  82 void cpu_io_recompile(CPUState *env, void *retaddr);
  83 TranslationBlock *tb_gen_code(CPUState *env,
  84                               target_ulong pc, target_ulong cs_base, int flags,
  85                               int cflags);
  86 void cpu_exec_init(CPUState *env);
  87 void QEMU_NORETURN cpu_loop_exit(void);
  88 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
  89 void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
  90                                    int is_cpu_write_access);
  91 void tb_invalidate_page_range(target_ulong start, target_ulong end);
  92 void tlb_flush_page(CPUState *env, target_ulong addr);
  93 void tlb_flush(CPUState *env, int flush_global);
  94 #if !defined(CONFIG_USER_ONLY)
  95 void tlb_set_page(CPUState *env, target_ulong vaddr,
  96                   target_phys_addr_t paddr, int prot,
  97                   int mmu_idx, target_ulong size);
  98 #endif
  99
 100 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 101
 102 #define CODE_GEN_PHYS_HASH_BITS     15
 103 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 104
 105 #define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)
 106
 107 /* estimated block size for TB allocation */
 108 /* XXX: use a per code average code fragment size and modulate it
 109    according to the host CPU */
 110 #if defined(CONFIG_SOFTMMU)
 111 #define CODE_GEN_AVG_BLOCK_SIZE 128
 112 #else
 113 #define CODE_GEN_AVG_BLOCK_SIZE 64
 114 #endif
 115
 116 #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
 117 #define USE_DIRECT_JUMP
 118 #endif
 119
 120 struct TranslationBlock {
 121     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 122     target_ulong cs_base; /* CS base for this block */
 123     uint64_t flags; /* flags defining in which context the code was generated */
 124     uint16_t size;      /* size of target code for this block (1 <=
 125                            size <= TARGET_PAGE_SIZE) */
 126     uint16_t cflags;    /* compile flags */
 127 #define CF_COUNT_MASK  0x7fff
 128 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 129
 130     uint8_t *tc_ptr;    /* pointer to the translated code */
 131     /* next matching tb for physical address. */
 132     struct TranslationBlock *phys_hash_next;
 133     /* first and second physical page containing code. The lower bit
 134        of the pointer tells the index in page_next[] */
 135     struct TranslationBlock *page_next[2];
 136     tb_page_addr_t page_addr[2];
 137
 138     /* the following data are used to directly call another TB from
 139        the code of this one. */
 140     uint16_t tb_next_offset[2]; /* offset of original jump target */
 141 #ifdef USE_DIRECT_JUMP
 142     uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
 143 #else
 144     unsigned long tb_next[2]; /* address of jump generated code */
 145 #endif
 146     /* list of TBs jumping to this one. This is a circular list using
 147        the two least significant bits of the pointers to tell what is
 148        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 149        jmp_first */
 150     struct TranslationBlock *jmp_next[2];
 151     struct TranslationBlock *jmp_first;
 152     uint32_t icount;
 153 };
 154
 155 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 156 {
 157     target_ulong tmp;
 158     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 159     return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
 160 }
 161
 162 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 163 {
 164     target_ulong tmp;
 165     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 166     return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
 167             | (tmp & TB_JMP_ADDR_MASK));
 168 }
 169
 170 static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
 171 {
 172     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 173 }
 174
 175 TranslationBlock *tb_alloc(target_ulong pc);
 176 void tb_free(TranslationBlock *tb);
 177 void tb_flush(CPUState *env);
 178 void tb_link_page(TranslationBlock *tb,
 179                   tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
 180 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 181
 182 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 183 extern uint8_t *code_gen_ptr;
 184 extern int code_gen_max_blocks;
 185
 186 #if defined(USE_DIRECT_JUMP)
 187
 188 #if defined(_ARCH_PPC)
 189 extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
 190 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 191 #elif defined(__i386__) || defined(__x86_64__)
 192 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 193 {
 194     /* patch the branch destination */
 195     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 196     /* no need to flush icache explicitly */
 197 }
 198 #elif defined(__arm__)
 199 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 200 {
 201 #if QEMU_GNUC_PREREQ(4, 1)
 202     void __clear_cache(char *beg, char *end);
 203 #else
 204     register unsigned long _beg __asm ("a1");
 205     register unsigned long _end __asm ("a2");
 206     register unsigned long _flg __asm ("a3");
 207 #endif
 208
 209     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 210     *(uint32_t *)jmp_addr =
 211         (*(uint32_t *)jmp_addr & ~0xffffff)
 212         | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
 213
 214 #if QEMU_GNUC_PREREQ(4, 1)
 215     __clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
 216 #else
 217     /* flush icache */
 218     _beg = jmp_addr;
 219     _end = jmp_addr + 4;
 220     _flg = 0;
 221     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 222 #endif
 223 }
 224 #endif
 225
 226 static inline void tb_set_jmp_target(TranslationBlock *tb,
 227                                      int n, unsigned long addr)
 228 {
 229     unsigned long offset;
 230
 231     offset = tb->tb_jmp_offset[n];
 232     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 233 }
 234
 235 #else
 236
 237 /* set the jump target */
 238 static inline void tb_set_jmp_target(TranslationBlock *tb,
 239                                      int n, unsigned long addr)
 240 {
 241     tb->tb_next[n] = addr;
 242 }
 243
 244 #endif
 245
 246 static inline void tb_add_jump(TranslationBlock *tb, int n,
 247                                TranslationBlock *tb_next)
 248 {
 249     /* NOTE: this test is only needed for thread safety */
 250     if (!tb->jmp_next[n]) {
 251         /* patch the native jump address */
 252         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 253
 254         /* add in TB jmp circular list */
 255         tb->jmp_next[n] = tb_next->jmp_first;
 256         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 257     }
 258 }
 259
 260 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 261
 262 #include "qemu-lock.h"
 263
 264 extern spinlock_t tb_lock;
 265
 266 extern int tb_invalidated_flag;
 267
 268 #if !defined(CONFIG_USER_ONLY)
 269
 270 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 271 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 272 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 273
 274 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
 275               void *retaddr);
 276
 277 #include "softmmu_defs.h"
 278
 279 #define ACCESS_TYPE (NB_MMU_MODES + 1)
 280 #define MEMSUFFIX _code
 281 #define env cpu_single_env
 282
 283 #define DATA_SIZE 1
 284 #include "softmmu_header.h"
 285
 286 #define DATA_SIZE 2
 287 #include "softmmu_header.h"
 288
 289 #define DATA_SIZE 4
 290 #include "softmmu_header.h"
 291
 292 #define DATA_SIZE 8
 293 #include "softmmu_header.h"
 294
 295 #undef ACCESS_TYPE
 296 #undef MEMSUFFIX
 297 #undef env
 298
 299 #endif
 300
 301 #if defined(CONFIG_USER_ONLY)
 302 static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
 303 {
 304     return addr;
 305 }
 306 #else
 307 /* NOTE: this function can trigger an exception */
 308 /* NOTE2: the returned address is not exactly the physical address: it
 309    is the offset relative to phys_ram_base */
 310 static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
 311 {
 312     int mmu_idx, page_index, pd;
 313     void *p;
 314
 315     page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 316     mmu_idx = cpu_mmu_index(env1);
 317     if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
 318                  (addr & TARGET_PAGE_MASK))) {
 319         ldub_code(addr);
 320     }
 321     pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
 322     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 323 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
 324         do_unassigned_access(addr, 0, 1, 0, 4);
 325 #else
 326         cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 327 #endif
 328     }
 329     p = (void *)(unsigned long)addr
 330         + env1->tlb_table[mmu_idx][page_index].addend;
 331     return qemu_ram_addr_from_host(p);
 332 }
 333 #endif
 334
 335 typedef void (CPUDebugExcpHandler)(CPUState *env);
 336
 337 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
 338
 339 /* vl.c */
 340 extern int singlestep;
 341
 342 #endif