4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
28 #define SH4_DEBUG_DISAS
29 //#define SH4_SINGLE_STEP
35 #include "qemu-common.h"
41 typedef struct DisasContext
{
42 struct TranslationBlock
*tb
;
51 int singlestep_enabled
;
56 #if defined(CONFIG_USER_ONLY)
57 #define IS_USER(ctx) 1
59 #define IS_USER(ctx) (!(ctx->sr & SR_MD))
63 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
66 BS_STOP
= 1, /* We want to stop translation for any reason */
67 BS_BRANCH
= 2, /* We reached a branch condition */
68 BS_EXCP
= 3, /* We reached an exception condition */
71 /* global register indexes */
72 static TCGv_ptr cpu_env
;
73 static TCGv cpu_gregs
[24];
74 static TCGv cpu_pc
, cpu_sr
, cpu_ssr
, cpu_spc
, cpu_gbr
;
75 static TCGv cpu_vbr
, cpu_sgr
, cpu_dbr
, cpu_mach
, cpu_macl
;
76 static TCGv cpu_pr
, cpu_fpscr
, cpu_fpul
, cpu_ldst
;
77 static TCGv cpu_fregs
[32];
79 /* internal register indexes */
80 static TCGv cpu_flags
, cpu_delayed_pc
;
82 #include "gen-icount.h"
84 static void sh4_translate_init(void)
87 static int done_init
= 0;
88 static const char * const gregnames
[24] = {
89 "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
90 "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
91 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
92 "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
93 "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
95 static const char * const fregnames
[32] = {
96 "FPR0_BANK0", "FPR1_BANK0", "FPR2_BANK0", "FPR3_BANK0",
97 "FPR4_BANK0", "FPR5_BANK0", "FPR6_BANK0", "FPR7_BANK0",
98 "FPR8_BANK0", "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0",
99 "FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0",
100 "FPR0_BANK1", "FPR1_BANK1", "FPR2_BANK1", "FPR3_BANK1",
101 "FPR4_BANK1", "FPR5_BANK1", "FPR6_BANK1", "FPR7_BANK1",
102 "FPR8_BANK1", "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1",
103 "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1",
109 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
111 for (i
= 0; i
< 24; i
++)
112 cpu_gregs
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
113 offsetof(CPUState
, gregs
[i
]),
116 cpu_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
117 offsetof(CPUState
, pc
), "PC");
118 cpu_sr
= tcg_global_mem_new_i32(TCG_AREG0
,
119 offsetof(CPUState
, sr
), "SR");
120 cpu_ssr
= tcg_global_mem_new_i32(TCG_AREG0
,
121 offsetof(CPUState
, ssr
), "SSR");
122 cpu_spc
= tcg_global_mem_new_i32(TCG_AREG0
,
123 offsetof(CPUState
, spc
), "SPC");
124 cpu_gbr
= tcg_global_mem_new_i32(TCG_AREG0
,
125 offsetof(CPUState
, gbr
), "GBR");
126 cpu_vbr
= tcg_global_mem_new_i32(TCG_AREG0
,
127 offsetof(CPUState
, vbr
), "VBR");
128 cpu_sgr
= tcg_global_mem_new_i32(TCG_AREG0
,
129 offsetof(CPUState
, sgr
), "SGR");
130 cpu_dbr
= tcg_global_mem_new_i32(TCG_AREG0
,
131 offsetof(CPUState
, dbr
), "DBR");
132 cpu_mach
= tcg_global_mem_new_i32(TCG_AREG0
,
133 offsetof(CPUState
, mach
), "MACH");
134 cpu_macl
= tcg_global_mem_new_i32(TCG_AREG0
,
135 offsetof(CPUState
, macl
), "MACL");
136 cpu_pr
= tcg_global_mem_new_i32(TCG_AREG0
,
137 offsetof(CPUState
, pr
), "PR");
138 cpu_fpscr
= tcg_global_mem_new_i32(TCG_AREG0
,
139 offsetof(CPUState
, fpscr
), "FPSCR");
140 cpu_fpul
= tcg_global_mem_new_i32(TCG_AREG0
,
141 offsetof(CPUState
, fpul
), "FPUL");
143 cpu_flags
= tcg_global_mem_new_i32(TCG_AREG0
,
144 offsetof(CPUState
, flags
), "_flags_");
145 cpu_delayed_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
146 offsetof(CPUState
, delayed_pc
),
148 cpu_ldst
= tcg_global_mem_new_i32(TCG_AREG0
,
149 offsetof(CPUState
, ldst
), "_ldst_");
151 for (i
= 0; i
< 32; i
++)
152 cpu_fregs
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
153 offsetof(CPUState
, fregs
[i
]),
156 /* register helpers */
163 void cpu_dump_state(CPUState
* env
, FILE * f
,
164 int (*cpu_fprintf
) (FILE * f
, const char *fmt
, ...),
168 cpu_fprintf(f
, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
169 env
->pc
, env
->sr
, env
->pr
, env
->fpscr
);
170 cpu_fprintf(f
, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
171 env
->spc
, env
->ssr
, env
->gbr
, env
->vbr
);
172 cpu_fprintf(f
, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
173 env
->sgr
, env
->dbr
, env
->delayed_pc
, env
->fpul
);
174 for (i
= 0; i
< 24; i
+= 4) {
175 cpu_fprintf(f
, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
176 i
, env
->gregs
[i
], i
+ 1, env
->gregs
[i
+ 1],
177 i
+ 2, env
->gregs
[i
+ 2], i
+ 3, env
->gregs
[i
+ 3]);
179 if (env
->flags
& DELAY_SLOT
) {
180 cpu_fprintf(f
, "in delay slot (delayed_pc=0x%08x)\n",
182 } else if (env
->flags
& DELAY_SLOT_CONDITIONAL
) {
183 cpu_fprintf(f
, "in conditional delay slot (delayed_pc=0x%08x)\n",
188 static void cpu_sh4_reset(CPUSH4State
* env
)
190 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
191 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
192 log_cpu_state(env
, 0);
195 #if defined(CONFIG_USER_ONLY)
198 env
->sr
= SR_MD
| SR_RB
| SR_BL
| SR_I3
| SR_I2
| SR_I1
| SR_I0
;
201 env
->pc
= 0xA0000000;
202 #if defined(CONFIG_USER_ONLY)
203 env
->fpscr
= FPSCR_PR
; /* value for userspace according to the kernel */
204 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
); /* ?! */
206 env
->fpscr
= 0x00040001; /* CPU reset value according to SH4 manual */
207 set_float_rounding_mode(float_round_to_zero
, &env
->fp_status
);
221 static sh4_def_t sh4_defs
[] = {
224 .id
= SH_CPU_SH7750R
,
228 .features
= SH_FEATURE_BCR3_AND_BCR4
,
231 .id
= SH_CPU_SH7751R
,
234 .cvr
= 0x00110000, /* Neutered caches, should be 0x20480000 */
235 .features
= SH_FEATURE_BCR3_AND_BCR4
,
242 .features
= SH_FEATURE_SH4A
,
246 static const sh4_def_t
*cpu_sh4_find_by_name(const char *name
)
250 if (strcasecmp(name
, "any") == 0)
253 for (i
= 0; i
< ARRAY_SIZE(sh4_defs
); i
++)
254 if (strcasecmp(name
, sh4_defs
[i
].name
) == 0)
260 void sh4_cpu_list(FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
264 for (i
= 0; i
< ARRAY_SIZE(sh4_defs
); i
++)
265 (*cpu_fprintf
)(f
, "%s\n", sh4_defs
[i
].name
);
268 static void cpu_sh4_register(CPUSH4State
*env
, const sh4_def_t
*def
)
276 CPUSH4State
*cpu_sh4_init(const char *cpu_model
)
279 const sh4_def_t
*def
;
281 def
= cpu_sh4_find_by_name(cpu_model
);
284 env
= qemu_mallocz(sizeof(CPUSH4State
));
285 env
->features
= def
->features
;
287 env
->movcal_backup_tail
= &(env
->movcal_backup
);
288 sh4_translate_init();
289 env
->cpu_model_str
= cpu_model
;
291 cpu_sh4_register(env
, def
);
297 static void gen_goto_tb(DisasContext
* ctx
, int n
, target_ulong dest
)
299 TranslationBlock
*tb
;
302 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
303 !ctx
->singlestep_enabled
) {
304 /* Use a direct jump if in same page and singlestep not enabled */
306 tcg_gen_movi_i32(cpu_pc
, dest
);
307 tcg_gen_exit_tb((long) tb
+ n
);
309 tcg_gen_movi_i32(cpu_pc
, dest
);
310 if (ctx
->singlestep_enabled
)
316 static void gen_jump(DisasContext
* ctx
)
318 if (ctx
->delayed_pc
== (uint32_t) - 1) {
319 /* Target is not statically known, it comes necessarily from a
320 delayed jump as immediate jump are conditinal jumps */
321 tcg_gen_mov_i32(cpu_pc
, cpu_delayed_pc
);
322 if (ctx
->singlestep_enabled
)
326 gen_goto_tb(ctx
, 0, ctx
->delayed_pc
);
330 static inline void gen_branch_slot(uint32_t delayed_pc
, int t
)
333 int label
= gen_new_label();
334 tcg_gen_movi_i32(cpu_delayed_pc
, delayed_pc
);
336 tcg_gen_andi_i32(sr
, cpu_sr
, SR_T
);
337 tcg_gen_brcondi_i32(TCG_COND_NE
, sr
, t
? SR_T
: 0, label
);
338 tcg_gen_ori_i32(cpu_flags
, cpu_flags
, DELAY_SLOT_TRUE
);
339 gen_set_label(label
);
342 /* Immediate conditional jump (bt or bf) */
343 static void gen_conditional_jump(DisasContext
* ctx
,
344 target_ulong ift
, target_ulong ifnott
)
349 l1
= gen_new_label();
351 tcg_gen_andi_i32(sr
, cpu_sr
, SR_T
);
352 tcg_gen_brcondi_i32(TCG_COND_EQ
, sr
, SR_T
, l1
);
353 gen_goto_tb(ctx
, 0, ifnott
);
355 gen_goto_tb(ctx
, 1, ift
);
358 /* Delayed conditional jump (bt or bf) */
359 static void gen_delayed_conditional_jump(DisasContext
* ctx
)
364 l1
= gen_new_label();
366 tcg_gen_andi_i32(ds
, cpu_flags
, DELAY_SLOT_TRUE
);
367 tcg_gen_brcondi_i32(TCG_COND_EQ
, ds
, DELAY_SLOT_TRUE
, l1
);
368 gen_goto_tb(ctx
, 1, ctx
->pc
+ 2);
370 tcg_gen_andi_i32(cpu_flags
, cpu_flags
, ~DELAY_SLOT_TRUE
);
374 static inline void gen_set_t(void)
376 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, SR_T
);
379 static inline void gen_clr_t(void)
381 tcg_gen_andi_i32(cpu_sr
, cpu_sr
, ~SR_T
);
384 static inline void gen_cmp(int cond
, TCGv t0
, TCGv t1
)
386 int label1
= gen_new_label();
387 int label2
= gen_new_label();
388 tcg_gen_brcond_i32(cond
, t1
, t0
, label1
);
391 gen_set_label(label1
);
393 gen_set_label(label2
);
396 static inline void gen_cmp_imm(int cond
, TCGv t0
, int32_t imm
)
398 int label1
= gen_new_label();
399 int label2
= gen_new_label();
400 tcg_gen_brcondi_i32(cond
, t0
, imm
, label1
);
403 gen_set_label(label1
);
405 gen_set_label(label2
);
408 static inline void gen_store_flags(uint32_t flags
)
410 tcg_gen_andi_i32(cpu_flags
, cpu_flags
, DELAY_SLOT_TRUE
);
411 tcg_gen_ori_i32(cpu_flags
, cpu_flags
, flags
);
414 static inline void gen_copy_bit_i32(TCGv t0
, int p0
, TCGv t1
, int p1
)
416 TCGv tmp
= tcg_temp_new();
421 tcg_gen_andi_i32(tmp
, t1
, (1 << p1
));
422 tcg_gen_andi_i32(t0
, t0
, ~(1 << p0
));
424 tcg_gen_shri_i32(tmp
, tmp
, p1
- p0
);
426 tcg_gen_shli_i32(tmp
, tmp
, p0
- p1
);
427 tcg_gen_or_i32(t0
, t0
, tmp
);
432 static inline void gen_load_fpr64(TCGv_i64 t
, int reg
)
434 tcg_gen_concat_i32_i64(t
, cpu_fregs
[reg
+ 1], cpu_fregs
[reg
]);
437 static inline void gen_store_fpr64 (TCGv_i64 t
, int reg
)
439 TCGv_i32 tmp
= tcg_temp_new_i32();
440 tcg_gen_trunc_i64_i32(tmp
, t
);
441 tcg_gen_mov_i32(cpu_fregs
[reg
+ 1], tmp
);
442 tcg_gen_shri_i64(t
, t
, 32);
443 tcg_gen_trunc_i64_i32(tmp
, t
);
444 tcg_gen_mov_i32(cpu_fregs
[reg
], tmp
);
445 tcg_temp_free_i32(tmp
);
448 #define B3_0 (ctx->opcode & 0xf)
449 #define B6_4 ((ctx->opcode >> 4) & 0x7)
450 #define B7_4 ((ctx->opcode >> 4) & 0xf)
451 #define B7_0 (ctx->opcode & 0xff)
452 #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff))
453 #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \
454 (ctx->opcode & 0xfff))
455 #define B11_8 ((ctx->opcode >> 8) & 0xf)
456 #define B15_12 ((ctx->opcode >> 12) & 0xf)
458 #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \
459 (cpu_gregs[x + 16]) : (cpu_gregs[x]))
461 #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \
462 ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
464 #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))
465 #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
466 #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
467 #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
469 #define CHECK_NOT_DELAY_SLOT \
470 if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
472 tcg_gen_movi_i32(cpu_pc, ctx->pc-2); \
473 gen_helper_raise_slot_illegal_instruction(); \
474 ctx->bstate = BS_EXCP; \
478 #define CHECK_PRIVILEGED \
479 if (IS_USER(ctx)) { \
480 tcg_gen_movi_i32(cpu_pc, ctx->pc); \
481 gen_helper_raise_illegal_instruction(); \
482 ctx->bstate = BS_EXCP; \
486 #define CHECK_FPU_ENABLED \
487 if (ctx->flags & SR_FD) { \
488 if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
489 tcg_gen_movi_i32(cpu_pc, ctx->pc-2); \
490 gen_helper_raise_slot_fpu_disable(); \
492 tcg_gen_movi_i32(cpu_pc, ctx->pc); \
493 gen_helper_raise_fpu_disable(); \
495 ctx->bstate = BS_EXCP; \
499 static void _decode_opc(DisasContext
* ctx
)
501 /* This code tries to make movcal emulation sufficiently
502 accurate for Linux purposes. This instruction writes
503 memory, and prior to that, always allocates a cache line.
504 It is used in two contexts:
505 - in memcpy, where data is copied in blocks, the first write
506 of to a block uses movca.l for performance.
507 - in arch/sh/mm/cache-sh4.c, movcal.l + ocbi combination is used
508 to flush the cache. Here, the data written by movcal.l is never
509 written to memory, and the data written is just bogus.
511 To simulate this, we simulate movcal.l, we store the value to memory,
512 but we also remember the previous content. If we see ocbi, we check
513 if movcal.l for that address was done previously. If so, the write should
514 not have hit the memory, so we restore the previous content.
515 When we see an instruction that is neither movca.l
516 nor ocbi, the previous content is discarded.
518 To optimize, we only try to flush stores when we're at the start of
519 TB, or if we already saw movca.l in this TB and did not flush stores
523 int opcode
= ctx
->opcode
& 0xf0ff;
524 if (opcode
!= 0x0093 /* ocbi */
525 && opcode
!= 0x00c3 /* movca.l */)
527 gen_helper_discard_movcal_backup ();
533 fprintf(stderr
, "Translating opcode 0x%04x\n", ctx
->opcode
);
536 switch (ctx
->opcode
) {
537 case 0x0019: /* div0u */
538 tcg_gen_andi_i32(cpu_sr
, cpu_sr
, ~(SR_M
| SR_Q
| SR_T
));
540 case 0x000b: /* rts */
542 tcg_gen_mov_i32(cpu_delayed_pc
, cpu_pr
);
543 ctx
->flags
|= DELAY_SLOT
;
544 ctx
->delayed_pc
= (uint32_t) - 1;
546 case 0x0028: /* clrmac */
547 tcg_gen_movi_i32(cpu_mach
, 0);
548 tcg_gen_movi_i32(cpu_macl
, 0);
550 case 0x0048: /* clrs */
551 tcg_gen_andi_i32(cpu_sr
, cpu_sr
, ~SR_S
);
553 case 0x0008: /* clrt */
556 case 0x0038: /* ldtlb */
560 case 0x002b: /* rte */
563 tcg_gen_mov_i32(cpu_sr
, cpu_ssr
);
564 tcg_gen_mov_i32(cpu_delayed_pc
, cpu_spc
);
565 ctx
->flags
|= DELAY_SLOT
;
566 ctx
->delayed_pc
= (uint32_t) - 1;
568 case 0x0058: /* sets */
569 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, SR_S
);
571 case 0x0018: /* sett */
574 case 0xfbfd: /* frchg */
575 tcg_gen_xori_i32(cpu_fpscr
, cpu_fpscr
, FPSCR_FR
);
576 ctx
->bstate
= BS_STOP
;
578 case 0xf3fd: /* fschg */
579 tcg_gen_xori_i32(cpu_fpscr
, cpu_fpscr
, FPSCR_SZ
);
580 ctx
->bstate
= BS_STOP
;
582 case 0x0009: /* nop */
584 case 0x001b: /* sleep */
586 gen_helper_sleep(tcg_const_i32(ctx
->pc
+ 2));
590 switch (ctx
->opcode
& 0xf000) {
591 case 0x1000: /* mov.l Rm,@(disp,Rn) */
593 TCGv addr
= tcg_temp_new();
594 tcg_gen_addi_i32(addr
, REG(B11_8
), B3_0
* 4);
595 tcg_gen_qemu_st32(REG(B7_4
), addr
, ctx
->memidx
);
599 case 0x5000: /* mov.l @(disp,Rm),Rn */
601 TCGv addr
= tcg_temp_new();
602 tcg_gen_addi_i32(addr
, REG(B7_4
), B3_0
* 4);
603 tcg_gen_qemu_ld32s(REG(B11_8
), addr
, ctx
->memidx
);
607 case 0xe000: /* mov #imm,Rn */
608 tcg_gen_movi_i32(REG(B11_8
), B7_0s
);
610 case 0x9000: /* mov.w @(disp,PC),Rn */
612 TCGv addr
= tcg_const_i32(ctx
->pc
+ 4 + B7_0
* 2);
613 tcg_gen_qemu_ld16s(REG(B11_8
), addr
, ctx
->memidx
);
617 case 0xd000: /* mov.l @(disp,PC),Rn */
619 TCGv addr
= tcg_const_i32((ctx
->pc
+ 4 + B7_0
* 4) & ~3);
620 tcg_gen_qemu_ld32s(REG(B11_8
), addr
, ctx
->memidx
);
624 case 0x7000: /* add #imm,Rn */
625 tcg_gen_addi_i32(REG(B11_8
), REG(B11_8
), B7_0s
);
627 case 0xa000: /* bra disp */
629 ctx
->delayed_pc
= ctx
->pc
+ 4 + B11_0s
* 2;
630 tcg_gen_movi_i32(cpu_delayed_pc
, ctx
->delayed_pc
);
631 ctx
->flags
|= DELAY_SLOT
;
633 case 0xb000: /* bsr disp */
635 tcg_gen_movi_i32(cpu_pr
, ctx
->pc
+ 4);
636 ctx
->delayed_pc
= ctx
->pc
+ 4 + B11_0s
* 2;
637 tcg_gen_movi_i32(cpu_delayed_pc
, ctx
->delayed_pc
);
638 ctx
->flags
|= DELAY_SLOT
;
642 switch (ctx
->opcode
& 0xf00f) {
643 case 0x6003: /* mov Rm,Rn */
644 tcg_gen_mov_i32(REG(B11_8
), REG(B7_4
));
646 case 0x2000: /* mov.b Rm,@Rn */
647 tcg_gen_qemu_st8(REG(B7_4
), REG(B11_8
), ctx
->memidx
);
649 case 0x2001: /* mov.w Rm,@Rn */
650 tcg_gen_qemu_st16(REG(B7_4
), REG(B11_8
), ctx
->memidx
);
652 case 0x2002: /* mov.l Rm,@Rn */
653 tcg_gen_qemu_st32(REG(B7_4
), REG(B11_8
), ctx
->memidx
);
655 case 0x6000: /* mov.b @Rm,Rn */
656 tcg_gen_qemu_ld8s(REG(B11_8
), REG(B7_4
), ctx
->memidx
);
658 case 0x6001: /* mov.w @Rm,Rn */
659 tcg_gen_qemu_ld16s(REG(B11_8
), REG(B7_4
), ctx
->memidx
);
661 case 0x6002: /* mov.l @Rm,Rn */
662 tcg_gen_qemu_ld32s(REG(B11_8
), REG(B7_4
), ctx
->memidx
);
664 case 0x2004: /* mov.b Rm,@-Rn */
666 TCGv addr
= tcg_temp_new();
667 tcg_gen_subi_i32(addr
, REG(B11_8
), 1);
668 tcg_gen_qemu_st8(REG(B7_4
), addr
, ctx
->memidx
); /* might cause re-execution */
669 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 1); /* modify register status */
673 case 0x2005: /* mov.w Rm,@-Rn */
675 TCGv addr
= tcg_temp_new();
676 tcg_gen_subi_i32(addr
, REG(B11_8
), 2);
677 tcg_gen_qemu_st16(REG(B7_4
), addr
, ctx
->memidx
);
678 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 2);
682 case 0x2006: /* mov.l Rm,@-Rn */
684 TCGv addr
= tcg_temp_new();
685 tcg_gen_subi_i32(addr
, REG(B11_8
), 4);
686 tcg_gen_qemu_st32(REG(B7_4
), addr
, ctx
->memidx
);
687 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 4);
690 case 0x6004: /* mov.b @Rm+,Rn */
691 tcg_gen_qemu_ld8s(REG(B11_8
), REG(B7_4
), ctx
->memidx
);
693 tcg_gen_addi_i32(REG(B7_4
), REG(B7_4
), 1);
695 case 0x6005: /* mov.w @Rm+,Rn */
696 tcg_gen_qemu_ld16s(REG(B11_8
), REG(B7_4
), ctx
->memidx
);
698 tcg_gen_addi_i32(REG(B7_4
), REG(B7_4
), 2);
700 case 0x6006: /* mov.l @Rm+,Rn */
701 tcg_gen_qemu_ld32s(REG(B11_8
), REG(B7_4
), ctx
->memidx
);
703 tcg_gen_addi_i32(REG(B7_4
), REG(B7_4
), 4);
705 case 0x0004: /* mov.b Rm,@(R0,Rn) */
707 TCGv addr
= tcg_temp_new();
708 tcg_gen_add_i32(addr
, REG(B11_8
), REG(0));
709 tcg_gen_qemu_st8(REG(B7_4
), addr
, ctx
->memidx
);
713 case 0x0005: /* mov.w Rm,@(R0,Rn) */
715 TCGv addr
= tcg_temp_new();
716 tcg_gen_add_i32(addr
, REG(B11_8
), REG(0));
717 tcg_gen_qemu_st16(REG(B7_4
), addr
, ctx
->memidx
);
721 case 0x0006: /* mov.l Rm,@(R0,Rn) */
723 TCGv addr
= tcg_temp_new();
724 tcg_gen_add_i32(addr
, REG(B11_8
), REG(0));
725 tcg_gen_qemu_st32(REG(B7_4
), addr
, ctx
->memidx
);
729 case 0x000c: /* mov.b @(R0,Rm),Rn */
731 TCGv addr
= tcg_temp_new();
732 tcg_gen_add_i32(addr
, REG(B7_4
), REG(0));
733 tcg_gen_qemu_ld8s(REG(B11_8
), addr
, ctx
->memidx
);
737 case 0x000d: /* mov.w @(R0,Rm),Rn */
739 TCGv addr
= tcg_temp_new();
740 tcg_gen_add_i32(addr
, REG(B7_4
), REG(0));
741 tcg_gen_qemu_ld16s(REG(B11_8
), addr
, ctx
->memidx
);
745 case 0x000e: /* mov.l @(R0,Rm),Rn */
747 TCGv addr
= tcg_temp_new();
748 tcg_gen_add_i32(addr
, REG(B7_4
), REG(0));
749 tcg_gen_qemu_ld32s(REG(B11_8
), addr
, ctx
->memidx
);
753 case 0x6008: /* swap.b Rm,Rn */
755 TCGv highw
, high
, low
;
756 highw
= tcg_temp_new();
757 tcg_gen_andi_i32(highw
, REG(B7_4
), 0xffff0000);
758 high
= tcg_temp_new();
759 tcg_gen_ext8u_i32(high
, REG(B7_4
));
760 tcg_gen_shli_i32(high
, high
, 8);
761 low
= tcg_temp_new();
762 tcg_gen_shri_i32(low
, REG(B7_4
), 8);
763 tcg_gen_ext8u_i32(low
, low
);
764 tcg_gen_or_i32(REG(B11_8
), high
, low
);
765 tcg_gen_or_i32(REG(B11_8
), REG(B11_8
), highw
);
770 case 0x6009: /* swap.w Rm,Rn */
773 high
= tcg_temp_new();
774 tcg_gen_ext16u_i32(high
, REG(B7_4
));
775 tcg_gen_shli_i32(high
, high
, 16);
776 low
= tcg_temp_new();
777 tcg_gen_shri_i32(low
, REG(B7_4
), 16);
778 tcg_gen_ext16u_i32(low
, low
);
779 tcg_gen_or_i32(REG(B11_8
), high
, low
);
784 case 0x200d: /* xtrct Rm,Rn */
787 high
= tcg_temp_new();
788 tcg_gen_ext16u_i32(high
, REG(B7_4
));
789 tcg_gen_shli_i32(high
, high
, 16);
790 low
= tcg_temp_new();
791 tcg_gen_shri_i32(low
, REG(B11_8
), 16);
792 tcg_gen_ext16u_i32(low
, low
);
793 tcg_gen_or_i32(REG(B11_8
), high
, low
);
798 case 0x300c: /* add Rm,Rn */
799 tcg_gen_add_i32(REG(B11_8
), REG(B11_8
), REG(B7_4
));
801 case 0x300e: /* addc Rm,Rn */
802 gen_helper_addc(REG(B11_8
), REG(B7_4
), REG(B11_8
));
804 case 0x300f: /* addv Rm,Rn */
805 gen_helper_addv(REG(B11_8
), REG(B7_4
), REG(B11_8
));
807 case 0x2009: /* and Rm,Rn */
808 tcg_gen_and_i32(REG(B11_8
), REG(B11_8
), REG(B7_4
));
810 case 0x3000: /* cmp/eq Rm,Rn */
811 gen_cmp(TCG_COND_EQ
, REG(B7_4
), REG(B11_8
));
813 case 0x3003: /* cmp/ge Rm,Rn */
814 gen_cmp(TCG_COND_GE
, REG(B7_4
), REG(B11_8
));
816 case 0x3007: /* cmp/gt Rm,Rn */
817 gen_cmp(TCG_COND_GT
, REG(B7_4
), REG(B11_8
));
819 case 0x3006: /* cmp/hi Rm,Rn */
820 gen_cmp(TCG_COND_GTU
, REG(B7_4
), REG(B11_8
));
822 case 0x3002: /* cmp/hs Rm,Rn */
823 gen_cmp(TCG_COND_GEU
, REG(B7_4
), REG(B11_8
));
825 case 0x200c: /* cmp/str Rm,Rn */
827 int label1
= gen_new_label();
828 int label2
= gen_new_label();
829 TCGv cmp1
= tcg_temp_local_new();
830 TCGv cmp2
= tcg_temp_local_new();
831 tcg_gen_xor_i32(cmp1
, REG(B7_4
), REG(B11_8
));
832 tcg_gen_andi_i32(cmp2
, cmp1
, 0xff000000);
833 tcg_gen_brcondi_i32(TCG_COND_EQ
, cmp2
, 0, label1
);
834 tcg_gen_andi_i32(cmp2
, cmp1
, 0x00ff0000);
835 tcg_gen_brcondi_i32(TCG_COND_EQ
, cmp2
, 0, label1
);
836 tcg_gen_andi_i32(cmp2
, cmp1
, 0x0000ff00);
837 tcg_gen_brcondi_i32(TCG_COND_EQ
, cmp2
, 0, label1
);
838 tcg_gen_andi_i32(cmp2
, cmp1
, 0x000000ff);
839 tcg_gen_brcondi_i32(TCG_COND_EQ
, cmp2
, 0, label1
);
840 tcg_gen_andi_i32(cpu_sr
, cpu_sr
, ~SR_T
);
842 gen_set_label(label1
);
843 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, SR_T
);
844 gen_set_label(label2
);
849 case 0x2007: /* div0s Rm,Rn */
851 gen_copy_bit_i32(cpu_sr
, 8, REG(B11_8
), 31); /* SR_Q */
852 gen_copy_bit_i32(cpu_sr
, 9, REG(B7_4
), 31); /* SR_M */
853 TCGv val
= tcg_temp_new();
854 tcg_gen_xor_i32(val
, REG(B7_4
), REG(B11_8
));
855 gen_copy_bit_i32(cpu_sr
, 0, val
, 31); /* SR_T */
859 case 0x3004: /* div1 Rm,Rn */
860 gen_helper_div1(REG(B11_8
), REG(B7_4
), REG(B11_8
));
862 case 0x300d: /* dmuls.l Rm,Rn */
864 TCGv_i64 tmp1
= tcg_temp_new_i64();
865 TCGv_i64 tmp2
= tcg_temp_new_i64();
867 tcg_gen_ext_i32_i64(tmp1
, REG(B7_4
));
868 tcg_gen_ext_i32_i64(tmp2
, REG(B11_8
));
869 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
870 tcg_gen_trunc_i64_i32(cpu_macl
, tmp1
);
871 tcg_gen_shri_i64(tmp1
, tmp1
, 32);
872 tcg_gen_trunc_i64_i32(cpu_mach
, tmp1
);
874 tcg_temp_free_i64(tmp2
);
875 tcg_temp_free_i64(tmp1
);
878 case 0x3005: /* dmulu.l Rm,Rn */
880 TCGv_i64 tmp1
= tcg_temp_new_i64();
881 TCGv_i64 tmp2
= tcg_temp_new_i64();
883 tcg_gen_extu_i32_i64(tmp1
, REG(B7_4
));
884 tcg_gen_extu_i32_i64(tmp2
, REG(B11_8
));
885 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
886 tcg_gen_trunc_i64_i32(cpu_macl
, tmp1
);
887 tcg_gen_shri_i64(tmp1
, tmp1
, 32);
888 tcg_gen_trunc_i64_i32(cpu_mach
, tmp1
);
890 tcg_temp_free_i64(tmp2
);
891 tcg_temp_free_i64(tmp1
);
894 case 0x600e: /* exts.b Rm,Rn */
895 tcg_gen_ext8s_i32(REG(B11_8
), REG(B7_4
));
897 case 0x600f: /* exts.w Rm,Rn */
898 tcg_gen_ext16s_i32(REG(B11_8
), REG(B7_4
));
900 case 0x600c: /* extu.b Rm,Rn */
901 tcg_gen_ext8u_i32(REG(B11_8
), REG(B7_4
));
903 case 0x600d: /* extu.w Rm,Rn */
904 tcg_gen_ext16u_i32(REG(B11_8
), REG(B7_4
));
906 case 0x000f: /* mac.l @Rm+,@Rn+ */
909 arg0
= tcg_temp_new();
910 tcg_gen_qemu_ld32s(arg0
, REG(B7_4
), ctx
->memidx
);
911 arg1
= tcg_temp_new();
912 tcg_gen_qemu_ld32s(arg1
, REG(B11_8
), ctx
->memidx
);
913 gen_helper_macl(arg0
, arg1
);
916 tcg_gen_addi_i32(REG(B7_4
), REG(B7_4
), 4);
917 tcg_gen_addi_i32(REG(B11_8
), REG(B11_8
), 4);
920 case 0x400f: /* mac.w @Rm+,@Rn+ */
923 arg0
= tcg_temp_new();
924 tcg_gen_qemu_ld32s(arg0
, REG(B7_4
), ctx
->memidx
);
925 arg1
= tcg_temp_new();
926 tcg_gen_qemu_ld32s(arg1
, REG(B11_8
), ctx
->memidx
);
927 gen_helper_macw(arg0
, arg1
);
930 tcg_gen_addi_i32(REG(B11_8
), REG(B11_8
), 2);
931 tcg_gen_addi_i32(REG(B7_4
), REG(B7_4
), 2);
934 case 0x0007: /* mul.l Rm,Rn */
935 tcg_gen_mul_i32(cpu_macl
, REG(B7_4
), REG(B11_8
));
937 case 0x200f: /* muls.w Rm,Rn */
940 arg0
= tcg_temp_new();
941 tcg_gen_ext16s_i32(arg0
, REG(B7_4
));
942 arg1
= tcg_temp_new();
943 tcg_gen_ext16s_i32(arg1
, REG(B11_8
));
944 tcg_gen_mul_i32(cpu_macl
, arg0
, arg1
);
949 case 0x200e: /* mulu.w Rm,Rn */
952 arg0
= tcg_temp_new();
953 tcg_gen_ext16u_i32(arg0
, REG(B7_4
));
954 arg1
= tcg_temp_new();
955 tcg_gen_ext16u_i32(arg1
, REG(B11_8
));
956 tcg_gen_mul_i32(cpu_macl
, arg0
, arg1
);
961 case 0x600b: /* neg Rm,Rn */
962 tcg_gen_neg_i32(REG(B11_8
), REG(B7_4
));
964 case 0x600a: /* negc Rm,Rn */
965 gen_helper_negc(REG(B11_8
), REG(B7_4
));
967 case 0x6007: /* not Rm,Rn */
968 tcg_gen_not_i32(REG(B11_8
), REG(B7_4
));
970 case 0x200b: /* or Rm,Rn */
971 tcg_gen_or_i32(REG(B11_8
), REG(B11_8
), REG(B7_4
));
973 case 0x400c: /* shad Rm,Rn */
975 int label1
= gen_new_label();
976 int label2
= gen_new_label();
977 int label3
= gen_new_label();
978 int label4
= gen_new_label();
979 TCGv shift
= tcg_temp_local_new();
980 tcg_gen_brcondi_i32(TCG_COND_LT
, REG(B7_4
), 0, label1
);
981 /* Rm positive, shift to the left */
982 tcg_gen_andi_i32(shift
, REG(B7_4
), 0x1f);
983 tcg_gen_shl_i32(REG(B11_8
), REG(B11_8
), shift
);
985 /* Rm negative, shift to the right */
986 gen_set_label(label1
);
987 tcg_gen_andi_i32(shift
, REG(B7_4
), 0x1f);
988 tcg_gen_brcondi_i32(TCG_COND_EQ
, shift
, 0, label2
);
989 tcg_gen_not_i32(shift
, REG(B7_4
));
990 tcg_gen_andi_i32(shift
, shift
, 0x1f);
991 tcg_gen_addi_i32(shift
, shift
, 1);
992 tcg_gen_sar_i32(REG(B11_8
), REG(B11_8
), shift
);
995 gen_set_label(label2
);
996 tcg_gen_brcondi_i32(TCG_COND_LT
, REG(B11_8
), 0, label3
);
997 tcg_gen_movi_i32(REG(B11_8
), 0);
999 gen_set_label(label3
);
1000 tcg_gen_movi_i32(REG(B11_8
), 0xffffffff);
1001 gen_set_label(label4
);
1002 tcg_temp_free(shift
);
1005 case 0x400d: /* shld Rm,Rn */
1007 int label1
= gen_new_label();
1008 int label2
= gen_new_label();
1009 int label3
= gen_new_label();
1010 TCGv shift
= tcg_temp_local_new();
1011 tcg_gen_brcondi_i32(TCG_COND_LT
, REG(B7_4
), 0, label1
);
1012 /* Rm positive, shift to the left */
1013 tcg_gen_andi_i32(shift
, REG(B7_4
), 0x1f);
1014 tcg_gen_shl_i32(REG(B11_8
), REG(B11_8
), shift
);
1016 /* Rm negative, shift to the right */
1017 gen_set_label(label1
);
1018 tcg_gen_andi_i32(shift
, REG(B7_4
), 0x1f);
1019 tcg_gen_brcondi_i32(TCG_COND_EQ
, shift
, 0, label2
);
1020 tcg_gen_not_i32(shift
, REG(B7_4
));
1021 tcg_gen_andi_i32(shift
, shift
, 0x1f);
1022 tcg_gen_addi_i32(shift
, shift
, 1);
1023 tcg_gen_shr_i32(REG(B11_8
), REG(B11_8
), shift
);
1026 gen_set_label(label2
);
1027 tcg_gen_movi_i32(REG(B11_8
), 0);
1028 gen_set_label(label3
);
1029 tcg_temp_free(shift
);
1032 case 0x3008: /* sub Rm,Rn */
1033 tcg_gen_sub_i32(REG(B11_8
), REG(B11_8
), REG(B7_4
));
1035 case 0x300a: /* subc Rm,Rn */
1036 gen_helper_subc(REG(B11_8
), REG(B7_4
), REG(B11_8
));
1038 case 0x300b: /* subv Rm,Rn */
1039 gen_helper_subv(REG(B11_8
), REG(B7_4
), REG(B11_8
));
1041 case 0x2008: /* tst Rm,Rn */
1043 TCGv val
= tcg_temp_new();
1044 tcg_gen_and_i32(val
, REG(B7_4
), REG(B11_8
));
1045 gen_cmp_imm(TCG_COND_EQ
, val
, 0);
1049 case 0x200a: /* xor Rm,Rn */
1050 tcg_gen_xor_i32(REG(B11_8
), REG(B11_8
), REG(B7_4
));
1052 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
1054 if (ctx
->fpscr
& FPSCR_SZ
) {
1055 TCGv_i64 fp
= tcg_temp_new_i64();
1056 gen_load_fpr64(fp
, XREG(B7_4
));
1057 gen_store_fpr64(fp
, XREG(B11_8
));
1058 tcg_temp_free_i64(fp
);
1060 tcg_gen_mov_i32(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B7_4
)]);
1063 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
1065 if (ctx
->fpscr
& FPSCR_SZ
) {
1066 TCGv addr_hi
= tcg_temp_new();
1067 int fr
= XREG(B7_4
);
1068 tcg_gen_addi_i32(addr_hi
, REG(B11_8
), 4);
1069 tcg_gen_qemu_st32(cpu_fregs
[fr
], REG(B11_8
), ctx
->memidx
);
1070 tcg_gen_qemu_st32(cpu_fregs
[fr
+1], addr_hi
, ctx
->memidx
);
1071 tcg_temp_free(addr_hi
);
1073 tcg_gen_qemu_st32(cpu_fregs
[FREG(B7_4
)], REG(B11_8
), ctx
->memidx
);
1076 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
1078 if (ctx
->fpscr
& FPSCR_SZ
) {
1079 TCGv addr_hi
= tcg_temp_new();
1080 int fr
= XREG(B11_8
);
1081 tcg_gen_addi_i32(addr_hi
, REG(B7_4
), 4);
1082 tcg_gen_qemu_ld32u(cpu_fregs
[fr
], REG(B7_4
), ctx
->memidx
);
1083 tcg_gen_qemu_ld32u(cpu_fregs
[fr
+1], addr_hi
, ctx
->memidx
);
1084 tcg_temp_free(addr_hi
);
1086 tcg_gen_qemu_ld32u(cpu_fregs
[FREG(B11_8
)], REG(B7_4
), ctx
->memidx
);
1089 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
1091 if (ctx
->fpscr
& FPSCR_SZ
) {
1092 TCGv addr_hi
= tcg_temp_new();
1093 int fr
= XREG(B11_8
);
1094 tcg_gen_addi_i32(addr_hi
, REG(B7_4
), 4);
1095 tcg_gen_qemu_ld32u(cpu_fregs
[fr
], REG(B7_4
), ctx
->memidx
);
1096 tcg_gen_qemu_ld32u(cpu_fregs
[fr
+1], addr_hi
, ctx
->memidx
);
1097 tcg_gen_addi_i32(REG(B7_4
), REG(B7_4
), 8);
1098 tcg_temp_free(addr_hi
);
1100 tcg_gen_qemu_ld32u(cpu_fregs
[FREG(B11_8
)], REG(B7_4
), ctx
->memidx
);
1101 tcg_gen_addi_i32(REG(B7_4
), REG(B7_4
), 4);
1104 case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
1106 if (ctx
->fpscr
& FPSCR_SZ
) {
1107 TCGv addr
= tcg_temp_new_i32();
1108 int fr
= XREG(B7_4
);
1109 tcg_gen_subi_i32(addr
, REG(B11_8
), 4);
1110 tcg_gen_qemu_st32(cpu_fregs
[fr
+1], addr
, ctx
->memidx
);
1111 tcg_gen_subi_i32(addr
, REG(B11_8
), 8);
1112 tcg_gen_qemu_st32(cpu_fregs
[fr
], addr
, ctx
->memidx
);
1113 tcg_gen_mov_i32(REG(B11_8
), addr
);
1114 tcg_temp_free(addr
);
1117 addr
= tcg_temp_new_i32();
1118 tcg_gen_subi_i32(addr
, REG(B11_8
), 4);
1119 tcg_gen_qemu_st32(cpu_fregs
[FREG(B7_4
)], addr
, ctx
->memidx
);
1120 tcg_temp_free(addr
);
1121 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 4);
1124 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
1127 TCGv addr
= tcg_temp_new_i32();
1128 tcg_gen_add_i32(addr
, REG(B7_4
), REG(0));
1129 if (ctx
->fpscr
& FPSCR_SZ
) {
1130 int fr
= XREG(B11_8
);
1131 tcg_gen_qemu_ld32u(cpu_fregs
[fr
], addr
, ctx
->memidx
);
1132 tcg_gen_addi_i32(addr
, addr
, 4);
1133 tcg_gen_qemu_ld32u(cpu_fregs
[fr
+1], addr
, ctx
->memidx
);
1135 tcg_gen_qemu_ld32u(cpu_fregs
[FREG(B11_8
)], addr
, ctx
->memidx
);
1137 tcg_temp_free(addr
);
1140 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
1143 TCGv addr
= tcg_temp_new();
1144 tcg_gen_add_i32(addr
, REG(B11_8
), REG(0));
1145 if (ctx
->fpscr
& FPSCR_SZ
) {
1146 int fr
= XREG(B7_4
);
1147 tcg_gen_qemu_ld32u(cpu_fregs
[fr
], addr
, ctx
->memidx
);
1148 tcg_gen_addi_i32(addr
, addr
, 4);
1149 tcg_gen_qemu_ld32u(cpu_fregs
[fr
+1], addr
, ctx
->memidx
);
1151 tcg_gen_qemu_st32(cpu_fregs
[FREG(B7_4
)], addr
, ctx
->memidx
);
1153 tcg_temp_free(addr
);
1156 case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1157 case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1158 case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1159 case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1160 case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1161 case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1164 if (ctx
->fpscr
& FPSCR_PR
) {
1167 if (ctx
->opcode
& 0x0110)
1168 break; /* illegal instruction */
1169 fp0
= tcg_temp_new_i64();
1170 fp1
= tcg_temp_new_i64();
1171 gen_load_fpr64(fp0
, DREG(B11_8
));
1172 gen_load_fpr64(fp1
, DREG(B7_4
));
1173 switch (ctx
->opcode
& 0xf00f) {
1174 case 0xf000: /* fadd Rm,Rn */
1175 gen_helper_fadd_DT(fp0
, fp0
, fp1
);
1177 case 0xf001: /* fsub Rm,Rn */
1178 gen_helper_fsub_DT(fp0
, fp0
, fp1
);
1180 case 0xf002: /* fmul Rm,Rn */
1181 gen_helper_fmul_DT(fp0
, fp0
, fp1
);
1183 case 0xf003: /* fdiv Rm,Rn */
1184 gen_helper_fdiv_DT(fp0
, fp0
, fp1
);
1186 case 0xf004: /* fcmp/eq Rm,Rn */
1187 gen_helper_fcmp_eq_DT(fp0
, fp1
);
1189 case 0xf005: /* fcmp/gt Rm,Rn */
1190 gen_helper_fcmp_gt_DT(fp0
, fp1
);
1193 gen_store_fpr64(fp0
, DREG(B11_8
));
1194 tcg_temp_free_i64(fp0
);
1195 tcg_temp_free_i64(fp1
);
1197 switch (ctx
->opcode
& 0xf00f) {
1198 case 0xf000: /* fadd Rm,Rn */
1199 gen_helper_fadd_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B7_4
)]);
1201 case 0xf001: /* fsub Rm,Rn */
1202 gen_helper_fsub_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B7_4
)]);
1204 case 0xf002: /* fmul Rm,Rn */
1205 gen_helper_fmul_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B7_4
)]);
1207 case 0xf003: /* fdiv Rm,Rn */
1208 gen_helper_fdiv_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B7_4
)]);
1210 case 0xf004: /* fcmp/eq Rm,Rn */
1211 gen_helper_fcmp_eq_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B7_4
)]);
1213 case 0xf005: /* fcmp/gt Rm,Rn */
1214 gen_helper_fcmp_gt_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B7_4
)]);
1220 case 0xf00e: /* fmac FR0,RM,Rn */
1223 if (ctx
->fpscr
& FPSCR_PR
) {
1224 break; /* illegal instruction */
1226 gen_helper_fmac_FT(cpu_fregs
[FREG(B11_8
)],
1227 cpu_fregs
[FREG(0)], cpu_fregs
[FREG(B7_4
)], cpu_fregs
[FREG(B11_8
)]);
1233 switch (ctx
->opcode
& 0xff00) {
1234 case 0xc900: /* and #imm,R0 */
1235 tcg_gen_andi_i32(REG(0), REG(0), B7_0
);
1237 case 0xcd00: /* and.b #imm,@(R0,GBR) */
1240 addr
= tcg_temp_new();
1241 tcg_gen_add_i32(addr
, REG(0), cpu_gbr
);
1242 val
= tcg_temp_new();
1243 tcg_gen_qemu_ld8u(val
, addr
, ctx
->memidx
);
1244 tcg_gen_andi_i32(val
, val
, B7_0
);
1245 tcg_gen_qemu_st8(val
, addr
, ctx
->memidx
);
1247 tcg_temp_free(addr
);
1250 case 0x8b00: /* bf label */
1251 CHECK_NOT_DELAY_SLOT
1252 gen_conditional_jump(ctx
, ctx
->pc
+ 2,
1253 ctx
->pc
+ 4 + B7_0s
* 2);
1254 ctx
->bstate
= BS_BRANCH
;
1256 case 0x8f00: /* bf/s label */
1257 CHECK_NOT_DELAY_SLOT
1258 gen_branch_slot(ctx
->delayed_pc
= ctx
->pc
+ 4 + B7_0s
* 2, 0);
1259 ctx
->flags
|= DELAY_SLOT_CONDITIONAL
;
1261 case 0x8900: /* bt label */
1262 CHECK_NOT_DELAY_SLOT
1263 gen_conditional_jump(ctx
, ctx
->pc
+ 4 + B7_0s
* 2,
1265 ctx
->bstate
= BS_BRANCH
;
1267 case 0x8d00: /* bt/s label */
1268 CHECK_NOT_DELAY_SLOT
1269 gen_branch_slot(ctx
->delayed_pc
= ctx
->pc
+ 4 + B7_0s
* 2, 1);
1270 ctx
->flags
|= DELAY_SLOT_CONDITIONAL
;
1272 case 0x8800: /* cmp/eq #imm,R0 */
1273 gen_cmp_imm(TCG_COND_EQ
, REG(0), B7_0s
);
1275 case 0xc400: /* mov.b @(disp,GBR),R0 */
1277 TCGv addr
= tcg_temp_new();
1278 tcg_gen_addi_i32(addr
, cpu_gbr
, B7_0
);
1279 tcg_gen_qemu_ld8s(REG(0), addr
, ctx
->memidx
);
1280 tcg_temp_free(addr
);
1283 case 0xc500: /* mov.w @(disp,GBR),R0 */
1285 TCGv addr
= tcg_temp_new();
1286 tcg_gen_addi_i32(addr
, cpu_gbr
, B7_0
* 2);
1287 tcg_gen_qemu_ld16s(REG(0), addr
, ctx
->memidx
);
1288 tcg_temp_free(addr
);
1291 case 0xc600: /* mov.l @(disp,GBR),R0 */
1293 TCGv addr
= tcg_temp_new();
1294 tcg_gen_addi_i32(addr
, cpu_gbr
, B7_0
* 4);
1295 tcg_gen_qemu_ld32s(REG(0), addr
, ctx
->memidx
);
1296 tcg_temp_free(addr
);
1299 case 0xc000: /* mov.b R0,@(disp,GBR) */
1301 TCGv addr
= tcg_temp_new();
1302 tcg_gen_addi_i32(addr
, cpu_gbr
, B7_0
);
1303 tcg_gen_qemu_st8(REG(0), addr
, ctx
->memidx
);
1304 tcg_temp_free(addr
);
1307 case 0xc100: /* mov.w R0,@(disp,GBR) */
1309 TCGv addr
= tcg_temp_new();
1310 tcg_gen_addi_i32(addr
, cpu_gbr
, B7_0
* 2);
1311 tcg_gen_qemu_st16(REG(0), addr
, ctx
->memidx
);
1312 tcg_temp_free(addr
);
1315 case 0xc200: /* mov.l R0,@(disp,GBR) */
1317 TCGv addr
= tcg_temp_new();
1318 tcg_gen_addi_i32(addr
, cpu_gbr
, B7_0
* 4);
1319 tcg_gen_qemu_st32(REG(0), addr
, ctx
->memidx
);
1320 tcg_temp_free(addr
);
1323 case 0x8000: /* mov.b R0,@(disp,Rn) */
1325 TCGv addr
= tcg_temp_new();
1326 tcg_gen_addi_i32(addr
, REG(B7_4
), B3_0
);
1327 tcg_gen_qemu_st8(REG(0), addr
, ctx
->memidx
);
1328 tcg_temp_free(addr
);
1331 case 0x8100: /* mov.w R0,@(disp,Rn) */
1333 TCGv addr
= tcg_temp_new();
1334 tcg_gen_addi_i32(addr
, REG(B7_4
), B3_0
* 2);
1335 tcg_gen_qemu_st16(REG(0), addr
, ctx
->memidx
);
1336 tcg_temp_free(addr
);
1339 case 0x8400: /* mov.b @(disp,Rn),R0 */
1341 TCGv addr
= tcg_temp_new();
1342 tcg_gen_addi_i32(addr
, REG(B7_4
), B3_0
);
1343 tcg_gen_qemu_ld8s(REG(0), addr
, ctx
->memidx
);
1344 tcg_temp_free(addr
);
1347 case 0x8500: /* mov.w @(disp,Rn),R0 */
1349 TCGv addr
= tcg_temp_new();
1350 tcg_gen_addi_i32(addr
, REG(B7_4
), B3_0
* 2);
1351 tcg_gen_qemu_ld16s(REG(0), addr
, ctx
->memidx
);
1352 tcg_temp_free(addr
);
1355 case 0xc700: /* mova @(disp,PC),R0 */
1356 tcg_gen_movi_i32(REG(0), ((ctx
->pc
& 0xfffffffc) + 4 + B7_0
* 4) & ~3);
1358 case 0xcb00: /* or #imm,R0 */
1359 tcg_gen_ori_i32(REG(0), REG(0), B7_0
);
1361 case 0xcf00: /* or.b #imm,@(R0,GBR) */
1364 addr
= tcg_temp_new();
1365 tcg_gen_add_i32(addr
, REG(0), cpu_gbr
);
1366 val
= tcg_temp_new();
1367 tcg_gen_qemu_ld8u(val
, addr
, ctx
->memidx
);
1368 tcg_gen_ori_i32(val
, val
, B7_0
);
1369 tcg_gen_qemu_st8(val
, addr
, ctx
->memidx
);
1371 tcg_temp_free(addr
);
1374 case 0xc300: /* trapa #imm */
1377 CHECK_NOT_DELAY_SLOT
1378 tcg_gen_movi_i32(cpu_pc
, ctx
->pc
);
1379 imm
= tcg_const_i32(B7_0
);
1380 gen_helper_trapa(imm
);
1382 ctx
->bstate
= BS_BRANCH
;
1385 case 0xc800: /* tst #imm,R0 */
1387 TCGv val
= tcg_temp_new();
1388 tcg_gen_andi_i32(val
, REG(0), B7_0
);
1389 gen_cmp_imm(TCG_COND_EQ
, val
, 0);
1393 case 0xcc00: /* tst.b #imm,@(R0,GBR) */
1395 TCGv val
= tcg_temp_new();
1396 tcg_gen_add_i32(val
, REG(0), cpu_gbr
);
1397 tcg_gen_qemu_ld8u(val
, val
, ctx
->memidx
);
1398 tcg_gen_andi_i32(val
, val
, B7_0
);
1399 gen_cmp_imm(TCG_COND_EQ
, val
, 0);
1403 case 0xca00: /* xor #imm,R0 */
1404 tcg_gen_xori_i32(REG(0), REG(0), B7_0
);
1406 case 0xce00: /* xor.b #imm,@(R0,GBR) */
1409 addr
= tcg_temp_new();
1410 tcg_gen_add_i32(addr
, REG(0), cpu_gbr
);
1411 val
= tcg_temp_new();
1412 tcg_gen_qemu_ld8u(val
, addr
, ctx
->memidx
);
1413 tcg_gen_xori_i32(val
, val
, B7_0
);
1414 tcg_gen_qemu_st8(val
, addr
, ctx
->memidx
);
1416 tcg_temp_free(addr
);
1421 switch (ctx
->opcode
& 0xf08f) {
1422 case 0x408e: /* ldc Rm,Rn_BANK */
1424 tcg_gen_mov_i32(ALTREG(B6_4
), REG(B11_8
));
1426 case 0x4087: /* ldc.l @Rm+,Rn_BANK */
1428 tcg_gen_qemu_ld32s(ALTREG(B6_4
), REG(B11_8
), ctx
->memidx
);
1429 tcg_gen_addi_i32(REG(B11_8
), REG(B11_8
), 4);
1431 case 0x0082: /* stc Rm_BANK,Rn */
1433 tcg_gen_mov_i32(REG(B11_8
), ALTREG(B6_4
));
1435 case 0x4083: /* stc.l Rm_BANK,@-Rn */
1438 TCGv addr
= tcg_temp_new();
1439 tcg_gen_subi_i32(addr
, REG(B11_8
), 4);
1440 tcg_gen_qemu_st32(ALTREG(B6_4
), addr
, ctx
->memidx
);
1441 tcg_temp_free(addr
);
1442 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 4);
1447 switch (ctx
->opcode
& 0xf0ff) {
1448 case 0x0023: /* braf Rn */
1449 CHECK_NOT_DELAY_SLOT
1450 tcg_gen_addi_i32(cpu_delayed_pc
, REG(B11_8
), ctx
->pc
+ 4);
1451 ctx
->flags
|= DELAY_SLOT
;
1452 ctx
->delayed_pc
= (uint32_t) - 1;
1454 case 0x0003: /* bsrf Rn */
1455 CHECK_NOT_DELAY_SLOT
1456 tcg_gen_movi_i32(cpu_pr
, ctx
->pc
+ 4);
1457 tcg_gen_add_i32(cpu_delayed_pc
, REG(B11_8
), cpu_pr
);
1458 ctx
->flags
|= DELAY_SLOT
;
1459 ctx
->delayed_pc
= (uint32_t) - 1;
1461 case 0x4015: /* cmp/pl Rn */
1462 gen_cmp_imm(TCG_COND_GT
, REG(B11_8
), 0);
1464 case 0x4011: /* cmp/pz Rn */
1465 gen_cmp_imm(TCG_COND_GE
, REG(B11_8
), 0);
1467 case 0x4010: /* dt Rn */
1468 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 1);
1469 gen_cmp_imm(TCG_COND_EQ
, REG(B11_8
), 0);
1471 case 0x402b: /* jmp @Rn */
1472 CHECK_NOT_DELAY_SLOT
1473 tcg_gen_mov_i32(cpu_delayed_pc
, REG(B11_8
));
1474 ctx
->flags
|= DELAY_SLOT
;
1475 ctx
->delayed_pc
= (uint32_t) - 1;
1477 case 0x400b: /* jsr @Rn */
1478 CHECK_NOT_DELAY_SLOT
1479 tcg_gen_movi_i32(cpu_pr
, ctx
->pc
+ 4);
1480 tcg_gen_mov_i32(cpu_delayed_pc
, REG(B11_8
));
1481 ctx
->flags
|= DELAY_SLOT
;
1482 ctx
->delayed_pc
= (uint32_t) - 1;
1484 case 0x400e: /* ldc Rm,SR */
1486 tcg_gen_andi_i32(cpu_sr
, REG(B11_8
), 0x700083f3);
1487 ctx
->bstate
= BS_STOP
;
1489 case 0x4007: /* ldc.l @Rm+,SR */
1492 TCGv val
= tcg_temp_new();
1493 tcg_gen_qemu_ld32s(val
, REG(B11_8
), ctx
->memidx
);
1494 tcg_gen_andi_i32(cpu_sr
, val
, 0x700083f3);
1496 tcg_gen_addi_i32(REG(B11_8
), REG(B11_8
), 4);
1497 ctx
->bstate
= BS_STOP
;
1500 case 0x0002: /* stc SR,Rn */
1502 tcg_gen_mov_i32(REG(B11_8
), cpu_sr
);
1504 case 0x4003: /* stc SR,@-Rn */
1507 TCGv addr
= tcg_temp_new();
1508 tcg_gen_subi_i32(addr
, REG(B11_8
), 4);
1509 tcg_gen_qemu_st32(cpu_sr
, addr
, ctx
->memidx
);
1510 tcg_temp_free(addr
);
1511 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 4);
1514 #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \
1517 tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \
1521 tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \
1522 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \
1526 tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \
1531 TCGv addr = tcg_temp_new(); \
1532 tcg_gen_subi_i32(addr, REG(B11_8), 4); \
1533 tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \
1534 tcg_temp_free(addr); \
1535 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \
1538 LDST(gbr
, 0x401e, 0x4017, 0x0012, 0x4013, {})
1539 LDST(vbr
, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED
)
1540 LDST(ssr
, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED
)
1541 LDST(spc
, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED
)
1542 LDST(dbr
, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED
)
1543 LDST(mach
, 0x400a, 0x4006, 0x000a, 0x4002, {})
1544 LDST(macl
, 0x401a, 0x4016, 0x001a, 0x4012, {})
1545 LDST(pr
, 0x402a, 0x4026, 0x002a, 0x4022, {})
1546 LDST(fpul
, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED
})
1547 case 0x406a: /* lds Rm,FPSCR */
1549 gen_helper_ld_fpscr(REG(B11_8
));
1550 ctx
->bstate
= BS_STOP
;
1552 case 0x4066: /* lds.l @Rm+,FPSCR */
1555 TCGv addr
= tcg_temp_new();
1556 tcg_gen_qemu_ld32s(addr
, REG(B11_8
), ctx
->memidx
);
1557 tcg_gen_addi_i32(REG(B11_8
), REG(B11_8
), 4);
1558 gen_helper_ld_fpscr(addr
);
1559 tcg_temp_free(addr
);
1560 ctx
->bstate
= BS_STOP
;
1563 case 0x006a: /* sts FPSCR,Rn */
1565 tcg_gen_andi_i32(REG(B11_8
), cpu_fpscr
, 0x003fffff);
1567 case 0x4062: /* sts FPSCR,@-Rn */
1571 val
= tcg_temp_new();
1572 tcg_gen_andi_i32(val
, cpu_fpscr
, 0x003fffff);
1573 addr
= tcg_temp_new();
1574 tcg_gen_subi_i32(addr
, REG(B11_8
), 4);
1575 tcg_gen_qemu_st32(val
, addr
, ctx
->memidx
);
1576 tcg_temp_free(addr
);
1578 tcg_gen_subi_i32(REG(B11_8
), REG(B11_8
), 4);
1581 case 0x00c3: /* movca.l R0,@Rm */
1583 TCGv val
= tcg_temp_new();
1584 tcg_gen_qemu_ld32u(val
, REG(B11_8
), ctx
->memidx
);
1585 gen_helper_movcal (REG(B11_8
), val
);
1586 tcg_gen_qemu_st32(REG(0), REG(B11_8
), ctx
->memidx
);
1588 ctx
->has_movcal
= 1;
1591 /* MOVUA.L @Rm,R0 (Rm) -> R0
1592 Load non-boundary-aligned data */
1593 tcg_gen_qemu_ld32u(REG(0), REG(B11_8
), ctx
->memidx
);
1596 /* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm
1597 Load non-boundary-aligned data */
1598 tcg_gen_qemu_ld32u(REG(0), REG(B11_8
), ctx
->memidx
);
1599 tcg_gen_addi_i32(REG(B11_8
), REG(B11_8
), 4);
1601 case 0x0029: /* movt Rn */
1602 tcg_gen_andi_i32(REG(B11_8
), cpu_sr
, SR_T
);
1607 If (T == 1) R0 -> (Rn)
1610 if (ctx
->features
& SH_FEATURE_SH4A
) {
1611 int label
= gen_new_label();
1613 tcg_gen_or_i32(cpu_sr
, cpu_sr
, cpu_ldst
);
1614 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_ldst
, 0, label
);
1615 tcg_gen_qemu_st32(REG(0), REG(B11_8
), ctx
->memidx
);
1616 gen_set_label(label
);
1617 tcg_gen_movi_i32(cpu_ldst
, 0);
1625 When interrupt/exception
1628 if (ctx
->features
& SH_FEATURE_SH4A
) {
1629 tcg_gen_movi_i32(cpu_ldst
, 0);
1630 tcg_gen_qemu_ld32s(REG(0), REG(B11_8
), ctx
->memidx
);
1631 tcg_gen_movi_i32(cpu_ldst
, 1);
1635 case 0x0093: /* ocbi @Rn */
1637 gen_helper_ocbi (REG(B11_8
));
1640 case 0x00a3: /* ocbp @Rn */
1642 TCGv dummy
= tcg_temp_new();
1643 tcg_gen_qemu_ld32s(dummy
, REG(B11_8
), ctx
->memidx
);
1644 tcg_temp_free(dummy
);
1647 case 0x00b3: /* ocbwb @Rn */
1649 TCGv dummy
= tcg_temp_new();
1650 tcg_gen_qemu_ld32s(dummy
, REG(B11_8
), ctx
->memidx
);
1651 tcg_temp_free(dummy
);
1654 case 0x0083: /* pref @Rn */
1656 case 0x00d3: /* prefi @Rn */
1657 if (ctx
->features
& SH_FEATURE_SH4A
)
1661 case 0x00e3: /* icbi @Rn */
1662 if (ctx
->features
& SH_FEATURE_SH4A
)
1666 case 0x00ab: /* synco */
1667 if (ctx
->features
& SH_FEATURE_SH4A
)
1671 case 0x4024: /* rotcl Rn */
1673 TCGv tmp
= tcg_temp_new();
1674 tcg_gen_mov_i32(tmp
, cpu_sr
);
1675 gen_copy_bit_i32(cpu_sr
, 0, REG(B11_8
), 31);
1676 tcg_gen_shli_i32(REG(B11_8
), REG(B11_8
), 1);
1677 gen_copy_bit_i32(REG(B11_8
), 0, tmp
, 0);
1681 case 0x4025: /* rotcr Rn */
1683 TCGv tmp
= tcg_temp_new();
1684 tcg_gen_mov_i32(tmp
, cpu_sr
);
1685 gen_copy_bit_i32(cpu_sr
, 0, REG(B11_8
), 0);
1686 tcg_gen_shri_i32(REG(B11_8
), REG(B11_8
), 1);
1687 gen_copy_bit_i32(REG(B11_8
), 31, tmp
, 0);
1691 case 0x4004: /* rotl Rn */
1692 gen_copy_bit_i32(cpu_sr
, 0, REG(B11_8
), 31);
1693 tcg_gen_shli_i32(REG(B11_8
), REG(B11_8
), 1);
1694 gen_copy_bit_i32(REG(B11_8
), 0, cpu_sr
, 0);
1696 case 0x4005: /* rotr Rn */
1697 gen_copy_bit_i32(cpu_sr
, 0, REG(B11_8
), 0);
1698 tcg_gen_shri_i32(REG(B11_8
), REG(B11_8
), 1);
1699 gen_copy_bit_i32(REG(B11_8
), 31, cpu_sr
, 0);
1701 case 0x4000: /* shll Rn */
1702 case 0x4020: /* shal Rn */
1703 gen_copy_bit_i32(cpu_sr
, 0, REG(B11_8
), 31);
1704 tcg_gen_shli_i32(REG(B11_8
), REG(B11_8
), 1);
1706 case 0x4021: /* shar Rn */
1707 gen_copy_bit_i32(cpu_sr
, 0, REG(B11_8
), 0);
1708 tcg_gen_sari_i32(REG(B11_8
), REG(B11_8
), 1);
1710 case 0x4001: /* shlr Rn */
1711 gen_copy_bit_i32(cpu_sr
, 0, REG(B11_8
), 0);
1712 tcg_gen_shri_i32(REG(B11_8
), REG(B11_8
), 1);
1714 case 0x4008: /* shll2 Rn */
1715 tcg_gen_shli_i32(REG(B11_8
), REG(B11_8
), 2);
1717 case 0x4018: /* shll8 Rn */
1718 tcg_gen_shli_i32(REG(B11_8
), REG(B11_8
), 8);
1720 case 0x4028: /* shll16 Rn */
1721 tcg_gen_shli_i32(REG(B11_8
), REG(B11_8
), 16);
1723 case 0x4009: /* shlr2 Rn */
1724 tcg_gen_shri_i32(REG(B11_8
), REG(B11_8
), 2);
1726 case 0x4019: /* shlr8 Rn */
1727 tcg_gen_shri_i32(REG(B11_8
), REG(B11_8
), 8);
1729 case 0x4029: /* shlr16 Rn */
1730 tcg_gen_shri_i32(REG(B11_8
), REG(B11_8
), 16);
1732 case 0x401b: /* tas.b @Rn */
1735 addr
= tcg_temp_local_new();
1736 tcg_gen_mov_i32(addr
, REG(B11_8
));
1737 val
= tcg_temp_local_new();
1738 tcg_gen_qemu_ld8u(val
, addr
, ctx
->memidx
);
1739 gen_cmp_imm(TCG_COND_EQ
, val
, 0);
1740 tcg_gen_ori_i32(val
, val
, 0x80);
1741 tcg_gen_qemu_st8(val
, addr
, ctx
->memidx
);
1743 tcg_temp_free(addr
);
1746 case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
1748 tcg_gen_mov_i32(cpu_fregs
[FREG(B11_8
)], cpu_fpul
);
1750 case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
1752 tcg_gen_mov_i32(cpu_fpul
, cpu_fregs
[FREG(B11_8
)]);
1754 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
1756 if (ctx
->fpscr
& FPSCR_PR
) {
1758 if (ctx
->opcode
& 0x0100)
1759 break; /* illegal instruction */
1760 fp
= tcg_temp_new_i64();
1761 gen_helper_float_DT(fp
, cpu_fpul
);
1762 gen_store_fpr64(fp
, DREG(B11_8
));
1763 tcg_temp_free_i64(fp
);
1766 gen_helper_float_FT(cpu_fregs
[FREG(B11_8
)], cpu_fpul
);
1769 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1771 if (ctx
->fpscr
& FPSCR_PR
) {
1773 if (ctx
->opcode
& 0x0100)
1774 break; /* illegal instruction */
1775 fp
= tcg_temp_new_i64();
1776 gen_load_fpr64(fp
, DREG(B11_8
));
1777 gen_helper_ftrc_DT(cpu_fpul
, fp
);
1778 tcg_temp_free_i64(fp
);
1781 gen_helper_ftrc_FT(cpu_fpul
, cpu_fregs
[FREG(B11_8
)]);
1784 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
1787 gen_helper_fneg_T(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B11_8
)]);
1790 case 0xf05d: /* fabs FRn/DRn */
1792 if (ctx
->fpscr
& FPSCR_PR
) {
1793 if (ctx
->opcode
& 0x0100)
1794 break; /* illegal instruction */
1795 TCGv_i64 fp
= tcg_temp_new_i64();
1796 gen_load_fpr64(fp
, DREG(B11_8
));
1797 gen_helper_fabs_DT(fp
, fp
);
1798 gen_store_fpr64(fp
, DREG(B11_8
));
1799 tcg_temp_free_i64(fp
);
1801 gen_helper_fabs_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B11_8
)]);
1804 case 0xf06d: /* fsqrt FRn */
1806 if (ctx
->fpscr
& FPSCR_PR
) {
1807 if (ctx
->opcode
& 0x0100)
1808 break; /* illegal instruction */
1809 TCGv_i64 fp
= tcg_temp_new_i64();
1810 gen_load_fpr64(fp
, DREG(B11_8
));
1811 gen_helper_fsqrt_DT(fp
, fp
);
1812 gen_store_fpr64(fp
, DREG(B11_8
));
1813 tcg_temp_free_i64(fp
);
1815 gen_helper_fsqrt_FT(cpu_fregs
[FREG(B11_8
)], cpu_fregs
[FREG(B11_8
)]);
1818 case 0xf07d: /* fsrra FRn */
1821 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
1823 if (!(ctx
->fpscr
& FPSCR_PR
)) {
1824 tcg_gen_movi_i32(cpu_fregs
[FREG(B11_8
)], 0);
1827 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
1829 if (!(ctx
->fpscr
& FPSCR_PR
)) {
1830 tcg_gen_movi_i32(cpu_fregs
[FREG(B11_8
)], 0x3f800000);
1833 case 0xf0ad: /* fcnvsd FPUL,DRn */
1836 TCGv_i64 fp
= tcg_temp_new_i64();
1837 gen_helper_fcnvsd_FT_DT(fp
, cpu_fpul
);
1838 gen_store_fpr64(fp
, DREG(B11_8
));
1839 tcg_temp_free_i64(fp
);
1842 case 0xf0bd: /* fcnvds DRn,FPUL */
1845 TCGv_i64 fp
= tcg_temp_new_i64();
1846 gen_load_fpr64(fp
, DREG(B11_8
));
1847 gen_helper_fcnvds_DT_FT(cpu_fpul
, fp
);
1848 tcg_temp_free_i64(fp
);
1853 fprintf(stderr
, "unknown instruction 0x%04x at pc 0x%08x\n",
1854 ctx
->opcode
, ctx
->pc
);
1857 gen_helper_raise_illegal_instruction();
1858 ctx
->bstate
= BS_EXCP
;
1861 static void decode_opc(DisasContext
* ctx
)
1863 uint32_t old_flags
= ctx
->flags
;
1867 if (old_flags
& (DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
)) {
1868 if (ctx
->flags
& DELAY_SLOT_CLEARME
) {
1871 /* go out of the delay slot */
1872 uint32_t new_flags
= ctx
->flags
;
1873 new_flags
&= ~(DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
);
1874 gen_store_flags(new_flags
);
1877 ctx
->bstate
= BS_BRANCH
;
1878 if (old_flags
& DELAY_SLOT_CONDITIONAL
) {
1879 gen_delayed_conditional_jump(ctx
);
1880 } else if (old_flags
& DELAY_SLOT
) {
1886 /* go into a delay slot */
1887 if (ctx
->flags
& (DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
))
1888 gen_store_flags(ctx
->flags
);
1892 gen_intermediate_code_internal(CPUState
* env
, TranslationBlock
* tb
,
1896 target_ulong pc_start
;
1897 static uint16_t *gen_opc_end
;
1904 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1906 ctx
.flags
= (uint32_t)tb
->flags
;
1907 ctx
.bstate
= BS_NONE
;
1909 ctx
.fpscr
= env
->fpscr
;
1910 ctx
.memidx
= (env
->sr
& SR_MD
) ? 1 : 0;
1911 /* We don't know if the delayed pc came from a dynamic or static branch,
1912 so assume it is a dynamic branch. */
1913 ctx
.delayed_pc
= -1; /* use delayed pc from env pointer */
1915 ctx
.singlestep_enabled
= env
->singlestep_enabled
;
1916 ctx
.features
= env
->features
;
1917 ctx
.has_movcal
= (tb
->flags
& TB_FLAG_PENDING_MOVCA
);
1920 qemu_log_mask(CPU_LOG_TB_CPU
,
1921 "------------------------------------------------\n");
1922 log_cpu_state_mask(CPU_LOG_TB_CPU
, env
, 0);
1927 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1929 max_insns
= CF_COUNT_MASK
;
1931 while (ctx
.bstate
== BS_NONE
&& gen_opc_ptr
< gen_opc_end
) {
1932 if (unlikely(!TAILQ_EMPTY(&env
->breakpoints
))) {
1933 TAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
1934 if (ctx
.pc
== bp
->pc
) {
1935 /* We have hit a breakpoint - make sure PC is up-to-date */
1936 tcg_gen_movi_i32(cpu_pc
, ctx
.pc
);
1938 ctx
.bstate
= BS_EXCP
;
1944 i
= gen_opc_ptr
- gen_opc_buf
;
1948 gen_opc_instr_start
[ii
++] = 0;
1950 gen_opc_pc
[ii
] = ctx
.pc
;
1951 gen_opc_hflags
[ii
] = ctx
.flags
;
1952 gen_opc_instr_start
[ii
] = 1;
1953 gen_opc_icount
[ii
] = num_insns
;
1955 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
1958 fprintf(stderr
, "Loading opcode at address 0x%08x\n", ctx
.pc
);
1961 ctx
.opcode
= lduw_code(ctx
.pc
);
1965 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
1967 if (env
->singlestep_enabled
)
1969 if (num_insns
>= max_insns
)
1974 if (tb
->cflags
& CF_LAST_IO
)
1976 if (env
->singlestep_enabled
) {
1977 tcg_gen_movi_i32(cpu_pc
, ctx
.pc
);
1980 switch (ctx
.bstate
) {
1982 /* gen_op_interrupt_restart(); */
1986 gen_store_flags(ctx
.flags
| DELAY_SLOT_CLEARME
);
1988 gen_goto_tb(&ctx
, 0, ctx
.pc
);
1991 /* gen_op_interrupt_restart(); */
2000 gen_icount_end(tb
, num_insns
);
2001 *gen_opc_ptr
= INDEX_op_end
;
2003 i
= gen_opc_ptr
- gen_opc_buf
;
2006 gen_opc_instr_start
[ii
++] = 0;
2008 tb
->size
= ctx
.pc
- pc_start
;
2009 tb
->icount
= num_insns
;
2013 #ifdef SH4_DEBUG_DISAS
2014 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "\n");
2016 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
2017 qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */
2018 log_target_disas(pc_start
, ctx
.pc
- pc_start
, 0);
2024 void gen_intermediate_code(CPUState
* env
, struct TranslationBlock
*tb
)
2026 gen_intermediate_code_internal(env
, tb
, 0);
2029 void gen_intermediate_code_pc(CPUState
* env
, struct TranslationBlock
*tb
)
2031 gen_intermediate_code_internal(env
, tb
, 1);
2034 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
2035 unsigned long searched_pc
, int pc_pos
, void *puc
)
2037 env
->pc
= gen_opc_pc
[pc_pos
];
2038 env
->flags
= gen_opc_hflags
[pc_pos
];