2 * Marvell MV88W8618 / Freecom MusicPal emulation.
4 * Copyright (c) 2008 Jan Kiszka
6 * This code is licenced under the GNU GPL v2.
16 #include "qemu-timer.h"
22 #define MP_MISC_BASE 0x80002000
23 #define MP_MISC_SIZE 0x00001000
25 #define MP_ETH_BASE 0x80008000
26 #define MP_ETH_SIZE 0x00001000
28 #define MP_WLAN_BASE 0x8000C000
29 #define MP_WLAN_SIZE 0x00000800
31 #define MP_UART1_BASE 0x8000C840
32 #define MP_UART2_BASE 0x8000C940
34 #define MP_GPIO_BASE 0x8000D000
35 #define MP_GPIO_SIZE 0x00001000
37 #define MP_FLASHCFG_BASE 0x90006000
38 #define MP_FLASHCFG_SIZE 0x00001000
40 #define MP_AUDIO_BASE 0x90007000
42 #define MP_PIC_BASE 0x90008000
43 #define MP_PIC_SIZE 0x00001000
45 #define MP_PIT_BASE 0x90009000
46 #define MP_PIT_SIZE 0x00001000
48 #define MP_LCD_BASE 0x9000c000
49 #define MP_LCD_SIZE 0x00001000
51 #define MP_SRAM_BASE 0xC0000000
52 #define MP_SRAM_SIZE 0x00020000
54 #define MP_RAM_DEFAULT_SIZE 32*1024*1024
55 #define MP_FLASH_SIZE_MAX 32*1024*1024
57 #define MP_TIMER1_IRQ 4
58 #define MP_TIMER2_IRQ 5
59 #define MP_TIMER3_IRQ 6
60 #define MP_TIMER4_IRQ 7
63 #define MP_UART1_IRQ 11
64 #define MP_UART2_IRQ 11
65 #define MP_GPIO_IRQ 12
67 #define MP_AUDIO_IRQ 30
69 /* Wolfson 8750 I2C address */
70 #define MP_WM_ADDR 0x34
72 /* Ethernet register offsets */
73 #define MP_ETH_SMIR 0x010
74 #define MP_ETH_PCXR 0x408
75 #define MP_ETH_SDCMR 0x448
76 #define MP_ETH_ICR 0x450
77 #define MP_ETH_IMR 0x458
78 #define MP_ETH_FRDP0 0x480
79 #define MP_ETH_FRDP1 0x484
80 #define MP_ETH_FRDP2 0x488
81 #define MP_ETH_FRDP3 0x48C
82 #define MP_ETH_CRDP0 0x4A0
83 #define MP_ETH_CRDP1 0x4A4
84 #define MP_ETH_CRDP2 0x4A8
85 #define MP_ETH_CRDP3 0x4AC
86 #define MP_ETH_CTDP0 0x4E0
87 #define MP_ETH_CTDP1 0x4E4
88 #define MP_ETH_CTDP2 0x4E8
89 #define MP_ETH_CTDP3 0x4EC
92 #define MP_ETH_SMIR_DATA 0x0000FFFF
93 #define MP_ETH_SMIR_ADDR 0x03FF0000
94 #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */
95 #define MP_ETH_SMIR_RDVALID (1 << 27)
98 #define MP_ETH_PHY1_BMSR 0x00210000
99 #define MP_ETH_PHY1_PHYSID1 0x00410000
100 #define MP_ETH_PHY1_PHYSID2 0x00610000
102 #define MP_PHY_BMSR_LINK 0x0004
103 #define MP_PHY_BMSR_AUTONEG 0x0008
105 #define MP_PHY_88E3015 0x01410E20
107 /* TX descriptor status */
108 #define MP_ETH_TX_OWN (1 << 31)
110 /* RX descriptor status */
111 #define MP_ETH_RX_OWN (1 << 31)
113 /* Interrupt cause/mask bits */
114 #define MP_ETH_IRQ_RX_BIT 0
115 #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT)
116 #define MP_ETH_IRQ_TXHI_BIT 2
117 #define MP_ETH_IRQ_TXLO_BIT 3
119 /* Port config bits */
120 #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */
122 /* SDMA command bits */
123 #define MP_ETH_CMD_TXHI (1 << 23)
124 #define MP_ETH_CMD_TXLO (1 << 22)
126 typedef struct mv88w8618_tx_desc
{
134 typedef struct mv88w8618_rx_desc
{
137 uint16_t buffer_size
;
142 typedef struct mv88w8618_eth_state
{
150 uint32_t tx_queue
[2];
151 uint32_t rx_queue
[4];
152 uint32_t frx_queue
[4];
155 } mv88w8618_eth_state
;
157 static void eth_rx_desc_put(uint32_t addr
, mv88w8618_rx_desc
*desc
)
159 cpu_to_le32s(&desc
->cmdstat
);
160 cpu_to_le16s(&desc
->bytes
);
161 cpu_to_le16s(&desc
->buffer_size
);
162 cpu_to_le32s(&desc
->buffer
);
163 cpu_to_le32s(&desc
->next
);
164 cpu_physical_memory_write(addr
, (void *)desc
, sizeof(*desc
));
167 static void eth_rx_desc_get(uint32_t addr
, mv88w8618_rx_desc
*desc
)
169 cpu_physical_memory_read(addr
, (void *)desc
, sizeof(*desc
));
170 le32_to_cpus(&desc
->cmdstat
);
171 le16_to_cpus(&desc
->bytes
);
172 le16_to_cpus(&desc
->buffer_size
);
173 le32_to_cpus(&desc
->buffer
);
174 le32_to_cpus(&desc
->next
);
177 static int eth_can_receive(VLANClientState
*vc
)
182 static ssize_t
eth_receive(VLANClientState
*vc
, const uint8_t *buf
, size_t size
)
184 mv88w8618_eth_state
*s
= vc
->opaque
;
186 mv88w8618_rx_desc desc
;
189 for (i
= 0; i
< 4; i
++) {
190 desc_addr
= s
->cur_rx
[i
];
194 eth_rx_desc_get(desc_addr
, &desc
);
195 if ((desc
.cmdstat
& MP_ETH_RX_OWN
) && desc
.buffer_size
>= size
) {
196 cpu_physical_memory_write(desc
.buffer
+ s
->vlan_header
,
198 desc
.bytes
= size
+ s
->vlan_header
;
199 desc
.cmdstat
&= ~MP_ETH_RX_OWN
;
200 s
->cur_rx
[i
] = desc
.next
;
202 s
->icr
|= MP_ETH_IRQ_RX
;
204 qemu_irq_raise(s
->irq
);
205 eth_rx_desc_put(desc_addr
, &desc
);
208 desc_addr
= desc
.next
;
209 } while (desc_addr
!= s
->rx_queue
[i
]);
214 static void eth_tx_desc_put(uint32_t addr
, mv88w8618_tx_desc
*desc
)
216 cpu_to_le32s(&desc
->cmdstat
);
217 cpu_to_le16s(&desc
->res
);
218 cpu_to_le16s(&desc
->bytes
);
219 cpu_to_le32s(&desc
->buffer
);
220 cpu_to_le32s(&desc
->next
);
221 cpu_physical_memory_write(addr
, (void *)desc
, sizeof(*desc
));
224 static void eth_tx_desc_get(uint32_t addr
, mv88w8618_tx_desc
*desc
)
226 cpu_physical_memory_read(addr
, (void *)desc
, sizeof(*desc
));
227 le32_to_cpus(&desc
->cmdstat
);
228 le16_to_cpus(&desc
->res
);
229 le16_to_cpus(&desc
->bytes
);
230 le32_to_cpus(&desc
->buffer
);
231 le32_to_cpus(&desc
->next
);
234 static void eth_send(mv88w8618_eth_state
*s
, int queue_index
)
236 uint32_t desc_addr
= s
->tx_queue
[queue_index
];
237 mv88w8618_tx_desc desc
;
245 eth_tx_desc_get(desc_addr
, &desc
);
246 if (desc
.cmdstat
& MP_ETH_TX_OWN
) {
249 cpu_physical_memory_read(desc
.buffer
, buf
, len
);
250 qemu_send_packet(s
->vc
, buf
, len
);
252 desc
.cmdstat
&= ~MP_ETH_TX_OWN
;
253 s
->icr
|= 1 << (MP_ETH_IRQ_TXLO_BIT
- queue_index
);
254 eth_tx_desc_put(desc_addr
, &desc
);
256 desc_addr
= desc
.next
;
257 } while (desc_addr
!= s
->tx_queue
[queue_index
]);
260 static uint32_t mv88w8618_eth_read(void *opaque
, target_phys_addr_t offset
)
262 mv88w8618_eth_state
*s
= opaque
;
266 if (s
->smir
& MP_ETH_SMIR_OPCODE
) {
267 switch (s
->smir
& MP_ETH_SMIR_ADDR
) {
268 case MP_ETH_PHY1_BMSR
:
269 return MP_PHY_BMSR_LINK
| MP_PHY_BMSR_AUTONEG
|
271 case MP_ETH_PHY1_PHYSID1
:
272 return (MP_PHY_88E3015
>> 16) | MP_ETH_SMIR_RDVALID
;
273 case MP_ETH_PHY1_PHYSID2
:
274 return (MP_PHY_88E3015
& 0xFFFF) | MP_ETH_SMIR_RDVALID
;
276 return MP_ETH_SMIR_RDVALID
;
287 case MP_ETH_FRDP0
... MP_ETH_FRDP3
:
288 return s
->frx_queue
[(offset
- MP_ETH_FRDP0
)/4];
290 case MP_ETH_CRDP0
... MP_ETH_CRDP3
:
291 return s
->rx_queue
[(offset
- MP_ETH_CRDP0
)/4];
293 case MP_ETH_CTDP0
... MP_ETH_CTDP3
:
294 return s
->tx_queue
[(offset
- MP_ETH_CTDP0
)/4];
301 static void mv88w8618_eth_write(void *opaque
, target_phys_addr_t offset
,
304 mv88w8618_eth_state
*s
= opaque
;
312 s
->vlan_header
= ((value
>> MP_ETH_PCXR_2BSM_BIT
) & 1) * 2;
316 if (value
& MP_ETH_CMD_TXHI
)
318 if (value
& MP_ETH_CMD_TXLO
)
320 if (value
& (MP_ETH_CMD_TXHI
| MP_ETH_CMD_TXLO
) && s
->icr
& s
->imr
)
321 qemu_irq_raise(s
->irq
);
331 qemu_irq_raise(s
->irq
);
334 case MP_ETH_FRDP0
... MP_ETH_FRDP3
:
335 s
->frx_queue
[(offset
- MP_ETH_FRDP0
)/4] = value
;
338 case MP_ETH_CRDP0
... MP_ETH_CRDP3
:
339 s
->rx_queue
[(offset
- MP_ETH_CRDP0
)/4] =
340 s
->cur_rx
[(offset
- MP_ETH_CRDP0
)/4] = value
;
343 case MP_ETH_CTDP0
... MP_ETH_CTDP3
:
344 s
->tx_queue
[(offset
- MP_ETH_CTDP0
)/4] = value
;
349 static CPUReadMemoryFunc
* const mv88w8618_eth_readfn
[] = {
355 static CPUWriteMemoryFunc
* const mv88w8618_eth_writefn
[] = {
361 static void eth_cleanup(VLANClientState
*vc
)
363 mv88w8618_eth_state
*s
= vc
->opaque
;
365 cpu_unregister_io_memory(s
->mmio_index
);
370 static int mv88w8618_eth_init(SysBusDevice
*dev
)
372 mv88w8618_eth_state
*s
= FROM_SYSBUS(mv88w8618_eth_state
, dev
);
374 sysbus_init_irq(dev
, &s
->irq
);
375 s
->vc
= qdev_get_vlan_client(&dev
->qdev
,
376 eth_can_receive
, eth_receive
, NULL
,
378 s
->mmio_index
= cpu_register_io_memory(mv88w8618_eth_readfn
,
379 mv88w8618_eth_writefn
, s
);
380 sysbus_init_mmio(dev
, MP_ETH_SIZE
, s
->mmio_index
);
384 /* LCD register offsets */
385 #define MP_LCD_IRQCTRL 0x180
386 #define MP_LCD_IRQSTAT 0x184
387 #define MP_LCD_SPICTRL 0x1ac
388 #define MP_LCD_INST 0x1bc
389 #define MP_LCD_DATA 0x1c0
392 #define MP_LCD_SPI_DATA 0x00100011
393 #define MP_LCD_SPI_CMD 0x00104011
394 #define MP_LCD_SPI_INVALID 0x00000000
397 #define MP_LCD_INST_SETPAGE0 0xB0
399 #define MP_LCD_INST_SETPAGE7 0xB7
401 #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
403 typedef struct musicpal_lcd_state
{
411 uint8_t video_ram
[128*64/8];
412 } musicpal_lcd_state
;
414 static uint8_t scale_lcd_color(musicpal_lcd_state
*s
, uint8_t col
)
416 switch (s
->brightness
) {
422 return (col
* s
->brightness
) / 7;
426 #define SET_LCD_PIXEL(depth, type) \
427 static inline void glue(set_lcd_pixel, depth) \
428 (musicpal_lcd_state *s, int x, int y, type col) \
431 type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
433 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
434 for (dx = 0; dx < 3; dx++, pixel++) \
437 SET_LCD_PIXEL(8, uint8_t)
438 SET_LCD_PIXEL(16, uint16_t)
439 SET_LCD_PIXEL(32, uint32_t)
441 #include "pixel_ops.h"
443 static void lcd_refresh(void *opaque
)
445 musicpal_lcd_state
*s
= opaque
;
448 switch (ds_get_bits_per_pixel(s
->ds
)) {
451 #define LCD_REFRESH(depth, func) \
453 col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
454 scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
455 scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
456 for (x = 0; x < 128; x++) \
457 for (y = 0; y < 64; y++) \
458 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
459 glue(set_lcd_pixel, depth)(s, x, y, col); \
461 glue(set_lcd_pixel, depth)(s, x, y, 0); \
463 LCD_REFRESH(8, rgb_to_pixel8
)
464 LCD_REFRESH(16, rgb_to_pixel16
)
465 LCD_REFRESH(32, (is_surface_bgr(s
->ds
->surface
) ?
466 rgb_to_pixel32bgr
: rgb_to_pixel32
))
468 hw_error("unsupported colour depth %i\n",
469 ds_get_bits_per_pixel(s
->ds
));
472 dpy_update(s
->ds
, 0, 0, 128*3, 64*3);
475 static void lcd_invalidate(void *opaque
)
479 static void musicpal_lcd_gpio_brigthness_in(void *opaque
, int irq
, int level
)
481 musicpal_lcd_state
*s
= opaque
;
482 s
->brightness
&= ~(1 << irq
);
483 s
->brightness
|= level
<< irq
;
486 static uint32_t musicpal_lcd_read(void *opaque
, target_phys_addr_t offset
)
488 musicpal_lcd_state
*s
= opaque
;
499 static void musicpal_lcd_write(void *opaque
, target_phys_addr_t offset
,
502 musicpal_lcd_state
*s
= opaque
;
510 if (value
== MP_LCD_SPI_DATA
|| value
== MP_LCD_SPI_CMD
)
513 s
->mode
= MP_LCD_SPI_INVALID
;
517 if (value
>= MP_LCD_INST_SETPAGE0
&& value
<= MP_LCD_INST_SETPAGE7
) {
518 s
->page
= value
- MP_LCD_INST_SETPAGE0
;
524 if (s
->mode
== MP_LCD_SPI_CMD
) {
525 if (value
>= MP_LCD_INST_SETPAGE0
&&
526 value
<= MP_LCD_INST_SETPAGE7
) {
527 s
->page
= value
- MP_LCD_INST_SETPAGE0
;
530 } else if (s
->mode
== MP_LCD_SPI_DATA
) {
531 s
->video_ram
[s
->page
*128 + s
->page_off
] = value
;
532 s
->page_off
= (s
->page_off
+ 1) & 127;
538 static CPUReadMemoryFunc
* const musicpal_lcd_readfn
[] = {
544 static CPUWriteMemoryFunc
* const musicpal_lcd_writefn
[] = {
550 static int musicpal_lcd_init(SysBusDevice
*dev
)
552 musicpal_lcd_state
*s
= FROM_SYSBUS(musicpal_lcd_state
, dev
);
557 iomemtype
= cpu_register_io_memory(musicpal_lcd_readfn
,
558 musicpal_lcd_writefn
, s
);
559 sysbus_init_mmio(dev
, MP_LCD_SIZE
, iomemtype
);
561 s
->ds
= graphic_console_init(lcd_refresh
, lcd_invalidate
,
563 qemu_console_resize(s
->ds
, 128*3, 64*3);
565 qdev_init_gpio_in(&dev
->qdev
, musicpal_lcd_gpio_brigthness_in
, 3);
570 /* PIC register offsets */
571 #define MP_PIC_STATUS 0x00
572 #define MP_PIC_ENABLE_SET 0x08
573 #define MP_PIC_ENABLE_CLR 0x0C
575 typedef struct mv88w8618_pic_state
581 } mv88w8618_pic_state
;
583 static void mv88w8618_pic_update(mv88w8618_pic_state
*s
)
585 qemu_set_irq(s
->parent_irq
, (s
->level
& s
->enabled
));
588 static void mv88w8618_pic_set_irq(void *opaque
, int irq
, int level
)
590 mv88w8618_pic_state
*s
= opaque
;
593 s
->level
|= 1 << irq
;
595 s
->level
&= ~(1 << irq
);
596 mv88w8618_pic_update(s
);
599 static uint32_t mv88w8618_pic_read(void *opaque
, target_phys_addr_t offset
)
601 mv88w8618_pic_state
*s
= opaque
;
605 return s
->level
& s
->enabled
;
612 static void mv88w8618_pic_write(void *opaque
, target_phys_addr_t offset
,
615 mv88w8618_pic_state
*s
= opaque
;
618 case MP_PIC_ENABLE_SET
:
622 case MP_PIC_ENABLE_CLR
:
623 s
->enabled
&= ~value
;
627 mv88w8618_pic_update(s
);
630 static void mv88w8618_pic_reset(void *opaque
)
632 mv88w8618_pic_state
*s
= opaque
;
638 static CPUReadMemoryFunc
* const mv88w8618_pic_readfn
[] = {
644 static CPUWriteMemoryFunc
* const mv88w8618_pic_writefn
[] = {
650 static int mv88w8618_pic_init(SysBusDevice
*dev
)
652 mv88w8618_pic_state
*s
= FROM_SYSBUS(mv88w8618_pic_state
, dev
);
655 qdev_init_gpio_in(&dev
->qdev
, mv88w8618_pic_set_irq
, 32);
656 sysbus_init_irq(dev
, &s
->parent_irq
);
657 iomemtype
= cpu_register_io_memory(mv88w8618_pic_readfn
,
658 mv88w8618_pic_writefn
, s
);
659 sysbus_init_mmio(dev
, MP_PIC_SIZE
, iomemtype
);
661 qemu_register_reset(mv88w8618_pic_reset
, s
);
665 /* PIT register offsets */
666 #define MP_PIT_TIMER1_LENGTH 0x00
668 #define MP_PIT_TIMER4_LENGTH 0x0C
669 #define MP_PIT_CONTROL 0x10
670 #define MP_PIT_TIMER1_VALUE 0x14
672 #define MP_PIT_TIMER4_VALUE 0x20
673 #define MP_BOARD_RESET 0x34
675 /* Magic board reset value (probably some watchdog behind it) */
676 #define MP_BOARD_RESET_MAGIC 0x10000
678 typedef struct mv88w8618_timer_state
{
679 ptimer_state
*ptimer
;
683 } mv88w8618_timer_state
;
685 typedef struct mv88w8618_pit_state
{
687 mv88w8618_timer_state timer
[4];
689 } mv88w8618_pit_state
;
691 static void mv88w8618_timer_tick(void *opaque
)
693 mv88w8618_timer_state
*s
= opaque
;
695 qemu_irq_raise(s
->irq
);
698 static void mv88w8618_timer_init(SysBusDevice
*dev
, mv88w8618_timer_state
*s
,
703 sysbus_init_irq(dev
, &s
->irq
);
706 bh
= qemu_bh_new(mv88w8618_timer_tick
, s
);
707 s
->ptimer
= ptimer_init(bh
);
710 static uint32_t mv88w8618_pit_read(void *opaque
, target_phys_addr_t offset
)
712 mv88w8618_pit_state
*s
= opaque
;
713 mv88w8618_timer_state
*t
;
716 case MP_PIT_TIMER1_VALUE
... MP_PIT_TIMER4_VALUE
:
717 t
= &s
->timer
[(offset
-MP_PIT_TIMER1_VALUE
) >> 2];
718 return ptimer_get_count(t
->ptimer
);
725 static void mv88w8618_pit_write(void *opaque
, target_phys_addr_t offset
,
728 mv88w8618_pit_state
*s
= opaque
;
729 mv88w8618_timer_state
*t
;
733 case MP_PIT_TIMER1_LENGTH
... MP_PIT_TIMER4_LENGTH
:
734 t
= &s
->timer
[offset
>> 2];
736 ptimer_set_limit(t
->ptimer
, t
->limit
, 1);
740 for (i
= 0; i
< 4; i
++) {
743 ptimer_set_limit(t
->ptimer
, t
->limit
, 0);
744 ptimer_set_freq(t
->ptimer
, t
->freq
);
745 ptimer_run(t
->ptimer
, 0);
752 if (value
== MP_BOARD_RESET_MAGIC
)
753 qemu_system_reset_request();
758 static CPUReadMemoryFunc
* const mv88w8618_pit_readfn
[] = {
764 static CPUWriteMemoryFunc
* const mv88w8618_pit_writefn
[] = {
770 static int mv88w8618_pit_init(SysBusDevice
*dev
)
773 mv88w8618_pit_state
*s
= FROM_SYSBUS(mv88w8618_pit_state
, dev
);
776 /* Letting them all run at 1 MHz is likely just a pragmatic
778 for (i
= 0; i
< 4; i
++) {
779 mv88w8618_timer_init(dev
, &s
->timer
[i
], 1000000);
782 iomemtype
= cpu_register_io_memory(mv88w8618_pit_readfn
,
783 mv88w8618_pit_writefn
, s
);
784 sysbus_init_mmio(dev
, MP_PIT_SIZE
, iomemtype
);
788 /* Flash config register offsets */
789 #define MP_FLASHCFG_CFGR0 0x04
791 typedef struct mv88w8618_flashcfg_state
{
794 } mv88w8618_flashcfg_state
;
796 static uint32_t mv88w8618_flashcfg_read(void *opaque
,
797 target_phys_addr_t offset
)
799 mv88w8618_flashcfg_state
*s
= opaque
;
802 case MP_FLASHCFG_CFGR0
:
810 static void mv88w8618_flashcfg_write(void *opaque
, target_phys_addr_t offset
,
813 mv88w8618_flashcfg_state
*s
= opaque
;
816 case MP_FLASHCFG_CFGR0
:
822 static CPUReadMemoryFunc
* const mv88w8618_flashcfg_readfn
[] = {
823 mv88w8618_flashcfg_read
,
824 mv88w8618_flashcfg_read
,
825 mv88w8618_flashcfg_read
828 static CPUWriteMemoryFunc
* const mv88w8618_flashcfg_writefn
[] = {
829 mv88w8618_flashcfg_write
,
830 mv88w8618_flashcfg_write
,
831 mv88w8618_flashcfg_write
834 static int mv88w8618_flashcfg_init(SysBusDevice
*dev
)
837 mv88w8618_flashcfg_state
*s
= FROM_SYSBUS(mv88w8618_flashcfg_state
, dev
);
839 s
->cfgr0
= 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
840 iomemtype
= cpu_register_io_memory(mv88w8618_flashcfg_readfn
,
841 mv88w8618_flashcfg_writefn
, s
);
842 sysbus_init_mmio(dev
, MP_FLASHCFG_SIZE
, iomemtype
);
846 /* Misc register offsets */
847 #define MP_MISC_BOARD_REVISION 0x18
849 #define MP_BOARD_REVISION 0x31
851 static uint32_t musicpal_misc_read(void *opaque
, target_phys_addr_t offset
)
854 case MP_MISC_BOARD_REVISION
:
855 return MP_BOARD_REVISION
;
862 static void musicpal_misc_write(void *opaque
, target_phys_addr_t offset
,
867 static CPUReadMemoryFunc
* const musicpal_misc_readfn
[] = {
873 static CPUWriteMemoryFunc
* const musicpal_misc_writefn
[] = {
879 static void musicpal_misc_init(void)
883 iomemtype
= cpu_register_io_memory(musicpal_misc_readfn
,
884 musicpal_misc_writefn
, NULL
);
885 cpu_register_physical_memory(MP_MISC_BASE
, MP_MISC_SIZE
, iomemtype
);
888 /* WLAN register offsets */
889 #define MP_WLAN_MAGIC1 0x11c
890 #define MP_WLAN_MAGIC2 0x124
892 static uint32_t mv88w8618_wlan_read(void *opaque
, target_phys_addr_t offset
)
895 /* Workaround to allow loading the binary-only wlandrv.ko crap
896 * from the original Freecom firmware. */
907 static void mv88w8618_wlan_write(void *opaque
, target_phys_addr_t offset
,
912 static CPUReadMemoryFunc
* const mv88w8618_wlan_readfn
[] = {
918 static CPUWriteMemoryFunc
* const mv88w8618_wlan_writefn
[] = {
919 mv88w8618_wlan_write
,
920 mv88w8618_wlan_write
,
921 mv88w8618_wlan_write
,
924 static int mv88w8618_wlan_init(SysBusDevice
*dev
)
928 iomemtype
= cpu_register_io_memory(mv88w8618_wlan_readfn
,
929 mv88w8618_wlan_writefn
, NULL
);
930 sysbus_init_mmio(dev
, MP_WLAN_SIZE
, iomemtype
);
934 /* GPIO register offsets */
935 #define MP_GPIO_OE_LO 0x008
936 #define MP_GPIO_OUT_LO 0x00c
937 #define MP_GPIO_IN_LO 0x010
938 #define MP_GPIO_IER_LO 0x014
939 #define MP_GPIO_IMR_LO 0x018
940 #define MP_GPIO_ISR_LO 0x020
941 #define MP_GPIO_OE_HI 0x508
942 #define MP_GPIO_OUT_HI 0x50c
943 #define MP_GPIO_IN_HI 0x510
944 #define MP_GPIO_IER_HI 0x514
945 #define MP_GPIO_IMR_HI 0x518
946 #define MP_GPIO_ISR_HI 0x520
948 /* GPIO bits & masks */
949 #define MP_GPIO_LCD_BRIGHTNESS 0x00070000
950 #define MP_GPIO_I2C_DATA_BIT 29
951 #define MP_GPIO_I2C_CLOCK_BIT 30
953 /* LCD brightness bits in GPIO_OE_HI */
954 #define MP_OE_LCD_BRIGHTNESS 0x0007
956 typedef struct musicpal_gpio_state
{
958 uint32_t lcd_brightness
;
965 qemu_irq out
[5]; /* 3 brightness out + 2 lcd (data and clock ) */
966 } musicpal_gpio_state
;
968 static void musicpal_gpio_brightness_update(musicpal_gpio_state
*s
) {
972 /* compute brightness ratio */
973 switch (s
->lcd_brightness
) {
1007 /* set lcd brightness GPIOs */
1008 for (i
= 0; i
<= 2; i
++)
1009 qemu_set_irq(s
->out
[i
], (brightness
>> i
) & 1);
1012 static void musicpal_gpio_pin_event(void *opaque
, int pin
, int level
)
1014 musicpal_gpio_state
*s
= opaque
;
1015 uint32_t mask
= 1 << pin
;
1016 uint32_t delta
= level
<< pin
;
1017 uint32_t old
= s
->in_state
& mask
;
1019 s
->in_state
&= ~mask
;
1020 s
->in_state
|= delta
;
1022 if ((old
^ delta
) &&
1023 ((level
&& (s
->imr
& mask
)) || (!level
&& (s
->ier
& mask
)))) {
1025 qemu_irq_raise(s
->irq
);
1029 static uint32_t musicpal_gpio_read(void *opaque
, target_phys_addr_t offset
)
1031 musicpal_gpio_state
*s
= opaque
;
1034 case MP_GPIO_OE_HI
: /* used for LCD brightness control */
1035 return s
->lcd_brightness
& MP_OE_LCD_BRIGHTNESS
;
1037 case MP_GPIO_OUT_LO
:
1038 return s
->out_state
& 0xFFFF;
1039 case MP_GPIO_OUT_HI
:
1040 return s
->out_state
>> 16;
1043 return s
->in_state
& 0xFFFF;
1045 return s
->in_state
>> 16;
1047 case MP_GPIO_IER_LO
:
1048 return s
->ier
& 0xFFFF;
1049 case MP_GPIO_IER_HI
:
1050 return s
->ier
>> 16;
1052 case MP_GPIO_IMR_LO
:
1053 return s
->imr
& 0xFFFF;
1054 case MP_GPIO_IMR_HI
:
1055 return s
->imr
>> 16;
1057 case MP_GPIO_ISR_LO
:
1058 return s
->isr
& 0xFFFF;
1059 case MP_GPIO_ISR_HI
:
1060 return s
->isr
>> 16;
1067 static void musicpal_gpio_write(void *opaque
, target_phys_addr_t offset
,
1070 musicpal_gpio_state
*s
= opaque
;
1072 case MP_GPIO_OE_HI
: /* used for LCD brightness control */
1073 s
->lcd_brightness
= (s
->lcd_brightness
& MP_GPIO_LCD_BRIGHTNESS
) |
1074 (value
& MP_OE_LCD_BRIGHTNESS
);
1075 musicpal_gpio_brightness_update(s
);
1078 case MP_GPIO_OUT_LO
:
1079 s
->out_state
= (s
->out_state
& 0xFFFF0000) | (value
& 0xFFFF);
1081 case MP_GPIO_OUT_HI
:
1082 s
->out_state
= (s
->out_state
& 0xFFFF) | (value
<< 16);
1083 s
->lcd_brightness
= (s
->lcd_brightness
& 0xFFFF) |
1084 (s
->out_state
& MP_GPIO_LCD_BRIGHTNESS
);
1085 musicpal_gpio_brightness_update(s
);
1086 qemu_set_irq(s
->out
[3], (s
->out_state
>> MP_GPIO_I2C_DATA_BIT
) & 1);
1087 qemu_set_irq(s
->out
[4], (s
->out_state
>> MP_GPIO_I2C_CLOCK_BIT
) & 1);
1090 case MP_GPIO_IER_LO
:
1091 s
->ier
= (s
->ier
& 0xFFFF0000) | (value
& 0xFFFF);
1093 case MP_GPIO_IER_HI
:
1094 s
->ier
= (s
->ier
& 0xFFFF) | (value
<< 16);
1097 case MP_GPIO_IMR_LO
:
1098 s
->imr
= (s
->imr
& 0xFFFF0000) | (value
& 0xFFFF);
1100 case MP_GPIO_IMR_HI
:
1101 s
->imr
= (s
->imr
& 0xFFFF) | (value
<< 16);
1106 static CPUReadMemoryFunc
* const musicpal_gpio_readfn
[] = {
1112 static CPUWriteMemoryFunc
* const musicpal_gpio_writefn
[] = {
1113 musicpal_gpio_write
,
1114 musicpal_gpio_write
,
1115 musicpal_gpio_write
,
1118 static void musicpal_gpio_reset(musicpal_gpio_state
*s
)
1120 s
->in_state
= 0xffffffff;
1126 static int musicpal_gpio_init(SysBusDevice
*dev
)
1128 musicpal_gpio_state
*s
= FROM_SYSBUS(musicpal_gpio_state
, dev
);
1131 sysbus_init_irq(dev
, &s
->irq
);
1133 iomemtype
= cpu_register_io_memory(musicpal_gpio_readfn
,
1134 musicpal_gpio_writefn
, s
);
1135 sysbus_init_mmio(dev
, MP_GPIO_SIZE
, iomemtype
);
1137 musicpal_gpio_reset(s
);
1139 qdev_init_gpio_out(&dev
->qdev
, s
->out
, ARRAY_SIZE(s
->out
));
1141 qdev_init_gpio_in(&dev
->qdev
, musicpal_gpio_pin_event
, 32);
1146 /* Keyboard codes & masks */
1147 #define KEY_RELEASED 0x80
1148 #define KEY_CODE 0x7f
1150 #define KEYCODE_TAB 0x0f
1151 #define KEYCODE_ENTER 0x1c
1152 #define KEYCODE_F 0x21
1153 #define KEYCODE_M 0x32
1155 #define KEYCODE_EXTENDED 0xe0
1156 #define KEYCODE_UP 0x48
1157 #define KEYCODE_DOWN 0x50
1158 #define KEYCODE_LEFT 0x4b
1159 #define KEYCODE_RIGHT 0x4d
1161 #define MP_KEY_WHEEL_VOL (1 << 0)
1162 #define MP_KEY_WHEEL_VOL_INV (1 << 1)
1163 #define MP_KEY_WHEEL_NAV (1 << 2)
1164 #define MP_KEY_WHEEL_NAV_INV (1 << 3)
1165 #define MP_KEY_BTN_FAVORITS (1 << 4)
1166 #define MP_KEY_BTN_MENU (1 << 5)
1167 #define MP_KEY_BTN_VOLUME (1 << 6)
1168 #define MP_KEY_BTN_NAVIGATION (1 << 7)
1170 typedef struct musicpal_key_state
{
1171 SysBusDevice busdev
;
1172 uint32_t kbd_extended
;
1173 uint32_t pressed_keys
;
1175 } musicpal_key_state
;
1177 static void musicpal_key_event(void *opaque
, int keycode
)
1179 musicpal_key_state
*s
= opaque
;
1183 if (keycode
== KEYCODE_EXTENDED
) {
1184 s
->kbd_extended
= 1;
1188 if (s
->kbd_extended
)
1189 switch (keycode
& KEY_CODE
) {
1191 event
= MP_KEY_WHEEL_NAV
| MP_KEY_WHEEL_NAV_INV
;
1195 event
= MP_KEY_WHEEL_NAV
;
1199 event
= MP_KEY_WHEEL_VOL
| MP_KEY_WHEEL_VOL_INV
;
1203 event
= MP_KEY_WHEEL_VOL
;
1207 switch (keycode
& KEY_CODE
) {
1209 event
= MP_KEY_BTN_FAVORITS
;
1213 event
= MP_KEY_BTN_VOLUME
;
1217 event
= MP_KEY_BTN_NAVIGATION
;
1221 event
= MP_KEY_BTN_MENU
;
1224 /* Do not repeat already pressed buttons */
1225 if (!(keycode
& KEY_RELEASED
) && (s
->pressed_keys
& event
)) {
1231 /* Raise GPIO pin first if repeating a key */
1232 if (!(keycode
& KEY_RELEASED
) && (s
->pressed_keys
& event
)) {
1233 for (i
= 0; i
<= 7; i
++) {
1234 if (event
& (1 << i
)) {
1235 qemu_set_irq(s
->out
[i
], 1);
1239 for (i
= 0; i
<= 7; i
++) {
1240 if (event
& (1 << i
)) {
1241 qemu_set_irq(s
->out
[i
], !!(keycode
& KEY_RELEASED
));
1244 if (keycode
& KEY_RELEASED
) {
1245 s
->pressed_keys
&= ~event
;
1247 s
->pressed_keys
|= event
;
1251 s
->kbd_extended
= 0;
1254 static int musicpal_key_init(SysBusDevice
*dev
)
1256 musicpal_key_state
*s
= FROM_SYSBUS(musicpal_key_state
, dev
);
1258 sysbus_init_mmio(dev
, 0x0, 0);
1260 s
->kbd_extended
= 0;
1261 s
->pressed_keys
= 0;
1263 qdev_init_gpio_out(&dev
->qdev
, s
->out
, ARRAY_SIZE(s
->out
));
1265 qemu_add_kbd_event_handler(musicpal_key_event
, s
);
1270 static struct arm_boot_info musicpal_binfo
= {
1271 .loader_start
= 0x0,
1275 static void musicpal_init(ram_addr_t ram_size
,
1276 const char *boot_device
,
1277 const char *kernel_filename
, const char *kernel_cmdline
,
1278 const char *initrd_filename
, const char *cpu_model
)
1284 DeviceState
*i2c_dev
;
1285 DeviceState
*lcd_dev
;
1286 DeviceState
*key_dev
;
1288 DeviceState
*wm8750_dev
;
1293 unsigned long flash_size
;
1295 ram_addr_t sram_off
;
1298 cpu_model
= "arm926";
1300 env
= cpu_init(cpu_model
);
1302 fprintf(stderr
, "Unable to find CPU definition\n");
1305 cpu_pic
= arm_pic_init_cpu(env
);
1307 /* For now we use a fixed - the original - RAM size */
1308 cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE
,
1309 qemu_ram_alloc(MP_RAM_DEFAULT_SIZE
));
1311 sram_off
= qemu_ram_alloc(MP_SRAM_SIZE
);
1312 cpu_register_physical_memory(MP_SRAM_BASE
, MP_SRAM_SIZE
, sram_off
);
1314 dev
= sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE
,
1315 cpu_pic
[ARM_PIC_CPU_IRQ
]);
1316 for (i
= 0; i
< 32; i
++) {
1317 pic
[i
] = qdev_get_gpio_in(dev
, i
);
1319 sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE
, pic
[MP_TIMER1_IRQ
],
1320 pic
[MP_TIMER2_IRQ
], pic
[MP_TIMER3_IRQ
],
1321 pic
[MP_TIMER4_IRQ
], NULL
);
1324 serial_mm_init(MP_UART1_BASE
, 2, pic
[MP_UART1_IRQ
], 1825000,
1327 serial_mm_init(MP_UART2_BASE
, 2, pic
[MP_UART2_IRQ
], 1825000,
1330 /* Register flash */
1331 dinfo
= drive_get(IF_PFLASH
, 0, 0);
1333 flash_size
= bdrv_getlength(dinfo
->bdrv
);
1334 if (flash_size
!= 8*1024*1024 && flash_size
!= 16*1024*1024 &&
1335 flash_size
!= 32*1024*1024) {
1336 fprintf(stderr
, "Invalid flash image size\n");
1341 * The original U-Boot accesses the flash at 0xFE000000 instead of
1342 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1343 * image is smaller than 32 MB.
1345 pflash_cfi02_register(0-MP_FLASH_SIZE_MAX
, qemu_ram_alloc(flash_size
),
1346 dinfo
->bdrv
, 0x10000,
1347 (flash_size
+ 0xffff) >> 16,
1348 MP_FLASH_SIZE_MAX
/ flash_size
,
1349 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1352 sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE
, NULL
);
1354 qemu_check_nic_model(&nd_table
[0], "mv88w8618");
1355 dev
= qdev_create(NULL
, "mv88w8618_eth");
1356 dev
->nd
= &nd_table
[0];
1358 sysbus_mmio_map(sysbus_from_qdev(dev
), 0, MP_ETH_BASE
);
1359 sysbus_connect_irq(sysbus_from_qdev(dev
), 0, pic
[MP_ETH_IRQ
]);
1361 sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE
, NULL
);
1363 musicpal_misc_init();
1365 dev
= sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE
, pic
[MP_GPIO_IRQ
]);
1366 i2c_dev
= sysbus_create_simple("bitbang_i2c", 0, NULL
);
1367 i2c
= (i2c_bus
*)qdev_get_child_bus(i2c_dev
, "i2c");
1369 lcd_dev
= sysbus_create_simple("musicpal_lcd", MP_LCD_BASE
, NULL
);
1370 key_dev
= sysbus_create_simple("musicpal_key", 0, NULL
);
1373 qdev_connect_gpio_out(i2c_dev
, 0,
1374 qdev_get_gpio_in(dev
, MP_GPIO_I2C_DATA_BIT
));
1376 qdev_connect_gpio_out(dev
, 3, qdev_get_gpio_in(i2c_dev
, 0));
1378 qdev_connect_gpio_out(dev
, 4, qdev_get_gpio_in(i2c_dev
, 1));
1380 for (i
= 0; i
< 3; i
++)
1381 qdev_connect_gpio_out(dev
, i
, qdev_get_gpio_in(lcd_dev
, i
));
1383 for (i
= 0; i
< 4; i
++) {
1384 qdev_connect_gpio_out(key_dev
, i
, qdev_get_gpio_in(dev
, i
+ 8));
1386 for (i
= 4; i
< 8; i
++) {
1387 qdev_connect_gpio_out(key_dev
, i
, qdev_get_gpio_in(dev
, i
+ 15));
1391 wm8750_dev
= i2c_create_slave(i2c
, "wm8750", MP_WM_ADDR
);
1392 dev
= qdev_create(NULL
, "mv88w8618_audio");
1393 s
= sysbus_from_qdev(dev
);
1394 qdev_prop_set_ptr(dev
, "wm8750", wm8750_dev
);
1396 sysbus_mmio_map(s
, 0, MP_AUDIO_BASE
);
1397 sysbus_connect_irq(s
, 0, pic
[MP_AUDIO_IRQ
]);
1400 musicpal_binfo
.ram_size
= MP_RAM_DEFAULT_SIZE
;
1401 musicpal_binfo
.kernel_filename
= kernel_filename
;
1402 musicpal_binfo
.kernel_cmdline
= kernel_cmdline
;
1403 musicpal_binfo
.initrd_filename
= initrd_filename
;
1404 arm_load_kernel(env
, &musicpal_binfo
);
1407 static QEMUMachine musicpal_machine
= {
1409 .desc
= "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1410 .init
= musicpal_init
,
1413 static void musicpal_machine_init(void)
1415 qemu_register_machine(&musicpal_machine
);
1418 machine_init(musicpal_machine_init
);
1420 static void musicpal_register_devices(void)
1422 sysbus_register_dev("mv88w8618_pic", sizeof(mv88w8618_pic_state
),
1423 mv88w8618_pic_init
);
1424 sysbus_register_dev("mv88w8618_pit", sizeof(mv88w8618_pit_state
),
1425 mv88w8618_pit_init
);
1426 sysbus_register_dev("mv88w8618_flashcfg", sizeof(mv88w8618_flashcfg_state
),
1427 mv88w8618_flashcfg_init
);
1428 sysbus_register_dev("mv88w8618_eth", sizeof(mv88w8618_eth_state
),
1429 mv88w8618_eth_init
);
1430 sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice
),
1431 mv88w8618_wlan_init
);
1432 sysbus_register_dev("musicpal_lcd", sizeof(musicpal_lcd_state
),
1434 sysbus_register_dev("musicpal_gpio", sizeof(musicpal_gpio_state
),
1435 musicpal_gpio_init
);
1436 sysbus_register_dev("musicpal_key", sizeof(musicpal_key_state
),
1440 device_init(musicpal_register_devices
)