hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "isa.h"
  30 #include "sysbus.h"
  31
  32 /*
  33  * I440FX chipset data sheet.
  34  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  35  */
  36
  37 typedef PCIHostState I440FXState;
  38
  39 typedef struct PIIX3State {
  40     PCIDevice dev;
  41     int pci_irq_levels[4];
  42     qemu_irq *pic;
  43 } PIIX3State;
  44
  45 struct PCII440FXState {
  46     PCIDevice dev;
  47     target_phys_addr_t isa_page_descs[384 / 4];
  48     uint8_t smm_enabled;
  49     PIIX3State *piix3;
  50 };
  51
  52
  53 #define I440FX_PAM      0x59
  54 #define I440FX_PAM_SIZE 7
  55 #define I440FX_SMRAM    0x72
  56
  57 static void piix3_set_irq(void *opaque, int irq_num, int level);
  58
  59 /* return the global irq number corresponding to a given device irq
  60    pin. We could also use the bus number to have a more precise
  61    mapping. */
  62 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
  63 {
  64     int slot_addend;
  65     slot_addend = (pci_dev->devfn >> 3) - 1;
  66     return (irq_num + slot_addend) & 3;
  67 }
  68
  69 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
  70 {
  71     uint32_t addr;
  72
  73     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
  74     switch(r) {
  75     case 3:
  76         /* RAM */
  77         cpu_register_physical_memory(start, end - start,
  78                                      start);
  79         break;
  80     case 1:
  81         /* ROM (XXX: not quite correct) */
  82         cpu_register_physical_memory(start, end - start,
  83                                      start | IO_MEM_ROM);
  84         break;
  85     case 2:
  86     case 0:
  87         /* XXX: should distinguish read/write cases */
  88         for(addr = start; addr < end; addr += 4096) {
  89             cpu_register_physical_memory(addr, 4096,
  90                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
  91         }
  92         break;
  93     }
  94 }
  95
  96 static void i440fx_update_memory_mappings(PCII440FXState *d)
  97 {
  98     int i, r;
  99     uint32_t smram, addr;
 100
 101     update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
 102     for(i = 0; i < 12; i++) {
 103         r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
 104         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
 105     }
 106     smram = d->dev.config[I440FX_SMRAM];
 107     if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 108         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
 109     } else {
 110         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
 111             cpu_register_physical_memory(addr, 4096,
 112                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 113         }
 114     }
 115 }
 116
 117 void i440fx_set_smm(PCII440FXState *d, int val)
 118 {
 119     val = (val != 0);
 120     if (d->smm_enabled != val) {
 121         d->smm_enabled = val;
 122         i440fx_update_memory_mappings(d);
 123     }
 124 }
 125
 126
 127 /* XXX: suppress when better memory API. We make the assumption that
 128    no device (in particular the VGA) changes the memory mappings in
 129    the 0xa0000-0x100000 range */
 130 void i440fx_init_memory_mappings(PCII440FXState *d)
 131 {
 132     int i;
 133     for(i = 0; i < 96; i++) {
 134         d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
 135     }
 136 }
 137
 138 static void i440fx_write_config(PCIDevice *dev,
 139                                 uint32_t address, uint32_t val, int len)
 140 {
 141     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 142
 143     /* XXX: implement SMRAM.D_LOCK */
 144     pci_default_write_config(dev, address, val, len);
 145     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 146         range_covers_byte(address, len, I440FX_SMRAM)) {
 147         i440fx_update_memory_mappings(d);
 148     }
 149 }
 150
 151 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 152 {
 153     PCII440FXState *d = opaque;
 154     int ret, i;
 155
 156     ret = pci_device_load(&d->dev, f);
 157     if (ret < 0)
 158         return ret;
 159     i440fx_update_memory_mappings(d);
 160     qemu_get_8s(f, &d->smm_enabled);
 161
 162     if (version_id == 2)
 163         for (i = 0; i < 4; i++)
 164             d->piix3->pci_irq_levels[i] = qemu_get_be32(f);
 165
 166     return 0;
 167 }
 168
 169 static int i440fx_post_load(void *opaque, int version_id)
 170 {
 171     PCII440FXState *d = opaque;
 172
 173     i440fx_update_memory_mappings(d);
 174     return 0;
 175 }
 176
 177 static const VMStateDescription vmstate_i440fx = {
 178     .name = "I440FX",
 179     .version_id = 3,
 180     .minimum_version_id = 3,
 181     .minimum_version_id_old = 1,
 182     .load_state_old = i440fx_load_old,
 183     .post_load = i440fx_post_load,
 184     .fields      = (VMStateField []) {
 185         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 186         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 187         VMSTATE_END_OF_LIST()
 188     }
 189 };
 190
 191 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 192 {
 193     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 194
 195     pci_host_conf_register_ioport(0xcf8, s);
 196
 197     pci_host_data_register_ioport(0xcfc, s);
 198     return 0;
 199 }
 200
 201 static int i440fx_initfn(PCIDevice *dev)
 202 {
 203     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 204
 205     pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
 206     pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
 207     d->dev.config[0x08] = 0x02; // revision
 208     pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
 209     d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 210
 211     d->dev.config[I440FX_SMRAM] = 0x02;
 212
 213     return 0;
 214 }
 215
 216 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
 217 {
 218     DeviceState *dev;
 219     PCIBus *b;
 220     PCIDevice *d;
 221     I440FXState *s;
 222     PIIX3State *piix3;
 223
 224     dev = qdev_create(NULL, "i440FX-pcihost");
 225     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 226     b = pci_bus_new(&s->busdev.qdev, NULL, 0);
 227     s->bus = b;
 228     qdev_init_nofail(dev);
 229
 230     d = pci_create_simple(b, 0, "i440FX");
 231     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 232
 233     piix3 = DO_UPCAST(PIIX3State, dev,
 234                                  pci_create_simple(b, -1, "PIIX3"));
 235     piix3->pic = pic;
 236     pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, 4);
 237     (*pi440fx_state)->piix3 = piix3;
 238
 239     *piix3_devfn = piix3->dev.devfn;
 240
 241     return b;
 242 }
 243
 244 /* PIIX3 PCI to ISA bridge */
 245
 246 static void piix3_set_irq(void *opaque, int irq_num, int level)
 247 {
 248     int i, pic_irq, pic_level;
 249     PIIX3State *piix3 = opaque;
 250
 251     piix3->pci_irq_levels[irq_num] = level;
 252
 253     /* now we change the pic irq level according to the piix irq mappings */
 254     /* XXX: optimize */
 255     pic_irq = piix3->dev.config[0x60 + irq_num];
 256     if (pic_irq < 16) {
 257         /* The pic level is the logical OR of all the PCI irqs mapped
 258            to it */
 259         pic_level = 0;
 260         for (i = 0; i < 4; i++) {
 261             if (pic_irq == piix3->dev.config[0x60 + i])
 262                 pic_level |= piix3->pci_irq_levels[i];
 263         }
 264         qemu_set_irq(piix3->pic[pic_irq], pic_level);
 265     }
 266 }
 267
 268 static void piix3_reset(void *opaque)
 269 {
 270     PIIX3State *d = opaque;
 271     uint8_t *pci_conf = d->dev.config;
 272
 273     pci_conf[0x04] = 0x07; // master, memory and I/O
 274     pci_conf[0x05] = 0x00;
 275     pci_conf[0x06] = 0x00;
 276     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 277     pci_conf[0x4c] = 0x4d;
 278     pci_conf[0x4e] = 0x03;
 279     pci_conf[0x4f] = 0x00;
 280     pci_conf[0x60] = 0x80;
 281     pci_conf[0x61] = 0x80;
 282     pci_conf[0x62] = 0x80;
 283     pci_conf[0x63] = 0x80;
 284     pci_conf[0x69] = 0x02;
 285     pci_conf[0x70] = 0x80;
 286     pci_conf[0x76] = 0x0c;
 287     pci_conf[0x77] = 0x0c;
 288     pci_conf[0x78] = 0x02;
 289     pci_conf[0x79] = 0x00;
 290     pci_conf[0x80] = 0x00;
 291     pci_conf[0x82] = 0x00;
 292     pci_conf[0xa0] = 0x08;
 293     pci_conf[0xa2] = 0x00;
 294     pci_conf[0xa3] = 0x00;
 295     pci_conf[0xa4] = 0x00;
 296     pci_conf[0xa5] = 0x00;
 297     pci_conf[0xa6] = 0x00;
 298     pci_conf[0xa7] = 0x00;
 299     pci_conf[0xa8] = 0x0f;
 300     pci_conf[0xaa] = 0x00;
 301     pci_conf[0xab] = 0x00;
 302     pci_conf[0xac] = 0x00;
 303     pci_conf[0xae] = 0x00;
 304
 305     memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
 306 }
 307
 308 static const VMStateDescription vmstate_piix3 = {
 309     .name = "PIIX3",
 310     .version_id = 3,
 311     .minimum_version_id = 2,
 312     .minimum_version_id_old = 2,
 313     .fields      = (VMStateField []) {
 314         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 315         VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3),
 316         VMSTATE_END_OF_LIST()
 317     }
 318 };
 319
 320 static int piix3_initfn(PCIDevice *dev)
 321 {
 322     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 323     uint8_t *pci_conf;
 324
 325     isa_bus_new(&d->dev.qdev);
 326
 327     pci_conf = d->dev.config;
 328     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 329     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 330     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
 331     pci_conf[PCI_HEADER_TYPE] =
 332         PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
 333
 334     qemu_register_reset(piix3_reset, d);
 335     return 0;
 336 }
 337
 338 static PCIDeviceInfo i440fx_info[] = {
 339     {
 340         .qdev.name    = "i440FX",
 341         .qdev.desc    = "Host bridge",
 342         .qdev.size    = sizeof(PCII440FXState),
 343         .qdev.vmsd    = &vmstate_i440fx,
 344         .qdev.no_user = 1,
 345         .init         = i440fx_initfn,
 346         .config_write = i440fx_write_config,
 347     },{
 348         .qdev.name    = "PIIX3",
 349         .qdev.desc    = "ISA bridge",
 350         .qdev.size    = sizeof(PIIX3State),
 351         .qdev.vmsd    = &vmstate_piix3,
 352         .qdev.no_user = 1,
 353         .init         = piix3_initfn,
 354     },{
 355         /* end of list */
 356     }
 357 };
 358
 359 static SysBusDeviceInfo i440fx_pcihost_info = {
 360     .init         = i440fx_pcihost_initfn,
 361     .qdev.name    = "i440FX-pcihost",
 362     .qdev.size    = sizeof(I440FXState),
 363     .qdev.no_user = 1,
 364 };
 365
 366 static void i440fx_register(void)
 367 {
 368     sysbus_register_withprop(&i440fx_pcihost_info);
 369     pci_qdev_register_many(i440fx_info);
 370 }
 371 device_init(i440fx_register);