hw/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "qemu-timer.h"
  26 #include "sysemu.h"
  27 #include "pc.h"
  28 #include "isa.h"
  29 #include "hpet_emul.h"
  30
  31 //#define DEBUG_CMOS
  32
  33 #define RTC_SECONDS             0
  34 #define RTC_SECONDS_ALARM       1
  35 #define RTC_MINUTES             2
  36 #define RTC_MINUTES_ALARM       3
  37 #define RTC_HOURS               4
  38 #define RTC_HOURS_ALARM         5
  39 #define RTC_ALARM_DONT_CARE    0xC0
  40
  41 #define RTC_DAY_OF_WEEK         6
  42 #define RTC_DAY_OF_MONTH        7
  43 #define RTC_MONTH               8
  44 #define RTC_YEAR                9
  45
  46 #define RTC_REG_A               10
  47 #define RTC_REG_B               11
  48 #define RTC_REG_C               12
  49 #define RTC_REG_D               13
  50
  51 #define REG_A_UIP 0x80
  52
  53 #define REG_B_SET  0x80
  54 #define REG_B_PIE  0x40
  55 #define REG_B_AIE  0x20
  56 #define REG_B_UIE  0x10
  57 #define REG_B_SQWE 0x08
  58 #define REG_B_DM   0x04
  59
  60 #define REG_C_UF   0x10
  61 #define REG_C_IRQF 0x80
  62 #define REG_C_PF   0x40
  63 #define REG_C_AF   0x20
  64
  65 struct RTCState {
  66     ISADevice dev;
  67     uint8_t cmos_data[128];
  68     uint8_t cmos_index;
  69     struct tm current_tm;
  70     int32_t base_year;
  71     qemu_irq irq;
  72     qemu_irq sqw_irq;
  73     int it_shift;
  74     /* periodic timer */
  75     QEMUTimer *periodic_timer;
  76     int64_t next_periodic_time;
  77     /* second update */
  78     int64_t next_second_time;
  79     uint32_t irq_coalesced;
  80     uint32_t period;
  81     QEMUTimer *coalesced_timer;
  82     QEMUTimer *second_timer;
  83     QEMUTimer *second_timer2;
  84 };
  85
  86 static void rtc_irq_raise(qemu_irq irq) {
  87     /* When HPET is operating in legacy mode, RTC interrupts are disabled
  88      * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
  89      * mode is established while interrupt is raised. We want it to
  90      * be lowered in any case
  91      */
  92 #if defined TARGET_I386
  93     if (!hpet_in_legacy_mode())
  94 #endif
  95         qemu_irq_raise(irq);
  96 }
  97
  98 static void rtc_set_time(RTCState *s);
  99 static void rtc_copy_date(RTCState *s);
 100
 101 #ifdef TARGET_I386
 102 static void rtc_coalesced_timer_update(RTCState *s)
 103 {
 104     if (s->irq_coalesced == 0) {
 105         qemu_del_timer(s->coalesced_timer);
 106     } else {
 107         /* divide each RTC interval to 2 - 8 smaller intervals */
 108         int c = MIN(s->irq_coalesced, 7) + 1;
 109         int64_t next_clock = qemu_get_clock(rtc_clock) +
 110             muldiv64(s->period / c, get_ticks_per_sec(), 32768);
 111         qemu_mod_timer(s->coalesced_timer, next_clock);
 112     }
 113 }
 114
 115 static void rtc_coalesced_timer(void *opaque)
 116 {
 117     RTCState *s = opaque;
 118
 119     if (s->irq_coalesced != 0) {
 120         apic_reset_irq_delivered();
 121         s->cmos_data[RTC_REG_C] |= 0xc0;
 122         rtc_irq_raise(s->irq);
 123         if (apic_get_irq_delivered()) {
 124             s->irq_coalesced--;
 125         }
 126     }
 127
 128     rtc_coalesced_timer_update(s);
 129 }
 130 #endif
 131
 132 static void rtc_timer_update(RTCState *s, int64_t current_time)
 133 {
 134     int period_code, period;
 135     int64_t cur_clock, next_irq_clock;
 136     int enable_pie;
 137
 138     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 139 #if defined TARGET_I386
 140     /* disable periodic timer if hpet is in legacy mode, since interrupts are
 141      * disabled anyway.
 142      */
 143     enable_pie = !hpet_in_legacy_mode();
 144 #else
 145     enable_pie = 1;
 146 #endif
 147     if (period_code != 0
 148         && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie)
 149             || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
 150         if (period_code <= 2)
 151             period_code += 7;
 152         /* period in 32 Khz cycles */
 153         period = 1 << (period_code - 1);
 154 #ifdef TARGET_I386
 155         if(period != s->period)
 156             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 157         s->period = period;
 158 #endif
 159         /* compute 32 khz clock */
 160         cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
 161         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 162         s->next_periodic_time =
 163             muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1;
 164         qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
 165     } else {
 166 #ifdef TARGET_I386
 167         s->irq_coalesced = 0;
 168 #endif
 169         qemu_del_timer(s->periodic_timer);
 170     }
 171 }
 172
 173 static void rtc_periodic_timer(void *opaque)
 174 {
 175     RTCState *s = opaque;
 176
 177     rtc_timer_update(s, s->next_periodic_time);
 178     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 179         s->cmos_data[RTC_REG_C] |= 0xc0;
 180 #ifdef TARGET_I386
 181         if(rtc_td_hack) {
 182             apic_reset_irq_delivered();
 183             rtc_irq_raise(s->irq);
 184             if (!apic_get_irq_delivered()) {
 185                 s->irq_coalesced++;
 186                 rtc_coalesced_timer_update(s);
 187             }
 188         } else
 189 #endif
 190         rtc_irq_raise(s->irq);
 191     }
 192     if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
 193         /* Not square wave at all but we don't want 2048Hz interrupts!
 194            Must be seen as a pulse.  */
 195         qemu_irq_raise(s->sqw_irq);
 196     }
 197 }
 198
 199 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
 200 {
 201     RTCState *s = opaque;
 202
 203     if ((addr & 1) == 0) {
 204         s->cmos_index = data & 0x7f;
 205     } else {
 206 #ifdef DEBUG_CMOS
 207         printf("cmos: write index=0x%02x val=0x%02x\n",
 208                s->cmos_index, data);
 209 #endif
 210         switch(s->cmos_index) {
 211         case RTC_SECONDS_ALARM:
 212         case RTC_MINUTES_ALARM:
 213         case RTC_HOURS_ALARM:
 214             /* XXX: not supported */
 215             s->cmos_data[s->cmos_index] = data;
 216             break;
 217         case RTC_SECONDS:
 218         case RTC_MINUTES:
 219         case RTC_HOURS:
 220         case RTC_DAY_OF_WEEK:
 221         case RTC_DAY_OF_MONTH:
 222         case RTC_MONTH:
 223         case RTC_YEAR:
 224             s->cmos_data[s->cmos_index] = data;
 225             /* if in set mode, do not update the time */
 226             if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 227                 rtc_set_time(s);
 228             }
 229             break;
 230         case RTC_REG_A:
 231             /* UIP bit is read only */
 232             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 233                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 234             rtc_timer_update(s, qemu_get_clock(rtc_clock));
 235             break;
 236         case RTC_REG_B:
 237             if (data & REG_B_SET) {
 238                 /* set mode: reset UIP mode */
 239                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 240                 data &= ~REG_B_UIE;
 241             } else {
 242                 /* if disabling set mode, update the time */
 243                 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
 244                     rtc_set_time(s);
 245                 }
 246             }
 247             s->cmos_data[RTC_REG_B] = data;
 248             rtc_timer_update(s, qemu_get_clock(rtc_clock));
 249             break;
 250         case RTC_REG_C:
 251         case RTC_REG_D:
 252             /* cannot write to them */
 253             break;
 254         default:
 255             s->cmos_data[s->cmos_index] = data;
 256             break;
 257         }
 258     }
 259 }
 260
 261 static inline int to_bcd(RTCState *s, int a)
 262 {
 263     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 264         return a;
 265     } else {
 266         return ((a / 10) << 4) | (a % 10);
 267     }
 268 }
 269
 270 static inline int from_bcd(RTCState *s, int a)
 271 {
 272     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 273         return a;
 274     } else {
 275         return ((a >> 4) * 10) + (a & 0x0f);
 276     }
 277 }
 278
 279 static void rtc_set_time(RTCState *s)
 280 {
 281     struct tm *tm = &s->current_tm;
 282
 283     tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
 284     tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
 285     tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 286     if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
 287         (s->cmos_data[RTC_HOURS] & 0x80)) {
 288         tm->tm_hour += 12;
 289     }
 290     tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 291     tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 292     tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 293     tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
 294 }
 295
 296 static void rtc_copy_date(RTCState *s)
 297 {
 298     const struct tm *tm = &s->current_tm;
 299     int year;
 300
 301     s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
 302     s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
 303     if (s->cmos_data[RTC_REG_B] & 0x02) {
 304         /* 24 hour format */
 305         s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
 306     } else {
 307         /* 12 hour format */
 308         s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
 309         if (tm->tm_hour >= 12)
 310             s->cmos_data[RTC_HOURS] |= 0x80;
 311     }
 312     s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday + 1);
 313     s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
 314     s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
 315     year = (tm->tm_year - s->base_year) % 100;
 316     if (year < 0)
 317         year += 100;
 318     s->cmos_data[RTC_YEAR] = to_bcd(s, year);
 319 }
 320
 321 /* month is between 0 and 11. */
 322 static int get_days_in_month(int month, int year)
 323 {
 324     static const int days_tab[12] = {
 325         31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
 326     };
 327     int d;
 328     if ((unsigned )month >= 12)
 329         return 31;
 330     d = days_tab[month];
 331     if (month == 1) {
 332         if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
 333             d++;
 334     }
 335     return d;
 336 }
 337
 338 /* update 'tm' to the next second */
 339 static void rtc_next_second(struct tm *tm)
 340 {
 341     int days_in_month;
 342
 343     tm->tm_sec++;
 344     if ((unsigned)tm->tm_sec >= 60) {
 345         tm->tm_sec = 0;
 346         tm->tm_min++;
 347         if ((unsigned)tm->tm_min >= 60) {
 348             tm->tm_min = 0;
 349             tm->tm_hour++;
 350             if ((unsigned)tm->tm_hour >= 24) {
 351                 tm->tm_hour = 0;
 352                 /* next day */
 353                 tm->tm_wday++;
 354                 if ((unsigned)tm->tm_wday >= 7)
 355                     tm->tm_wday = 0;
 356                 days_in_month = get_days_in_month(tm->tm_mon,
 357                                                   tm->tm_year + 1900);
 358                 tm->tm_mday++;
 359                 if (tm->tm_mday < 1) {
 360                     tm->tm_mday = 1;
 361                 } else if (tm->tm_mday > days_in_month) {
 362                     tm->tm_mday = 1;
 363                     tm->tm_mon++;
 364                     if (tm->tm_mon >= 12) {
 365                         tm->tm_mon = 0;
 366                         tm->tm_year++;
 367                     }
 368                 }
 369             }
 370         }
 371     }
 372 }
 373
 374
 375 static void rtc_update_second(void *opaque)
 376 {
 377     RTCState *s = opaque;
 378     int64_t delay;
 379
 380     /* if the oscillator is not in normal operation, we do not update */
 381     if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
 382         s->next_second_time += get_ticks_per_sec();
 383         qemu_mod_timer(s->second_timer, s->next_second_time);
 384     } else {
 385         rtc_next_second(&s->current_tm);
 386
 387         if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 388             /* update in progress bit */
 389             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 390         }
 391         /* should be 244 us = 8 / 32768 seconds, but currently the
 392            timers do not have the necessary resolution. */
 393         delay = (get_ticks_per_sec() * 1) / 100;
 394         if (delay < 1)
 395             delay = 1;
 396         qemu_mod_timer(s->second_timer2,
 397                        s->next_second_time + delay);
 398     }
 399 }
 400
 401 static void rtc_update_second2(void *opaque)
 402 {
 403     RTCState *s = opaque;
 404
 405     if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 406         rtc_copy_date(s);
 407     }
 408
 409     /* check alarm */
 410     if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 411         if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
 412              s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
 413             ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
 414              s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
 415             ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
 416              s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
 417
 418             s->cmos_data[RTC_REG_C] |= 0xa0;
 419             rtc_irq_raise(s->irq);
 420         }
 421     }
 422
 423     /* update ended interrupt */
 424     s->cmos_data[RTC_REG_C] |= REG_C_UF;
 425     if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
 426       s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 427       rtc_irq_raise(s->irq);
 428     }
 429
 430     /* clear update in progress bit */
 431     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 432
 433     s->next_second_time += get_ticks_per_sec();
 434     qemu_mod_timer(s->second_timer, s->next_second_time);
 435 }
 436
 437 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
 438 {
 439     RTCState *s = opaque;
 440     int ret;
 441     if ((addr & 1) == 0) {
 442         return 0xff;
 443     } else {
 444         switch(s->cmos_index) {
 445         case RTC_SECONDS:
 446         case RTC_MINUTES:
 447         case RTC_HOURS:
 448         case RTC_DAY_OF_WEEK:
 449         case RTC_DAY_OF_MONTH:
 450         case RTC_MONTH:
 451         case RTC_YEAR:
 452             ret = s->cmos_data[s->cmos_index];
 453             break;
 454         case RTC_REG_A:
 455             ret = s->cmos_data[s->cmos_index];
 456             break;
 457         case RTC_REG_C:
 458             ret = s->cmos_data[s->cmos_index];
 459             qemu_irq_lower(s->irq);
 460             s->cmos_data[RTC_REG_C] = 0x00;
 461             break;
 462         default:
 463             ret = s->cmos_data[s->cmos_index];
 464             break;
 465         }
 466 #ifdef DEBUG_CMOS
 467         printf("cmos: read index=0x%02x val=0x%02x\n",
 468                s->cmos_index, ret);
 469 #endif
 470         return ret;
 471     }
 472 }
 473
 474 void rtc_set_memory(RTCState *s, int addr, int val)
 475 {
 476     if (addr >= 0 && addr <= 127)
 477         s->cmos_data[addr] = val;
 478 }
 479
 480 void rtc_set_date(RTCState *s, const struct tm *tm)
 481 {
 482     s->current_tm = *tm;
 483     rtc_copy_date(s);
 484 }
 485
 486 /* PC cmos mappings */
 487 #define REG_IBM_CENTURY_BYTE        0x32
 488 #define REG_IBM_PS2_CENTURY_BYTE    0x37
 489
 490 static void rtc_set_date_from_host(RTCState *s)
 491 {
 492     struct tm tm;
 493     int val;
 494
 495     /* set the CMOS date */
 496     qemu_get_timedate(&tm, 0);
 497     rtc_set_date(s, &tm);
 498
 499     val = to_bcd(s, (tm.tm_year / 100) + 19);
 500     rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
 501     rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
 502 }
 503
 504 static void rtc_save(QEMUFile *f, void *opaque)
 505 {
 506     RTCState *s = opaque;
 507
 508     qemu_put_buffer(f, s->cmos_data, 128);
 509     qemu_put_8s(f, &s->cmos_index);
 510
 511     qemu_put_be32(f, s->current_tm.tm_sec);
 512     qemu_put_be32(f, s->current_tm.tm_min);
 513     qemu_put_be32(f, s->current_tm.tm_hour);
 514     qemu_put_be32(f, s->current_tm.tm_wday);
 515     qemu_put_be32(f, s->current_tm.tm_mday);
 516     qemu_put_be32(f, s->current_tm.tm_mon);
 517     qemu_put_be32(f, s->current_tm.tm_year);
 518
 519     qemu_put_timer(f, s->periodic_timer);
 520     qemu_put_be64(f, s->next_periodic_time);
 521
 522     qemu_put_be64(f, s->next_second_time);
 523     qemu_put_timer(f, s->second_timer);
 524     qemu_put_timer(f, s->second_timer2);
 525     qemu_put_be32(f, s->irq_coalesced);
 526     qemu_put_be32(f, s->period);
 527 }
 528
 529 static int rtc_load(QEMUFile *f, void *opaque, int version_id)
 530 {
 531     RTCState *s = opaque;
 532
 533     if (version_id < 1 || version_id > 2)
 534         return -EINVAL;
 535
 536     qemu_get_buffer(f, s->cmos_data, 128);
 537     qemu_get_8s(f, &s->cmos_index);
 538
 539     s->current_tm.tm_sec=qemu_get_be32(f);
 540     s->current_tm.tm_min=qemu_get_be32(f);
 541     s->current_tm.tm_hour=qemu_get_be32(f);
 542     s->current_tm.tm_wday=qemu_get_be32(f);
 543     s->current_tm.tm_mday=qemu_get_be32(f);
 544     s->current_tm.tm_mon=qemu_get_be32(f);
 545     s->current_tm.tm_year=qemu_get_be32(f);
 546
 547     qemu_get_timer(f, s->periodic_timer);
 548     s->next_periodic_time=qemu_get_be64(f);
 549
 550     s->next_second_time=qemu_get_be64(f);
 551     qemu_get_timer(f, s->second_timer);
 552     qemu_get_timer(f, s->second_timer2);
 553
 554     if (version_id >= 2) {
 555         s->irq_coalesced = qemu_get_be32(f);
 556         s->period = qemu_get_be32(f);
 557 #ifdef TARGET_I386
 558         if (rtc_td_hack) {
 559             rtc_coalesced_timer_update(s);
 560         }
 561 #endif
 562     }
 563     return 0;
 564 }
 565
 566 static void rtc_reset(void *opaque)
 567 {
 568     RTCState *s = opaque;
 569
 570     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 571     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 572
 573     qemu_irq_lower(s->irq);
 574
 575 #ifdef TARGET_I386
 576     if (rtc_td_hack)
 577             s->irq_coalesced = 0;
 578 #endif
 579 }
 580
 581 static int rtc_initfn(ISADevice *dev)
 582 {
 583     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 584     int base = 0x70;
 585     int isairq = 8;
 586
 587     isa_init_irq(dev, &s->irq, isairq);
 588
 589     s->cmos_data[RTC_REG_A] = 0x26;
 590     s->cmos_data[RTC_REG_B] = 0x02;
 591     s->cmos_data[RTC_REG_C] = 0x00;
 592     s->cmos_data[RTC_REG_D] = 0x80;
 593
 594     rtc_set_date_from_host(s);
 595
 596     s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s);
 597 #ifdef TARGET_I386
 598     if (rtc_td_hack)
 599         s->coalesced_timer =
 600             qemu_new_timer(rtc_clock, rtc_coalesced_timer, s);
 601 #endif
 602     s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s);
 603     s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s);
 604
 605     s->next_second_time =
 606         qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
 607     qemu_mod_timer(s->second_timer2, s->next_second_time);
 608
 609     register_ioport_write(base, 2, 1, cmos_ioport_write, s);
 610     register_ioport_read(base, 2, 1, cmos_ioport_read, s);
 611
 612     register_savevm("mc146818rtc", base, 2, rtc_save, rtc_load, s);
 613     qemu_register_reset(rtc_reset, s);
 614     return 0;
 615 }
 616
 617 RTCState *rtc_init(int base_year)
 618 {
 619     ISADevice *dev;
 620
 621     dev = isa_create("mc146818rtc");
 622     qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
 623     qdev_init_nofail(&dev->qdev);
 624     return DO_UPCAST(RTCState, dev, dev);
 625 }
 626
 627 static ISADeviceInfo mc146818rtc_info = {
 628     .qdev.name     = "mc146818rtc",
 629     .qdev.size     = sizeof(RTCState),
 630     .qdev.no_user  = 1,
 631     .init          = rtc_initfn,
 632     .qdev.props    = (Property[]) {
 633         DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 634         DEFINE_PROP_END_OF_LIST(),
 635     }
 636 };
 637
 638 static void mc146818rtc_register(void)
 639 {
 640     isa_qdev_register(&mc146818rtc_info);
 641 }
 642 device_init(mc146818rtc_register)
 643
 644 /* Memory mapped interface */
 645 static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
 646 {
 647     RTCState *s = opaque;
 648
 649     return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF;
 650 }
 651
 652 static void cmos_mm_writeb (void *opaque,
 653                             target_phys_addr_t addr, uint32_t value)
 654 {
 655     RTCState *s = opaque;
 656
 657     cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
 658 }
 659
 660 static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
 661 {
 662     RTCState *s = opaque;
 663     uint32_t val;
 664
 665     val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
 666 #ifdef TARGET_WORDS_BIGENDIAN
 667     val = bswap16(val);
 668 #endif
 669     return val;
 670 }
 671
 672 static void cmos_mm_writew (void *opaque,
 673                             target_phys_addr_t addr, uint32_t value)
 674 {
 675     RTCState *s = opaque;
 676 #ifdef TARGET_WORDS_BIGENDIAN
 677     value = bswap16(value);
 678 #endif
 679     cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
 680 }
 681
 682 static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
 683 {
 684     RTCState *s = opaque;
 685     uint32_t val;
 686
 687     val = cmos_ioport_read(s, addr >> s->it_shift);
 688 #ifdef TARGET_WORDS_BIGENDIAN
 689     val = bswap32(val);
 690 #endif
 691     return val;
 692 }
 693
 694 static void cmos_mm_writel (void *opaque,
 695                             target_phys_addr_t addr, uint32_t value)
 696 {
 697     RTCState *s = opaque;
 698 #ifdef TARGET_WORDS_BIGENDIAN
 699     value = bswap32(value);
 700 #endif
 701     cmos_ioport_write(s, addr >> s->it_shift, value);
 702 }
 703
 704 static CPUReadMemoryFunc * const rtc_mm_read[] = {
 705     &cmos_mm_readb,
 706     &cmos_mm_readw,
 707     &cmos_mm_readl,
 708 };
 709
 710 static CPUWriteMemoryFunc * const rtc_mm_write[] = {
 711     &cmos_mm_writeb,
 712     &cmos_mm_writew,
 713     &cmos_mm_writel,
 714 };
 715
 716 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
 717                       int base_year)
 718 {
 719     RTCState *s;
 720     int io_memory;
 721
 722     s = qemu_mallocz(sizeof(RTCState));
 723
 724     s->irq = irq;
 725     s->cmos_data[RTC_REG_A] = 0x26;
 726     s->cmos_data[RTC_REG_B] = 0x02;
 727     s->cmos_data[RTC_REG_C] = 0x00;
 728     s->cmos_data[RTC_REG_D] = 0x80;
 729
 730     s->base_year = base_year;
 731     rtc_set_date_from_host(s);
 732
 733     s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s);
 734     s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s);
 735     s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s);
 736
 737     s->next_second_time =
 738         qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
 739     qemu_mod_timer(s->second_timer2, s->next_second_time);
 740
 741     io_memory = cpu_register_io_memory(rtc_mm_read, rtc_mm_write, s);
 742     cpu_register_physical_memory(base, 2 << it_shift, io_memory);
 743
 744     register_savevm("mc146818rtc", base, 2, rtc_save, rtc_load, s);
 745     qemu_register_reset(rtc_reset, s);
 746     return s;
 747 }