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target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren
2023-09-11 Rob Bradfordtarget/riscv: Implement WARL behaviour for mcountinhibit...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Max Choutarget/riscv: Add Zvksed ISA extension support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Max Choucrypto: Add SM4 constant parameter CK
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Max Choucrypto: Create sm4_subword
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Nazar Kazakovtarget/riscv: Add Zvkg ISA extension support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Lawrence Huntertarget/riscv: Add Zvksh ISA extension support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Kiran Ostrolenktarget/riscv: Add Zvknh ISA extension support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Nazar Kazakovtarget/riscv: Add Zvkned ISA extension support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Dickon Hoodtarget/riscv: Add Zvbb ISA extension support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Kiran Ostrolenktarget/riscv: Refactor some of the generic vector functionality
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Dickon Hoodtarget/riscv: Refactor translation of vector-widening...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Nazar Kazakovtarget/riscv: Move vector translation checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Lawrence Huntertarget/riscv: Add Zvbc ISA extension support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Nazar Kazakovtarget/riscv: Remove redundant "cpu_vl == 0" checks
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Kiran Ostrolenktarget/riscv: Refactor vector-vector translation macro
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Kiran Ostrolenktarget/riscv: Refactor some of the generic vector functionality
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Ard Biesheuveltarget/riscv: Use existing lookup tables for MixColumns
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 LIU Zhiweitarget/riscv: Fix page_check_range use in fault-only...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Daniel Henrique... target/riscv/cpu.c: add smepmp isa string
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Daniel Henrique... target/riscv/cpu.c: add zmmul isa string
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Thomas Huthhw/char/riscv_htif: Fix the console syscall on big...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Thomas Huthhw/char/riscv_htif: Fix printing of console characters...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Daniel Henrique... target/riscv/cpu.c: do not run 'host' CPU with TCG
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-08-11 Daniel Henrique... hw/riscv/virt.c: change 'aclint' TCG check
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-08-11 Daniel Henrique... target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids()
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-23 Bin Mengroms/opensbi: Upgrade from v1.3 to v1.3.1
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-19 Rob Bradfordtarget/riscv: Fix LMUL check to use VLEN
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-19 Zhao Liuhw/riscv: Fix typo field in error_report
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-19 Daniel Henrique... target/riscv/cpu.c: check priv_ver before auto-enable...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-19 Christoph Müllnerriscv/disas: Fix disas output of upper immediates
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-19 Daniel Henrique... docs/system/target-riscv.rst: tidy CPU firmware section
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Christoph Müllnerriscv: Add support for the Zfa extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/kvm.c: read/write (cbom|cboz)_blocksize...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv: update multi-letter extension KVM properties
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu.c: create KVM mock properties
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu.c: remove priv_ver check from riscv_isa_str...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu.c: add satp_mode properties earlier
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/kvm.c: add multi-letter extension KVM...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/kvm.c: update KVM MISA bits
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv: add KVM specific MISA properties
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu: add misa_ext_info_arr[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv: handle mvendorid/marchid/mimpid for KVM...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv: read marchid/mimpid in kvm_riscv_init_machine_...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv: use KVM scratch CPUs to init KVM properties
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu.c: restrict 'marchid' value
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu.c: restrict 'mimpid' value
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu.c: restrict 'mvendorid' value
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv: skip features setup for KVM CPUs
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Lakshmi Bai Raja... hw/riscv: virt: Convert fdt_load_addr to uint64_t
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Guenter Roeckriscv: Generate devicetree only after machine initialization...
Cc: Alistair Francis <alistair23@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 yang.zhangtarget/riscv KVM_RISCV_SET_TIMER macro is not configured...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Add disas support for BF16 extensions
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Jason Chientarget/riscv: Set the correct exception for implict...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Expose properties for BF16 extensions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Add support for Zvfbfwma extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Add support for Zvfbfmin extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Add support for Zfbfmin extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Add properties for BF16 extensions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Robbin Ehnlinux-user/riscv: Add syscall riscv_hwprobe
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Philippe Mathieu... hw/riscv/virt: Restrict ACLINT to TCG
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Ivan Klokovtarget/riscv: Add RVV registers to log
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Philippe Mathieu... target/riscv: Only build KVM guest with same wordsize...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Philippe Mathieu... target/riscv: Only unify 'riscv32/64' -> 'riscv' for...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Tommy Wutests/qtest: sifive-e-aon-watchdog-test.c: Add QTest...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Tommy Wuhw/riscv: sifive_e: Support the watchdog timer of HiFive...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Tommy Wuhw/misc: sifive_e_aon: Support the watchdog timer of...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Bin Mengtests/avocado: riscv: Enable 32-bit Spike OpenSBI boot...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Bin Mengroms/opensbi: Upgrade from v1.2 to v1.3
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: update cur_pmbase/pmmask based on mode...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Add additional xlen for address when...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Daniel Henrique... target/riscv/cpu.c: fix veyron-v1 CPU properties
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Remove redundant assignment to SXL
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Support MSTATUS.MPV/GVA only when RVH...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Weiwei Litarget/riscv: Make MPV only work when MPP != PRV_M
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Christoph Müllnerdisas/riscv: Add support for XThead* instructions
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Christoph Müllnerdisas/riscv: Add support for XVentanaCondOps
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Christoph Müllnerdisas/riscv: Provide infrastructure for vendor extensions
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Christoph Müllnerdisas/riscv: Encapsulate opcode_data into decode
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Christoph Müllnerdisas/riscv: Make rv_op_illegal a shared enum value
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Christoph Müllnerdisas/riscv: Move types/constants to new header file
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 Christoph Müllnertarget/riscv: Factor out extension tests to cpu_cfg.h
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-07-10 LIU Zhiweitarget/riscv: Use xl instead of mxl for disassemble
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-14 Tommy Wuhw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfg...
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Himanshu Chauhantarget/riscv: Smepmp: Return error when access permission...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Xiao Wangtarget/riscv/vector_helper.c: Remove the check for...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Xiao Wangtarget/riscv/vector_helper.c: clean up reference of...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Fix initialized value for cur_pmmask
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Ivan Klokovutil/log: Add vector registers to log
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Sunil V Ldocs/system: riscv: Add pflash usage details
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Sunil V Lriscv/virt: Support using pflash via -blockdev option
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Sunil V Lhw/riscv: virt: Assume M-mode FW in pflash0 only when...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Remove pc_succ_insn from DisasContext
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Enable PC-relative translation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Use true diff for gen_pc_plus_diff
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Change gen_set_pc_imm to gen_update_pc
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-06-13 Weiwei Litarget/riscv: Change gen_goto_tb to work on displacements
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 commit | commitdiff | tree
2023-06-13 Weiwei Litarget/riscv: Introduce cur_insn_len into DisasContext
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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