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target/riscv: Fix the bug of HLVX/HLV/HSV
2020-11-17
Alistair
F
ranc
i
s
r
eg
i
ste
r
: Rem
o
ve unnecessary N
U
LL
c
h
eck
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Alistair Francis
intc
/
ibex_plic: Ensu
r
e
we
don't loose interrupts
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-14
Alistair Francis
intc/ibex_p
l
ic: Fix so
m
e typ
o
s
i
n the comments
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistai
r
F
rancis
hw/intc/ibex_plic: Clear th
e
claim
r
egis
t
er when rea
d
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistair Francis
targ
e
t/risc
v
: Split the Hypervisor execute load helper
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
Alistai
r
Francis
target/riscv: Remove the hyp l
o
a
d
and store func
t
ions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
A
l
istair Franci
s
target/r
i
scv: Remove the HS_TWO
_
STAG
E
flag
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
A
l
istair F
r
ancis
target
/
riscv
:
Set
the
v
irtuali
s
ed MMU mode when doing
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-09
A
l
i
s
t
ai
r
Francis
target/ris
c
v: Add
a virtuali
s
ed MMU
Mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-11-04
Al
i
s
tair Francis
linu
x
-
u
ser/syscall: Fix
m
issing target_to_host_t
i
m
e
spec64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alis
t
air Francis
hw/riscv: Load th
e
kernel after the fi
r
mware
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alist
a
i
r
Fran
c
i
s
h
w
/
risc
v
:
A
dd a riscv_is_32_b
i
t() function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Ali
s
tair F
r
ancis
hw/riscv
:
Return the end addres
s
of the
l
o
aded firmw
a
r
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
A
l
istair
F
r
ancis
h
w
/ri
s
cv: sifive_u: Allow specifying
t
he
C
P
U
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-10-22
Alist
a
ir Francis
riscv: Co
n
vert
i
n
t
errupt
l
o
gs to use qemu_log
_
mask()
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-09-25
A
listair Francis
co
r
e/regis
t
er: Specify insta
n
c
e_
s
ize
i
n
the TypeInfo
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Ali
s
tair
F
rancis
targ
e
t/
r
iscv
:
Sup
p
ort
t
he Virtual Instruction fault
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistai
r
F
ranc
i
s
target
/
riscv: R
e
turn the
exception
f
rom
invalid
CSR
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alist
a
ir Francis
tar
g
et/r
i
scv
:
Suppor
t
t
h
e
v
0
.
6
H
yp
e
rvisor ex
t
e
n
sion
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fran
c
is
targe
t
/r
i
s
c
v
:
O
n
l
y
supp
o
rt little
e
ndian guest
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
Fra
n
cis
targe
t
/
riscv
:
On
l
y support a single V
S
X
L
length
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
listair
F
ra
n
cis
targe
t
/riscv: Upd
a
te the CSRs to
the v0
.
6
H
yp extensio
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
Francis
target/r
i
s
cv: Update the
H
ypervisor
t
rap return/entry
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Francis
t
a
rget/
r
iscv:
F
ix the interr
u
pt
c
ause code
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
is
t
air Fra
n
c
is
targe
t
/riscv: Convert
M
S
TA
T
US MTL to G
V
A
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
ista
i
r Francis
t
a
rget/riscv: D
o
n't
a
llow guest
t
o
write to htinst
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
l
i
stair Francis
targ
e
t/riscv: Do two-st
a
ge lookups on hlv/hlvx/h
s
v
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair Fran
c
i
s
target/riscv: A
l
l
o
w g
e
nerati
n
g hlv/hlvx/hsv i
n
struction
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Alistair
F
rancis
target
/
riscv:
A
llow setting a two-st
a
g
e
l
ookup in
t
he
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair Francis
hw/intc: i
b
e
x
_plic: Honour source p
r
i
orities
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alistair Francis
hw/in
t
c: ib
e
x_p
l
ic: Don't allow
repeat in
t
errupts on
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-22
Alista
i
r
F
rancis
hw/intc: ibex_plic:
U
pdate the
p
e
nding irqs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-08-21
A
listair
F
rancis
hw/sd/pl181
:
Replace f
p
rint
f
(stderr, "*\
n
")
w
ith error_report
(
)
Signed-off-by:
Alistair Francis
<alistair.francis@xilinx.com>
commit
|
commitdiff
|
tree
2020-07-14
Alist
a
ir Fra
n
cis
hw/char: Conver
t
the Ibex UART to use the registerfields API
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-14
Alistai
r
Francis
hw/char: Convert the Ibex UA
R
T
to use the
q
dev
Clock
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-07-02
Alistair Francis
hw/riscv: Allow 64 bit
a
ccess
t
o SiFive CLINT
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Fr
a
ncis
target/r
i
s
cv:
Use
a
smaller
g
uess size for no-MMU
PMP
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Francis
r
i
scv/
o
pen
t
it
a
n: Connect the UART d
e
vice
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Franc
i
s
r
iscv/opentitan
:
Conne
c
t the
PLIC devi
c
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alist
a
i
r Francis
hw/intc: Initial c
o
m
mit of l
o
wRISC Ibex PLIC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
l
i
stair Fran
c
is
hw/char: Initia
l
com
m
i
t of Ib
e
x UART
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Ali
s
tair Francis
riscv/o
p
entitan: Fix the
ROM size
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Al
i
stair
Francis
tar
g
et/ri
s
c
v
: Implement check
s
for hfence
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair F
r
anc
i
s
ta
r
g
et/riscv: Move the hf
e
nce instructi
o
ns to the rv
h
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
l
istair Francis
ta
r
ge
t
/riscv
:
Report
e
rrors validatin
g
2nd-stag
e
PTEs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
A
listair F
r
a
ncis
targe
t
/ris
c
v
:
S
e
t
access
a
s d
a
ta_load
whe
n
validating
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-19
Alistair Fr
a
ncis
sifive_e: Suppor
t
the re
v
B
machine
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alista
i
r Francis
risc
v
: Init
i
al commit of OpenT
i
tan machi
n
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alist
a
ir Francis
target
/
ri
s
cv: Add the
lo
w
RISC
Ibex CPU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Franc
i
s
t
a
rget/riscv:
D
on't set PMP f
e
ature in the cp
u
init
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alist
a
ir
Fran
c
i
s
ta
r
get/
r
iscv: Di
s
able the M
M
U
correctly
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alist
a
i
r
Francis
target/riscv:
D
o
n't overwrite th
e
reset vector
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Al
i
stai
r
Fra
n
cis
riscv/boot: Add a missing header includ
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
l
istair Fra
n
cis
ris
c
v:
s
i
f
ive_e: Manually
define the machi
n
e
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair
Franc
i
s
docs: depr
e
cated: Upda
t
e
the
-
bio
s
doc
u
me
n
tatio
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Alistair Fr
a
ncis
target/
r
iscv: Dro
p
su
p
port f
o
r
ISA sp
e
c
v
e
rsi
o
n 1
.
09
.
1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
Ali
s
tai
r
Fran
c
i
s
tar
g
et/riscv: R
e
m
ov
e
the deprecated C
P
Us
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-06-03
A
l
istair
Francis
hw/
r
iscv
:
sp
i
ke: Rem
o
ve deprecated
ISA specific
m
a
c
hines
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistair Francis
riscv: AND stage-1 and stage-2 protectio
n
flags
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alistai
r
Francis
riscv: Don't use stage-2
P
TE
l
ookup p
r
otection fl
a
g
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alis
t
a
i
r
Fran
c
i
s
riscv/sifive_u: Add
a
serial pr
o
perty to
t
he sifiv
e
_
u SoC
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Alist
a
ir Francis
riscv/sifive_
u
:
Fix up file o
r
d
ering
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-30
Alista
i
r Francis
l
inux
-
user: S
u
pport futex_time
6
4
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alis
t
air Francis
linux
-
us
e
r/ri
s
cv
:
Update the sys
c
all_nr'
s
to the 5
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Al
i
stair Fran
c
is
linux-user/sys
c
all: Add suppo
r
t for clock_gettime64
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-20
Alis
t
air Fran
c
i
s
linux-
u
ser
:
Protec
t
more sysc
a
lls
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-03-17
Alis
t
air Francis
target
/
riscv: Correctl
y
implement TSR trap
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alista
i
r
F
ra
n
cis
target/riscv:
A
llow ena
b
ling the Hyper
v
is
o
r extension
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Ali
s
t
air
F
rancis
target
/
r
iscv: Add the MSTATUS_MPV
_
IS
S
ET helper ma
c
r
o
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
li
s
tair Francis
target/ris
c
v: Add support f
o
r
the 32-bit
M
S
T
A
TUS
H
CSR
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alistair
F
r
a
ncis
tar
g
et/riscv:
S
e
t
htval and m
t
val2 o
n
execptions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Al
i
stair Francis
targ
e
t
/riscv: Ra
i
s
e the ne
w
execpti
o
ns
w
hen
2nd stage
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
A
li
s
tair Franci
s
targ
e
t/ris
c
v: Impleme
n
t second st
a
ge
M
MU
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Alist
a
ir
F
rancis
target/ri
s
cv
:
Allow
specifying MMU stage
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Francis
targ
e
t/riscv: Resp
e
ct
M
PRV and SPR
V
f
o
r floating point op
s
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair F
r
a
nci
s
target/
r
i
scv:
M
ark both
s
status
a
nd m
s
s
t
atus_h
s
a
s
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Francis
target/
r
i
scv: Disabl
e
gues
t
FP su
p
p
o
r
t
based o
n
virtual
.
.
.
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Al
i
stai
r
Francis
ta
r
g
e
t/riscv: O
n
ly set TB fl
a
g
s with FP status if enabled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Francis
target/riscv: Remove
the hret ins
t
r
ucti
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
A
listair Franci
s
target/riscv: Ad
d
hfence i
n
struc
t
ions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Francis
t
arge
t
/
riscv: Add Hyperviso
r
t
r
ap return support
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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commitdiff
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tree
2020-02-27
Alista
i
r Francis
target/riscv: Add
h
ypv
e
r
visor trap s
u
pport
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Ali
s
tair
Francis
target/
r
iscv: Generate illegal
i
nstruction on WFI when V=1
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2020-02-27
Al
i
stair F
r
ancis
target/rics
v
: Flush the
TLB o
n
v
ir
t
uli
s
atio
n
mode changes
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2020-02-27
A
listair Francis
tar
g
e
t/riscv: Add
support
f
or virtual interrupt setting
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair
F
rancis
t
arget/risc
v
:
E
xt
e
nd the SIP CSR to sup
p
o
r
t
vi
r
tulisat
i
on
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2020-02-27
Alistai
r
Franc
i
s
t
a
rget/r
i
scv: Extend the MIE CSR to
su
p
p
o
rt
v
irtulisat
i
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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tree
2020-02-27
A
l
istair F
r
ancis
targ
e
t/
r
i
s
cv:
S
et VS
bits in midel
e
g
f
or
Hyp
exte
n
s
i
o
n
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Franc
i
s
target/riscv: Ad
d
vi
r
tual
r
egister s
w
apping function
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair
F
r
a
ncis
target/riscv: Ad
d
Hypervisor machin
e
C
S
Rs acce
s
ses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair Fran
c
is
tar
g
e
t/riscv
:
A
d
d Hypervisor virtual CSRs accesses
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair
F
rancis
target/ris
c
v:
Add H
y
pe
r
visor CSR
a
cce
s
s functions
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair
F
rancis
ta
r
get/ri
s
cv
:
Dump Hypervisor registers if en
a
bled
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alistair
F
r
a
ncis
tar
g
et/riscv: Print priv and vir
t
in disas log
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2020-02-27
Alistair Franc
i
s
target/r
i
s
c
v
:
Fix CSR perm checking for HS m
o
de
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2020-02-27
Alis
t
air Francis
target/riscv: Add
t
he force HS e
x
c
e
ption mode
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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tree
2020-02-27
Alistair Fra
n
cis
target/risc
v
: Add the virt
u
l
isat
i
on m
o
de
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
commit
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2020-02-27
Alist
a
ir Fran
c
i
s
target/riscv:
R
e
n
a
m
e
the H irqs t
o
VS irqs
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Alistair Fran
c
is
t
ar
g
et/riscv: Ad
d
sup
p
or
t
for the new exe
c
pt
i
on nu
m
bers
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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2020-02-27
Al
i
s
t
air Fra
n
cis
target/ris
c
v:
Add the Hypervisor CSR
s
to CPUState
Signed-off-by:
Alistair Francis
<alistair.francis@wdc.com>
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