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hw/intc: sifive_plic: Drop PLICMode_H
2023-01-06
Anup Patel
target/
r
is
c
v: Typo fix in sstc() predicate
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2022-09-07
Anup Pate
l
target/ris
c
v: Use official extension name
s
f
or AIA
.
.
.
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2022-09-07
Anu
p
Patel
targe
t
/riscv: Force disable ext
e
nsions if priv spec
.
.
.
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2022-09-07
Anup Patel
target/riscv: Up
d
ate [m|h
]
tinst CSR in ri
s
cv_cpu_do_interr
u
p
t
()
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2022-07-03
Anup Patel
target/riscv: Up
d
ate defau
l
t
priority table for local
.
.
.
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2022-07-03
Anup Patel
target/riscv: Remove
C
SRs
t
hat s
e
t/clear an IMSIC
i
nterrup
t
.
.
.
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2022-07-03
Anup Pate
l
tar
g
et
/
r
i
scv:
S
e
t
minumum priv spec ve
r
sio
n
fo
r
m
counti
n
hibit
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2022-07-03
A
n
up
P
a
t
el
target/riscv: Don't force
update priv spec v
e
rsion
.
.
.
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2022-05-24
Anup Pa
t
el
hw
/
riscv: virt: Fix i
n
ter
r
u
p
t paren
t
f
o
r
dy
n
a
m
i
c
platform
.
.
.
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2022-05-24
Anup Patel
target/
r
is
c
v: Se
t
[m
|
s]tval for both illegal and virtual
.
.
.
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2022-05-24
Anup P
a
tel
target/
r
iscv: Fix hstatu
s
.
GVA bit
s
e
tting for
t
raps
.
.
.
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2022-05-24
Anup Pa
t
el
tar
g
et/riscv: Fix csr number based pr
i
vi
l
ege checkin
g
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2022-03-03
Anup Patel
h
w
/riscv: virt: Incre
a
s
e
m
a
ximum numb
e
r
o
f allowed
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-03-03
Anup Patel
docs
/
system: r
i
sc
v
:
Document AIA options for virt ma
c
hine
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-03-03
Anup Patel
hw/riscv: virt: Add optional AIA IMSIC support to virt
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-03-03
A
n
up Pat
e
l
hw/i
n
tc
:
A
d
d
RISC-V AIA IMSIC device emulati
o
n
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-03-03
An
u
p Patel
hw/riscv
:
virt: Ad
d
optional AIA APLIC su
p
port to
v
irt
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
Anup P
a
tel
hw/intc
:
Ad
d
RI
S
C-
V
AIA APLIC device emula
t
ion
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
A
nup Pat
e
l
targe
t
/
r
iscv: Allow users to
f
orce enable AIA CS
R
s
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
A
n
up
P
a
te
l
hw/riscv: virt: U
s
e
AIA INTC compatible string wh
e
n
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
Anup Patel
tar
g
et/riscv: Implement
AIA IMSIC interfa
c
e CSRs
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
Anup Pa
t
e
l
target/riscv: Implement AIA xisele
c
t and xireg
CSRs
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
A
n
up
P
atel
target/riscv:
Implement AIA mtopi, stopi, and vs
t
opi
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
A
n
u
p
P
atel
target/r
i
scv:
I
mplement AIA interr
u
pt filter
i
ng CSRs
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
Anup Patel
target/riscv: Implement
A
IA hvictl and
hvipr
i
oX CSRs
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
Anup
Patel
t
a
rge
t
/ri
s
c
v
: Impl
e
me
n
t
AIA CSRs for 64 local interrupts
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
Anup Patel
t
a
r
get/ris
c
v: Imp
l
ement AIA local interrupt
priorities
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
Anup Patel
t
arget/riscv:
A
ll
o
w
AIA device emulation to set ireg
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
An
u
p
P
atel
target/ris
c
v: Add defines for AIA CSRs
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
An
u
p Patel
ta
r
ge
t
/riscv: Add AIA cpu feature
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
Anup Pa
t
e
l
target/riscv: Al
l
o
w
settin
g
C
P
U
feature from machine
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
Anup P
a
t
el
targ
e
t/risc
v
:
Improve deliv
e
r
y
of
g
ue
s
t externa
l
i
n
terrupts
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
Anup Patel
target/riscv:
Impleme
n
t hgeie and hge
i
p C
S
Rs
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
Anu
p
Patel
target/riscv: Imple
m
ent SGEIP bit
in h
i
p and hi
e
CS
R
s
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-02-16
A
n
u
p
Patel
target/riscv
:
Fi
x
trap c
a
u
s
e
for RV32 HS-mode CSR acc
e
s
s
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
Signed-off-by:
Anup Patel
<anup@brainfault.org>
commit
|
commitdiff
|
tree
2022-01-21
Anup
Patel
roms
/
o
pensb
i
: Remove ELF images
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2022-01-21
Anup
Patel
hw/ris
c
v:
Remove macro
s
f
o
r
EL
F
BIOS image names
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2022-01-21
Anup Pa
t
el
h
w
/r
i
scv: spike: Allow us
i
n
g
b
inary firmwa
r
e as bios
Signed-off-by:
Anup Patel
<apatel@ventanamicro.com>
commit
|
commitdiff
|
tree
2021-09-20
A
nup Patel
hw/riscv:
v
irt: Add op
t
ional ACLINT support to virt
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Anup Patel
hw/
r
is
c
v:
v
irt: Re
-
fac
t
or F
D
T generation
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
Anup Patel
hw/intc: Upgrade the SiFive CLIN
T
implementa
t
ion to
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2021-09-20
A
nup Patel
hw/intc: Renam
e
sifive_clint sources to riscv_ac
l
i
nt
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Anup Pate
l
hw/risc
v
: sifi
v
e_u: Add UART1 DT node in th
e
generated DTB
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-11-03
Anup P
a
tel
hw
/
ris
c
v: virt: Allow passing custom DTB
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-11-03
A
nup Patel
hw/r
i
scv: sif
i
ve_u: A
l
l
o
w
passing custom
D
TB
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
A
nup Pa
t
el
h
w
/
r
iscv: vi
r
t:
A
llo
w
c
r
eating multip
l
e NUMA s
o
c
kets
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anup P
a
t
e
l
h
w
/r
i
s
cv: sp
i
ke: Allow creating multiple NUMA sockets
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anup Patel
hw/riscv: Add
h
e
lper
s
fo
r
RISC-V mu
l
ti
-
socket NU
M
A
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anup Patel
hw/r
i
s
cv: Allow
c
reating multiple in
s
t
a
nce
s
of PLIC
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anup Patel
hw/riscv: Allo
w
creating multiple instances of CLINT
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Anup Patel
hw/riscv/
s
pike: Allow more t
h
an one CPUs
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Anup Patel
hw/r
i
scv/sp
i
ke: Allow loading firmware separa
t
e
l
y
using
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
A
nup Patel
hw/riscv: Add optional symb
o
l callback ptr to ri
s
cv_
l
oad
_
fir
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Anup Pate
l
riscv:
Fix S
t
age2 SV32 page ta
b
le wal
k
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Anup Patel
hw/ris
c
v: Provide rdtime cal
l
bac
k
fo
r
TCG in CLINT
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Anup Pate
l
t
arget
/
r
i
scv: E
m
ul
a
te TIME CSRs for
privileged
mode
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
Anup Pa
t
el
M
A
INTAINER
S
: A
d
d
m
a
intainer entry
f
or Goldfish RTC
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
An
u
p P
a
tel
risc
v
: vir
t
: Use Goldfish RTC devi
c
e
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
An
u
p Patel
hw: rtc: Ad
d
Goldfish RTC
d
evice
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
Anup Patel
r
is
c
v
/
virt: Add syscon
r
e
boot a
n
d pow
e
ro
f
f DT nod
e
s
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2018-12-20
Anup P
a
tel
t
a
rget/ris
c
v/pmp
.
c:
F
ix pmp_d
e
co
d
e
_na
p
ot
(
)
Signed-off-by:
Anup Patel
<anup@brainfault.org>
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2018-12-20
Anup
P
atel
sifive_u: Set 'cl
o
c
k
-frequency' DT proper
t
y for Si
F
iv
e
.
.
.
Signed-off-by:
Anup Patel
<anup@brainfault.org>
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2018-12-20
Anup
Patel
sif
i
ve_
u
: Add c
l
ock DT node for GEM ethernet
Signed-off-by:
Anup Patel
<anup@brainfault.org>
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree