hw/rdma/vmw/pvrdma_main.c

   1 /*
   2  * QEMU paravirtual RDMA
   3  *
   4  * Copyright (C) 2018 Oracle
   5  * Copyright (C) 2018 Red Hat Inc
   6  *
   7  * Authors:
   8  *     Yuval Shaia <yuval.shaia@oracle.com>
   9  *     Marcel Apfelbaum <marcel@redhat.com>
  10  *
  11  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  12  * See the COPYING file in the top-level directory.
  13  *
  14  */
  15
  16 #include "qemu/osdep.h"
  17 #include "qapi/error.h"
  18 #include "hw/hw.h"
  19 #include "hw/pci/pci.h"
  20 #include "hw/pci/pci_ids.h"
  21 #include "hw/pci/msi.h"
  22 #include "hw/pci/msix.h"
  23 #include "hw/qdev-core.h"
  24 #include "hw/qdev-properties.h"
  25 #include "cpu.h"
  26 #include "trace.h"
  27 #include "sysemu/sysemu.h"
  28
  29 #include "../rdma_rm.h"
  30 #include "../rdma_backend.h"
  31 #include "../rdma_utils.h"
  32
  33 #include <infiniband/verbs.h>
  34 #include "pvrdma.h"
  35 #include "standard-headers/rdma/vmw_pvrdma-abi.h"
  36 #include "standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h"
  37 #include "pvrdma_qp_ops.h"
  38
  39 static Property pvrdma_dev_properties[] = {
  40     DEFINE_PROP_STRING("netdev", PVRDMADev, backend_eth_device_name),
  41     DEFINE_PROP_STRING("ibdev", PVRDMADev, backend_device_name),
  42     DEFINE_PROP_UINT8("ibport", PVRDMADev, backend_port_num, 1),
  43     DEFINE_PROP_UINT64("dev-caps-max-mr-size", PVRDMADev, dev_attr.max_mr_size,
  44                        MAX_MR_SIZE),
  45     DEFINE_PROP_INT32("dev-caps-max-qp", PVRDMADev, dev_attr.max_qp, MAX_QP),
  46     DEFINE_PROP_INT32("dev-caps-max-cq", PVRDMADev, dev_attr.max_cq, MAX_CQ),
  47     DEFINE_PROP_INT32("dev-caps-max-mr", PVRDMADev, dev_attr.max_mr, MAX_MR),
  48     DEFINE_PROP_INT32("dev-caps-max-pd", PVRDMADev, dev_attr.max_pd, MAX_PD),
  49     DEFINE_PROP_INT32("dev-caps-qp-rd-atom", PVRDMADev, dev_attr.max_qp_rd_atom,
  50                       MAX_QP_RD_ATOM),
  51     DEFINE_PROP_INT32("dev-caps-max-qp-init-rd-atom", PVRDMADev,
  52                       dev_attr.max_qp_init_rd_atom, MAX_QP_INIT_RD_ATOM),
  53     DEFINE_PROP_INT32("dev-caps-max-ah", PVRDMADev, dev_attr.max_ah, MAX_AH),
  54     DEFINE_PROP_CHR("mad-chardev", PVRDMADev, mad_chr),
  55     DEFINE_PROP_END_OF_LIST(),
  56 };
  57
  58 static void free_dev_ring(PCIDevice *pci_dev, PvrdmaRing *ring,
  59                           void *ring_state)
  60 {
  61     pvrdma_ring_free(ring);
  62     rdma_pci_dma_unmap(pci_dev, ring_state, TARGET_PAGE_SIZE);
  63 }
  64
  65 static int init_dev_ring(PvrdmaRing *ring, struct pvrdma_ring **ring_state,
  66                          const char *name, PCIDevice *pci_dev,
  67                          dma_addr_t dir_addr, uint32_t num_pages)
  68 {
  69     uint64_t *dir, *tbl;
  70     int rc = 0;
  71
  72     pr_dbg("Initializing device ring %s\n", name);
  73     pr_dbg("pdir_dma=0x%llx\n", (long long unsigned int)dir_addr);
  74     pr_dbg("num_pages=%d\n", num_pages);
  75     dir = rdma_pci_dma_map(pci_dev, dir_addr, TARGET_PAGE_SIZE);
  76     if (!dir) {
  77         pr_err("Failed to map to page directory\n");
  78         rc = -ENOMEM;
  79         goto out;
  80     }
  81     tbl = rdma_pci_dma_map(pci_dev, dir[0], TARGET_PAGE_SIZE);
  82     if (!tbl) {
  83         pr_err("Failed to map to page table\n");
  84         rc = -ENOMEM;
  85         goto out_free_dir;
  86     }
  87
  88     *ring_state = rdma_pci_dma_map(pci_dev, tbl[0], TARGET_PAGE_SIZE);
  89     if (!*ring_state) {
  90         pr_err("Failed to map to ring state\n");
  91         rc = -ENOMEM;
  92         goto out_free_tbl;
  93     }
  94     /* RX ring is the second */
  95     (*ring_state)++;
  96     rc = pvrdma_ring_init(ring, name, pci_dev,
  97                           (struct pvrdma_ring *)*ring_state,
  98                           (num_pages - 1) * TARGET_PAGE_SIZE /
  99                           sizeof(struct pvrdma_cqne),
 100                           sizeof(struct pvrdma_cqne),
 101                           (dma_addr_t *)&tbl[1], (dma_addr_t)num_pages - 1);
 102     if (rc) {
 103         pr_err("Failed to initialize ring\n");
 104         rc = -ENOMEM;
 105         goto out_free_ring_state;
 106     }
 107
 108     goto out_free_tbl;
 109
 110 out_free_ring_state:
 111     rdma_pci_dma_unmap(pci_dev, *ring_state, TARGET_PAGE_SIZE);
 112
 113 out_free_tbl:
 114     rdma_pci_dma_unmap(pci_dev, tbl, TARGET_PAGE_SIZE);
 115
 116 out_free_dir:
 117     rdma_pci_dma_unmap(pci_dev, dir, TARGET_PAGE_SIZE);
 118
 119 out:
 120     return rc;
 121 }
 122
 123 static void free_dsr(PVRDMADev *dev)
 124 {
 125     PCIDevice *pci_dev = PCI_DEVICE(dev);
 126
 127     if (!dev->dsr_info.dsr) {
 128         return;
 129     }
 130
 131     free_dev_ring(pci_dev, &dev->dsr_info.async,
 132                   dev->dsr_info.async_ring_state);
 133
 134     free_dev_ring(pci_dev, &dev->dsr_info.cq, dev->dsr_info.cq_ring_state);
 135
 136     rdma_pci_dma_unmap(pci_dev, dev->dsr_info.req,
 137                          sizeof(union pvrdma_cmd_req));
 138
 139     rdma_pci_dma_unmap(pci_dev, dev->dsr_info.rsp,
 140                          sizeof(union pvrdma_cmd_resp));
 141
 142     rdma_pci_dma_unmap(pci_dev, dev->dsr_info.dsr,
 143                          sizeof(struct pvrdma_device_shared_region));
 144
 145     dev->dsr_info.dsr = NULL;
 146 }
 147
 148 static int load_dsr(PVRDMADev *dev)
 149 {
 150     int rc = 0;
 151     PCIDevice *pci_dev = PCI_DEVICE(dev);
 152     DSRInfo *dsr_info;
 153     struct pvrdma_device_shared_region *dsr;
 154
 155     free_dsr(dev);
 156
 157     /* Map to DSR */
 158     pr_dbg("dsr_dma=0x%llx\n", (long long unsigned int)dev->dsr_info.dma);
 159     dev->dsr_info.dsr = rdma_pci_dma_map(pci_dev, dev->dsr_info.dma,
 160                               sizeof(struct pvrdma_device_shared_region));
 161     if (!dev->dsr_info.dsr) {
 162         pr_err("Failed to map to DSR\n");
 163         rc = -ENOMEM;
 164         goto out;
 165     }
 166
 167     /* Shortcuts */
 168     dsr_info = &dev->dsr_info;
 169     dsr = dsr_info->dsr;
 170
 171     /* Map to command slot */
 172     pr_dbg("cmd_dma=0x%llx\n", (long long unsigned int)dsr->cmd_slot_dma);
 173     dsr_info->req = rdma_pci_dma_map(pci_dev, dsr->cmd_slot_dma,
 174                                      sizeof(union pvrdma_cmd_req));
 175     if (!dsr_info->req) {
 176         pr_err("Failed to map to command slot address\n");
 177         rc = -ENOMEM;
 178         goto out_free_dsr;
 179     }
 180
 181     /* Map to response slot */
 182     pr_dbg("rsp_dma=0x%llx\n", (long long unsigned int)dsr->resp_slot_dma);
 183     dsr_info->rsp = rdma_pci_dma_map(pci_dev, dsr->resp_slot_dma,
 184                                      sizeof(union pvrdma_cmd_resp));
 185     if (!dsr_info->rsp) {
 186         pr_err("Failed to map to response slot address\n");
 187         rc = -ENOMEM;
 188         goto out_free_req;
 189     }
 190
 191     /* Map to CQ notification ring */
 192     rc = init_dev_ring(&dsr_info->cq, &dsr_info->cq_ring_state, "dev_cq",
 193                        pci_dev, dsr->cq_ring_pages.pdir_dma,
 194                        dsr->cq_ring_pages.num_pages);
 195     if (rc) {
 196         pr_err("Failed to map to initialize CQ ring\n");
 197         rc = -ENOMEM;
 198         goto out_free_rsp;
 199     }
 200
 201     /* Map to event notification ring */
 202     rc = init_dev_ring(&dsr_info->async, &dsr_info->async_ring_state,
 203                        "dev_async", pci_dev, dsr->async_ring_pages.pdir_dma,
 204                        dsr->async_ring_pages.num_pages);
 205     if (rc) {
 206         pr_err("Failed to map to initialize event ring\n");
 207         rc = -ENOMEM;
 208         goto out_free_rsp;
 209     }
 210
 211     goto out;
 212
 213 out_free_rsp:
 214     rdma_pci_dma_unmap(pci_dev, dsr_info->rsp, sizeof(union pvrdma_cmd_resp));
 215
 216 out_free_req:
 217     rdma_pci_dma_unmap(pci_dev, dsr_info->req, sizeof(union pvrdma_cmd_req));
 218
 219 out_free_dsr:
 220     rdma_pci_dma_unmap(pci_dev, dsr_info->dsr,
 221                        sizeof(struct pvrdma_device_shared_region));
 222     dsr_info->dsr = NULL;
 223
 224 out:
 225     return rc;
 226 }
 227
 228 static void init_dsr_dev_caps(PVRDMADev *dev)
 229 {
 230     struct pvrdma_device_shared_region *dsr;
 231
 232     if (dev->dsr_info.dsr == NULL) {
 233         pr_err("Can't initialized DSR\n");
 234         return;
 235     }
 236
 237     dsr = dev->dsr_info.dsr;
 238
 239     dsr->caps.fw_ver = PVRDMA_FW_VERSION;
 240     pr_dbg("fw_ver=0x%" PRIx64 "\n", dsr->caps.fw_ver);
 241
 242     dsr->caps.mode = PVRDMA_DEVICE_MODE_ROCE;
 243     pr_dbg("mode=%d\n", dsr->caps.mode);
 244
 245     dsr->caps.gid_types |= PVRDMA_GID_TYPE_FLAG_ROCE_V1;
 246     pr_dbg("gid_types=0x%x\n", dsr->caps.gid_types);
 247
 248     dsr->caps.max_uar = RDMA_BAR2_UAR_SIZE;
 249     pr_dbg("max_uar=%d\n", dsr->caps.max_uar);
 250
 251     dsr->caps.max_mr_size = dev->dev_attr.max_mr_size;
 252     dsr->caps.max_qp = dev->dev_attr.max_qp;
 253     dsr->caps.max_qp_wr = dev->dev_attr.max_qp_wr;
 254     dsr->caps.max_sge = dev->dev_attr.max_sge;
 255     dsr->caps.max_cq = dev->dev_attr.max_cq;
 256     dsr->caps.max_cqe = dev->dev_attr.max_cqe;
 257     dsr->caps.max_mr = dev->dev_attr.max_mr;
 258     dsr->caps.max_pd = dev->dev_attr.max_pd;
 259     dsr->caps.max_ah = dev->dev_attr.max_ah;
 260
 261     dsr->caps.gid_tbl_len = MAX_GIDS;
 262     pr_dbg("gid_tbl_len=%d\n", dsr->caps.gid_tbl_len);
 263
 264     dsr->caps.sys_image_guid = 0;
 265     pr_dbg("sys_image_guid=%" PRIx64 "\n", dsr->caps.sys_image_guid);
 266
 267     dsr->caps.node_guid = dev->node_guid;
 268     pr_dbg("node_guid=%" PRIx64 "\n", be64_to_cpu(dsr->caps.node_guid));
 269
 270     dsr->caps.phys_port_cnt = MAX_PORTS;
 271     pr_dbg("phys_port_cnt=%d\n", dsr->caps.phys_port_cnt);
 272
 273     dsr->caps.max_pkeys = MAX_PKEYS;
 274     pr_dbg("max_pkeys=%d\n", dsr->caps.max_pkeys);
 275
 276     pr_dbg("Initialized\n");
 277 }
 278
 279 static void uninit_msix(PCIDevice *pdev, int used_vectors)
 280 {
 281     PVRDMADev *dev = PVRDMA_DEV(pdev);
 282     int i;
 283
 284     for (i = 0; i < used_vectors; i++) {
 285         msix_vector_unuse(pdev, i);
 286     }
 287
 288     msix_uninit(pdev, &dev->msix, &dev->msix);
 289 }
 290
 291 static int init_msix(PCIDevice *pdev, Error **errp)
 292 {
 293     PVRDMADev *dev = PVRDMA_DEV(pdev);
 294     int i;
 295     int rc;
 296
 297     rc = msix_init(pdev, RDMA_MAX_INTRS, &dev->msix, RDMA_MSIX_BAR_IDX,
 298                    RDMA_MSIX_TABLE, &dev->msix, RDMA_MSIX_BAR_IDX,
 299                    RDMA_MSIX_PBA, 0, NULL);
 300
 301     if (rc < 0) {
 302         error_setg(errp, "Failed to initialize MSI-X");
 303         return rc;
 304     }
 305
 306     for (i = 0; i < RDMA_MAX_INTRS; i++) {
 307         rc = msix_vector_use(PCI_DEVICE(dev), i);
 308         if (rc < 0) {
 309             error_setg(errp, "Fail mark MSI-X vector %d", i);
 310             uninit_msix(pdev, i);
 311             return rc;
 312         }
 313     }
 314
 315     return 0;
 316 }
 317
 318 static void pvrdma_fini(PCIDevice *pdev)
 319 {
 320     PVRDMADev *dev = PVRDMA_DEV(pdev);
 321
 322     pr_dbg("Closing device %s %x.%x\n", pdev->name, PCI_SLOT(pdev->devfn),
 323            PCI_FUNC(pdev->devfn));
 324
 325     pvrdma_qp_ops_fini();
 326
 327     rdma_rm_fini(&dev->rdma_dev_res, &dev->backend_dev,
 328                  dev->backend_eth_device_name);
 329
 330     rdma_backend_fini(&dev->backend_dev);
 331
 332     free_dsr(dev);
 333
 334     if (msix_enabled(pdev)) {
 335         uninit_msix(pdev, RDMA_MAX_INTRS);
 336     }
 337
 338     pr_dbg("Device %s %x.%x is down\n", pdev->name, PCI_SLOT(pdev->devfn),
 339            PCI_FUNC(pdev->devfn));
 340 }
 341
 342 static void pvrdma_stop(PVRDMADev *dev)
 343 {
 344     rdma_backend_stop(&dev->backend_dev);
 345 }
 346
 347 static void pvrdma_start(PVRDMADev *dev)
 348 {
 349     rdma_backend_start(&dev->backend_dev);
 350 }
 351
 352 static void activate_device(PVRDMADev *dev)
 353 {
 354     pvrdma_start(dev);
 355     set_reg_val(dev, PVRDMA_REG_ERR, 0);
 356     pr_dbg("Device activated\n");
 357 }
 358
 359 static int unquiesce_device(PVRDMADev *dev)
 360 {
 361     pr_dbg("Device unquiesced\n");
 362     return 0;
 363 }
 364
 365 static void reset_device(PVRDMADev *dev)
 366 {
 367     pvrdma_stop(dev);
 368
 369     pr_dbg("Device reset complete\n");
 370 }
 371
 372 static uint64_t regs_read(void *opaque, hwaddr addr, unsigned size)
 373 {
 374     PVRDMADev *dev = opaque;
 375     uint32_t val;
 376
 377     /* pr_dbg("addr=0x%lx, size=%d\n", addr, size); */
 378
 379     if (get_reg_val(dev, addr, &val)) {
 380         pr_dbg("Error trying to read REG value from address 0x%x\n",
 381                (uint32_t)addr);
 382         return -EINVAL;
 383     }
 384
 385     trace_pvrdma_regs_read(addr, val);
 386
 387     return val;
 388 }
 389
 390 static void regs_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
 391 {
 392     PVRDMADev *dev = opaque;
 393
 394     /* pr_dbg("addr=0x%lx, val=0x%x, size=%d\n", addr, (uint32_t)val, size); */
 395
 396     if (set_reg_val(dev, addr, val)) {
 397         pr_err("Fail to set REG value, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
 398                addr, val);
 399         return;
 400     }
 401
 402     trace_pvrdma_regs_write(addr, val);
 403
 404     switch (addr) {
 405     case PVRDMA_REG_DSRLOW:
 406         dev->dsr_info.dma = val;
 407         break;
 408     case PVRDMA_REG_DSRHIGH:
 409         dev->dsr_info.dma |= val << 32;
 410         load_dsr(dev);
 411         init_dsr_dev_caps(dev);
 412         break;
 413     case PVRDMA_REG_CTL:
 414         switch (val) {
 415         case PVRDMA_DEVICE_CTL_ACTIVATE:
 416             activate_device(dev);
 417             break;
 418         case PVRDMA_DEVICE_CTL_UNQUIESCE:
 419             unquiesce_device(dev);
 420             break;
 421         case PVRDMA_DEVICE_CTL_RESET:
 422             reset_device(dev);
 423             break;
 424         }
 425         break;
 426     case PVRDMA_REG_IMR:
 427         pr_dbg("Interrupt mask=0x%" PRIx64 "\n", val);
 428         dev->interrupt_mask = val;
 429         break;
 430     case PVRDMA_REG_REQUEST:
 431         if (val == 0) {
 432             execute_command(dev);
 433         }
 434         break;
 435     default:
 436         break;
 437     }
 438 }
 439
 440 static const MemoryRegionOps regs_ops = {
 441     .read = regs_read,
 442     .write = regs_write,
 443     .endianness = DEVICE_LITTLE_ENDIAN,
 444     .impl = {
 445         .min_access_size = sizeof(uint32_t),
 446         .max_access_size = sizeof(uint32_t),
 447     },
 448 };
 449
 450 static uint64_t uar_read(void *opaque, hwaddr addr, unsigned size)
 451 {
 452     return 0xffffffff;
 453 }
 454
 455 static void uar_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
 456 {
 457     PVRDMADev *dev = opaque;
 458
 459     /* pr_dbg("addr=0x%lx, val=0x%x, size=%d\n", addr, (uint32_t)val, size); */
 460
 461     switch (addr & 0xFFF) { /* Mask with 0xFFF as each UC gets page */
 462     case PVRDMA_UAR_QP_OFFSET:
 463         pr_dbg("UAR QP command, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
 464                (uint64_t)addr, val);
 465         if (val & PVRDMA_UAR_QP_SEND) {
 466             pvrdma_qp_send(dev, val & PVRDMA_UAR_HANDLE_MASK);
 467         }
 468         if (val & PVRDMA_UAR_QP_RECV) {
 469             pvrdma_qp_recv(dev, val & PVRDMA_UAR_HANDLE_MASK);
 470         }
 471         break;
 472     case PVRDMA_UAR_CQ_OFFSET:
 473         /* pr_dbg("UAR CQ cmd, addr=0x%x, val=0x%lx\n", (uint32_t)addr, val); */
 474         if (val & PVRDMA_UAR_CQ_ARM) {
 475             rdma_rm_req_notify_cq(&dev->rdma_dev_res,
 476                                   val & PVRDMA_UAR_HANDLE_MASK,
 477                                   !!(val & PVRDMA_UAR_CQ_ARM_SOL));
 478         }
 479         if (val & PVRDMA_UAR_CQ_ARM_SOL) {
 480             pr_dbg("UAR_CQ_ARM_SOL (%" PRIx64 ")\n",
 481                    val & PVRDMA_UAR_HANDLE_MASK);
 482         }
 483         if (val & PVRDMA_UAR_CQ_POLL) {
 484             pr_dbg("UAR_CQ_POLL (%" PRIx64 ")\n", val & PVRDMA_UAR_HANDLE_MASK);
 485             pvrdma_cq_poll(&dev->rdma_dev_res, val & PVRDMA_UAR_HANDLE_MASK);
 486         }
 487         break;
 488     default:
 489         pr_err("Unsupported command, addr=0x%" PRIx64 ", val=0x%" PRIx64 "\n",
 490                addr, val);
 491         break;
 492     }
 493 }
 494
 495 static const MemoryRegionOps uar_ops = {
 496     .read = uar_read,
 497     .write = uar_write,
 498     .endianness = DEVICE_LITTLE_ENDIAN,
 499     .impl = {
 500         .min_access_size = sizeof(uint32_t),
 501         .max_access_size = sizeof(uint32_t),
 502     },
 503 };
 504
 505 static void init_pci_config(PCIDevice *pdev)
 506 {
 507     pdev->config[PCI_INTERRUPT_PIN] = 1;
 508 }
 509
 510 static void init_bars(PCIDevice *pdev)
 511 {
 512     PVRDMADev *dev = PVRDMA_DEV(pdev);
 513
 514     /* BAR 0 - MSI-X */
 515     memory_region_init(&dev->msix, OBJECT(dev), "pvrdma-msix",
 516                        RDMA_BAR0_MSIX_SIZE);
 517     pci_register_bar(pdev, RDMA_MSIX_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
 518                      &dev->msix);
 519
 520     /* BAR 1 - Registers */
 521     memset(&dev->regs_data, 0, sizeof(dev->regs_data));
 522     memory_region_init_io(&dev->regs, OBJECT(dev), &regs_ops, dev,
 523                           "pvrdma-regs", sizeof(dev->regs_data));
 524     pci_register_bar(pdev, RDMA_REG_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
 525                      &dev->regs);
 526
 527     /* BAR 2 - UAR */
 528     memset(&dev->uar_data, 0, sizeof(dev->uar_data));
 529     memory_region_init_io(&dev->uar, OBJECT(dev), &uar_ops, dev, "rdma-uar",
 530                           sizeof(dev->uar_data));
 531     pci_register_bar(pdev, RDMA_UAR_BAR_IDX, PCI_BASE_ADDRESS_SPACE_MEMORY,
 532                      &dev->uar);
 533 }
 534
 535 static void init_regs(PCIDevice *pdev)
 536 {
 537     PVRDMADev *dev = PVRDMA_DEV(pdev);
 538
 539     set_reg_val(dev, PVRDMA_REG_VERSION, PVRDMA_HW_VERSION);
 540     set_reg_val(dev, PVRDMA_REG_ERR, 0xFFFF);
 541 }
 542
 543 static void init_dev_caps(PVRDMADev *dev)
 544 {
 545     size_t pg_tbl_bytes = TARGET_PAGE_SIZE *
 546                           (TARGET_PAGE_SIZE / sizeof(uint64_t));
 547     size_t wr_sz = MAX(sizeof(struct pvrdma_sq_wqe_hdr),
 548                        sizeof(struct pvrdma_rq_wqe_hdr));
 549
 550     dev->dev_attr.max_qp_wr = pg_tbl_bytes /
 551                               (wr_sz + sizeof(struct pvrdma_sge) *
 552                               dev->dev_attr.max_sge) - TARGET_PAGE_SIZE;
 553                               /* First page is ring state  ^^^^ */
 554     pr_dbg("max_qp_wr=%d\n", dev->dev_attr.max_qp_wr);
 555
 556     dev->dev_attr.max_cqe = pg_tbl_bytes / sizeof(struct pvrdma_cqe) -
 557                             TARGET_PAGE_SIZE; /* First page is ring state */
 558     pr_dbg("max_cqe=%d\n", dev->dev_attr.max_cqe);
 559 }
 560
 561 static int pvrdma_check_ram_shared(Object *obj, void *opaque)
 562 {
 563     bool *shared = opaque;
 564
 565     if (object_dynamic_cast(obj, "memory-backend-ram")) {
 566         *shared = object_property_get_bool(obj, "share", NULL);
 567     }
 568
 569     return 0;
 570 }
 571
 572 static void pvrdma_shutdown_notifier(Notifier *n, void *opaque)
 573 {
 574     PVRDMADev *dev = container_of(n, PVRDMADev, shutdown_notifier);
 575     PCIDevice *pci_dev = PCI_DEVICE(dev);
 576
 577     pvrdma_fini(pci_dev);
 578 }
 579
 580 static void pvrdma_realize(PCIDevice *pdev, Error **errp)
 581 {
 582     int rc = 0;
 583     PVRDMADev *dev = PVRDMA_DEV(pdev);
 584     Object *memdev_root;
 585     bool ram_shared = false;
 586     PCIDevice *func0;
 587
 588     init_pr_dbg();
 589
 590     pr_dbg("Initializing device %s %x.%x\n", pdev->name,
 591            PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
 592
 593     if (TARGET_PAGE_SIZE != getpagesize()) {
 594         error_setg(errp, "Target page size must be the same as host page size");
 595         return;
 596     }
 597
 598     func0 = pci_get_function_0(pdev);
 599     /* Break if not vmxnet3 device in slot 0 */
 600     if (strcmp(object_get_typename(&func0->qdev.parent_obj), TYPE_VMXNET3)) {
 601         pr_dbg("func0 type is %s\n",
 602                object_get_typename(&func0->qdev.parent_obj));
 603         error_setg(errp, "Device on %x.0 must be %s", PCI_SLOT(pdev->devfn),
 604                    TYPE_VMXNET3);
 605         return;
 606     }
 607     dev->func0 = VMXNET3(func0);
 608
 609     addrconf_addr_eui48((unsigned char *)&dev->node_guid,
 610                         (const char *)&dev->func0->conf.macaddr.a);
 611
 612     memdev_root = object_resolve_path("/objects", NULL);
 613     if (memdev_root) {
 614         object_child_foreach(memdev_root, pvrdma_check_ram_shared, &ram_shared);
 615     }
 616     if (!ram_shared) {
 617         error_setg(errp, "Only shared memory backed ram is supported");
 618         return;
 619     }
 620
 621     dev->dsr_info.dsr = NULL;
 622
 623     init_pci_config(pdev);
 624
 625     init_bars(pdev);
 626
 627     init_regs(pdev);
 628
 629     rc = init_msix(pdev, errp);
 630     if (rc) {
 631         goto out;
 632     }
 633
 634     rc = rdma_backend_init(&dev->backend_dev, pdev, &dev->rdma_dev_res,
 635                            dev->backend_device_name, dev->backend_port_num,
 636                            &dev->dev_attr, &dev->mad_chr, errp);
 637     if (rc) {
 638         goto out;
 639     }
 640
 641     init_dev_caps(dev);
 642
 643     rc = rdma_rm_init(&dev->rdma_dev_res, &dev->dev_attr, errp);
 644     if (rc) {
 645         goto out;
 646     }
 647
 648     rc = pvrdma_qp_ops_init();
 649     if (rc) {
 650         goto out;
 651     }
 652
 653     dev->shutdown_notifier.notify = pvrdma_shutdown_notifier;
 654     qemu_register_shutdown_notifier(&dev->shutdown_notifier);
 655
 656 out:
 657     if (rc) {
 658         pvrdma_fini(pdev);
 659         error_append_hint(errp, "Device fail to load\n");
 660     }
 661 }
 662
 663 static void pvrdma_exit(PCIDevice *pdev)
 664 {
 665     pvrdma_fini(pdev);
 666 }
 667
 668 static void pvrdma_class_init(ObjectClass *klass, void *data)
 669 {
 670     DeviceClass *dc = DEVICE_CLASS(klass);
 671     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 672
 673     k->realize = pvrdma_realize;
 674     k->exit = pvrdma_exit;
 675     k->vendor_id = PCI_VENDOR_ID_VMWARE;
 676     k->device_id = PCI_DEVICE_ID_VMWARE_PVRDMA;
 677     k->revision = 0x00;
 678     k->class_id = PCI_CLASS_NETWORK_OTHER;
 679
 680     dc->desc = "RDMA Device";
 681     dc->props = pvrdma_dev_properties;
 682     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 683 }
 684
 685 static const TypeInfo pvrdma_info = {
 686     .name = PVRDMA_HW_NAME,
 687     .parent = TYPE_PCI_DEVICE,
 688     .instance_size = sizeof(PVRDMADev),
 689     .class_init = pvrdma_class_init,
 690     .interfaces = (InterfaceInfo[]) {
 691         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 692         { }
 693     }
 694 };
 695
 696 static void register_types(void)
 697 {
 698     type_register_static(&pvrdma_info);
 699 }
 700
 701 type_init(register_types)