hw/ppc/prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  * Copyright (c) 2017 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/rtc/m48t59.h"
  28 #include "hw/char/serial.h"
  29 #include "hw/block/fdc.h"
  30 #include "net/net.h"
  31 #include "hw/isa/isa.h"
  32 #include "hw/pci/pci.h"
  33 #include "hw/pci/pci_host.h"
  34 #include "hw/ppc/ppc.h"
  35 #include "hw/boards.h"
  36 #include "qapi/error.h"
  37 #include "qemu/error-report.h"
  38 #include "qemu/log.h"
  39 #include "hw/loader.h"
  40 #include "hw/rtc/mc146818rtc.h"
  41 #include "hw/isa/pc87312.h"
  42 #include "hw/qdev-properties.h"
  43 #include "sysemu/kvm.h"
  44 #include "sysemu/reset.h"
  45 #include "trace.h"
  46 #include "elf.h"
  47 #include "qemu/units.h"
  48 #include "audio/audio.h"
  49
  50 /* SMP is not enabled, for now */
  51 #define MAX_CPUS 1
  52
  53 #define CFG_ADDR 0xf0000510
  54
  55 #define KERNEL_LOAD_ADDR 0x01000000
  56 #define INITRD_LOAD_ADDR 0x01800000
  57
  58 #define NVRAM_SIZE        0x2000
  59
  60 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
  61                             Error **errp)
  62 {
  63     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  64 }
  65
  66 static void ppc_prep_reset(void *opaque)
  67 {
  68     PowerPCCPU *cpu = opaque;
  69
  70     cpu_reset(CPU(cpu));
  71     cpu_ppc_tb_reset(&cpu->env);
  72 }
  73
  74
  75 /*****************************************************************************/
  76 /* NVRAM helpers */
  77 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
  78 {
  79     NvramClass *k = NVRAM_GET_CLASS(nvram);
  80     return (k->read)(nvram, addr);
  81 }
  82
  83 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
  84 {
  85     NvramClass *k = NVRAM_GET_CLASS(nvram);
  86     (k->write)(nvram, addr, val);
  87 }
  88
  89 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
  90 {
  91     nvram_write(nvram, addr, value);
  92 }
  93
  94 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
  95 {
  96     return nvram_read(nvram, addr);
  97 }
  98
  99 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
 100 {
 101     nvram_write(nvram, addr, value >> 8);
 102     nvram_write(nvram, addr + 1, value & 0xFF);
 103 }
 104
 105 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
 106 {
 107     uint16_t tmp;
 108
 109     tmp = nvram_read(nvram, addr) << 8;
 110     tmp |= nvram_read(nvram, addr + 1);
 111
 112     return tmp;
 113 }
 114
 115 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
 116 {
 117     nvram_write(nvram, addr, value >> 24);
 118     nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
 119     nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
 120     nvram_write(nvram, addr + 3, value & 0xFF);
 121 }
 122
 123 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
 124                              uint32_t max)
 125 {
 126     int i;
 127
 128     for (i = 0; i < max && str[i] != '\0'; i++) {
 129         nvram_write(nvram, addr + i, str[i]);
 130     }
 131     nvram_write(nvram, addr + i, str[i]);
 132     nvram_write(nvram, addr + max - 1, '\0');
 133 }
 134
 135 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
 136 {
 137     uint16_t tmp;
 138     uint16_t pd, pd1, pd2;
 139
 140     tmp = prev >> 8;
 141     pd = prev ^ value;
 142     pd1 = pd & 0x000F;
 143     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
 144     tmp ^= (pd1 << 3) | (pd1 << 8);
 145     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
 146
 147     return tmp;
 148 }
 149
 150 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
 151 {
 152     uint32_t i;
 153     uint16_t crc = 0xFFFF;
 154     int odd;
 155
 156     odd = count & 1;
 157     count &= ~1;
 158     for (i = 0; i != count; i++) {
 159         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
 160     }
 161     if (odd) {
 162         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
 163     }
 164
 165     return crc;
 166 }
 167
 168 #define CMDLINE_ADDR 0x017ff000
 169
 170 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
 171                           const char *arch,
 172                           uint32_t RAM_size, int boot_device,
 173                           uint32_t kernel_image, uint32_t kernel_size,
 174                           const char *cmdline,
 175                           uint32_t initrd_image, uint32_t initrd_size,
 176                           uint32_t NVRAM_image,
 177                           int width, int height, int depth)
 178 {
 179     uint16_t crc;
 180
 181     /* Set parameters for Open Hack'Ware BIOS */
 182     NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
 183     NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
 184     NVRAM_set_word(nvram,   0x14, NVRAM_size);
 185     NVRAM_set_string(nvram, 0x20, arch, 16);
 186     NVRAM_set_lword(nvram,  0x30, RAM_size);
 187     NVRAM_set_byte(nvram,   0x34, boot_device);
 188     NVRAM_set_lword(nvram,  0x38, kernel_image);
 189     NVRAM_set_lword(nvram,  0x3C, kernel_size);
 190     if (cmdline) {
 191         /* XXX: put the cmdline in NVRAM too ? */
 192         pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
 193                          cmdline);
 194         NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
 195         NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
 196     } else {
 197         NVRAM_set_lword(nvram,  0x40, 0);
 198         NVRAM_set_lword(nvram,  0x44, 0);
 199     }
 200     NVRAM_set_lword(nvram,  0x48, initrd_image);
 201     NVRAM_set_lword(nvram,  0x4C, initrd_size);
 202     NVRAM_set_lword(nvram,  0x50, NVRAM_image);
 203
 204     NVRAM_set_word(nvram,   0x54, width);
 205     NVRAM_set_word(nvram,   0x56, height);
 206     NVRAM_set_word(nvram,   0x58, depth);
 207     crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
 208     NVRAM_set_word(nvram,   0xFC, crc);
 209
 210     return 0;
 211 }
 212
 213 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
 214 {
 215     uint16_t checksum = *(uint16_t *)opaque;
 216
 217     if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
 218         MC146818RtcState *rtc = MC146818_RTC(dev);
 219         mc146818rtc_set_cmos_data(rtc, 0x2e, checksum & 0xff);
 220         mc146818rtc_set_cmos_data(rtc, 0x3e, checksum & 0xff);
 221         mc146818rtc_set_cmos_data(rtc, 0x2f, checksum >> 8);
 222         mc146818rtc_set_cmos_data(rtc, 0x3f, checksum >> 8);
 223
 224         object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
 225                                   "date");
 226     }
 227     return 0;
 228 }
 229
 230 static void ibm_40p_init(MachineState *machine)
 231 {
 232     const char *bios_name = machine->firmware ?: "openbios-ppc";
 233     MachineClass *mc = MACHINE_GET_CLASS(machine);
 234     CPUPPCState *env = NULL;
 235     uint16_t cmos_checksum;
 236     PowerPCCPU *cpu;
 237     DeviceState *dev, *i82378_dev;
 238     SysBusDevice *pcihost, *s;
 239     Nvram *m48t59 = NULL;
 240     PCIBus *pci_bus;
 241     ISADevice *isa_dev;
 242     ISABus *isa_bus;
 243     void *fw_cfg;
 244     uint32_t kernel_base = 0, initrd_base = 0;
 245     long kernel_size = 0, initrd_size = 0;
 246     char boot_device;
 247
 248     if (kvm_enabled()) {
 249         error_report("machine %s does not support the KVM accelerator",
 250                      MACHINE_GET_CLASS(machine)->name);
 251         exit(EXIT_FAILURE);
 252     }
 253
 254     /* init CPU */
 255     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 256     env = &cpu->env;
 257     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 258         error_report("only 6xx bus is supported on this machine");
 259         exit(1);
 260     }
 261
 262     /* Set time-base frequency to 100 Mhz */
 263     cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 264     qemu_register_reset(ppc_prep_reset, cpu);
 265
 266     /* PCI host */
 267     dev = qdev_new("raven-pcihost");
 268     qdev_prop_set_string(dev, "bios-name", bios_name);
 269     qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
 270     pcihost = SYS_BUS_DEVICE(dev);
 271     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev));
 272     sysbus_realize_and_unref(pcihost, &error_fatal);
 273     pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
 274     if (!pci_bus) {
 275         error_report("could not create PCI host controller");
 276         exit(1);
 277     }
 278
 279     /* PCI -> ISA bridge */
 280     i82378_dev = DEVICE(pci_new(PCI_DEVFN(11, 0), "i82378"));
 281     qdev_realize_and_unref(i82378_dev, BUS(pci_bus), &error_fatal);
 282     qdev_connect_gpio_out(i82378_dev, 0,
 283                           qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT));
 284
 285     sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
 286     isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
 287
 288     /* Memory controller */
 289     isa_dev = isa_new("rs6000-mc");
 290     dev = DEVICE(isa_dev);
 291     qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
 292     isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 293
 294     /* RTC */
 295     isa_dev = isa_new(TYPE_MC146818_RTC);
 296     dev = DEVICE(isa_dev);
 297     qdev_prop_set_int32(dev, "base_year", 1900);
 298     isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 299
 300     /* initialize CMOS checksums */
 301     cmos_checksum = 0x6aa9;
 302     qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
 303                        &cmos_checksum);
 304
 305     /* add some more devices */
 306     if (defaults_enabled()) {
 307         m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
 308
 309         isa_dev = isa_new("cs4231a");
 310         dev = DEVICE(isa_dev);
 311         qdev_prop_set_uint32(dev, "iobase", 0x830);
 312         qdev_prop_set_uint32(dev, "irq", 10);
 313
 314         if (machine->audiodev) {
 315             qdev_prop_set_string(dev, "audiodev", machine->audiodev);
 316         }
 317         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 318
 319         isa_dev = isa_new("pc87312");
 320         dev = DEVICE(isa_dev);
 321         qdev_prop_set_uint32(dev, "config", 12);
 322         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 323
 324         isa_dev = isa_new("prep-systemio");
 325         dev = DEVICE(isa_dev);
 326         qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
 327         qdev_prop_set_uint32(dev, "equipment", 0xc0);
 328         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 329
 330         dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
 331                                        "lsi53c810"));
 332         lsi53c8xx_handle_legacy_cmdline(dev);
 333         qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13));
 334
 335         /* XXX: s3-trio at PCI_DEVFN(2, 0) */
 336         pci_vga_init(pci_bus);
 337
 338         /* First PCNET device at PCI_DEVFN(3, 0) */
 339         pci_init_nic_in_slot(pci_bus, mc->default_nic, NULL, "3");
 340         pci_init_nic_devices(pci_bus, mc->default_nic);
 341     }
 342
 343     /* Prepare firmware configuration for OpenBIOS */
 344     dev = qdev_new(TYPE_FW_CFG_MEM);
 345     fw_cfg = FW_CFG(dev);
 346     qdev_prop_set_uint32(dev, "data_width", 1);
 347     qdev_prop_set_bit(dev, "dma_enabled", false);
 348     object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
 349                               OBJECT(fw_cfg));
 350     s = SYS_BUS_DEVICE(dev);
 351     sysbus_realize_and_unref(s, &error_fatal);
 352     sysbus_mmio_map(s, 0, CFG_ADDR);
 353     sysbus_mmio_map(s, 1, CFG_ADDR + 2);
 354
 355     if (machine->kernel_filename) {
 356         /* load kernel */
 357         kernel_base = KERNEL_LOAD_ADDR;
 358         kernel_size = load_image_targphys(machine->kernel_filename,
 359                                           kernel_base,
 360                                           machine->ram_size - kernel_base);
 361         if (kernel_size < 0) {
 362             error_report("could not load kernel '%s'",
 363                          machine->kernel_filename);
 364             exit(1);
 365         }
 366         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 367         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 368         /* load initrd */
 369         if (machine->initrd_filename) {
 370             initrd_base = INITRD_LOAD_ADDR;
 371             initrd_size = load_image_targphys(machine->initrd_filename,
 372                                               initrd_base,
 373                                               machine->ram_size - initrd_base);
 374             if (initrd_size < 0) {
 375                 error_report("could not load initial ram disk '%s'",
 376                              machine->initrd_filename);
 377                 exit(1);
 378             }
 379             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 380             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 381         }
 382         if (machine->kernel_cmdline && *machine->kernel_cmdline) {
 383             fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 384             pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
 385                              machine->kernel_cmdline);
 386             fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
 387                               machine->kernel_cmdline);
 388             fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 389                            strlen(machine->kernel_cmdline) + 1);
 390         }
 391         boot_device = 'm';
 392     } else {
 393         boot_device = machine->boot_config.order[0];
 394     }
 395
 396     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
 397     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
 398     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
 399
 400     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 401     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 402     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 403
 404     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
 405     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
 406     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 407
 408     /* Prepare firmware configuration for Open Hack'Ware */
 409     if (m48t59) {
 410         PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", machine->ram_size,
 411                              boot_device,
 412                              kernel_base, kernel_size,
 413                              machine->kernel_cmdline,
 414                              initrd_base, initrd_size,
 415                              /* XXX: need an option to load a NVRAM image */
 416                              0,
 417                              graphic_width, graphic_height, graphic_depth);
 418     }
 419 }
 420
 421 static void ibm_40p_machine_init(MachineClass *mc)
 422 {
 423     mc->desc = "IBM RS/6000 7020 (40p)",
 424     mc->init = ibm_40p_init;
 425     mc->max_cpus = 1;
 426     mc->default_ram_size = 128 * MiB;
 427     mc->block_default_type = IF_SCSI;
 428     mc->default_boot_order = "c";
 429     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
 430     mc->default_display = "std";
 431     mc->default_nic = "pcnet";
 432
 433     machine_add_audiodev_property(mc);
 434 }
 435
 436 DEFINE_MACHINE("40p", ibm_40p_machine_init)