hw/char/stm32f2xx_usart.c

   1 /*
   2  * STM32F2XX USART
   3  *
   4  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/char/stm32f2xx_usart.h"
  27 #include "hw/irq.h"
  28 #include "hw/qdev-properties.h"
  29 #include "hw/qdev-properties-system.h"
  30 #include "qemu/log.h"
  31 #include "qemu/module.h"
  32
  33 #ifndef STM_USART_ERR_DEBUG
  34 #define STM_USART_ERR_DEBUG 0
  35 #endif
  36
  37 #define DB_PRINT_L(lvl, fmt, args...) do { \
  38     if (STM_USART_ERR_DEBUG >= lvl) { \
  39         qemu_log("%s: " fmt, __func__, ## args); \
  40     } \
  41 } while (0)
  42
  43 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
  44
  45 static int stm32f2xx_usart_can_receive(void *opaque)
  46 {
  47     STM32F2XXUsartState *s = opaque;
  48
  49     if (!(s->usart_sr & USART_SR_RXNE)) {
  50         return 1;
  51     }
  52
  53     return 0;
  54 }
  55
  56 static void stm32f2xx_update_irq(STM32F2XXUsartState *s)
  57 {
  58     uint32_t mask = s->usart_sr & s->usart_cr1;
  59
  60     if (mask & (USART_SR_TXE | USART_SR_TC | USART_SR_RXNE)) {
  61         qemu_set_irq(s->irq, 1);
  62     } else {
  63         qemu_set_irq(s->irq, 0);
  64     }
  65 }
  66
  67 static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
  68 {
  69     STM32F2XXUsartState *s = opaque;
  70
  71     if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
  72         /* USART not enabled - drop the chars */
  73         DB_PRINT("Dropping the chars\n");
  74         return;
  75     }
  76
  77     s->usart_dr = *buf;
  78     s->usart_sr |= USART_SR_RXNE;
  79
  80     stm32f2xx_update_irq(s);
  81
  82     DB_PRINT("Receiving: %c\n", s->usart_dr);
  83 }
  84
  85 static void stm32f2xx_usart_reset(DeviceState *dev)
  86 {
  87     STM32F2XXUsartState *s = STM32F2XX_USART(dev);
  88
  89     s->usart_sr = USART_SR_RESET;
  90     s->usart_dr = 0x00000000;
  91     s->usart_brr = 0x00000000;
  92     s->usart_cr1 = 0x00000000;
  93     s->usart_cr2 = 0x00000000;
  94     s->usart_cr3 = 0x00000000;
  95     s->usart_gtpr = 0x00000000;
  96
  97     stm32f2xx_update_irq(s);
  98 }
  99
 100 static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
 101                                        unsigned int size)
 102 {
 103     STM32F2XXUsartState *s = opaque;
 104     uint64_t retvalue;
 105
 106     DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
 107
 108     switch (addr) {
 109     case USART_SR:
 110         retvalue = s->usart_sr;
 111         qemu_chr_fe_accept_input(&s->chr);
 112         return retvalue;
 113     case USART_DR:
 114         DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
 115         retvalue = s->usart_dr & 0x3FF;
 116         s->usart_sr &= ~USART_SR_RXNE;
 117         qemu_chr_fe_accept_input(&s->chr);
 118         stm32f2xx_update_irq(s);
 119         return retvalue;
 120     case USART_BRR:
 121         return s->usart_brr;
 122     case USART_CR1:
 123         return s->usart_cr1;
 124     case USART_CR2:
 125         return s->usart_cr2;
 126     case USART_CR3:
 127         return s->usart_cr3;
 128     case USART_GTPR:
 129         return s->usart_gtpr;
 130     default:
 131         qemu_log_mask(LOG_GUEST_ERROR,
 132                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 133         return 0;
 134     }
 135
 136     return 0;
 137 }
 138
 139 static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
 140                                   uint64_t val64, unsigned int size)
 141 {
 142     STM32F2XXUsartState *s = opaque;
 143     uint32_t value = val64;
 144     unsigned char ch;
 145
 146     DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);
 147
 148     switch (addr) {
 149     case USART_SR:
 150         if (value <= 0x3FF) {
 151             /* I/O being synchronous, TXE is always set. In addition, it may
 152                only be set by hardware, so keep it set here. */
 153             s->usart_sr = value | USART_SR_TXE;
 154         } else {
 155             s->usart_sr &= value;
 156         }
 157         stm32f2xx_update_irq(s);
 158         return;
 159     case USART_DR:
 160         if (value < 0xF000) {
 161             ch = value;
 162             /* XXX this blocks entire thread. Rewrite to use
 163              * qemu_chr_fe_write and background I/O callbacks */
 164             qemu_chr_fe_write_all(&s->chr, &ch, 1);
 165             /* XXX I/O are currently synchronous, making it impossible for
 166                software to observe transient states where TXE or TC aren't
 167                set. Unlike TXE however, which is read-only, software may
 168                clear TC by writing 0 to the SR register, so set it again
 169                on each write. */
 170             s->usart_sr |= USART_SR_TC;
 171             stm32f2xx_update_irq(s);
 172         }
 173         return;
 174     case USART_BRR:
 175         s->usart_brr = value;
 176         return;
 177     case USART_CR1:
 178         s->usart_cr1 = value;
 179         stm32f2xx_update_irq(s);
 180         return;
 181     case USART_CR2:
 182         s->usart_cr2 = value;
 183         return;
 184     case USART_CR3:
 185         s->usart_cr3 = value;
 186         return;
 187     case USART_GTPR:
 188         s->usart_gtpr = value;
 189         return;
 190     default:
 191         qemu_log_mask(LOG_GUEST_ERROR,
 192                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 193     }
 194 }
 195
 196 static const MemoryRegionOps stm32f2xx_usart_ops = {
 197     .read = stm32f2xx_usart_read,
 198     .write = stm32f2xx_usart_write,
 199     .endianness = DEVICE_NATIVE_ENDIAN,
 200 };
 201
 202 static Property stm32f2xx_usart_properties[] = {
 203     DEFINE_PROP_CHR("chardev", STM32F2XXUsartState, chr),
 204     DEFINE_PROP_END_OF_LIST(),
 205 };
 206
 207 static void stm32f2xx_usart_init(Object *obj)
 208 {
 209     STM32F2XXUsartState *s = STM32F2XX_USART(obj);
 210
 211     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 212
 213     memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
 214                           TYPE_STM32F2XX_USART, 0x400);
 215     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 216 }
 217
 218 static void stm32f2xx_usart_realize(DeviceState *dev, Error **errp)
 219 {
 220     STM32F2XXUsartState *s = STM32F2XX_USART(dev);
 221
 222     qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive,
 223                              stm32f2xx_usart_receive, NULL, NULL,
 224                              s, NULL, true);
 225 }
 226
 227 static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data)
 228 {
 229     DeviceClass *dc = DEVICE_CLASS(klass);
 230
 231     dc->reset = stm32f2xx_usart_reset;
 232     device_class_set_props(dc, stm32f2xx_usart_properties);
 233     dc->realize = stm32f2xx_usart_realize;
 234 }
 235
 236 static const TypeInfo stm32f2xx_usart_info = {
 237     .name          = TYPE_STM32F2XX_USART,
 238     .parent        = TYPE_SYS_BUS_DEVICE,
 239     .instance_size = sizeof(STM32F2XXUsartState),
 240     .instance_init = stm32f2xx_usart_init,
 241     .class_init    = stm32f2xx_usart_class_init,
 242 };
 243
 244 static void stm32f2xx_usart_register_types(void)
 245 {
 246     type_register_static(&stm32f2xx_usart_info);
 247 }
 248
 249 type_init(stm32f2xx_usart_register_types)