hw/net/igb.c

   1 /*
   2  * QEMU Intel 82576 SR/IOV Ethernet Controller Emulation
   3  *
   4  * Datasheet:
   5  * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf
   6  *
   7  * Copyright (c) 2020-2023 Red Hat, Inc.
   8  * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
   9  * Developed by Daynix Computing LTD (http://www.daynix.com)
  10  *
  11  * Authors:
  12  * Akihiko Odaki <akihiko.odaki@daynix.com>
  13  * Gal Hammmer <gal.hammer@sap.com>
  14  * Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
  15  * Dmitry Fleytman <dmitry@daynix.com>
  16  * Leonid Bloch <leonid@daynix.com>
  17  * Yan Vugenfirer <yan@daynix.com>
  18  *
  19  * Based on work done by:
  20  * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
  21  * Copyright (c) 2008 Qumranet
  22  * Based on work done by:
  23  * Copyright (c) 2007 Dan Aloni
  24  * Copyright (c) 2004 Antony T Curtis
  25  *
  26  * This library is free software; you can redistribute it and/or
  27  * modify it under the terms of the GNU Lesser General Public
  28  * License as published by the Free Software Foundation; either
  29  * version 2.1 of the License, or (at your option) any later version.
  30  *
  31  * This library is distributed in the hope that it will be useful,
  32  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  33  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  34  * Lesser General Public License for more details.
  35  *
  36  * You should have received a copy of the GNU Lesser General Public
  37  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  38  */
  39
  40 #include "qemu/osdep.h"
  41 #include "qemu/units.h"
  42 #include "net/eth.h"
  43 #include "net/net.h"
  44 #include "net/tap.h"
  45 #include "qemu/module.h"
  46 #include "qemu/range.h"
  47 #include "sysemu/sysemu.h"
  48 #include "hw/hw.h"
  49 #include "hw/net/mii.h"
  50 #include "hw/pci/pci.h"
  51 #include "hw/pci/pcie.h"
  52 #include "hw/pci/pcie_sriov.h"
  53 #include "hw/pci/msi.h"
  54 #include "hw/pci/msix.h"
  55 #include "hw/qdev-properties.h"
  56 #include "migration/vmstate.h"
  57
  58 #include "igb_common.h"
  59 #include "igb_core.h"
  60
  61 #include "trace.h"
  62 #include "qapi/error.h"
  63 #include "qom/object.h"
  64
  65 #define TYPE_IGB "igb"
  66 OBJECT_DECLARE_SIMPLE_TYPE(IGBState, IGB)
  67
  68 struct IGBState {
  69     PCIDevice parent_obj;
  70     NICState *nic;
  71     NICConf conf;
  72
  73     MemoryRegion mmio;
  74     MemoryRegion flash;
  75     MemoryRegion io;
  76     MemoryRegion msix;
  77
  78     uint32_t ioaddr;
  79
  80     IGBCore core;
  81 };
  82
  83 #define IGB_CAP_SRIOV_OFFSET    (0x160)
  84 #define IGB_VF_OFFSET           (0x80)
  85 #define IGB_VF_STRIDE           (2)
  86
  87 #define E1000E_MMIO_IDX     0
  88 #define E1000E_FLASH_IDX    1
  89 #define E1000E_IO_IDX       2
  90 #define E1000E_MSIX_IDX     3
  91
  92 #define E1000E_MMIO_SIZE    (128 * KiB)
  93 #define E1000E_FLASH_SIZE   (128 * KiB)
  94 #define E1000E_IO_SIZE      (32)
  95 #define E1000E_MSIX_SIZE    (16 * KiB)
  96
  97 static void igb_write_config(PCIDevice *dev, uint32_t addr,
  98     uint32_t val, int len)
  99 {
 100     IGBState *s = IGB(dev);
 101
 102     trace_igb_write_config(addr, val, len);
 103     pci_default_write_config(dev, addr, val, len);
 104
 105     if (range_covers_byte(addr, len, PCI_COMMAND) &&
 106         (dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
 107         igb_start_recv(&s->core);
 108     }
 109 }
 110
 111 uint64_t
 112 igb_mmio_read(void *opaque, hwaddr addr, unsigned size)
 113 {
 114     IGBState *s = opaque;
 115     return igb_core_read(&s->core, addr, size);
 116 }
 117
 118 void
 119 igb_mmio_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
 120 {
 121     IGBState *s = opaque;
 122     igb_core_write(&s->core, addr, val, size);
 123 }
 124
 125 void igb_vf_reset(void *opaque, uint16_t vfn)
 126 {
 127     IGBState *s = opaque;
 128     igb_core_vf_reset(&s->core, vfn);
 129 }
 130
 131 static bool
 132 igb_io_get_reg_index(IGBState *s, uint32_t *idx)
 133 {
 134     if (s->ioaddr < 0x1FFFF) {
 135         *idx = s->ioaddr;
 136         return true;
 137     }
 138
 139     if (s->ioaddr < 0x7FFFF) {
 140         trace_e1000e_wrn_io_addr_undefined(s->ioaddr);
 141         return false;
 142     }
 143
 144     if (s->ioaddr < 0xFFFFF) {
 145         trace_e1000e_wrn_io_addr_flash(s->ioaddr);
 146         return false;
 147     }
 148
 149     trace_e1000e_wrn_io_addr_unknown(s->ioaddr);
 150     return false;
 151 }
 152
 153 static uint64_t
 154 igb_io_read(void *opaque, hwaddr addr, unsigned size)
 155 {
 156     IGBState *s = opaque;
 157     uint32_t idx = 0;
 158     uint64_t val;
 159
 160     switch (addr) {
 161     case E1000_IOADDR:
 162         trace_e1000e_io_read_addr(s->ioaddr);
 163         return s->ioaddr;
 164     case E1000_IODATA:
 165         if (igb_io_get_reg_index(s, &idx)) {
 166             val = igb_core_read(&s->core, idx, sizeof(val));
 167             trace_e1000e_io_read_data(idx, val);
 168             return val;
 169         }
 170         return 0;
 171     default:
 172         trace_e1000e_wrn_io_read_unknown(addr);
 173         return 0;
 174     }
 175 }
 176
 177 static void
 178 igb_io_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
 179 {
 180     IGBState *s = opaque;
 181     uint32_t idx = 0;
 182
 183     switch (addr) {
 184     case E1000_IOADDR:
 185         trace_e1000e_io_write_addr(val);
 186         s->ioaddr = (uint32_t) val;
 187         return;
 188     case E1000_IODATA:
 189         if (igb_io_get_reg_index(s, &idx)) {
 190             trace_e1000e_io_write_data(idx, val);
 191             igb_core_write(&s->core, idx, val, sizeof(val));
 192         }
 193         return;
 194     default:
 195         trace_e1000e_wrn_io_write_unknown(addr);
 196         return;
 197     }
 198 }
 199
 200 static const MemoryRegionOps mmio_ops = {
 201     .read = igb_mmio_read,
 202     .write = igb_mmio_write,
 203     .endianness = DEVICE_LITTLE_ENDIAN,
 204     .impl = {
 205         .min_access_size = 4,
 206         .max_access_size = 4,
 207     },
 208 };
 209
 210 static const MemoryRegionOps io_ops = {
 211     .read = igb_io_read,
 212     .write = igb_io_write,
 213     .endianness = DEVICE_LITTLE_ENDIAN,
 214     .impl = {
 215         .min_access_size = 4,
 216         .max_access_size = 4,
 217     },
 218 };
 219
 220 static bool
 221 igb_nc_can_receive(NetClientState *nc)
 222 {
 223     IGBState *s = qemu_get_nic_opaque(nc);
 224     return igb_can_receive(&s->core);
 225 }
 226
 227 static ssize_t
 228 igb_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
 229 {
 230     IGBState *s = qemu_get_nic_opaque(nc);
 231     return igb_receive_iov(&s->core, iov, iovcnt);
 232 }
 233
 234 static ssize_t
 235 igb_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size)
 236 {
 237     IGBState *s = qemu_get_nic_opaque(nc);
 238     return igb_receive(&s->core, buf, size);
 239 }
 240
 241 static void
 242 igb_set_link_status(NetClientState *nc)
 243 {
 244     IGBState *s = qemu_get_nic_opaque(nc);
 245     igb_core_set_link_status(&s->core);
 246 }
 247
 248 static NetClientInfo net_igb_info = {
 249     .type = NET_CLIENT_DRIVER_NIC,
 250     .size = sizeof(NICState),
 251     .can_receive = igb_nc_can_receive,
 252     .receive = igb_nc_receive,
 253     .receive_iov = igb_nc_receive_iov,
 254     .link_status_changed = igb_set_link_status,
 255 };
 256
 257 /*
 258  * EEPROM (NVM) contents documented in section 6.1, table 6-1:
 259  * and in 6.10 Software accessed words.
 260  */
 261 static const uint16_t igb_eeprom_template[] = {
 262   /*        Address        |Compat.|OEM sp.| ImRev |    OEM sp.    */
 263     0x0000, 0x0000, 0x0000, 0x0d34, 0xffff, 0x2010, 0xffff, 0xffff,
 264   /*      PBA      |ICtrl1 | SSID  | SVID  | DevID |-------|ICtrl2 */
 265     0x1040, 0xffff, 0x002b, 0x0000, 0x8086, 0x10c9, 0x0000, 0x70c3,
 266   /* SwPin0| DevID | EESZ  |-------|ICtrl3 |PCI-tc | MSIX  | APtr  */
 267     0x0004, 0x10c9, 0x5c00, 0x0000, 0x2880, 0x0014, 0x4a40, 0x0060,
 268   /* PCIe Init. Conf 1,2,3 |PCICtrl| LD1,3 |DDevID |DevRev | LD0,2 */
 269     0x6cfb, 0xc7b0, 0x0abe, 0x0403, 0x0783, 0x10a6, 0x0001, 0x0602,
 270   /* SwPin1| FunC  |LAN-PWR|ManHwC |ICtrl3 | IOVct |VDevID |-------*/
 271     0x0004, 0x0020, 0x0000, 0x004a, 0x2080, 0x00f5, 0x10ca, 0x0000,
 272   /*---------------| LD1,3 | LD0,2 | ROEnd | ROSta | Wdog  | VPD   */
 273     0x0000, 0x0000, 0x4784, 0x4602, 0x0000, 0x0000, 0x1000, 0xffff,
 274   /* PCSet0| Ccfg0 |PXEver |IBAcap |PCSet1 | Ccfg1 |iSCVer | ??    */
 275     0x0100, 0x4000, 0x131f, 0x4013, 0x0100, 0x4000, 0xffff, 0xffff,
 276   /* PCSet2| Ccfg2 |PCSet3 | Ccfg3 | ??    |AltMacP| ??    |CHKSUM */
 277     0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x00e0, 0xffff, 0x0000,
 278   /* NC-SIC */
 279     0x0003,
 280 };
 281
 282 static void igb_core_realize(IGBState *s)
 283 {
 284     s->core.owner = &s->parent_obj;
 285     s->core.owner_nic = s->nic;
 286 }
 287
 288 static void
 289 igb_init_msix(IGBState *s)
 290 {
 291     int i, res;
 292
 293     res = msix_init(PCI_DEVICE(s), IGB_MSIX_VEC_NUM,
 294                     &s->msix,
 295                     E1000E_MSIX_IDX, 0,
 296                     &s->msix,
 297                     E1000E_MSIX_IDX, 0x2000,
 298                     0x70, NULL);
 299
 300     if (res < 0) {
 301         trace_e1000e_msix_init_fail(res);
 302     } else {
 303         for (i = 0; i < IGB_MSIX_VEC_NUM; i++) {
 304             msix_vector_use(PCI_DEVICE(s), i);
 305         }
 306     }
 307 }
 308
 309 static void
 310 igb_cleanup_msix(IGBState *s)
 311 {
 312     msix_unuse_all_vectors(PCI_DEVICE(s));
 313     msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix);
 314 }
 315
 316 static void
 317 igb_init_net_peer(IGBState *s, PCIDevice *pci_dev, uint8_t *macaddr)
 318 {
 319     DeviceState *dev = DEVICE(pci_dev);
 320     NetClientState *nc;
 321     int i;
 322
 323     s->nic = qemu_new_nic(&net_igb_info, &s->conf,
 324         object_get_typename(OBJECT(s)), dev->id, s);
 325
 326     s->core.max_queue_num = s->conf.peers.queues ? s->conf.peers.queues - 1 : 0;
 327
 328     trace_e1000e_mac_set_permanent(MAC_ARG(macaddr));
 329     memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac));
 330
 331     qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr);
 332
 333     /* Setup virtio headers */
 334     for (i = 0; i < s->conf.peers.queues; i++) {
 335         nc = qemu_get_subqueue(s->nic, i);
 336         if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) {
 337             trace_e1000e_cfg_support_virtio(false);
 338             return;
 339         }
 340     }
 341
 342     trace_e1000e_cfg_support_virtio(true);
 343     s->core.has_vnet = true;
 344
 345     for (i = 0; i < s->conf.peers.queues; i++) {
 346         nc = qemu_get_subqueue(s->nic, i);
 347         qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr));
 348         qemu_using_vnet_hdr(nc->peer, true);
 349     }
 350 }
 351
 352 static int
 353 igb_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
 354 {
 355     Error *local_err = NULL;
 356     int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset,
 357                                  PCI_PM_SIZEOF, &local_err);
 358
 359     if (local_err) {
 360         error_report_err(local_err);
 361         return ret;
 362     }
 363
 364     pci_set_word(pdev->config + offset + PCI_PM_PMC,
 365                  PCI_PM_CAP_VER_1_1 |
 366                  pmc);
 367
 368     pci_set_word(pdev->wmask + offset + PCI_PM_CTRL,
 369                  PCI_PM_CTRL_STATE_MASK |
 370                  PCI_PM_CTRL_PME_ENABLE |
 371                  PCI_PM_CTRL_DATA_SEL_MASK);
 372
 373     pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL,
 374                  PCI_PM_CTRL_PME_STATUS);
 375
 376     return ret;
 377 }
 378
 379 static void igb_pci_realize(PCIDevice *pci_dev, Error **errp)
 380 {
 381     IGBState *s = IGB(pci_dev);
 382     uint8_t *macaddr;
 383     int ret;
 384
 385     trace_e1000e_cb_pci_realize();
 386
 387     pci_dev->config_write = igb_write_config;
 388
 389     pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
 390     pci_dev->config[PCI_INTERRUPT_PIN] = 1;
 391
 392     /* Define IO/MMIO regions */
 393     memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s,
 394                           "igb-mmio", E1000E_MMIO_SIZE);
 395     pci_register_bar(pci_dev, E1000E_MMIO_IDX,
 396                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
 397
 398     /*
 399      * We provide a dummy implementation for the flash BAR
 400      * for drivers that may theoretically probe for its presence.
 401      */
 402     memory_region_init(&s->flash, OBJECT(s),
 403                        "igb-flash", E1000E_FLASH_SIZE);
 404     pci_register_bar(pci_dev, E1000E_FLASH_IDX,
 405                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash);
 406
 407     memory_region_init_io(&s->io, OBJECT(s), &io_ops, s,
 408                           "igb-io", E1000E_IO_SIZE);
 409     pci_register_bar(pci_dev, E1000E_IO_IDX,
 410                      PCI_BASE_ADDRESS_SPACE_IO, &s->io);
 411
 412     memory_region_init(&s->msix, OBJECT(s), "igb-msix",
 413                        E1000E_MSIX_SIZE);
 414     pci_register_bar(pci_dev, E1000E_MSIX_IDX,
 415                      PCI_BASE_ADDRESS_MEM_TYPE_64, &s->msix);
 416
 417     /* Create networking backend */
 418     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 419     macaddr = s->conf.macaddr.a;
 420
 421     /* Add PCI capabilities in reverse order */
 422     assert(pcie_endpoint_cap_init(pci_dev, 0xa0) > 0);
 423
 424     igb_init_msix(s);
 425
 426     ret = msi_init(pci_dev, 0x50, 1, true, true, NULL);
 427     if (ret) {
 428         trace_e1000e_msi_init_fail(ret);
 429     }
 430
 431     if (igb_add_pm_capability(pci_dev, 0x40, PCI_PM_CAP_DSI) < 0) {
 432         hw_error("Failed to initialize PM capability");
 433     }
 434
 435     /* PCIe extended capabilities (in order) */
 436     if (pcie_aer_init(pci_dev, 1, 0x100, 0x40, errp) < 0) {
 437         hw_error("Failed to initialize AER capability");
 438     }
 439
 440     pcie_ari_init(pci_dev, 0x150);
 441
 442     pcie_sriov_pf_init(pci_dev, IGB_CAP_SRIOV_OFFSET, TYPE_IGBVF,
 443         IGB_82576_VF_DEV_ID, IGB_MAX_VF_FUNCTIONS, IGB_MAX_VF_FUNCTIONS,
 444         IGB_VF_OFFSET, IGB_VF_STRIDE);
 445
 446     pcie_sriov_pf_init_vf_bar(pci_dev, IGBVF_MMIO_BAR_IDX,
 447         PCI_BASE_ADDRESS_MEM_TYPE_64 | PCI_BASE_ADDRESS_MEM_PREFETCH,
 448         IGBVF_MMIO_SIZE);
 449     pcie_sriov_pf_init_vf_bar(pci_dev, IGBVF_MSIX_BAR_IDX,
 450         PCI_BASE_ADDRESS_MEM_TYPE_64 | PCI_BASE_ADDRESS_MEM_PREFETCH,
 451         IGBVF_MSIX_SIZE);
 452
 453     igb_init_net_peer(s, pci_dev, macaddr);
 454
 455     /* Initialize core */
 456     igb_core_realize(s);
 457
 458     igb_core_pci_realize(&s->core,
 459                          igb_eeprom_template,
 460                          sizeof(igb_eeprom_template),
 461                          macaddr);
 462 }
 463
 464 static void igb_pci_uninit(PCIDevice *pci_dev)
 465 {
 466     IGBState *s = IGB(pci_dev);
 467
 468     trace_e1000e_cb_pci_uninit();
 469
 470     igb_core_pci_uninit(&s->core);
 471
 472     pcie_sriov_pf_exit(pci_dev);
 473     pcie_cap_exit(pci_dev);
 474
 475     qemu_del_nic(s->nic);
 476
 477     igb_cleanup_msix(s);
 478     msi_uninit(pci_dev);
 479 }
 480
 481 static void igb_qdev_reset_hold(Object *obj)
 482 {
 483     PCIDevice *d = PCI_DEVICE(obj);
 484     IGBState *s = IGB(obj);
 485
 486     trace_e1000e_cb_qdev_reset_hold();
 487
 488     pcie_sriov_pf_disable_vfs(d);
 489     igb_core_reset(&s->core);
 490 }
 491
 492 static int igb_pre_save(void *opaque)
 493 {
 494     IGBState *s = opaque;
 495
 496     trace_e1000e_cb_pre_save();
 497
 498     igb_core_pre_save(&s->core);
 499
 500     return 0;
 501 }
 502
 503 static int igb_post_load(void *opaque, int version_id)
 504 {
 505     IGBState *s = opaque;
 506
 507     trace_e1000e_cb_post_load();
 508     return igb_core_post_load(&s->core);
 509 }
 510
 511 static const VMStateDescription igb_vmstate_tx_ctx = {
 512     .name = "igb-tx-ctx",
 513     .version_id = 1,
 514     .minimum_version_id = 1,
 515     .fields = (VMStateField[]) {
 516         VMSTATE_UINT32(vlan_macip_lens, struct e1000_adv_tx_context_desc),
 517         VMSTATE_UINT32(seqnum_seed, struct e1000_adv_tx_context_desc),
 518         VMSTATE_UINT32(type_tucmd_mlhl, struct e1000_adv_tx_context_desc),
 519         VMSTATE_UINT32(mss_l4len_idx, struct e1000_adv_tx_context_desc),
 520         VMSTATE_END_OF_LIST()
 521     }
 522 };
 523
 524 static const VMStateDescription igb_vmstate_tx = {
 525     .name = "igb-tx",
 526     .version_id = 2,
 527     .minimum_version_id = 2,
 528     .fields = (VMStateField[]) {
 529         VMSTATE_STRUCT_ARRAY(ctx, struct igb_tx, 2, 0, igb_vmstate_tx_ctx,
 530                              struct e1000_adv_tx_context_desc),
 531         VMSTATE_UINT32(first_cmd_type_len, struct igb_tx),
 532         VMSTATE_UINT32(first_olinfo_status, struct igb_tx),
 533         VMSTATE_BOOL(first, struct igb_tx),
 534         VMSTATE_BOOL(skip_cp, struct igb_tx),
 535         VMSTATE_END_OF_LIST()
 536     }
 537 };
 538
 539 static const VMStateDescription igb_vmstate_intr_timer = {
 540     .name = "igb-intr-timer",
 541     .version_id = 1,
 542     .minimum_version_id = 1,
 543     .fields = (VMStateField[]) {
 544         VMSTATE_TIMER_PTR(timer, IGBIntrDelayTimer),
 545         VMSTATE_BOOL(running, IGBIntrDelayTimer),
 546         VMSTATE_END_OF_LIST()
 547     }
 548 };
 549
 550 #define VMSTATE_IGB_INTR_DELAY_TIMER(_f, _s)                        \
 551     VMSTATE_STRUCT(_f, _s, 0,                                       \
 552                    igb_vmstate_intr_timer, IGBIntrDelayTimer)
 553
 554 #define VMSTATE_IGB_INTR_DELAY_TIMER_ARRAY(_f, _s, _num)            \
 555     VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0,                           \
 556                          igb_vmstate_intr_timer, IGBIntrDelayTimer)
 557
 558 static const VMStateDescription igb_vmstate = {
 559     .name = "igb",
 560     .version_id = 1,
 561     .minimum_version_id = 1,
 562     .pre_save = igb_pre_save,
 563     .post_load = igb_post_load,
 564     .fields = (VMStateField[]) {
 565         VMSTATE_PCI_DEVICE(parent_obj, IGBState),
 566         VMSTATE_MSIX(parent_obj, IGBState),
 567
 568         VMSTATE_UINT32(ioaddr, IGBState),
 569         VMSTATE_UINT8(core.rx_desc_len, IGBState),
 570         VMSTATE_UINT16_ARRAY(core.eeprom, IGBState, IGB_EEPROM_SIZE),
 571         VMSTATE_UINT16_ARRAY(core.phy, IGBState, MAX_PHY_REG_ADDRESS + 1),
 572         VMSTATE_UINT32_ARRAY(core.mac, IGBState, E1000E_MAC_SIZE),
 573         VMSTATE_UINT8_ARRAY(core.permanent_mac, IGBState, ETH_ALEN),
 574
 575         VMSTATE_IGB_INTR_DELAY_TIMER_ARRAY(core.eitr, IGBState,
 576                                            IGB_INTR_NUM),
 577
 578         VMSTATE_UINT32_ARRAY(core.eitr_guest_value, IGBState, IGB_INTR_NUM),
 579
 580         VMSTATE_STRUCT_ARRAY(core.tx, IGBState, IGB_NUM_QUEUES, 0,
 581                              igb_vmstate_tx, struct igb_tx),
 582
 583         VMSTATE_INT64(core.timadj, IGBState),
 584
 585         VMSTATE_END_OF_LIST()
 586     }
 587 };
 588
 589 static Property igb_properties[] = {
 590     DEFINE_NIC_PROPERTIES(IGBState, conf),
 591     DEFINE_PROP_END_OF_LIST(),
 592 };
 593
 594 static void igb_class_init(ObjectClass *class, void *data)
 595 {
 596     DeviceClass *dc = DEVICE_CLASS(class);
 597     ResettableClass *rc = RESETTABLE_CLASS(class);
 598     PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
 599
 600     c->realize = igb_pci_realize;
 601     c->exit = igb_pci_uninit;
 602     c->vendor_id = PCI_VENDOR_ID_INTEL;
 603     c->device_id = E1000_DEV_ID_82576;
 604     c->revision = 1;
 605     c->class_id = PCI_CLASS_NETWORK_ETHERNET;
 606
 607     rc->phases.hold = igb_qdev_reset_hold;
 608
 609     dc->desc = "Intel 82576 Gigabit Ethernet Controller";
 610     dc->vmsd = &igb_vmstate;
 611
 612     device_class_set_props(dc, igb_properties);
 613     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 614 }
 615
 616 static void igb_instance_init(Object *obj)
 617 {
 618     IGBState *s = IGB(obj);
 619     device_add_bootindex_property(obj, &s->conf.bootindex,
 620                                   "bootindex", "/ethernet-phy@0",
 621                                   DEVICE(obj));
 622 }
 623
 624 static const TypeInfo igb_info = {
 625     .name = TYPE_IGB,
 626     .parent = TYPE_PCI_DEVICE,
 627     .instance_size = sizeof(IGBState),
 628     .class_init = igb_class_init,
 629     .instance_init = igb_instance_init,
 630     .interfaces = (InterfaceInfo[]) {
 631         { INTERFACE_PCIE_DEVICE },
 632         { }
 633     },
 634 };
 635
 636 static void igb_register_types(void)
 637 {
 638     type_register_static(&igb_info);
 639 }
 640
 641 type_init(igb_register_types)