target/ppc/ppc-qmp-cmds.c

   1 /*
   2  * QEMU PPC (monitor definitions)
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "cpu.h"
  27 #include "monitor/monitor.h"
  28 #include "qemu/ctype.h"
  29 #include "monitor/hmp-target.h"
  30 #include "monitor/hmp.h"
  31 #include "qapi/qapi-commands-machine-target.h"
  32 #include "cpu-models.h"
  33 #include "cpu-qom.h"
  34
  35 static target_long monitor_get_ccr(Monitor *mon, const struct MonitorDef *md,
  36                                    int val)
  37 {
  38     CPUArchState *env = mon_get_cpu_env(mon);
  39     unsigned int u;
  40
  41     u = ppc_get_cr(env);
  42
  43     return u;
  44 }
  45
  46 static target_long monitor_get_xer(Monitor *mon, const struct MonitorDef *md,
  47                                    int val)
  48 {
  49     CPUArchState *env = mon_get_cpu_env(mon);
  50     return cpu_read_xer(env);
  51 }
  52
  53 static target_long monitor_get_decr(Monitor *mon, const struct MonitorDef *md,
  54                                     int val)
  55 {
  56     CPUArchState *env = mon_get_cpu_env(mon);
  57     if (!env->tb_env) {
  58         return 0;
  59     }
  60     return cpu_ppc_load_decr(env);
  61 }
  62
  63 static target_long monitor_get_tbu(Monitor *mon, const struct MonitorDef *md,
  64                                    int val)
  65 {
  66     CPUArchState *env = mon_get_cpu_env(mon);
  67     if (!env->tb_env) {
  68         return 0;
  69     }
  70     return cpu_ppc_load_tbu(env);
  71 }
  72
  73 static target_long monitor_get_tbl(Monitor *mon, const struct MonitorDef *md,
  74                                    int val)
  75 {
  76     CPUArchState *env = mon_get_cpu_env(mon);
  77     if (!env->tb_env) {
  78         return 0;
  79     }
  80     return cpu_ppc_load_tbl(env);
  81 }
  82
  83 void hmp_info_tlb(Monitor *mon, const QDict *qdict)
  84 {
  85     CPUArchState *env1 = mon_get_cpu_env(mon);
  86
  87     if (!env1) {
  88         monitor_printf(mon, "No CPU available\n");
  89         return;
  90     }
  91     dump_mmu(env1);
  92 }
  93
  94 const MonitorDef monitor_defs[] = {
  95     { "fpscr", offsetof(CPUPPCState, fpscr) },
  96     /* Next instruction pointer */
  97     { "nip|pc", offsetof(CPUPPCState, nip) },
  98     { "lr", offsetof(CPUPPCState, lr) },
  99     { "ctr", offsetof(CPUPPCState, ctr) },
 100     { "decr", 0, &monitor_get_decr, },
 101     { "ccr|cr", 0, &monitor_get_ccr, },
 102     /* Machine state register */
 103     { "xer", 0, &monitor_get_xer },
 104     { "msr", offsetof(CPUPPCState, msr) },
 105     { "tbu", 0, &monitor_get_tbu, },
 106 #if defined(TARGET_PPC64)
 107     { "tb", 0, &monitor_get_tbl, },
 108 #else
 109     { "tbl", 0, &monitor_get_tbl, },
 110 #endif
 111     { NULL },
 112 };
 113
 114 const MonitorDef *target_monitor_defs(void)
 115 {
 116     return monitor_defs;
 117 }
 118
 119 static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum)
 120 {
 121     int regnum;
 122     char *endptr = NULL;
 123
 124     if (!*numstr) {
 125         return false;
 126     }
 127
 128     regnum = strtoul(numstr, &endptr, 10);
 129     if (*endptr || (regnum >= maxnum)) {
 130         return false;
 131     }
 132     *pregnum = regnum;
 133
 134     return true;
 135 }
 136
 137 int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
 138 {
 139     int i, regnum;
 140     PowerPCCPU *cpu = POWERPC_CPU(cs);
 141     CPUPPCState *env = &cpu->env;
 142
 143     /* General purpose registers */
 144     if ((qemu_tolower(name[0]) == 'r') &&
 145         ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->gpr), &regnum)) {
 146         *pval = env->gpr[regnum];
 147         return 0;
 148     }
 149
 150     /* Floating point registers */
 151     if ((qemu_tolower(name[0]) == 'f') &&
 152         ppc_cpu_get_reg_num(name + 1, 32, &regnum)) {
 153         *pval = *cpu_fpr_ptr(env, regnum);
 154         return 0;
 155     }
 156
 157     /* Special purpose registers */
 158     for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) {
 159         ppc_spr_t *spr = &env->spr_cb[i];
 160
 161         if (spr->name && (strcasecmp(name, spr->name) == 0)) {
 162             *pval = env->spr[i];
 163             return 0;
 164         }
 165     }
 166
 167     /* Segment registers */
 168 #if !defined(CONFIG_USER_ONLY)
 169     if ((strncasecmp(name, "sr", 2) == 0) &&
 170         ppc_cpu_get_reg_num(name + 2, ARRAY_SIZE(env->sr), &regnum)) {
 171         *pval = env->sr[regnum];
 172         return 0;
 173     }
 174 #endif
 175
 176     return -EINVAL;
 177 }
 178
 179 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
 180 {
 181     ObjectClass *oc = data;
 182     CpuDefinitionInfoList **first = user_data;
 183     const char *typename;
 184     CpuDefinitionInfo *info;
 185
 186     typename = object_class_get_name(oc);
 187     info = g_malloc0(sizeof(*info));
 188     info->name = cpu_model_from_type(typename);
 189
 190     QAPI_LIST_PREPEND(*first, info);
 191 }
 192
 193 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 194 {
 195     CpuDefinitionInfoList *cpu_list = NULL;
 196     GSList *list;
 197     int i;
 198
 199     list = object_class_get_list(TYPE_POWERPC_CPU, false);
 200     g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
 201     g_slist_free(list);
 202
 203     for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
 204         PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
 205         ObjectClass *oc;
 206         CpuDefinitionInfo *info;
 207
 208         oc = ppc_cpu_class_by_name(alias->model);
 209         if (oc == NULL) {
 210             continue;
 211         }
 212
 213         info = g_malloc0(sizeof(*info));
 214         info->name = g_strdup(alias->alias);
 215         info->q_typename = g_strdup(object_class_get_name(oc));
 216
 217         QAPI_LIST_PREPEND(cpu_list, info);
 218     }
 219
 220     return cpu_list;
 221 }