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target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro
[qemu/kevin.git] / target-ppc / translate.c
blob0219d38acec83b5f607156a5e4c5efa236352348
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "qemu/host-utils.h"
26 #include "exec/cpu_ldst.h"
27
28 #include "exec/helper-proto.h"
29 #include "exec/helper-gen.h"
30
31 #include "trace-tcg.h"
32
33
34 #define CPU_SINGLE_STEP 0x1
35 #define CPU_BRANCH_STEP 0x2
36 #define GDBSTUB_SINGLE_STEP 0x4
37
38 /* Include definitions for instructions classes and implementations flags */
39 //#define PPC_DEBUG_DISAS
40 //#define DO_PPC_STATISTICS
41
42 #ifdef PPC_DEBUG_DISAS
43 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
44 #else
45 # define LOG_DISAS(...) do { } while (0)
46 #endif
47 /*****************************************************************************/
48 /* Code translation helpers */
49
50 /* global register indexes */
51 static TCGv_ptr cpu_env;
52 static char cpu_reg_names[10*3 + 22*4 /* GPR */
53 + 10*4 + 22*5 /* SPE GPRh */
54 + 10*4 + 22*5 /* FPR */
55 + 2*(10*6 + 22*7) /* AVRh, AVRl */
56 + 10*5 + 22*6 /* VSR */
57 + 8*5 /* CRF */];
58 static TCGv cpu_gpr[32];
59 static TCGv cpu_gprh[32];
60 static TCGv_i64 cpu_fpr[32];
61 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
62 static TCGv_i64 cpu_vsr[32];
63 static TCGv_i32 cpu_crf[8];
64 static TCGv cpu_nip;
65 static TCGv cpu_msr;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 #if defined(TARGET_PPC64)
69 static TCGv cpu_cfar;
70 #endif
71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
72 static TCGv cpu_reserve;
73 static TCGv cpu_fpscr;
74 static TCGv_i32 cpu_access_type;
75
76 #include "exec/gen-icount.h"
77
78 void ppc_translate_init(void)
79 {
80 int i;
81 char* p;
82 size_t cpu_reg_names_size;
83 static int done_init = 0;
84
85 if (done_init)
86 return;
87
88 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
89
90 p = cpu_reg_names;
91 cpu_reg_names_size = sizeof(cpu_reg_names);
92
93 for (i = 0; i < 8; i++) {
94 snprintf(p, cpu_reg_names_size, "crf%d", i);
95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUPPCState, crf[i]), p);
97 p += 5;
98 cpu_reg_names_size -= 5;
99 }
100
101 for (i = 0; i < 32; i++) {
102 snprintf(p, cpu_reg_names_size, "r%d", i);
103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
104 offsetof(CPUPPCState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106 cpu_reg_names_size -= (i < 10) ? 3 : 4;
107 snprintf(p, cpu_reg_names_size, "r%dH", i);
108 cpu_gprh[i] = tcg_global_mem_new(TCG_AREG0,
109 offsetof(CPUPPCState, gprh[i]), p);
110 p += (i < 10) ? 4 : 5;
111 cpu_reg_names_size -= (i < 10) ? 4 : 5;
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 snprintf(p, cpu_reg_names_size, "vsr%d", i);
141 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
142 offsetof(CPUPPCState, vsr[i]), p);
143 p += (i < 10) ? 5 : 6;
144 cpu_reg_names_size -= (i < 10) ? 5 : 6;
145 }
146
147 cpu_nip = tcg_global_mem_new(TCG_AREG0,
148 offsetof(CPUPPCState, nip), "nip");
149
150 cpu_msr = tcg_global_mem_new(TCG_AREG0,
151 offsetof(CPUPPCState, msr), "msr");
152
153 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
154 offsetof(CPUPPCState, ctr), "ctr");
155
156 cpu_lr = tcg_global_mem_new(TCG_AREG0,
157 offsetof(CPUPPCState, lr), "lr");
158
159 #if defined(TARGET_PPC64)
160 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
161 offsetof(CPUPPCState, cfar), "cfar");
162 #endif
163
164 cpu_xer = tcg_global_mem_new(TCG_AREG0,
165 offsetof(CPUPPCState, xer), "xer");
166 cpu_so = tcg_global_mem_new(TCG_AREG0,
167 offsetof(CPUPPCState, so), "SO");
168 cpu_ov = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, ov), "OV");
170 cpu_ca = tcg_global_mem_new(TCG_AREG0,
171 offsetof(CPUPPCState, ca), "CA");
172
173 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
174 offsetof(CPUPPCState, reserve_addr),
175 "reserve_addr");
176
177 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
178 offsetof(CPUPPCState, fpscr), "fpscr");
179
180 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
181 offsetof(CPUPPCState, access_type), "access_type");
182
183 done_init = 1;
184 }
185
186 /* internal defines */
187 struct DisasContext {
188 struct TranslationBlock *tb;
189 target_ulong nip;
190 uint32_t opcode;
191 uint32_t exception;
192 /* Routine used to access memory */
193 bool pr, hv;
194 int mem_idx;
195 int access_type;
196 /* Translation flags */
197 int le_mode;
198 TCGMemOp default_tcg_memop_mask;
199 #if defined(TARGET_PPC64)
200 int sf_mode;
201 int has_cfar;
202 #endif
203 int fpu_enabled;
204 int altivec_enabled;
205 int vsx_enabled;
206 int spe_enabled;
207 int tm_enabled;
208 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
209 int singlestep_enabled;
210 uint64_t insns_flags;
211 uint64_t insns_flags2;
212 };
213
214 /* Return true iff byteswap is needed in a scalar memop */
215 static inline bool need_byteswap(const DisasContext *ctx)
216 {
217 #if defined(TARGET_WORDS_BIGENDIAN)
218 return ctx->le_mode;
219 #else
220 return !ctx->le_mode;
221 #endif
222 }
223
224 /* True when active word size < size of target_long. */
225 #ifdef TARGET_PPC64
226 # define NARROW_MODE(C) (!(C)->sf_mode)
227 #else
228 # define NARROW_MODE(C) 0
229 #endif
230
231 struct opc_handler_t {
232 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
233 uint32_t inval1;
234 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
235 uint32_t inval2;
236 /* instruction type */
237 uint64_t type;
238 /* extended instruction type */
239 uint64_t type2;
240 /* handler */
241 void (*handler)(DisasContext *ctx);
242 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
243 const char *oname;
244 #endif
245 #if defined(DO_PPC_STATISTICS)
246 uint64_t count;
247 #endif
248 };
249
250 static inline void gen_reset_fpstatus(void)
251 {
252 gen_helper_reset_fpstatus(cpu_env);
253 }
254
255 static inline void gen_compute_fprf(TCGv_i64 arg)
256 {
257 gen_helper_compute_fprf(cpu_env, arg);
258 gen_helper_float_check_status(cpu_env);
259 }
260
261 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
262 {
263 if (ctx->access_type != access_type) {
264 tcg_gen_movi_i32(cpu_access_type, access_type);
265 ctx->access_type = access_type;
266 }
267 }
268
269 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
270 {
271 if (NARROW_MODE(ctx)) {
272 nip = (uint32_t)nip;
273 }
274 tcg_gen_movi_tl(cpu_nip, nip);
275 }
276
277 void gen_update_current_nip(void *opaque)
278 {
279 DisasContext *ctx = opaque;
280
281 tcg_gen_movi_tl(cpu_nip, ctx->nip);
282 }
283
284 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
285 {
286 TCGv_i32 t0, t1;
287 if (ctx->exception == POWERPC_EXCP_NONE) {
288 gen_update_nip(ctx, ctx->nip);
289 }
290 t0 = tcg_const_i32(excp);
291 t1 = tcg_const_i32(error);
292 gen_helper_raise_exception_err(cpu_env, t0, t1);
293 tcg_temp_free_i32(t0);
294 tcg_temp_free_i32(t1);
295 ctx->exception = (excp);
296 }
297
298 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
299 {
300 TCGv_i32 t0;
301 if (ctx->exception == POWERPC_EXCP_NONE) {
302 gen_update_nip(ctx, ctx->nip);
303 }
304 t0 = tcg_const_i32(excp);
305 gen_helper_raise_exception(cpu_env, t0);
306 tcg_temp_free_i32(t0);
307 ctx->exception = (excp);
308 }
309
310 static inline void gen_debug_exception(DisasContext *ctx)
311 {
312 TCGv_i32 t0;
313
314 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
315 (ctx->exception != POWERPC_EXCP_SYNC)) {
316 gen_update_nip(ctx, ctx->nip);
317 }
318 t0 = tcg_const_i32(EXCP_DEBUG);
319 gen_helper_raise_exception(cpu_env, t0);
320 tcg_temp_free_i32(t0);
321 }
322
323 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
324 {
325 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
326 }
327
328 /* Stop translation */
329 static inline void gen_stop_exception(DisasContext *ctx)
330 {
331 gen_update_nip(ctx, ctx->nip);
332 ctx->exception = POWERPC_EXCP_STOP;
333 }
334
335 #ifndef CONFIG_USER_ONLY
336 /* No need to update nip here, as execution flow will change */
337 static inline void gen_sync_exception(DisasContext *ctx)
338 {
339 ctx->exception = POWERPC_EXCP_SYNC;
340 }
341 #endif
342
343 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
344 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
345
346 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
347 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
348
349 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
350 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
351
352 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
353 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
354
355 typedef struct opcode_t {
356 unsigned char opc1, opc2, opc3;
357 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
358 unsigned char pad[5];
359 #else
360 unsigned char pad[1];
361 #endif
362 opc_handler_t handler;
363 const char *oname;
364 } opcode_t;
365
366 /*****************************************************************************/
367 /*** Instruction decoding ***/
368 #define EXTRACT_HELPER(name, shift, nb) \
369 static inline uint32_t name(uint32_t opcode) \
370 { \
371 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
372 }
373
374 #define EXTRACT_SHELPER(name, shift, nb) \
375 static inline int32_t name(uint32_t opcode) \
376 { \
377 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
378 }
379
380 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
381 static inline uint32_t name(uint32_t opcode) \
382 { \
383 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
384 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
385 }
386 /* Opcode part 1 */
387 EXTRACT_HELPER(opc1, 26, 6);
388 /* Opcode part 2 */
389 EXTRACT_HELPER(opc2, 1, 5);
390 /* Opcode part 3 */
391 EXTRACT_HELPER(opc3, 6, 5);
392 /* Update Cr0 flags */
393 EXTRACT_HELPER(Rc, 0, 1);
394 /* Update Cr6 flags (Altivec) */
395 EXTRACT_HELPER(Rc21, 10, 1);
396 /* Destination */
397 EXTRACT_HELPER(rD, 21, 5);
398 /* Source */
399 EXTRACT_HELPER(rS, 21, 5);
400 /* First operand */
401 EXTRACT_HELPER(rA, 16, 5);
402 /* Second operand */
403 EXTRACT_HELPER(rB, 11, 5);
404 /* Third operand */
405 EXTRACT_HELPER(rC, 6, 5);
406 /*** Get CRn ***/
407 EXTRACT_HELPER(crfD, 23, 3);
408 EXTRACT_HELPER(crfS, 18, 3);
409 EXTRACT_HELPER(crbD, 21, 5);
410 EXTRACT_HELPER(crbA, 16, 5);
411 EXTRACT_HELPER(crbB, 11, 5);
412 /* SPR / TBL */
413 EXTRACT_HELPER(_SPR, 11, 10);
414 static inline uint32_t SPR(uint32_t opcode)
415 {
416 uint32_t sprn = _SPR(opcode);
417
418 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
419 }
420 /*** Get constants ***/
421 /* 16 bits signed immediate value */
422 EXTRACT_SHELPER(SIMM, 0, 16);
423 /* 16 bits unsigned immediate value */
424 EXTRACT_HELPER(UIMM, 0, 16);
425 /* 5 bits signed immediate value */
426 EXTRACT_HELPER(SIMM5, 16, 5);
427 /* 5 bits signed immediate value */
428 EXTRACT_HELPER(UIMM5, 16, 5);
429 /* Bit count */
430 EXTRACT_HELPER(NB, 11, 5);
431 /* Shift count */
432 EXTRACT_HELPER(SH, 11, 5);
433 /* Vector shift count */
434 EXTRACT_HELPER(VSH, 6, 4);
435 /* Mask start */
436 EXTRACT_HELPER(MB, 6, 5);
437 /* Mask end */
438 EXTRACT_HELPER(ME, 1, 5);
439 /* Trap operand */
440 EXTRACT_HELPER(TO, 21, 5);
441
442 EXTRACT_HELPER(CRM, 12, 8);
443
444 #ifndef CONFIG_USER_ONLY
445 EXTRACT_HELPER(SR, 16, 4);
446 #endif
447
448 /* mtfsf/mtfsfi */
449 EXTRACT_HELPER(FPBF, 23, 3);
450 EXTRACT_HELPER(FPIMM, 12, 4);
451 EXTRACT_HELPER(FPL, 25, 1);
452 EXTRACT_HELPER(FPFLM, 17, 8);
453 EXTRACT_HELPER(FPW, 16, 1);
454
455 /*** Jump target decoding ***/
456 /* Immediate address */
457 static inline target_ulong LI(uint32_t opcode)
458 {
459 return (opcode >> 0) & 0x03FFFFFC;
460 }
461
462 static inline uint32_t BD(uint32_t opcode)
463 {
464 return (opcode >> 0) & 0xFFFC;
465 }
466
467 EXTRACT_HELPER(BO, 21, 5);
468 EXTRACT_HELPER(BI, 16, 5);
469 /* Absolute/relative address */
470 EXTRACT_HELPER(AA, 1, 1);
471 /* Link */
472 EXTRACT_HELPER(LK, 0, 1);
473
474 /* DFP Z22-form */
475 EXTRACT_HELPER(DCM, 10, 6)
476
477 /* DFP Z23-form */
478 EXTRACT_HELPER(RMC, 9, 2)
479
480 /* Create a mask between <start> and <end> bits */
481 static inline target_ulong MASK(uint32_t start, uint32_t end)
482 {
483 target_ulong ret;
484
485 #if defined(TARGET_PPC64)
486 if (likely(start == 0)) {
487 ret = UINT64_MAX << (63 - end);
488 } else if (likely(end == 63)) {
489 ret = UINT64_MAX >> start;
490 }
491 #else
492 if (likely(start == 0)) {
493 ret = UINT32_MAX << (31 - end);
494 } else if (likely(end == 31)) {
495 ret = UINT32_MAX >> start;
496 }
497 #endif
498 else {
499 ret = (((target_ulong)(-1ULL)) >> (start)) ^
500 (((target_ulong)(-1ULL) >> (end)) >> 1);
501 if (unlikely(start > end))
502 return ~ret;
503 }
504
505 return ret;
506 }
507
508 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
509 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
510 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
511 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
512 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
513 EXTRACT_HELPER(DM, 8, 2);
514 EXTRACT_HELPER(UIM, 16, 2);
515 EXTRACT_HELPER(SHW, 8, 2);
516 EXTRACT_HELPER(SP, 19, 2);
517 /*****************************************************************************/
518 /* PowerPC instructions table */
519
520 #if defined(DO_PPC_STATISTICS)
521 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
522 { \
523 .opc1 = op1, \
524 .opc2 = op2, \
525 .opc3 = op3, \
526 .pad = { 0, }, \
527 .handler = { \
528 .inval1 = invl, \
529 .type = _typ, \
530 .type2 = _typ2, \
531 .handler = &gen_##name, \
532 .oname = stringify(name), \
533 }, \
534 .oname = stringify(name), \
535 }
536 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
537 { \
538 .opc1 = op1, \
539 .opc2 = op2, \
540 .opc3 = op3, \
541 .pad = { 0, }, \
542 .handler = { \
543 .inval1 = invl1, \
544 .inval2 = invl2, \
545 .type = _typ, \
546 .type2 = _typ2, \
547 .handler = &gen_##name, \
548 .oname = stringify(name), \
549 }, \
550 .oname = stringify(name), \
551 }
552 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
553 { \
554 .opc1 = op1, \
555 .opc2 = op2, \
556 .opc3 = op3, \
557 .pad = { 0, }, \
558 .handler = { \
559 .inval1 = invl, \
560 .type = _typ, \
561 .type2 = _typ2, \
562 .handler = &gen_##name, \
563 .oname = onam, \
564 }, \
565 .oname = onam, \
566 }
567 #else
568 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
569 { \
570 .opc1 = op1, \
571 .opc2 = op2, \
572 .opc3 = op3, \
573 .pad = { 0, }, \
574 .handler = { \
575 .inval1 = invl, \
576 .type = _typ, \
577 .type2 = _typ2, \
578 .handler = &gen_##name, \
579 }, \
580 .oname = stringify(name), \
581 }
582 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
583 { \
584 .opc1 = op1, \
585 .opc2 = op2, \
586 .opc3 = op3, \
587 .pad = { 0, }, \
588 .handler = { \
589 .inval1 = invl1, \
590 .inval2 = invl2, \
591 .type = _typ, \
592 .type2 = _typ2, \
593 .handler = &gen_##name, \
594 }, \
595 .oname = stringify(name), \
596 }
597 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
598 { \
599 .opc1 = op1, \
600 .opc2 = op2, \
601 .opc3 = op3, \
602 .pad = { 0, }, \
603 .handler = { \
604 .inval1 = invl, \
605 .type = _typ, \
606 .type2 = _typ2, \
607 .handler = &gen_##name, \
608 }, \
609 .oname = onam, \
610 }
611 #endif
612
613 /* SPR load/store helpers */
614 static inline void gen_load_spr(TCGv t, int reg)
615 {
616 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
617 }
618
619 static inline void gen_store_spr(int reg, TCGv t)
620 {
621 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
622 }
623
624 /* Invalid instruction */
625 static void gen_invalid(DisasContext *ctx)
626 {
627 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
628 }
629
630 static opc_handler_t invalid_handler = {
631 .inval1 = 0xFFFFFFFF,
632 .inval2 = 0xFFFFFFFF,
633 .type = PPC_NONE,
634 .type2 = PPC_NONE,
635 .handler = gen_invalid,
636 };
637
638 /*** Integer comparison ***/
639
640 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
641 {
642 TCGv t0 = tcg_temp_new();
643 TCGv_i32 t1 = tcg_temp_new_i32();
644
645 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
646
647 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
648 tcg_gen_trunc_tl_i32(t1, t0);
649 tcg_gen_shli_i32(t1, t1, CRF_LT);
650 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
651
652 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
653 tcg_gen_trunc_tl_i32(t1, t0);
654 tcg_gen_shli_i32(t1, t1, CRF_GT);
655 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
656
657 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
658 tcg_gen_trunc_tl_i32(t1, t0);
659 tcg_gen_shli_i32(t1, t1, CRF_EQ);
660 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
661
662 tcg_temp_free(t0);
663 tcg_temp_free_i32(t1);
664 }
665
666 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
667 {
668 TCGv t0 = tcg_const_tl(arg1);
669 gen_op_cmp(arg0, t0, s, crf);
670 tcg_temp_free(t0);
671 }
672
673 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
674 {
675 TCGv t0, t1;
676 t0 = tcg_temp_new();
677 t1 = tcg_temp_new();
678 if (s) {
679 tcg_gen_ext32s_tl(t0, arg0);
680 tcg_gen_ext32s_tl(t1, arg1);
681 } else {
682 tcg_gen_ext32u_tl(t0, arg0);
683 tcg_gen_ext32u_tl(t1, arg1);
684 }
685 gen_op_cmp(t0, t1, s, crf);
686 tcg_temp_free(t1);
687 tcg_temp_free(t0);
688 }
689
690 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
691 {
692 TCGv t0 = tcg_const_tl(arg1);
693 gen_op_cmp32(arg0, t0, s, crf);
694 tcg_temp_free(t0);
695 }
696
697 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
698 {
699 if (NARROW_MODE(ctx)) {
700 gen_op_cmpi32(reg, 0, 1, 0);
701 } else {
702 gen_op_cmpi(reg, 0, 1, 0);
703 }
704 }
705
706 /* cmp */
707 static void gen_cmp(DisasContext *ctx)
708 {
709 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
710 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
711 1, crfD(ctx->opcode));
712 } else {
713 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
714 1, crfD(ctx->opcode));
715 }
716 }
717
718 /* cmpi */
719 static void gen_cmpi(DisasContext *ctx)
720 {
721 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
722 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
723 1, crfD(ctx->opcode));
724 } else {
725 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
726 1, crfD(ctx->opcode));
727 }
728 }
729
730 /* cmpl */
731 static void gen_cmpl(DisasContext *ctx)
732 {
733 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
734 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
735 0, crfD(ctx->opcode));
736 } else {
737 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
738 0, crfD(ctx->opcode));
739 }
740 }
741
742 /* cmpli */
743 static void gen_cmpli(DisasContext *ctx)
744 {
745 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
746 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
747 0, crfD(ctx->opcode));
748 } else {
749 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
750 0, crfD(ctx->opcode));
751 }
752 }
753
754 /* isel (PowerPC 2.03 specification) */
755 static void gen_isel(DisasContext *ctx)
756 {
757 TCGLabel *l1, *l2;
758 uint32_t bi = rC(ctx->opcode);
759 uint32_t mask;
760 TCGv_i32 t0;
761
762 l1 = gen_new_label();
763 l2 = gen_new_label();
764
765 mask = 0x08 >> (bi & 0x03);
766 t0 = tcg_temp_new_i32();
767 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
768 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
769 if (rA(ctx->opcode) == 0)
770 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
771 else
772 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
773 tcg_gen_br(l2);
774 gen_set_label(l1);
775 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
776 gen_set_label(l2);
777 tcg_temp_free_i32(t0);
778 }
779
780 /* cmpb: PowerPC 2.05 specification */
781 static void gen_cmpb(DisasContext *ctx)
782 {
783 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
784 cpu_gpr[rB(ctx->opcode)]);
785 }
786
787 /*** Integer arithmetic ***/
788
789 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
790 TCGv arg1, TCGv arg2, int sub)
791 {
792 TCGv t0 = tcg_temp_new();
793
794 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
795 tcg_gen_xor_tl(t0, arg1, arg2);
796 if (sub) {
797 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
798 } else {
799 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
800 }
801 tcg_temp_free(t0);
802 if (NARROW_MODE(ctx)) {
803 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
804 }
805 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
806 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
807 }
808
809 /* Common add function */
810 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
811 TCGv arg2, bool add_ca, bool compute_ca,
812 bool compute_ov, bool compute_rc0)
813 {
814 TCGv t0 = ret;
815
816 if (compute_ca || compute_ov) {
817 t0 = tcg_temp_new();
818 }
819
820 if (compute_ca) {
821 if (NARROW_MODE(ctx)) {
822 /* Caution: a non-obvious corner case of the spec is that we
823 must produce the *entire* 64-bit addition, but produce the
824 carry into bit 32. */
825 TCGv t1 = tcg_temp_new();
826 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
827 tcg_gen_add_tl(t0, arg1, arg2);
828 if (add_ca) {
829 tcg_gen_add_tl(t0, t0, cpu_ca);
830 }
831 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
832 tcg_temp_free(t1);
833 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
834 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
835 } else {
836 TCGv zero = tcg_const_tl(0);
837 if (add_ca) {
838 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
839 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
840 } else {
841 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
842 }
843 tcg_temp_free(zero);
844 }
845 } else {
846 tcg_gen_add_tl(t0, arg1, arg2);
847 if (add_ca) {
848 tcg_gen_add_tl(t0, t0, cpu_ca);
849 }
850 }
851
852 if (compute_ov) {
853 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
854 }
855 if (unlikely(compute_rc0)) {
856 gen_set_Rc0(ctx, t0);
857 }
858
859 if (!TCGV_EQUAL(t0, ret)) {
860 tcg_gen_mov_tl(ret, t0);
861 tcg_temp_free(t0);
862 }
863 }
864 /* Add functions with two operands */
865 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
866 static void glue(gen_, name)(DisasContext *ctx) \
867 { \
868 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
869 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
870 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
871 }
872 /* Add functions with one operand and one immediate */
873 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
874 add_ca, compute_ca, compute_ov) \
875 static void glue(gen_, name)(DisasContext *ctx) \
876 { \
877 TCGv t0 = tcg_const_tl(const_val); \
878 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
879 cpu_gpr[rA(ctx->opcode)], t0, \
880 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
881 tcg_temp_free(t0); \
882 }
883
884 /* add add. addo addo. */
885 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
886 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
887 /* addc addc. addco addco. */
888 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
889 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
890 /* adde adde. addeo addeo. */
891 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
892 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
893 /* addme addme. addmeo addmeo. */
894 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
895 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
896 /* addze addze. addzeo addzeo.*/
897 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
898 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
899 /* addi */
900 static void gen_addi(DisasContext *ctx)
901 {
902 target_long simm = SIMM(ctx->opcode);
903
904 if (rA(ctx->opcode) == 0) {
905 /* li case */
906 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
907 } else {
908 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
909 cpu_gpr[rA(ctx->opcode)], simm);
910 }
911 }
912 /* addic addic.*/
913 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
914 {
915 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
916 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
917 c, 0, 1, 0, compute_rc0);
918 tcg_temp_free(c);
919 }
920
921 static void gen_addic(DisasContext *ctx)
922 {
923 gen_op_addic(ctx, 0);
924 }
925
926 static void gen_addic_(DisasContext *ctx)
927 {
928 gen_op_addic(ctx, 1);
929 }
930
931 /* addis */
932 static void gen_addis(DisasContext *ctx)
933 {
934 target_long simm = SIMM(ctx->opcode);
935
936 if (rA(ctx->opcode) == 0) {
937 /* lis case */
938 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
939 } else {
940 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
941 cpu_gpr[rA(ctx->opcode)], simm << 16);
942 }
943 }
944
945 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
946 TCGv arg2, int sign, int compute_ov)
947 {
948 TCGLabel *l1 = gen_new_label();
949 TCGLabel *l2 = gen_new_label();
950 TCGv_i32 t0 = tcg_temp_local_new_i32();
951 TCGv_i32 t1 = tcg_temp_local_new_i32();
952
953 tcg_gen_trunc_tl_i32(t0, arg1);
954 tcg_gen_trunc_tl_i32(t1, arg2);
955 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
956 if (sign) {
957 TCGLabel *l3 = gen_new_label();
958 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
959 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
960 gen_set_label(l3);
961 tcg_gen_div_i32(t0, t0, t1);
962 } else {
963 tcg_gen_divu_i32(t0, t0, t1);
964 }
965 if (compute_ov) {
966 tcg_gen_movi_tl(cpu_ov, 0);
967 }
968 tcg_gen_br(l2);
969 gen_set_label(l1);
970 if (sign) {
971 tcg_gen_sari_i32(t0, t0, 31);
972 } else {
973 tcg_gen_movi_i32(t0, 0);
974 }
975 if (compute_ov) {
976 tcg_gen_movi_tl(cpu_ov, 1);
977 tcg_gen_movi_tl(cpu_so, 1);
978 }
979 gen_set_label(l2);
980 tcg_gen_extu_i32_tl(ret, t0);
981 tcg_temp_free_i32(t0);
982 tcg_temp_free_i32(t1);
983 if (unlikely(Rc(ctx->opcode) != 0))
984 gen_set_Rc0(ctx, ret);
985 }
986 /* Div functions */
987 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
988 static void glue(gen_, name)(DisasContext *ctx) \
989 { \
990 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
991 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
992 sign, compute_ov); \
993 }
994 /* divwu divwu. divwuo divwuo. */
995 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
996 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
997 /* divw divw. divwo divwo. */
998 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
999 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1000
1001 /* div[wd]eu[o][.] */
1002 #define GEN_DIVE(name, hlpr, compute_ov) \
1003 static void gen_##name(DisasContext *ctx) \
1004 { \
1005 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1006 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1007 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1008 tcg_temp_free_i32(t0); \
1009 if (unlikely(Rc(ctx->opcode) != 0)) { \
1010 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1011 } \
1012 }
1013
1014 GEN_DIVE(divweu, divweu, 0);
1015 GEN_DIVE(divweuo, divweu, 1);
1016 GEN_DIVE(divwe, divwe, 0);
1017 GEN_DIVE(divweo, divwe, 1);
1018
1019 #if defined(TARGET_PPC64)
1020 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1021 TCGv arg2, int sign, int compute_ov)
1022 {
1023 TCGLabel *l1 = gen_new_label();
1024 TCGLabel *l2 = gen_new_label();
1025
1026 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1027 if (sign) {
1028 TCGLabel *l3 = gen_new_label();
1029 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1030 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1031 gen_set_label(l3);
1032 tcg_gen_div_i64(ret, arg1, arg2);
1033 } else {
1034 tcg_gen_divu_i64(ret, arg1, arg2);
1035 }
1036 if (compute_ov) {
1037 tcg_gen_movi_tl(cpu_ov, 0);
1038 }
1039 tcg_gen_br(l2);
1040 gen_set_label(l1);
1041 if (sign) {
1042 tcg_gen_sari_i64(ret, arg1, 63);
1043 } else {
1044 tcg_gen_movi_i64(ret, 0);
1045 }
1046 if (compute_ov) {
1047 tcg_gen_movi_tl(cpu_ov, 1);
1048 tcg_gen_movi_tl(cpu_so, 1);
1049 }
1050 gen_set_label(l2);
1051 if (unlikely(Rc(ctx->opcode) != 0))
1052 gen_set_Rc0(ctx, ret);
1053 }
1054 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1055 static void glue(gen_, name)(DisasContext *ctx) \
1056 { \
1057 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1058 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1059 sign, compute_ov); \
1060 }
1061 /* divwu divwu. divwuo divwuo. */
1062 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1063 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1064 /* divw divw. divwo divwo. */
1065 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1066 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1067
1068 GEN_DIVE(divdeu, divdeu, 0);
1069 GEN_DIVE(divdeuo, divdeu, 1);
1070 GEN_DIVE(divde, divde, 0);
1071 GEN_DIVE(divdeo, divde, 1);
1072 #endif
1073
1074 /* mulhw mulhw. */
1075 static void gen_mulhw(DisasContext *ctx)
1076 {
1077 TCGv_i32 t0 = tcg_temp_new_i32();
1078 TCGv_i32 t1 = tcg_temp_new_i32();
1079
1080 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1081 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1082 tcg_gen_muls2_i32(t0, t1, t0, t1);
1083 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1084 tcg_temp_free_i32(t0);
1085 tcg_temp_free_i32(t1);
1086 if (unlikely(Rc(ctx->opcode) != 0))
1087 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1088 }
1089
1090 /* mulhwu mulhwu. */
1091 static void gen_mulhwu(DisasContext *ctx)
1092 {
1093 TCGv_i32 t0 = tcg_temp_new_i32();
1094 TCGv_i32 t1 = tcg_temp_new_i32();
1095
1096 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1097 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1098 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1099 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1100 tcg_temp_free_i32(t0);
1101 tcg_temp_free_i32(t1);
1102 if (unlikely(Rc(ctx->opcode) != 0))
1103 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1104 }
1105
1106 /* mullw mullw. */
1107 static void gen_mullw(DisasContext *ctx)
1108 {
1109 #if defined(TARGET_PPC64)
1110 TCGv_i64 t0, t1;
1111 t0 = tcg_temp_new_i64();
1112 t1 = tcg_temp_new_i64();
1113 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1114 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1115 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1116 tcg_temp_free(t0);
1117 tcg_temp_free(t1);
1118 #else
1119 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1120 cpu_gpr[rB(ctx->opcode)]);
1121 #endif
1122 if (unlikely(Rc(ctx->opcode) != 0))
1123 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1124 }
1125
1126 /* mullwo mullwo. */
1127 static void gen_mullwo(DisasContext *ctx)
1128 {
1129 TCGv_i32 t0 = tcg_temp_new_i32();
1130 TCGv_i32 t1 = tcg_temp_new_i32();
1131
1132 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1133 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1134 tcg_gen_muls2_i32(t0, t1, t0, t1);
1135 #if defined(TARGET_PPC64)
1136 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1137 #else
1138 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1139 #endif
1140
1141 tcg_gen_sari_i32(t0, t0, 31);
1142 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1143 tcg_gen_extu_i32_tl(cpu_ov, t0);
1144 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1145
1146 tcg_temp_free_i32(t0);
1147 tcg_temp_free_i32(t1);
1148 if (unlikely(Rc(ctx->opcode) != 0))
1149 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1150 }
1151
1152 /* mulli */
1153 static void gen_mulli(DisasContext *ctx)
1154 {
1155 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1156 SIMM(ctx->opcode));
1157 }
1158
1159 #if defined(TARGET_PPC64)
1160 /* mulhd mulhd. */
1161 static void gen_mulhd(DisasContext *ctx)
1162 {
1163 TCGv lo = tcg_temp_new();
1164 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1165 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1166 tcg_temp_free(lo);
1167 if (unlikely(Rc(ctx->opcode) != 0)) {
1168 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1169 }
1170 }
1171
1172 /* mulhdu mulhdu. */
1173 static void gen_mulhdu(DisasContext *ctx)
1174 {
1175 TCGv lo = tcg_temp_new();
1176 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1177 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1178 tcg_temp_free(lo);
1179 if (unlikely(Rc(ctx->opcode) != 0)) {
1180 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1181 }
1182 }
1183
1184 /* mulld mulld. */
1185 static void gen_mulld(DisasContext *ctx)
1186 {
1187 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1188 cpu_gpr[rB(ctx->opcode)]);
1189 if (unlikely(Rc(ctx->opcode) != 0))
1190 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1191 }
1192
1193 /* mulldo mulldo. */
1194 static void gen_mulldo(DisasContext *ctx)
1195 {
1196 TCGv_i64 t0 = tcg_temp_new_i64();
1197 TCGv_i64 t1 = tcg_temp_new_i64();
1198
1199 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1200 cpu_gpr[rB(ctx->opcode)]);
1201 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1202
1203 tcg_gen_sari_i64(t0, t0, 63);
1204 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1205 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1206
1207 tcg_temp_free_i64(t0);
1208 tcg_temp_free_i64(t1);
1209
1210 if (unlikely(Rc(ctx->opcode) != 0)) {
1211 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1212 }
1213 }
1214 #endif
1215
1216 /* Common subf function */
1217 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1218 TCGv arg2, bool add_ca, bool compute_ca,
1219 bool compute_ov, bool compute_rc0)
1220 {
1221 TCGv t0 = ret;
1222
1223 if (compute_ca || compute_ov) {
1224 t0 = tcg_temp_new();
1225 }
1226
1227 if (compute_ca) {
1228 /* dest = ~arg1 + arg2 [+ ca]. */
1229 if (NARROW_MODE(ctx)) {
1230 /* Caution: a non-obvious corner case of the spec is that we
1231 must produce the *entire* 64-bit addition, but produce the
1232 carry into bit 32. */
1233 TCGv inv1 = tcg_temp_new();
1234 TCGv t1 = tcg_temp_new();
1235 tcg_gen_not_tl(inv1, arg1);
1236 if (add_ca) {
1237 tcg_gen_add_tl(t0, arg2, cpu_ca);
1238 } else {
1239 tcg_gen_addi_tl(t0, arg2, 1);
1240 }
1241 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1242 tcg_gen_add_tl(t0, t0, inv1);
1243 tcg_temp_free(inv1);
1244 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1245 tcg_temp_free(t1);
1246 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1247 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1248 } else if (add_ca) {
1249 TCGv zero, inv1 = tcg_temp_new();
1250 tcg_gen_not_tl(inv1, arg1);
1251 zero = tcg_const_tl(0);
1252 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1253 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1254 tcg_temp_free(zero);
1255 tcg_temp_free(inv1);
1256 } else {
1257 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1258 tcg_gen_sub_tl(t0, arg2, arg1);
1259 }
1260 } else if (add_ca) {
1261 /* Since we're ignoring carry-out, we can simplify the
1262 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1263 tcg_gen_sub_tl(t0, arg2, arg1);
1264 tcg_gen_add_tl(t0, t0, cpu_ca);
1265 tcg_gen_subi_tl(t0, t0, 1);
1266 } else {
1267 tcg_gen_sub_tl(t0, arg2, arg1);
1268 }
1269
1270 if (compute_ov) {
1271 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1272 }
1273 if (unlikely(compute_rc0)) {
1274 gen_set_Rc0(ctx, t0);
1275 }
1276
1277 if (!TCGV_EQUAL(t0, ret)) {
1278 tcg_gen_mov_tl(ret, t0);
1279 tcg_temp_free(t0);
1280 }
1281 }
1282 /* Sub functions with Two operands functions */
1283 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1284 static void glue(gen_, name)(DisasContext *ctx) \
1285 { \
1286 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1287 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1288 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1289 }
1290 /* Sub functions with one operand and one immediate */
1291 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1292 add_ca, compute_ca, compute_ov) \
1293 static void glue(gen_, name)(DisasContext *ctx) \
1294 { \
1295 TCGv t0 = tcg_const_tl(const_val); \
1296 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1297 cpu_gpr[rA(ctx->opcode)], t0, \
1298 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1299 tcg_temp_free(t0); \
1300 }
1301 /* subf subf. subfo subfo. */
1302 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1303 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1304 /* subfc subfc. subfco subfco. */
1305 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1306 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1307 /* subfe subfe. subfeo subfo. */
1308 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1309 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1310 /* subfme subfme. subfmeo subfmeo. */
1311 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1312 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1313 /* subfze subfze. subfzeo subfzeo.*/
1314 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1315 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1316
1317 /* subfic */
1318 static void gen_subfic(DisasContext *ctx)
1319 {
1320 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1321 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1322 c, 0, 1, 0, 0);
1323 tcg_temp_free(c);
1324 }
1325
1326 /* neg neg. nego nego. */
1327 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1328 {
1329 TCGv zero = tcg_const_tl(0);
1330 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1331 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1332 tcg_temp_free(zero);
1333 }
1334
1335 static void gen_neg(DisasContext *ctx)
1336 {
1337 gen_op_arith_neg(ctx, 0);
1338 }
1339
1340 static void gen_nego(DisasContext *ctx)
1341 {
1342 gen_op_arith_neg(ctx, 1);
1343 }
1344
1345 /*** Integer logical ***/
1346 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1347 static void glue(gen_, name)(DisasContext *ctx) \
1348 { \
1349 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1350 cpu_gpr[rB(ctx->opcode)]); \
1351 if (unlikely(Rc(ctx->opcode) != 0)) \
1352 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1353 }
1354
1355 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1356 static void glue(gen_, name)(DisasContext *ctx) \
1357 { \
1358 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1359 if (unlikely(Rc(ctx->opcode) != 0)) \
1360 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1361 }
1362
1363 /* and & and. */
1364 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1365 /* andc & andc. */
1366 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1367
1368 /* andi. */
1369 static void gen_andi_(DisasContext *ctx)
1370 {
1371 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1372 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1373 }
1374
1375 /* andis. */
1376 static void gen_andis_(DisasContext *ctx)
1377 {
1378 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1379 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1380 }
1381
1382 /* cntlzw */
1383 static void gen_cntlzw(DisasContext *ctx)
1384 {
1385 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1386 if (unlikely(Rc(ctx->opcode) != 0))
1387 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1388 }
1389 /* eqv & eqv. */
1390 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1391 /* extsb & extsb. */
1392 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1393 /* extsh & extsh. */
1394 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1395 /* nand & nand. */
1396 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1397 /* nor & nor. */
1398 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1399
1400 /* or & or. */
1401 static void gen_or(DisasContext *ctx)
1402 {
1403 int rs, ra, rb;
1404
1405 rs = rS(ctx->opcode);
1406 ra = rA(ctx->opcode);
1407 rb = rB(ctx->opcode);
1408 /* Optimisation for mr. ri case */
1409 if (rs != ra || rs != rb) {
1410 if (rs != rb)
1411 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1412 else
1413 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1414 if (unlikely(Rc(ctx->opcode) != 0))
1415 gen_set_Rc0(ctx, cpu_gpr[ra]);
1416 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1417 gen_set_Rc0(ctx, cpu_gpr[rs]);
1418 #if defined(TARGET_PPC64)
1419 } else {
1420 int prio = 0;
1421
1422 switch (rs) {
1423 case 1:
1424 /* Set process priority to low */
1425 prio = 2;
1426 break;
1427 case 6:
1428 /* Set process priority to medium-low */
1429 prio = 3;
1430 break;
1431 case 2:
1432 /* Set process priority to normal */
1433 prio = 4;
1434 break;
1435 #if !defined(CONFIG_USER_ONLY)
1436 case 31:
1437 if (!ctx->pr) {
1438 /* Set process priority to very low */
1439 prio = 1;
1440 }
1441 break;
1442 case 5:
1443 if (!ctx->pr) {
1444 /* Set process priority to medium-hight */
1445 prio = 5;
1446 }
1447 break;
1448 case 3:
1449 if (!ctx->pr) {
1450 /* Set process priority to high */
1451 prio = 6;
1452 }
1453 break;
1454 case 7:
1455 if (ctx->hv) {
1456 /* Set process priority to very high */
1457 prio = 7;
1458 }
1459 break;
1460 #endif
1461 default:
1462 /* nop */
1463 break;
1464 }
1465 if (prio) {
1466 TCGv t0 = tcg_temp_new();
1467 gen_load_spr(t0, SPR_PPR);
1468 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1469 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1470 gen_store_spr(SPR_PPR, t0);
1471 tcg_temp_free(t0);
1472 }
1473 #endif
1474 }
1475 }
1476 /* orc & orc. */
1477 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1478
1479 /* xor & xor. */
1480 static void gen_xor(DisasContext *ctx)
1481 {
1482 /* Optimisation for "set to zero" case */
1483 if (rS(ctx->opcode) != rB(ctx->opcode))
1484 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1485 else
1486 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1487 if (unlikely(Rc(ctx->opcode) != 0))
1488 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1489 }
1490
1491 /* ori */
1492 static void gen_ori(DisasContext *ctx)
1493 {
1494 target_ulong uimm = UIMM(ctx->opcode);
1495
1496 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1497 /* NOP */
1498 /* XXX: should handle special NOPs for POWER series */
1499 return;
1500 }
1501 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1502 }
1503
1504 /* oris */
1505 static void gen_oris(DisasContext *ctx)
1506 {
1507 target_ulong uimm = UIMM(ctx->opcode);
1508
1509 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1510 /* NOP */
1511 return;
1512 }
1513 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1514 }
1515
1516 /* xori */
1517 static void gen_xori(DisasContext *ctx)
1518 {
1519 target_ulong uimm = UIMM(ctx->opcode);
1520
1521 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1522 /* NOP */
1523 return;
1524 }
1525 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1526 }
1527
1528 /* xoris */
1529 static void gen_xoris(DisasContext *ctx)
1530 {
1531 target_ulong uimm = UIMM(ctx->opcode);
1532
1533 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1534 /* NOP */
1535 return;
1536 }
1537 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1538 }
1539
1540 /* popcntb : PowerPC 2.03 specification */
1541 static void gen_popcntb(DisasContext *ctx)
1542 {
1543 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1544 }
1545
1546 static void gen_popcntw(DisasContext *ctx)
1547 {
1548 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1549 }
1550
1551 #if defined(TARGET_PPC64)
1552 /* popcntd: PowerPC 2.06 specification */
1553 static void gen_popcntd(DisasContext *ctx)
1554 {
1555 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1556 }
1557 #endif
1558
1559 /* prtyw: PowerPC 2.05 specification */
1560 static void gen_prtyw(DisasContext *ctx)
1561 {
1562 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1563 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1564 TCGv t0 = tcg_temp_new();
1565 tcg_gen_shri_tl(t0, rs, 16);
1566 tcg_gen_xor_tl(ra, rs, t0);
1567 tcg_gen_shri_tl(t0, ra, 8);
1568 tcg_gen_xor_tl(ra, ra, t0);
1569 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1570 tcg_temp_free(t0);
1571 }
1572
1573 #if defined(TARGET_PPC64)
1574 /* prtyd: PowerPC 2.05 specification */
1575 static void gen_prtyd(DisasContext *ctx)
1576 {
1577 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1578 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1579 TCGv t0 = tcg_temp_new();
1580 tcg_gen_shri_tl(t0, rs, 32);
1581 tcg_gen_xor_tl(ra, rs, t0);
1582 tcg_gen_shri_tl(t0, ra, 16);
1583 tcg_gen_xor_tl(ra, ra, t0);
1584 tcg_gen_shri_tl(t0, ra, 8);
1585 tcg_gen_xor_tl(ra, ra, t0);
1586 tcg_gen_andi_tl(ra, ra, 1);
1587 tcg_temp_free(t0);
1588 }
1589 #endif
1590
1591 #if defined(TARGET_PPC64)
1592 /* bpermd */
1593 static void gen_bpermd(DisasContext *ctx)
1594 {
1595 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1596 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1597 }
1598 #endif
1599
1600 #if defined(TARGET_PPC64)
1601 /* extsw & extsw. */
1602 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1603
1604 /* cntlzd */
1605 static void gen_cntlzd(DisasContext *ctx)
1606 {
1607 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1608 if (unlikely(Rc(ctx->opcode) != 0))
1609 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1610 }
1611 #endif
1612
1613 /*** Integer rotate ***/
1614
1615 /* rlwimi & rlwimi. */
1616 static void gen_rlwimi(DisasContext *ctx)
1617 {
1618 uint32_t mb, me, sh;
1619
1620 mb = MB(ctx->opcode);
1621 me = ME(ctx->opcode);
1622 sh = SH(ctx->opcode);
1623 if (likely(sh == (31-me) && mb <= me)) {
1624 tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1625 cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
1626 } else {
1627 target_ulong mask;
1628 TCGv t1;
1629 TCGv t0 = tcg_temp_new();
1630 #if defined(TARGET_PPC64)
1631 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1632 cpu_gpr[rS(ctx->opcode)], 32, 32);
1633 tcg_gen_rotli_i64(t0, t0, sh);
1634 #else
1635 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1636 #endif
1637 #if defined(TARGET_PPC64)
1638 mb += 32;
1639 me += 32;
1640 #endif
1641 mask = MASK(mb, me);
1642 t1 = tcg_temp_new();
1643 tcg_gen_andi_tl(t0, t0, mask);
1644 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1645 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1646 tcg_temp_free(t0);
1647 tcg_temp_free(t1);
1648 }
1649 if (unlikely(Rc(ctx->opcode) != 0))
1650 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1651 }
1652
1653 /* rlwinm & rlwinm. */
1654 static void gen_rlwinm(DisasContext *ctx)
1655 {
1656 uint32_t mb, me, sh;
1657
1658 sh = SH(ctx->opcode);
1659 mb = MB(ctx->opcode);
1660 me = ME(ctx->opcode);
1661
1662 if (likely(mb == 0 && me == (31 - sh))) {
1663 if (likely(sh == 0)) {
1664 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1665 } else {
1666 TCGv t0 = tcg_temp_new();
1667 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1668 tcg_gen_shli_tl(t0, t0, sh);
1669 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1670 tcg_temp_free(t0);
1671 }
1672 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1673 TCGv t0 = tcg_temp_new();
1674 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1675 tcg_gen_shri_tl(t0, t0, mb);
1676 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1677 tcg_temp_free(t0);
1678 } else if (likely(mb == 0 && me == 31)) {
1679 TCGv_i32 t0 = tcg_temp_new_i32();
1680 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
1681 tcg_gen_rotli_i32(t0, t0, sh);
1682 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
1683 tcg_temp_free_i32(t0);
1684 } else {
1685 TCGv t0 = tcg_temp_new();
1686 #if defined(TARGET_PPC64)
1687 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1688 cpu_gpr[rS(ctx->opcode)], 32, 32);
1689 tcg_gen_rotli_i64(t0, t0, sh);
1690 #else
1691 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1692 #endif
1693 #if defined(TARGET_PPC64)
1694 mb += 32;
1695 me += 32;
1696 #endif
1697 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1698 tcg_temp_free(t0);
1699 }
1700 if (unlikely(Rc(ctx->opcode) != 0))
1701 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1702 }
1703
1704 /* rlwnm & rlwnm. */
1705 static void gen_rlwnm(DisasContext *ctx)
1706 {
1707 uint32_t mb, me;
1708 mb = MB(ctx->opcode);
1709 me = ME(ctx->opcode);
1710
1711 if (likely(mb == 0 && me == 31)) {
1712 TCGv_i32 t0, t1;
1713 t0 = tcg_temp_new_i32();
1714 t1 = tcg_temp_new_i32();
1715 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
1716 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1717 tcg_gen_andi_i32(t0, t0, 0x1f);
1718 tcg_gen_rotl_i32(t1, t1, t0);
1719 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
1720 tcg_temp_free_i32(t0);
1721 tcg_temp_free_i32(t1);
1722 } else {
1723 TCGv t0;
1724 #if defined(TARGET_PPC64)
1725 TCGv t1;
1726 #endif
1727
1728 t0 = tcg_temp_new();
1729 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1730 #if defined(TARGET_PPC64)
1731 t1 = tcg_temp_new_i64();
1732 tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
1733 cpu_gpr[rS(ctx->opcode)], 32, 32);
1734 tcg_gen_rotl_i64(t0, t1, t0);
1735 tcg_temp_free_i64(t1);
1736 #else
1737 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1738 #endif
1739 if (unlikely(mb != 0 || me != 31)) {
1740 #if defined(TARGET_PPC64)
1741 mb += 32;
1742 me += 32;
1743 #endif
1744 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1745 } else {
1746 tcg_gen_andi_tl(t0, t0, MASK(32, 63));
1747 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1748 }
1749 tcg_temp_free(t0);
1750 }
1751 if (unlikely(Rc(ctx->opcode) != 0))
1752 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1753 }
1754
1755 #if defined(TARGET_PPC64)
1756 #define GEN_PPC64_R2(name, opc1, opc2) \
1757 static void glue(gen_, name##0)(DisasContext *ctx) \
1758 { \
1759 gen_##name(ctx, 0); \
1760 } \
1761 \
1762 static void glue(gen_, name##1)(DisasContext *ctx) \
1763 { \
1764 gen_##name(ctx, 1); \
1765 }
1766 #define GEN_PPC64_R4(name, opc1, opc2) \
1767 static void glue(gen_, name##0)(DisasContext *ctx) \
1768 { \
1769 gen_##name(ctx, 0, 0); \
1770 } \
1771 \
1772 static void glue(gen_, name##1)(DisasContext *ctx) \
1773 { \
1774 gen_##name(ctx, 0, 1); \
1775 } \
1776 \
1777 static void glue(gen_, name##2)(DisasContext *ctx) \
1778 { \
1779 gen_##name(ctx, 1, 0); \
1780 } \
1781 \
1782 static void glue(gen_, name##3)(DisasContext *ctx) \
1783 { \
1784 gen_##name(ctx, 1, 1); \
1785 }
1786
1787 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1788 uint32_t sh)
1789 {
1790 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1791 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1792 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1793 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1794 } else {
1795 TCGv t0 = tcg_temp_new();
1796 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1797 if (likely(mb == 0 && me == 63)) {
1798 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1799 } else {
1800 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1801 }
1802 tcg_temp_free(t0);
1803 }
1804 if (unlikely(Rc(ctx->opcode) != 0))
1805 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1806 }
1807 /* rldicl - rldicl. */
1808 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1809 {
1810 uint32_t sh, mb;
1811
1812 sh = SH(ctx->opcode) | (shn << 5);
1813 mb = MB(ctx->opcode) | (mbn << 5);
1814 gen_rldinm(ctx, mb, 63, sh);
1815 }
1816 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1817 /* rldicr - rldicr. */
1818 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1819 {
1820 uint32_t sh, me;
1821
1822 sh = SH(ctx->opcode) | (shn << 5);
1823 me = MB(ctx->opcode) | (men << 5);
1824 gen_rldinm(ctx, 0, me, sh);
1825 }
1826 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1827 /* rldic - rldic. */
1828 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1829 {
1830 uint32_t sh, mb;
1831
1832 sh = SH(ctx->opcode) | (shn << 5);
1833 mb = MB(ctx->opcode) | (mbn << 5);
1834 gen_rldinm(ctx, mb, 63 - sh, sh);
1835 }
1836 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1837
1838 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1839 {
1840 TCGv t0;
1841
1842 t0 = tcg_temp_new();
1843 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1844 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1845 if (unlikely(mb != 0 || me != 63)) {
1846 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1847 } else {
1848 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1849 }
1850 tcg_temp_free(t0);
1851 if (unlikely(Rc(ctx->opcode) != 0))
1852 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1853 }
1854
1855 /* rldcl - rldcl. */
1856 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1857 {
1858 uint32_t mb;
1859
1860 mb = MB(ctx->opcode) | (mbn << 5);
1861 gen_rldnm(ctx, mb, 63);
1862 }
1863 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1864 /* rldcr - rldcr. */
1865 static inline void gen_rldcr(DisasContext *ctx, int men)
1866 {
1867 uint32_t me;
1868
1869 me = MB(ctx->opcode) | (men << 5);
1870 gen_rldnm(ctx, 0, me);
1871 }
1872 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1873 /* rldimi - rldimi. */
1874 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1875 {
1876 uint32_t sh, mb, me;
1877
1878 sh = SH(ctx->opcode) | (shn << 5);
1879 mb = MB(ctx->opcode) | (mbn << 5);
1880 me = 63 - sh;
1881 if (unlikely(sh == 0 && mb == 0)) {
1882 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1883 } else {
1884 TCGv t0, t1;
1885 target_ulong mask;
1886
1887 t0 = tcg_temp_new();
1888 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1889 t1 = tcg_temp_new();
1890 mask = MASK(mb, me);
1891 tcg_gen_andi_tl(t0, t0, mask);
1892 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1893 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1894 tcg_temp_free(t0);
1895 tcg_temp_free(t1);
1896 }
1897 if (unlikely(Rc(ctx->opcode) != 0))
1898 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1899 }
1900 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1901 #endif
1902
1903 /*** Integer shift ***/
1904
1905 /* slw & slw. */
1906 static void gen_slw(DisasContext *ctx)
1907 {
1908 TCGv t0, t1;
1909
1910 t0 = tcg_temp_new();
1911 /* AND rS with a mask that is 0 when rB >= 0x20 */
1912 #if defined(TARGET_PPC64)
1913 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1914 tcg_gen_sari_tl(t0, t0, 0x3f);
1915 #else
1916 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1917 tcg_gen_sari_tl(t0, t0, 0x1f);
1918 #endif
1919 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1920 t1 = tcg_temp_new();
1921 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1922 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1923 tcg_temp_free(t1);
1924 tcg_temp_free(t0);
1925 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1926 if (unlikely(Rc(ctx->opcode) != 0))
1927 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1928 }
1929
1930 /* sraw & sraw. */
1931 static void gen_sraw(DisasContext *ctx)
1932 {
1933 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1934 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1935 if (unlikely(Rc(ctx->opcode) != 0))
1936 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1937 }
1938
1939 /* srawi & srawi. */
1940 static void gen_srawi(DisasContext *ctx)
1941 {
1942 int sh = SH(ctx->opcode);
1943 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1944 TCGv src = cpu_gpr[rS(ctx->opcode)];
1945 if (sh == 0) {
1946 tcg_gen_ext32s_tl(dst, src);
1947 tcg_gen_movi_tl(cpu_ca, 0);
1948 } else {
1949 TCGv t0;
1950 tcg_gen_ext32s_tl(dst, src);
1951 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1952 t0 = tcg_temp_new();
1953 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1954 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1955 tcg_temp_free(t0);
1956 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1957 tcg_gen_sari_tl(dst, dst, sh);
1958 }
1959 if (unlikely(Rc(ctx->opcode) != 0)) {
1960 gen_set_Rc0(ctx, dst);
1961 }
1962 }
1963
1964 /* srw & srw. */
1965 static void gen_srw(DisasContext *ctx)
1966 {
1967 TCGv t0, t1;
1968
1969 t0 = tcg_temp_new();
1970 /* AND rS with a mask that is 0 when rB >= 0x20 */
1971 #if defined(TARGET_PPC64)
1972 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1973 tcg_gen_sari_tl(t0, t0, 0x3f);
1974 #else
1975 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1976 tcg_gen_sari_tl(t0, t0, 0x1f);
1977 #endif
1978 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1979 tcg_gen_ext32u_tl(t0, t0);
1980 t1 = tcg_temp_new();
1981 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1982 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1983 tcg_temp_free(t1);
1984 tcg_temp_free(t0);
1985 if (unlikely(Rc(ctx->opcode) != 0))
1986 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1987 }
1988
1989 #if defined(TARGET_PPC64)
1990 /* sld & sld. */
1991 static void gen_sld(DisasContext *ctx)
1992 {
1993 TCGv t0, t1;
1994
1995 t0 = tcg_temp_new();
1996 /* AND rS with a mask that is 0 when rB >= 0x40 */
1997 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1998 tcg_gen_sari_tl(t0, t0, 0x3f);
1999 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2000 t1 = tcg_temp_new();
2001 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2002 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2003 tcg_temp_free(t1);
2004 tcg_temp_free(t0);
2005 if (unlikely(Rc(ctx->opcode) != 0))
2006 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2007 }
2008
2009 /* srad & srad. */
2010 static void gen_srad(DisasContext *ctx)
2011 {
2012 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2013 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2014 if (unlikely(Rc(ctx->opcode) != 0))
2015 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2016 }
2017 /* sradi & sradi. */
2018 static inline void gen_sradi(DisasContext *ctx, int n)
2019 {
2020 int sh = SH(ctx->opcode) + (n << 5);
2021 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2022 TCGv src = cpu_gpr[rS(ctx->opcode)];
2023 if (sh == 0) {
2024 tcg_gen_mov_tl(dst, src);
2025 tcg_gen_movi_tl(cpu_ca, 0);
2026 } else {
2027 TCGv t0;
2028 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2029 t0 = tcg_temp_new();
2030 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2031 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2032 tcg_temp_free(t0);
2033 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2034 tcg_gen_sari_tl(dst, src, sh);
2035 }
2036 if (unlikely(Rc(ctx->opcode) != 0)) {
2037 gen_set_Rc0(ctx, dst);
2038 }
2039 }
2040
2041 static void gen_sradi0(DisasContext *ctx)
2042 {
2043 gen_sradi(ctx, 0);
2044 }
2045
2046 static void gen_sradi1(DisasContext *ctx)
2047 {
2048 gen_sradi(ctx, 1);
2049 }
2050
2051 /* srd & srd. */
2052 static void gen_srd(DisasContext *ctx)
2053 {
2054 TCGv t0, t1;
2055
2056 t0 = tcg_temp_new();
2057 /* AND rS with a mask that is 0 when rB >= 0x40 */
2058 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2059 tcg_gen_sari_tl(t0, t0, 0x3f);
2060 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2061 t1 = tcg_temp_new();
2062 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2063 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2064 tcg_temp_free(t1);
2065 tcg_temp_free(t0);
2066 if (unlikely(Rc(ctx->opcode) != 0))
2067 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2068 }
2069 #endif
2070
2071 #if defined(TARGET_PPC64)
2072 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2073 {
2074 TCGv_i32 tmp = tcg_temp_new_i32();
2075 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2076 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2077 tcg_temp_free_i32(tmp);
2078 }
2079 #else
2080 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2081 {
2082 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2083 }
2084 #endif
2085
2086 /*** Floating-Point arithmetic ***/
2087 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2088 static void gen_f##name(DisasContext *ctx) \
2089 { \
2090 if (unlikely(!ctx->fpu_enabled)) { \
2091 gen_exception(ctx, POWERPC_EXCP_FPU); \
2092 return; \
2093 } \
2094 /* NIP cannot be restored if the memory exception comes from an helper */ \
2095 gen_update_nip(ctx, ctx->nip - 4); \
2096 gen_reset_fpstatus(); \
2097 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2098 cpu_fpr[rA(ctx->opcode)], \
2099 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2100 if (isfloat) { \
2101 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2102 cpu_fpr[rD(ctx->opcode)]); \
2103 } \
2104 if (set_fprf) { \
2105 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2106 } \
2107 if (unlikely(Rc(ctx->opcode) != 0)) { \
2108 gen_set_cr1_from_fpscr(ctx); \
2109 } \
2110 }
2111
2112 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2113 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2114 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2115
2116 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2117 static void gen_f##name(DisasContext *ctx) \
2118 { \
2119 if (unlikely(!ctx->fpu_enabled)) { \
2120 gen_exception(ctx, POWERPC_EXCP_FPU); \
2121 return; \
2122 } \
2123 /* NIP cannot be restored if the memory exception comes from an helper */ \
2124 gen_update_nip(ctx, ctx->nip - 4); \
2125 gen_reset_fpstatus(); \
2126 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2127 cpu_fpr[rA(ctx->opcode)], \
2128 cpu_fpr[rB(ctx->opcode)]); \
2129 if (isfloat) { \
2130 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2131 cpu_fpr[rD(ctx->opcode)]); \
2132 } \
2133 if (set_fprf) { \
2134 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2135 } \
2136 if (unlikely(Rc(ctx->opcode) != 0)) { \
2137 gen_set_cr1_from_fpscr(ctx); \
2138 } \
2139 }
2140 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2141 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2142 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2143
2144 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2145 static void gen_f##name(DisasContext *ctx) \
2146 { \
2147 if (unlikely(!ctx->fpu_enabled)) { \
2148 gen_exception(ctx, POWERPC_EXCP_FPU); \
2149 return; \
2150 } \
2151 /* NIP cannot be restored if the memory exception comes from an helper */ \
2152 gen_update_nip(ctx, ctx->nip - 4); \
2153 gen_reset_fpstatus(); \
2154 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2155 cpu_fpr[rA(ctx->opcode)], \
2156 cpu_fpr[rC(ctx->opcode)]); \
2157 if (isfloat) { \
2158 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2159 cpu_fpr[rD(ctx->opcode)]); \
2160 } \
2161 if (set_fprf) { \
2162 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2163 } \
2164 if (unlikely(Rc(ctx->opcode) != 0)) { \
2165 gen_set_cr1_from_fpscr(ctx); \
2166 } \
2167 }
2168 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2169 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2170 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2171
2172 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2173 static void gen_f##name(DisasContext *ctx) \
2174 { \
2175 if (unlikely(!ctx->fpu_enabled)) { \
2176 gen_exception(ctx, POWERPC_EXCP_FPU); \
2177 return; \
2178 } \
2179 /* NIP cannot be restored if the memory exception comes from an helper */ \
2180 gen_update_nip(ctx, ctx->nip - 4); \
2181 gen_reset_fpstatus(); \
2182 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2183 cpu_fpr[rB(ctx->opcode)]); \
2184 if (set_fprf) { \
2185 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2186 } \
2187 if (unlikely(Rc(ctx->opcode) != 0)) { \
2188 gen_set_cr1_from_fpscr(ctx); \
2189 } \
2190 }
2191
2192 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2193 static void gen_f##name(DisasContext *ctx) \
2194 { \
2195 if (unlikely(!ctx->fpu_enabled)) { \
2196 gen_exception(ctx, POWERPC_EXCP_FPU); \
2197 return; \
2198 } \
2199 /* NIP cannot be restored if the memory exception comes from an helper */ \
2200 gen_update_nip(ctx, ctx->nip - 4); \
2201 gen_reset_fpstatus(); \
2202 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2203 cpu_fpr[rB(ctx->opcode)]); \
2204 if (set_fprf) { \
2205 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2206 } \
2207 if (unlikely(Rc(ctx->opcode) != 0)) { \
2208 gen_set_cr1_from_fpscr(ctx); \
2209 } \
2210 }
2211
2212 /* fadd - fadds */
2213 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2214 /* fdiv - fdivs */
2215 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2216 /* fmul - fmuls */
2217 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2218
2219 /* fre */
2220 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2221
2222 /* fres */
2223 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2224
2225 /* frsqrte */
2226 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2227
2228 /* frsqrtes */
2229 static void gen_frsqrtes(DisasContext *ctx)
2230 {
2231 if (unlikely(!ctx->fpu_enabled)) {
2232 gen_exception(ctx, POWERPC_EXCP_FPU);
2233 return;
2234 }
2235 /* NIP cannot be restored if the memory exception comes from an helper */
2236 gen_update_nip(ctx, ctx->nip - 4);
2237 gen_reset_fpstatus();
2238 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2239 cpu_fpr[rB(ctx->opcode)]);
2240 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2241 cpu_fpr[rD(ctx->opcode)]);
2242 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2243 if (unlikely(Rc(ctx->opcode) != 0)) {
2244 gen_set_cr1_from_fpscr(ctx);
2245 }
2246 }
2247
2248 /* fsel */
2249 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2250 /* fsub - fsubs */
2251 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2252 /* Optional: */
2253
2254 /* fsqrt */
2255 static void gen_fsqrt(DisasContext *ctx)
2256 {
2257 if (unlikely(!ctx->fpu_enabled)) {
2258 gen_exception(ctx, POWERPC_EXCP_FPU);
2259 return;
2260 }
2261 /* NIP cannot be restored if the memory exception comes from an helper */
2262 gen_update_nip(ctx, ctx->nip - 4);
2263 gen_reset_fpstatus();
2264 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2265 cpu_fpr[rB(ctx->opcode)]);
2266 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2267 if (unlikely(Rc(ctx->opcode) != 0)) {
2268 gen_set_cr1_from_fpscr(ctx);
2269 }
2270 }
2271
2272 static void gen_fsqrts(DisasContext *ctx)
2273 {
2274 if (unlikely(!ctx->fpu_enabled)) {
2275 gen_exception(ctx, POWERPC_EXCP_FPU);
2276 return;
2277 }
2278 /* NIP cannot be restored if the memory exception comes from an helper */
2279 gen_update_nip(ctx, ctx->nip - 4);
2280 gen_reset_fpstatus();
2281 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2282 cpu_fpr[rB(ctx->opcode)]);
2283 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2284 cpu_fpr[rD(ctx->opcode)]);
2285 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2286 if (unlikely(Rc(ctx->opcode) != 0)) {
2287 gen_set_cr1_from_fpscr(ctx);
2288 }
2289 }
2290
2291 /*** Floating-Point multiply-and-add ***/
2292 /* fmadd - fmadds */
2293 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2294 /* fmsub - fmsubs */
2295 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2296 /* fnmadd - fnmadds */
2297 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2298 /* fnmsub - fnmsubs */
2299 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2300
2301 /*** Floating-Point round & convert ***/
2302 /* fctiw */
2303 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2304 /* fctiwu */
2305 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2306 /* fctiwz */
2307 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2308 /* fctiwuz */
2309 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2310 /* frsp */
2311 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2312 /* fcfid */
2313 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2314 /* fcfids */
2315 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2316 /* fcfidu */
2317 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2318 /* fcfidus */
2319 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2320 /* fctid */
2321 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2322 /* fctidu */
2323 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2324 /* fctidz */
2325 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2326 /* fctidu */
2327 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2328
2329 /* frin */
2330 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2331 /* friz */
2332 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2333 /* frip */
2334 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2335 /* frim */
2336 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2337
2338 static void gen_ftdiv(DisasContext *ctx)
2339 {
2340 if (unlikely(!ctx->fpu_enabled)) {
2341 gen_exception(ctx, POWERPC_EXCP_FPU);
2342 return;
2343 }
2344 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2345 cpu_fpr[rB(ctx->opcode)]);
2346 }
2347
2348 static void gen_ftsqrt(DisasContext *ctx)
2349 {
2350 if (unlikely(!ctx->fpu_enabled)) {
2351 gen_exception(ctx, POWERPC_EXCP_FPU);
2352 return;
2353 }
2354 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2355 }
2356
2357
2358
2359 /*** Floating-Point compare ***/
2360
2361 /* fcmpo */
2362 static void gen_fcmpo(DisasContext *ctx)
2363 {
2364 TCGv_i32 crf;
2365 if (unlikely(!ctx->fpu_enabled)) {
2366 gen_exception(ctx, POWERPC_EXCP_FPU);
2367 return;
2368 }
2369 /* NIP cannot be restored if the memory exception comes from an helper */
2370 gen_update_nip(ctx, ctx->nip - 4);
2371 gen_reset_fpstatus();
2372 crf = tcg_const_i32(crfD(ctx->opcode));
2373 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2374 cpu_fpr[rB(ctx->opcode)], crf);
2375 tcg_temp_free_i32(crf);
2376 gen_helper_float_check_status(cpu_env);
2377 }
2378
2379 /* fcmpu */
2380 static void gen_fcmpu(DisasContext *ctx)
2381 {
2382 TCGv_i32 crf;
2383 if (unlikely(!ctx->fpu_enabled)) {
2384 gen_exception(ctx, POWERPC_EXCP_FPU);
2385 return;
2386 }
2387 /* NIP cannot be restored if the memory exception comes from an helper */
2388 gen_update_nip(ctx, ctx->nip - 4);
2389 gen_reset_fpstatus();
2390 crf = tcg_const_i32(crfD(ctx->opcode));
2391 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2392 cpu_fpr[rB(ctx->opcode)], crf);
2393 tcg_temp_free_i32(crf);
2394 gen_helper_float_check_status(cpu_env);
2395 }
2396
2397 /*** Floating-point move ***/
2398 /* fabs */
2399 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2400 static void gen_fabs(DisasContext *ctx)
2401 {
2402 if (unlikely(!ctx->fpu_enabled)) {
2403 gen_exception(ctx, POWERPC_EXCP_FPU);
2404 return;
2405 }
2406 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2407 ~(1ULL << 63));
2408 if (unlikely(Rc(ctx->opcode))) {
2409 gen_set_cr1_from_fpscr(ctx);
2410 }
2411 }
2412
2413 /* fmr - fmr. */
2414 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2415 static void gen_fmr(DisasContext *ctx)
2416 {
2417 if (unlikely(!ctx->fpu_enabled)) {
2418 gen_exception(ctx, POWERPC_EXCP_FPU);
2419 return;
2420 }
2421 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2422 if (unlikely(Rc(ctx->opcode))) {
2423 gen_set_cr1_from_fpscr(ctx);
2424 }
2425 }
2426
2427 /* fnabs */
2428 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2429 static void gen_fnabs(DisasContext *ctx)
2430 {
2431 if (unlikely(!ctx->fpu_enabled)) {
2432 gen_exception(ctx, POWERPC_EXCP_FPU);
2433 return;
2434 }
2435 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2436 1ULL << 63);
2437 if (unlikely(Rc(ctx->opcode))) {
2438 gen_set_cr1_from_fpscr(ctx);
2439 }
2440 }
2441
2442 /* fneg */
2443 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2444 static void gen_fneg(DisasContext *ctx)
2445 {
2446 if (unlikely(!ctx->fpu_enabled)) {
2447 gen_exception(ctx, POWERPC_EXCP_FPU);
2448 return;
2449 }
2450 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2451 1ULL << 63);
2452 if (unlikely(Rc(ctx->opcode))) {
2453 gen_set_cr1_from_fpscr(ctx);
2454 }
2455 }
2456
2457 /* fcpsgn: PowerPC 2.05 specification */
2458 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2459 static void gen_fcpsgn(DisasContext *ctx)
2460 {
2461 if (unlikely(!ctx->fpu_enabled)) {
2462 gen_exception(ctx, POWERPC_EXCP_FPU);
2463 return;
2464 }
2465 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2466 cpu_fpr[rB(ctx->opcode)], 0, 63);
2467 if (unlikely(Rc(ctx->opcode))) {
2468 gen_set_cr1_from_fpscr(ctx);
2469 }
2470 }
2471
2472 static void gen_fmrgew(DisasContext *ctx)
2473 {
2474 TCGv_i64 b0;
2475 if (unlikely(!ctx->fpu_enabled)) {
2476 gen_exception(ctx, POWERPC_EXCP_FPU);
2477 return;
2478 }
2479 b0 = tcg_temp_new_i64();
2480 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2481 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2482 b0, 0, 32);
2483 tcg_temp_free_i64(b0);
2484 }
2485
2486 static void gen_fmrgow(DisasContext *ctx)
2487 {
2488 if (unlikely(!ctx->fpu_enabled)) {
2489 gen_exception(ctx, POWERPC_EXCP_FPU);
2490 return;
2491 }
2492 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2493 cpu_fpr[rB(ctx->opcode)],
2494 cpu_fpr[rA(ctx->opcode)],
2495 32, 32);
2496 }
2497
2498 /*** Floating-Point status & ctrl register ***/
2499
2500 /* mcrfs */
2501 static void gen_mcrfs(DisasContext *ctx)
2502 {
2503 TCGv tmp = tcg_temp_new();
2504 int bfa;
2505
2506 if (unlikely(!ctx->fpu_enabled)) {
2507 gen_exception(ctx, POWERPC_EXCP_FPU);
2508 return;
2509 }
2510 bfa = 4 * (7 - crfS(ctx->opcode));
2511 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2512 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2513 tcg_temp_free(tmp);
2514 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2515 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2516 }
2517
2518 /* mffs */
2519 static void gen_mffs(DisasContext *ctx)
2520 {
2521 if (unlikely(!ctx->fpu_enabled)) {
2522 gen_exception(ctx, POWERPC_EXCP_FPU);
2523 return;
2524 }
2525 gen_reset_fpstatus();
2526 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2527 if (unlikely(Rc(ctx->opcode))) {
2528 gen_set_cr1_from_fpscr(ctx);
2529 }
2530 }
2531
2532 /* mtfsb0 */
2533 static void gen_mtfsb0(DisasContext *ctx)
2534 {
2535 uint8_t crb;
2536
2537 if (unlikely(!ctx->fpu_enabled)) {
2538 gen_exception(ctx, POWERPC_EXCP_FPU);
2539 return;
2540 }
2541 crb = 31 - crbD(ctx->opcode);
2542 gen_reset_fpstatus();
2543 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2544 TCGv_i32 t0;
2545 /* NIP cannot be restored if the memory exception comes from an helper */
2546 gen_update_nip(ctx, ctx->nip - 4);
2547 t0 = tcg_const_i32(crb);
2548 gen_helper_fpscr_clrbit(cpu_env, t0);
2549 tcg_temp_free_i32(t0);
2550 }
2551 if (unlikely(Rc(ctx->opcode) != 0)) {
2552 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2553 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2554 }
2555 }
2556
2557 /* mtfsb1 */
2558 static void gen_mtfsb1(DisasContext *ctx)
2559 {
2560 uint8_t crb;
2561
2562 if (unlikely(!ctx->fpu_enabled)) {
2563 gen_exception(ctx, POWERPC_EXCP_FPU);
2564 return;
2565 }
2566 crb = 31 - crbD(ctx->opcode);
2567 gen_reset_fpstatus();
2568 /* XXX: we pretend we can only do IEEE floating-point computations */
2569 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2570 TCGv_i32 t0;
2571 /* NIP cannot be restored if the memory exception comes from an helper */
2572 gen_update_nip(ctx, ctx->nip - 4);
2573 t0 = tcg_const_i32(crb);
2574 gen_helper_fpscr_setbit(cpu_env, t0);
2575 tcg_temp_free_i32(t0);
2576 }
2577 if (unlikely(Rc(ctx->opcode) != 0)) {
2578 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2579 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2580 }
2581 /* We can raise a differed exception */
2582 gen_helper_float_check_status(cpu_env);
2583 }
2584
2585 /* mtfsf */
2586 static void gen_mtfsf(DisasContext *ctx)
2587 {
2588 TCGv_i32 t0;
2589 int flm, l, w;
2590
2591 if (unlikely(!ctx->fpu_enabled)) {
2592 gen_exception(ctx, POWERPC_EXCP_FPU);
2593 return;
2594 }
2595 flm = FPFLM(ctx->opcode);
2596 l = FPL(ctx->opcode);
2597 w = FPW(ctx->opcode);
2598 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2599 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2600 return;
2601 }
2602 /* NIP cannot be restored if the memory exception comes from an helper */
2603 gen_update_nip(ctx, ctx->nip - 4);
2604 gen_reset_fpstatus();
2605 if (l) {
2606 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2607 } else {
2608 t0 = tcg_const_i32(flm << (w * 8));
2609 }
2610 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2611 tcg_temp_free_i32(t0);
2612 if (unlikely(Rc(ctx->opcode) != 0)) {
2613 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2614 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2615 }
2616 /* We can raise a differed exception */
2617 gen_helper_float_check_status(cpu_env);
2618 }
2619
2620 /* mtfsfi */
2621 static void gen_mtfsfi(DisasContext *ctx)
2622 {
2623 int bf, sh, w;
2624 TCGv_i64 t0;
2625 TCGv_i32 t1;
2626
2627 if (unlikely(!ctx->fpu_enabled)) {
2628 gen_exception(ctx, POWERPC_EXCP_FPU);
2629 return;
2630 }
2631 w = FPW(ctx->opcode);
2632 bf = FPBF(ctx->opcode);
2633 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2634 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2635 return;
2636 }
2637 sh = (8 * w) + 7 - bf;
2638 /* NIP cannot be restored if the memory exception comes from an helper */
2639 gen_update_nip(ctx, ctx->nip - 4);
2640 gen_reset_fpstatus();
2641 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2642 t1 = tcg_const_i32(1 << sh);
2643 gen_helper_store_fpscr(cpu_env, t0, t1);
2644 tcg_temp_free_i64(t0);
2645 tcg_temp_free_i32(t1);
2646 if (unlikely(Rc(ctx->opcode) != 0)) {
2647 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2648 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2649 }
2650 /* We can raise a differed exception */
2651 gen_helper_float_check_status(cpu_env);
2652 }
2653
2654 /*** Addressing modes ***/
2655 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2656 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2657 target_long maskl)
2658 {
2659 target_long simm = SIMM(ctx->opcode);
2660
2661 simm &= ~maskl;
2662 if (rA(ctx->opcode) == 0) {
2663 if (NARROW_MODE(ctx)) {
2664 simm = (uint32_t)simm;
2665 }
2666 tcg_gen_movi_tl(EA, simm);
2667 } else if (likely(simm != 0)) {
2668 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2669 if (NARROW_MODE(ctx)) {
2670 tcg_gen_ext32u_tl(EA, EA);
2671 }
2672 } else {
2673 if (NARROW_MODE(ctx)) {
2674 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2675 } else {
2676 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2677 }
2678 }
2679 }
2680
2681 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2682 {
2683 if (rA(ctx->opcode) == 0) {
2684 if (NARROW_MODE(ctx)) {
2685 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2686 } else {
2687 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2688 }
2689 } else {
2690 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2691 if (NARROW_MODE(ctx)) {
2692 tcg_gen_ext32u_tl(EA, EA);
2693 }
2694 }
2695 }
2696
2697 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2698 {
2699 if (rA(ctx->opcode) == 0) {
2700 tcg_gen_movi_tl(EA, 0);
2701 } else if (NARROW_MODE(ctx)) {
2702 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2703 } else {
2704 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2705 }
2706 }
2707
2708 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2709 target_long val)
2710 {
2711 tcg_gen_addi_tl(ret, arg1, val);
2712 if (NARROW_MODE(ctx)) {
2713 tcg_gen_ext32u_tl(ret, ret);
2714 }
2715 }
2716
2717 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2718 {
2719 TCGLabel *l1 = gen_new_label();
2720 TCGv t0 = tcg_temp_new();
2721 TCGv_i32 t1, t2;
2722 /* NIP cannot be restored if the memory exception comes from an helper */
2723 gen_update_nip(ctx, ctx->nip - 4);
2724 tcg_gen_andi_tl(t0, EA, mask);
2725 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2726 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2727 t2 = tcg_const_i32(0);
2728 gen_helper_raise_exception_err(cpu_env, t1, t2);
2729 tcg_temp_free_i32(t1);
2730 tcg_temp_free_i32(t2);
2731 gen_set_label(l1);
2732 tcg_temp_free(t0);
2733 }
2734
2735 /*** Integer load ***/
2736 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2737 {
2738 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2739 }
2740
2741 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2742 {
2743 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2744 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2745 }
2746
2747 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2748 {
2749 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2750 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2751 }
2752
2753 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2754 {
2755 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2756 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2757 }
2758
2759 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2760 {
2761 TCGv tmp = tcg_temp_new();
2762 gen_qemu_ld32u(ctx, tmp, addr);
2763 tcg_gen_extu_tl_i64(val, tmp);
2764 tcg_temp_free(tmp);
2765 }
2766
2767 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2768 {
2769 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2770 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2771 }
2772
2773 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2774 {
2775 TCGv tmp = tcg_temp_new();
2776 gen_qemu_ld32s(ctx, tmp, addr);
2777 tcg_gen_ext_tl_i64(val, tmp);
2778 tcg_temp_free(tmp);
2779 }
2780
2781 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2782 {
2783 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2784 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2785 }
2786
2787 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2788 {
2789 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2790 }
2791
2792 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2793 {
2794 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2795 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2796 }
2797
2798 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2799 {
2800 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2801 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2802 }
2803
2804 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2805 {
2806 TCGv tmp = tcg_temp_new();
2807 tcg_gen_trunc_i64_tl(tmp, val);
2808 gen_qemu_st32(ctx, tmp, addr);
2809 tcg_temp_free(tmp);
2810 }
2811
2812 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2813 {
2814 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2815 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2816 }
2817
2818 #define GEN_LD(name, ldop, opc, type) \
2819 static void glue(gen_, name)(DisasContext *ctx) \
2820 { \
2821 TCGv EA; \
2822 gen_set_access_type(ctx, ACCESS_INT); \
2823 EA = tcg_temp_new(); \
2824 gen_addr_imm_index(ctx, EA, 0); \
2825 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2826 tcg_temp_free(EA); \
2827 }
2828
2829 #define GEN_LDU(name, ldop, opc, type) \
2830 static void glue(gen_, name##u)(DisasContext *ctx) \
2831 { \
2832 TCGv EA; \
2833 if (unlikely(rA(ctx->opcode) == 0 || \
2834 rA(ctx->opcode) == rD(ctx->opcode))) { \
2835 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2836 return; \
2837 } \
2838 gen_set_access_type(ctx, ACCESS_INT); \
2839 EA = tcg_temp_new(); \
2840 if (type == PPC_64B) \
2841 gen_addr_imm_index(ctx, EA, 0x03); \
2842 else \
2843 gen_addr_imm_index(ctx, EA, 0); \
2844 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2845 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2846 tcg_temp_free(EA); \
2847 }
2848
2849 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2850 static void glue(gen_, name##ux)(DisasContext *ctx) \
2851 { \
2852 TCGv EA; \
2853 if (unlikely(rA(ctx->opcode) == 0 || \
2854 rA(ctx->opcode) == rD(ctx->opcode))) { \
2855 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2856 return; \
2857 } \
2858 gen_set_access_type(ctx, ACCESS_INT); \
2859 EA = tcg_temp_new(); \
2860 gen_addr_reg_index(ctx, EA); \
2861 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2862 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2863 tcg_temp_free(EA); \
2864 }
2865
2866 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2867 static void glue(gen_, name##x)(DisasContext *ctx) \
2868 { \
2869 TCGv EA; \
2870 gen_set_access_type(ctx, ACCESS_INT); \
2871 EA = tcg_temp_new(); \
2872 gen_addr_reg_index(ctx, EA); \
2873 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2874 tcg_temp_free(EA); \
2875 }
2876 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2877 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2878
2879 #define GEN_LDS(name, ldop, op, type) \
2880 GEN_LD(name, ldop, op | 0x20, type); \
2881 GEN_LDU(name, ldop, op | 0x21, type); \
2882 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2883 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2884
2885 /* lbz lbzu lbzux lbzx */
2886 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2887 /* lha lhau lhaux lhax */
2888 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2889 /* lhz lhzu lhzux lhzx */
2890 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2891 /* lwz lwzu lwzux lwzx */
2892 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2893 #if defined(TARGET_PPC64)
2894 /* lwaux */
2895 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2896 /* lwax */
2897 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2898 /* ldux */
2899 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2900 /* ldx */
2901 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2902
2903 static void gen_ld(DisasContext *ctx)
2904 {
2905 TCGv EA;
2906 if (Rc(ctx->opcode)) {
2907 if (unlikely(rA(ctx->opcode) == 0 ||
2908 rA(ctx->opcode) == rD(ctx->opcode))) {
2909 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2910 return;
2911 }
2912 }
2913 gen_set_access_type(ctx, ACCESS_INT);
2914 EA = tcg_temp_new();
2915 gen_addr_imm_index(ctx, EA, 0x03);
2916 if (ctx->opcode & 0x02) {
2917 /* lwa (lwau is undefined) */
2918 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2919 } else {
2920 /* ld - ldu */
2921 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2922 }
2923 if (Rc(ctx->opcode))
2924 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2925 tcg_temp_free(EA);
2926 }
2927
2928 /* lq */
2929 static void gen_lq(DisasContext *ctx)
2930 {
2931 int ra, rd;
2932 TCGv EA;
2933
2934 /* lq is a legal user mode instruction starting in ISA 2.07 */
2935 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2936 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2937
2938 if (!legal_in_user_mode && ctx->pr) {
2939 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2940 return;
2941 }
2942
2943 if (!le_is_supported && ctx->le_mode) {
2944 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2945 return;
2946 }
2947
2948 ra = rA(ctx->opcode);
2949 rd = rD(ctx->opcode);
2950 if (unlikely((rd & 1) || rd == ra)) {
2951 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2952 return;
2953 }
2954
2955 gen_set_access_type(ctx, ACCESS_INT);
2956 EA = tcg_temp_new();
2957 gen_addr_imm_index(ctx, EA, 0x0F);
2958
2959 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2960 64-bit byteswap already. */
2961 if (unlikely(ctx->le_mode)) {
2962 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2963 gen_addr_add(ctx, EA, EA, 8);
2964 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2965 } else {
2966 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2967 gen_addr_add(ctx, EA, EA, 8);
2968 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2969 }
2970 tcg_temp_free(EA);
2971 }
2972 #endif
2973
2974 /*** Integer store ***/
2975 #define GEN_ST(name, stop, opc, type) \
2976 static void glue(gen_, name)(DisasContext *ctx) \
2977 { \
2978 TCGv EA; \
2979 gen_set_access_type(ctx, ACCESS_INT); \
2980 EA = tcg_temp_new(); \
2981 gen_addr_imm_index(ctx, EA, 0); \
2982 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2983 tcg_temp_free(EA); \
2984 }
2985
2986 #define GEN_STU(name, stop, opc, type) \
2987 static void glue(gen_, stop##u)(DisasContext *ctx) \
2988 { \
2989 TCGv EA; \
2990 if (unlikely(rA(ctx->opcode) == 0)) { \
2991 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2992 return; \
2993 } \
2994 gen_set_access_type(ctx, ACCESS_INT); \
2995 EA = tcg_temp_new(); \
2996 if (type == PPC_64B) \
2997 gen_addr_imm_index(ctx, EA, 0x03); \
2998 else \
2999 gen_addr_imm_index(ctx, EA, 0); \
3000 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3001 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3002 tcg_temp_free(EA); \
3003 }
3004
3005 #define GEN_STUX(name, stop, opc2, opc3, type) \
3006 static void glue(gen_, name##ux)(DisasContext *ctx) \
3007 { \
3008 TCGv EA; \
3009 if (unlikely(rA(ctx->opcode) == 0)) { \
3010 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3011 return; \
3012 } \
3013 gen_set_access_type(ctx, ACCESS_INT); \
3014 EA = tcg_temp_new(); \
3015 gen_addr_reg_index(ctx, EA); \
3016 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3017 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3018 tcg_temp_free(EA); \
3019 }
3020
3021 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3022 static void glue(gen_, name##x)(DisasContext *ctx) \
3023 { \
3024 TCGv EA; \
3025 gen_set_access_type(ctx, ACCESS_INT); \
3026 EA = tcg_temp_new(); \
3027 gen_addr_reg_index(ctx, EA); \
3028 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3029 tcg_temp_free(EA); \
3030 }
3031 #define GEN_STX(name, stop, opc2, opc3, type) \
3032 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3033
3034 #define GEN_STS(name, stop, op, type) \
3035 GEN_ST(name, stop, op | 0x20, type); \
3036 GEN_STU(name, stop, op | 0x21, type); \
3037 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3038 GEN_STX(name, stop, 0x17, op | 0x00, type)
3039
3040 /* stb stbu stbux stbx */
3041 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3042 /* sth sthu sthux sthx */
3043 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3044 /* stw stwu stwux stwx */
3045 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3046 #if defined(TARGET_PPC64)
3047 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3048 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3049
3050 static void gen_std(DisasContext *ctx)
3051 {
3052 int rs;
3053 TCGv EA;
3054
3055 rs = rS(ctx->opcode);
3056 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3057
3058 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3059 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3060
3061 if (!legal_in_user_mode && ctx->pr) {
3062 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3063 return;
3064 }
3065
3066 if (!le_is_supported && ctx->le_mode) {
3067 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3068 return;
3069 }
3070
3071 if (unlikely(rs & 1)) {
3072 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3073 return;
3074 }
3075 gen_set_access_type(ctx, ACCESS_INT);
3076 EA = tcg_temp_new();
3077 gen_addr_imm_index(ctx, EA, 0x03);
3078
3079 /* We only need to swap high and low halves. gen_qemu_st64 does
3080 necessary 64-bit byteswap already. */
3081 if (unlikely(ctx->le_mode)) {
3082 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3083 gen_addr_add(ctx, EA, EA, 8);
3084 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3085 } else {
3086 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3087 gen_addr_add(ctx, EA, EA, 8);
3088 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3089 }
3090 tcg_temp_free(EA);
3091 } else {
3092 /* std / stdu*/
3093 if (Rc(ctx->opcode)) {
3094 if (unlikely(rA(ctx->opcode) == 0)) {
3095 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3096 return;
3097 }
3098 }
3099 gen_set_access_type(ctx, ACCESS_INT);
3100 EA = tcg_temp_new();
3101 gen_addr_imm_index(ctx, EA, 0x03);
3102 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3103 if (Rc(ctx->opcode))
3104 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3105 tcg_temp_free(EA);
3106 }
3107 }
3108 #endif
3109 /*** Integer load and store with byte reverse ***/
3110
3111 /* lhbrx */
3112 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3113 {
3114 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3115 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3116 }
3117 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3118
3119 /* lwbrx */
3120 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3121 {
3122 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3123 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3124 }
3125 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3126
3127 #if defined(TARGET_PPC64)
3128 /* ldbrx */
3129 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3130 {
3131 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3132 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3133 }
3134 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3135 #endif /* TARGET_PPC64 */
3136
3137 /* sthbrx */
3138 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3139 {
3140 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3141 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3142 }
3143 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3144
3145 /* stwbrx */
3146 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3147 {
3148 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3149 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3150 }
3151 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3152
3153 #if defined(TARGET_PPC64)
3154 /* stdbrx */
3155 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3156 {
3157 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3158 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3159 }
3160 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3161 #endif /* TARGET_PPC64 */
3162
3163 /*** Integer load and store multiple ***/
3164
3165 /* lmw */
3166 static void gen_lmw(DisasContext *ctx)
3167 {
3168 TCGv t0;
3169 TCGv_i32 t1;
3170 gen_set_access_type(ctx, ACCESS_INT);
3171 /* NIP cannot be restored if the memory exception comes from an helper */
3172 gen_update_nip(ctx, ctx->nip - 4);
3173 t0 = tcg_temp_new();
3174 t1 = tcg_const_i32(rD(ctx->opcode));
3175 gen_addr_imm_index(ctx, t0, 0);
3176 gen_helper_lmw(cpu_env, t0, t1);
3177 tcg_temp_free(t0);
3178 tcg_temp_free_i32(t1);
3179 }
3180
3181 /* stmw */
3182 static void gen_stmw(DisasContext *ctx)
3183 {
3184 TCGv t0;
3185 TCGv_i32 t1;
3186 gen_set_access_type(ctx, ACCESS_INT);
3187 /* NIP cannot be restored if the memory exception comes from an helper */
3188 gen_update_nip(ctx, ctx->nip - 4);
3189 t0 = tcg_temp_new();
3190 t1 = tcg_const_i32(rS(ctx->opcode));
3191 gen_addr_imm_index(ctx, t0, 0);
3192 gen_helper_stmw(cpu_env, t0, t1);
3193 tcg_temp_free(t0);
3194 tcg_temp_free_i32(t1);
3195 }
3196
3197 /*** Integer load and store strings ***/
3198
3199 /* lswi */
3200 /* PowerPC32 specification says we must generate an exception if
3201 * rA is in the range of registers to be loaded.
3202 * In an other hand, IBM says this is valid, but rA won't be loaded.
3203 * For now, I'll follow the spec...
3204 */
3205 static void gen_lswi(DisasContext *ctx)
3206 {
3207 TCGv t0;
3208 TCGv_i32 t1, t2;
3209 int nb = NB(ctx->opcode);
3210 int start = rD(ctx->opcode);
3211 int ra = rA(ctx->opcode);
3212 int nr;
3213
3214 if (nb == 0)
3215 nb = 32;
3216 nr = nb / 4;
3217 if (unlikely(((start + nr) > 32 &&
3218 start <= ra && (start + nr - 32) > ra) ||
3219 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3220 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3221 return;
3222 }
3223 gen_set_access_type(ctx, ACCESS_INT);
3224 /* NIP cannot be restored if the memory exception comes from an helper */
3225 gen_update_nip(ctx, ctx->nip - 4);
3226 t0 = tcg_temp_new();
3227 gen_addr_register(ctx, t0);
3228 t1 = tcg_const_i32(nb);
3229 t2 = tcg_const_i32(start);
3230 gen_helper_lsw(cpu_env, t0, t1, t2);
3231 tcg_temp_free(t0);
3232 tcg_temp_free_i32(t1);
3233 tcg_temp_free_i32(t2);
3234 }
3235
3236 /* lswx */
3237 static void gen_lswx(DisasContext *ctx)
3238 {
3239 TCGv t0;
3240 TCGv_i32 t1, t2, t3;
3241 gen_set_access_type(ctx, ACCESS_INT);
3242 /* NIP cannot be restored if the memory exception comes from an helper */
3243 gen_update_nip(ctx, ctx->nip - 4);
3244 t0 = tcg_temp_new();
3245 gen_addr_reg_index(ctx, t0);
3246 t1 = tcg_const_i32(rD(ctx->opcode));
3247 t2 = tcg_const_i32(rA(ctx->opcode));
3248 t3 = tcg_const_i32(rB(ctx->opcode));
3249 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3250 tcg_temp_free(t0);
3251 tcg_temp_free_i32(t1);
3252 tcg_temp_free_i32(t2);
3253 tcg_temp_free_i32(t3);
3254 }
3255
3256 /* stswi */
3257 static void gen_stswi(DisasContext *ctx)
3258 {
3259 TCGv t0;
3260 TCGv_i32 t1, t2;
3261 int nb = NB(ctx->opcode);
3262 gen_set_access_type(ctx, ACCESS_INT);
3263 /* NIP cannot be restored if the memory exception comes from an helper */
3264 gen_update_nip(ctx, ctx->nip - 4);
3265 t0 = tcg_temp_new();
3266 gen_addr_register(ctx, t0);
3267 if (nb == 0)
3268 nb = 32;
3269 t1 = tcg_const_i32(nb);
3270 t2 = tcg_const_i32(rS(ctx->opcode));
3271 gen_helper_stsw(cpu_env, t0, t1, t2);
3272 tcg_temp_free(t0);
3273 tcg_temp_free_i32(t1);
3274 tcg_temp_free_i32(t2);
3275 }
3276
3277 /* stswx */
3278 static void gen_stswx(DisasContext *ctx)
3279 {
3280 TCGv t0;
3281 TCGv_i32 t1, t2;
3282 gen_set_access_type(ctx, ACCESS_INT);
3283 /* NIP cannot be restored if the memory exception comes from an helper */
3284 gen_update_nip(ctx, ctx->nip - 4);
3285 t0 = tcg_temp_new();
3286 gen_addr_reg_index(ctx, t0);
3287 t1 = tcg_temp_new_i32();
3288 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3289 tcg_gen_andi_i32(t1, t1, 0x7F);
3290 t2 = tcg_const_i32(rS(ctx->opcode));
3291 gen_helper_stsw(cpu_env, t0, t1, t2);
3292 tcg_temp_free(t0);
3293 tcg_temp_free_i32(t1);
3294 tcg_temp_free_i32(t2);
3295 }
3296
3297 /*** Memory synchronisation ***/
3298 /* eieio */
3299 static void gen_eieio(DisasContext *ctx)
3300 {
3301 }
3302
3303 /* isync */
3304 static void gen_isync(DisasContext *ctx)
3305 {
3306 gen_stop_exception(ctx);
3307 }
3308
3309 #define LARX(name, len, loadop) \
3310 static void gen_##name(DisasContext *ctx) \
3311 { \
3312 TCGv t0; \
3313 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3314 gen_set_access_type(ctx, ACCESS_RES); \
3315 t0 = tcg_temp_local_new(); \
3316 gen_addr_reg_index(ctx, t0); \
3317 if ((len) > 1) { \
3318 gen_check_align(ctx, t0, (len)-1); \
3319 } \
3320 gen_qemu_##loadop(ctx, gpr, t0); \
3321 tcg_gen_mov_tl(cpu_reserve, t0); \
3322 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3323 tcg_temp_free(t0); \
3324 }
3325
3326 /* lwarx */
3327 LARX(lbarx, 1, ld8u);
3328 LARX(lharx, 2, ld16u);
3329 LARX(lwarx, 4, ld32u);
3330
3331
3332 #if defined(CONFIG_USER_ONLY)
3333 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3334 int reg, int size)
3335 {
3336 TCGv t0 = tcg_temp_new();
3337 uint32_t save_exception = ctx->exception;
3338
3339 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3340 tcg_gen_movi_tl(t0, (size << 5) | reg);
3341 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3342 tcg_temp_free(t0);
3343 gen_update_nip(ctx, ctx->nip-4);
3344 ctx->exception = POWERPC_EXCP_BRANCH;
3345 gen_exception(ctx, POWERPC_EXCP_STCX);
3346 ctx->exception = save_exception;
3347 }
3348 #else
3349 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3350 int reg, int size)
3351 {
3352 TCGLabel *l1;
3353
3354 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3355 l1 = gen_new_label();
3356 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3357 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3358 #if defined(TARGET_PPC64)
3359 if (size == 8) {
3360 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3361 } else
3362 #endif
3363 if (size == 4) {
3364 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3365 } else if (size == 2) {
3366 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3367 #if defined(TARGET_PPC64)
3368 } else if (size == 16) {
3369 TCGv gpr1, gpr2 , EA8;
3370 if (unlikely(ctx->le_mode)) {
3371 gpr1 = cpu_gpr[reg+1];
3372 gpr2 = cpu_gpr[reg];
3373 } else {
3374 gpr1 = cpu_gpr[reg];
3375 gpr2 = cpu_gpr[reg+1];
3376 }
3377 gen_qemu_st64(ctx, gpr1, EA);
3378 EA8 = tcg_temp_local_new();
3379 gen_addr_add(ctx, EA8, EA, 8);
3380 gen_qemu_st64(ctx, gpr2, EA8);
3381 tcg_temp_free(EA8);
3382 #endif
3383 } else {
3384 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3385 }
3386 gen_set_label(l1);
3387 tcg_gen_movi_tl(cpu_reserve, -1);
3388 }
3389 #endif
3390
3391 #define STCX(name, len) \
3392 static void gen_##name(DisasContext *ctx) \
3393 { \
3394 TCGv t0; \
3395 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3396 gen_inval_exception(ctx, \
3397 POWERPC_EXCP_INVAL_INVAL); \
3398 return; \
3399 } \
3400 gen_set_access_type(ctx, ACCESS_RES); \
3401 t0 = tcg_temp_local_new(); \
3402 gen_addr_reg_index(ctx, t0); \
3403 if (len > 1) { \
3404 gen_check_align(ctx, t0, (len)-1); \
3405 } \
3406 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3407 tcg_temp_free(t0); \
3408 }
3409
3410 STCX(stbcx_, 1);
3411 STCX(sthcx_, 2);
3412 STCX(stwcx_, 4);
3413
3414 #if defined(TARGET_PPC64)
3415 /* ldarx */
3416 LARX(ldarx, 8, ld64);
3417
3418 /* lqarx */
3419 static void gen_lqarx(DisasContext *ctx)
3420 {
3421 TCGv EA;
3422 int rd = rD(ctx->opcode);
3423 TCGv gpr1, gpr2;
3424
3425 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3426 (rd == rB(ctx->opcode)))) {
3427 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3428 return;
3429 }
3430
3431 gen_set_access_type(ctx, ACCESS_RES);
3432 EA = tcg_temp_local_new();
3433 gen_addr_reg_index(ctx, EA);
3434 gen_check_align(ctx, EA, 15);
3435 if (unlikely(ctx->le_mode)) {
3436 gpr1 = cpu_gpr[rd+1];
3437 gpr2 = cpu_gpr[rd];
3438 } else {
3439 gpr1 = cpu_gpr[rd];
3440 gpr2 = cpu_gpr[rd+1];
3441 }
3442 gen_qemu_ld64(ctx, gpr1, EA);
3443 tcg_gen_mov_tl(cpu_reserve, EA);
3444
3445 gen_addr_add(ctx, EA, EA, 8);
3446 gen_qemu_ld64(ctx, gpr2, EA);
3447
3448 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3449 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3450
3451 tcg_temp_free(EA);
3452 }
3453
3454 /* stdcx. */
3455 STCX(stdcx_, 8);
3456 STCX(stqcx_, 16);
3457 #endif /* defined(TARGET_PPC64) */
3458
3459 /* sync */
3460 static void gen_sync(DisasContext *ctx)
3461 {
3462 }
3463
3464 /* wait */
3465 static void gen_wait(DisasContext *ctx)
3466 {
3467 TCGv_i32 t0 = tcg_temp_new_i32();
3468 tcg_gen_st_i32(t0, cpu_env,
3469 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3470 tcg_temp_free_i32(t0);
3471 /* Stop translation, as the CPU is supposed to sleep from now */
3472 gen_exception_err(ctx, EXCP_HLT, 1);
3473 }
3474
3475 /*** Floating-point load ***/
3476 #define GEN_LDF(name, ldop, opc, type) \
3477 static void glue(gen_, name)(DisasContext *ctx) \
3478 { \
3479 TCGv EA; \
3480 if (unlikely(!ctx->fpu_enabled)) { \
3481 gen_exception(ctx, POWERPC_EXCP_FPU); \
3482 return; \
3483 } \
3484 gen_set_access_type(ctx, ACCESS_FLOAT); \
3485 EA = tcg_temp_new(); \
3486 gen_addr_imm_index(ctx, EA, 0); \
3487 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3488 tcg_temp_free(EA); \
3489 }
3490
3491 #define GEN_LDUF(name, ldop, opc, type) \
3492 static void glue(gen_, name##u)(DisasContext *ctx) \
3493 { \
3494 TCGv EA; \
3495 if (unlikely(!ctx->fpu_enabled)) { \
3496 gen_exception(ctx, POWERPC_EXCP_FPU); \
3497 return; \
3498 } \
3499 if (unlikely(rA(ctx->opcode) == 0)) { \
3500 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3501 return; \
3502 } \
3503 gen_set_access_type(ctx, ACCESS_FLOAT); \
3504 EA = tcg_temp_new(); \
3505 gen_addr_imm_index(ctx, EA, 0); \
3506 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3507 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3508 tcg_temp_free(EA); \
3509 }
3510
3511 #define GEN_LDUXF(name, ldop, opc, type) \
3512 static void glue(gen_, name##ux)(DisasContext *ctx) \
3513 { \
3514 TCGv EA; \
3515 if (unlikely(!ctx->fpu_enabled)) { \
3516 gen_exception(ctx, POWERPC_EXCP_FPU); \
3517 return; \
3518 } \
3519 if (unlikely(rA(ctx->opcode) == 0)) { \
3520 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3521 return; \
3522 } \
3523 gen_set_access_type(ctx, ACCESS_FLOAT); \
3524 EA = tcg_temp_new(); \
3525 gen_addr_reg_index(ctx, EA); \
3526 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3527 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3528 tcg_temp_free(EA); \
3529 }
3530
3531 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3532 static void glue(gen_, name##x)(DisasContext *ctx) \
3533 { \
3534 TCGv EA; \
3535 if (unlikely(!ctx->fpu_enabled)) { \
3536 gen_exception(ctx, POWERPC_EXCP_FPU); \
3537 return; \
3538 } \
3539 gen_set_access_type(ctx, ACCESS_FLOAT); \
3540 EA = tcg_temp_new(); \
3541 gen_addr_reg_index(ctx, EA); \
3542 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3543 tcg_temp_free(EA); \
3544 }
3545
3546 #define GEN_LDFS(name, ldop, op, type) \
3547 GEN_LDF(name, ldop, op | 0x20, type); \
3548 GEN_LDUF(name, ldop, op | 0x21, type); \
3549 GEN_LDUXF(name, ldop, op | 0x01, type); \
3550 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3551
3552 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3553 {
3554 TCGv t0 = tcg_temp_new();
3555 TCGv_i32 t1 = tcg_temp_new_i32();
3556 gen_qemu_ld32u(ctx, t0, arg2);
3557 tcg_gen_trunc_tl_i32(t1, t0);
3558 tcg_temp_free(t0);
3559 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3560 tcg_temp_free_i32(t1);
3561 }
3562
3563 /* lfd lfdu lfdux lfdx */
3564 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3565 /* lfs lfsu lfsux lfsx */
3566 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3567
3568 /* lfdp */
3569 static void gen_lfdp(DisasContext *ctx)
3570 {
3571 TCGv EA;
3572 if (unlikely(!ctx->fpu_enabled)) {
3573 gen_exception(ctx, POWERPC_EXCP_FPU);
3574 return;
3575 }
3576 gen_set_access_type(ctx, ACCESS_FLOAT);
3577 EA = tcg_temp_new();
3578 gen_addr_imm_index(ctx, EA, 0);
3579 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3580 64-bit byteswap already. */
3581 if (unlikely(ctx->le_mode)) {
3582 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3583 tcg_gen_addi_tl(EA, EA, 8);
3584 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3585 } else {
3586 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3587 tcg_gen_addi_tl(EA, EA, 8);
3588 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3589 }
3590 tcg_temp_free(EA);
3591 }
3592
3593 /* lfdpx */
3594 static void gen_lfdpx(DisasContext *ctx)
3595 {
3596 TCGv EA;
3597 if (unlikely(!ctx->fpu_enabled)) {
3598 gen_exception(ctx, POWERPC_EXCP_FPU);
3599 return;
3600 }
3601 gen_set_access_type(ctx, ACCESS_FLOAT);
3602 EA = tcg_temp_new();
3603 gen_addr_reg_index(ctx, EA);
3604 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3605 64-bit byteswap already. */
3606 if (unlikely(ctx->le_mode)) {
3607 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3608 tcg_gen_addi_tl(EA, EA, 8);
3609 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3610 } else {
3611 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3612 tcg_gen_addi_tl(EA, EA, 8);
3613 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3614 }
3615 tcg_temp_free(EA);
3616 }
3617
3618 /* lfiwax */
3619 static void gen_lfiwax(DisasContext *ctx)
3620 {
3621 TCGv EA;
3622 TCGv t0;
3623 if (unlikely(!ctx->fpu_enabled)) {
3624 gen_exception(ctx, POWERPC_EXCP_FPU);
3625 return;
3626 }
3627 gen_set_access_type(ctx, ACCESS_FLOAT);
3628 EA = tcg_temp_new();
3629 t0 = tcg_temp_new();
3630 gen_addr_reg_index(ctx, EA);
3631 gen_qemu_ld32s(ctx, t0, EA);
3632 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3633 tcg_temp_free(EA);
3634 tcg_temp_free(t0);
3635 }
3636
3637 /* lfiwzx */
3638 static void gen_lfiwzx(DisasContext *ctx)
3639 {
3640 TCGv EA;
3641 if (unlikely(!ctx->fpu_enabled)) {
3642 gen_exception(ctx, POWERPC_EXCP_FPU);
3643 return;
3644 }
3645 gen_set_access_type(ctx, ACCESS_FLOAT);
3646 EA = tcg_temp_new();
3647 gen_addr_reg_index(ctx, EA);
3648 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3649 tcg_temp_free(EA);
3650 }
3651 /*** Floating-point store ***/
3652 #define GEN_STF(name, stop, opc, type) \
3653 static void glue(gen_, name)(DisasContext *ctx) \
3654 { \
3655 TCGv EA; \
3656 if (unlikely(!ctx->fpu_enabled)) { \
3657 gen_exception(ctx, POWERPC_EXCP_FPU); \
3658 return; \
3659 } \
3660 gen_set_access_type(ctx, ACCESS_FLOAT); \
3661 EA = tcg_temp_new(); \
3662 gen_addr_imm_index(ctx, EA, 0); \
3663 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3664 tcg_temp_free(EA); \
3665 }
3666
3667 #define GEN_STUF(name, stop, opc, type) \
3668 static void glue(gen_, name##u)(DisasContext *ctx) \
3669 { \
3670 TCGv EA; \
3671 if (unlikely(!ctx->fpu_enabled)) { \
3672 gen_exception(ctx, POWERPC_EXCP_FPU); \
3673 return; \
3674 } \
3675 if (unlikely(rA(ctx->opcode) == 0)) { \
3676 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3677 return; \
3678 } \
3679 gen_set_access_type(ctx, ACCESS_FLOAT); \
3680 EA = tcg_temp_new(); \
3681 gen_addr_imm_index(ctx, EA, 0); \
3682 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3683 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3684 tcg_temp_free(EA); \
3685 }
3686
3687 #define GEN_STUXF(name, stop, opc, type) \
3688 static void glue(gen_, name##ux)(DisasContext *ctx) \
3689 { \
3690 TCGv EA; \
3691 if (unlikely(!ctx->fpu_enabled)) { \
3692 gen_exception(ctx, POWERPC_EXCP_FPU); \
3693 return; \
3694 } \
3695 if (unlikely(rA(ctx->opcode) == 0)) { \
3696 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3697 return; \
3698 } \
3699 gen_set_access_type(ctx, ACCESS_FLOAT); \
3700 EA = tcg_temp_new(); \
3701 gen_addr_reg_index(ctx, EA); \
3702 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3703 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3704 tcg_temp_free(EA); \
3705 }
3706
3707 #define GEN_STXF(name, stop, opc2, opc3, type) \
3708 static void glue(gen_, name##x)(DisasContext *ctx) \
3709 { \
3710 TCGv EA; \
3711 if (unlikely(!ctx->fpu_enabled)) { \
3712 gen_exception(ctx, POWERPC_EXCP_FPU); \
3713 return; \
3714 } \
3715 gen_set_access_type(ctx, ACCESS_FLOAT); \
3716 EA = tcg_temp_new(); \
3717 gen_addr_reg_index(ctx, EA); \
3718 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3719 tcg_temp_free(EA); \
3720 }
3721
3722 #define GEN_STFS(name, stop, op, type) \
3723 GEN_STF(name, stop, op | 0x20, type); \
3724 GEN_STUF(name, stop, op | 0x21, type); \
3725 GEN_STUXF(name, stop, op | 0x01, type); \
3726 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3727
3728 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3729 {
3730 TCGv_i32 t0 = tcg_temp_new_i32();
3731 TCGv t1 = tcg_temp_new();
3732 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3733 tcg_gen_extu_i32_tl(t1, t0);
3734 tcg_temp_free_i32(t0);
3735 gen_qemu_st32(ctx, t1, arg2);
3736 tcg_temp_free(t1);
3737 }
3738
3739 /* stfd stfdu stfdux stfdx */
3740 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3741 /* stfs stfsu stfsux stfsx */
3742 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3743
3744 /* stfdp */
3745 static void gen_stfdp(DisasContext *ctx)
3746 {
3747 TCGv EA;
3748 if (unlikely(!ctx->fpu_enabled)) {
3749 gen_exception(ctx, POWERPC_EXCP_FPU);
3750 return;
3751 }
3752 gen_set_access_type(ctx, ACCESS_FLOAT);
3753 EA = tcg_temp_new();
3754 gen_addr_imm_index(ctx, EA, 0);
3755 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3756 64-bit byteswap already. */
3757 if (unlikely(ctx->le_mode)) {
3758 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3759 tcg_gen_addi_tl(EA, EA, 8);
3760 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3761 } else {
3762 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3763 tcg_gen_addi_tl(EA, EA, 8);
3764 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3765 }
3766 tcg_temp_free(EA);
3767 }
3768
3769 /* stfdpx */
3770 static void gen_stfdpx(DisasContext *ctx)
3771 {
3772 TCGv EA;
3773 if (unlikely(!ctx->fpu_enabled)) {
3774 gen_exception(ctx, POWERPC_EXCP_FPU);
3775 return;
3776 }
3777 gen_set_access_type(ctx, ACCESS_FLOAT);
3778 EA = tcg_temp_new();
3779 gen_addr_reg_index(ctx, EA);
3780 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3781 64-bit byteswap already. */
3782 if (unlikely(ctx->le_mode)) {
3783 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3784 tcg_gen_addi_tl(EA, EA, 8);
3785 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3786 } else {
3787 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3788 tcg_gen_addi_tl(EA, EA, 8);
3789 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3790 }
3791 tcg_temp_free(EA);
3792 }
3793
3794 /* Optional: */
3795 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3796 {
3797 TCGv t0 = tcg_temp_new();
3798 tcg_gen_trunc_i64_tl(t0, arg1),
3799 gen_qemu_st32(ctx, t0, arg2);
3800 tcg_temp_free(t0);
3801 }
3802 /* stfiwx */
3803 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3804
3805 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3806 {
3807 #if defined(TARGET_PPC64)
3808 if (ctx->has_cfar)
3809 tcg_gen_movi_tl(cpu_cfar, nip);
3810 #endif
3811 }
3812
3813 /*** Branch ***/
3814 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3815 {
3816 TranslationBlock *tb;
3817 tb = ctx->tb;
3818 if (NARROW_MODE(ctx)) {
3819 dest = (uint32_t) dest;
3820 }
3821 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3822 likely(!ctx->singlestep_enabled)) {
3823 tcg_gen_goto_tb(n);
3824 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3825 tcg_gen_exit_tb((uintptr_t)tb + n);
3826 } else {
3827 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3828 if (unlikely(ctx->singlestep_enabled)) {
3829 if ((ctx->singlestep_enabled &
3830 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3831 (ctx->exception == POWERPC_EXCP_BRANCH ||
3832 ctx->exception == POWERPC_EXCP_TRACE)) {
3833 target_ulong tmp = ctx->nip;
3834 ctx->nip = dest;
3835 gen_exception(ctx, POWERPC_EXCP_TRACE);
3836 ctx->nip = tmp;
3837 }
3838 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3839 gen_debug_exception(ctx);
3840 }
3841 }
3842 tcg_gen_exit_tb(0);
3843 }
3844 }
3845
3846 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3847 {
3848 if (NARROW_MODE(ctx)) {
3849 nip = (uint32_t)nip;
3850 }
3851 tcg_gen_movi_tl(cpu_lr, nip);
3852 }
3853
3854 /* b ba bl bla */
3855 static void gen_b(DisasContext *ctx)
3856 {
3857 target_ulong li, target;
3858
3859 ctx->exception = POWERPC_EXCP_BRANCH;
3860 /* sign extend LI */
3861 li = LI(ctx->opcode);
3862 li = (li ^ 0x02000000) - 0x02000000;
3863 if (likely(AA(ctx->opcode) == 0)) {
3864 target = ctx->nip + li - 4;
3865 } else {
3866 target = li;
3867 }
3868 if (LK(ctx->opcode)) {
3869 gen_setlr(ctx, ctx->nip);
3870 }
3871 gen_update_cfar(ctx, ctx->nip);
3872 gen_goto_tb(ctx, 0, target);
3873 }
3874
3875 #define BCOND_IM 0
3876 #define BCOND_LR 1
3877 #define BCOND_CTR 2
3878 #define BCOND_TAR 3
3879
3880 static inline void gen_bcond(DisasContext *ctx, int type)
3881 {
3882 uint32_t bo = BO(ctx->opcode);
3883 TCGLabel *l1;
3884 TCGv target;
3885
3886 ctx->exception = POWERPC_EXCP_BRANCH;
3887 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3888 target = tcg_temp_local_new();
3889 if (type == BCOND_CTR)
3890 tcg_gen_mov_tl(target, cpu_ctr);
3891 else if (type == BCOND_TAR)
3892 gen_load_spr(target, SPR_TAR);
3893 else
3894 tcg_gen_mov_tl(target, cpu_lr);
3895 } else {
3896 TCGV_UNUSED(target);
3897 }
3898 if (LK(ctx->opcode))
3899 gen_setlr(ctx, ctx->nip);
3900 l1 = gen_new_label();
3901 if ((bo & 0x4) == 0) {
3902 /* Decrement and test CTR */
3903 TCGv temp = tcg_temp_new();
3904 if (unlikely(type == BCOND_CTR)) {
3905 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3906 return;
3907 }
3908 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3909 if (NARROW_MODE(ctx)) {
3910 tcg_gen_ext32u_tl(temp, cpu_ctr);
3911 } else {
3912 tcg_gen_mov_tl(temp, cpu_ctr);
3913 }
3914 if (bo & 0x2) {
3915 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3916 } else {
3917 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3918 }
3919 tcg_temp_free(temp);
3920 }
3921 if ((bo & 0x10) == 0) {
3922 /* Test CR */
3923 uint32_t bi = BI(ctx->opcode);
3924 uint32_t mask = 0x08 >> (bi & 0x03);
3925 TCGv_i32 temp = tcg_temp_new_i32();
3926
3927 if (bo & 0x8) {
3928 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3929 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3930 } else {
3931 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3932 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3933 }
3934 tcg_temp_free_i32(temp);
3935 }
3936 gen_update_cfar(ctx, ctx->nip);
3937 if (type == BCOND_IM) {
3938 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3939 if (likely(AA(ctx->opcode) == 0)) {
3940 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3941 } else {
3942 gen_goto_tb(ctx, 0, li);
3943 }
3944 gen_set_label(l1);
3945 gen_goto_tb(ctx, 1, ctx->nip);
3946 } else {
3947 if (NARROW_MODE(ctx)) {
3948 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3949 } else {
3950 tcg_gen_andi_tl(cpu_nip, target, ~3);
3951 }
3952 tcg_gen_exit_tb(0);
3953 gen_set_label(l1);
3954 gen_update_nip(ctx, ctx->nip);
3955 tcg_gen_exit_tb(0);
3956 }
3957 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3958 tcg_temp_free(target);
3959 }
3960 }
3961
3962 static void gen_bc(DisasContext *ctx)
3963 {
3964 gen_bcond(ctx, BCOND_IM);
3965 }
3966
3967 static void gen_bcctr(DisasContext *ctx)
3968 {
3969 gen_bcond(ctx, BCOND_CTR);
3970 }
3971
3972 static void gen_bclr(DisasContext *ctx)
3973 {
3974 gen_bcond(ctx, BCOND_LR);
3975 }
3976
3977 static void gen_bctar(DisasContext *ctx)
3978 {
3979 gen_bcond(ctx, BCOND_TAR);
3980 }
3981
3982 /*** Condition register logical ***/
3983 #define GEN_CRLOGIC(name, tcg_op, opc) \
3984 static void glue(gen_, name)(DisasContext *ctx) \
3985 { \
3986 uint8_t bitmask; \
3987 int sh; \
3988 TCGv_i32 t0, t1; \
3989 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3990 t0 = tcg_temp_new_i32(); \
3991 if (sh > 0) \
3992 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3993 else if (sh < 0) \
3994 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3995 else \
3996 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3997 t1 = tcg_temp_new_i32(); \
3998 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3999 if (sh > 0) \
4000 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4001 else if (sh < 0) \
4002 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4003 else \
4004 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4005 tcg_op(t0, t0, t1); \
4006 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4007 tcg_gen_andi_i32(t0, t0, bitmask); \
4008 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4009 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4010 tcg_temp_free_i32(t0); \
4011 tcg_temp_free_i32(t1); \
4012 }
4013
4014 /* crand */
4015 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4016 /* crandc */
4017 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4018 /* creqv */
4019 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4020 /* crnand */
4021 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4022 /* crnor */
4023 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4024 /* cror */
4025 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4026 /* crorc */
4027 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4028 /* crxor */
4029 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4030
4031 /* mcrf */
4032 static void gen_mcrf(DisasContext *ctx)
4033 {
4034 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4035 }
4036
4037 /*** System linkage ***/
4038
4039 /* rfi (supervisor only) */
4040 static void gen_rfi(DisasContext *ctx)
4041 {
4042 #if defined(CONFIG_USER_ONLY)
4043 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4044 #else
4045 /* Restore CPU state */
4046 if (unlikely(ctx->pr)) {
4047 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4048 return;
4049 }
4050 gen_update_cfar(ctx, ctx->nip);
4051 gen_helper_rfi(cpu_env);
4052 gen_sync_exception(ctx);
4053 #endif
4054 }
4055
4056 #if defined(TARGET_PPC64)
4057 static void gen_rfid(DisasContext *ctx)
4058 {
4059 #if defined(CONFIG_USER_ONLY)
4060 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4061 #else
4062 /* Restore CPU state */
4063 if (unlikely(ctx->pr)) {
4064 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4065 return;
4066 }
4067 gen_update_cfar(ctx, ctx->nip);
4068 gen_helper_rfid(cpu_env);
4069 gen_sync_exception(ctx);
4070 #endif
4071 }
4072
4073 static void gen_hrfid(DisasContext *ctx)
4074 {
4075 #if defined(CONFIG_USER_ONLY)
4076 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4077 #else
4078 /* Restore CPU state */
4079 if (unlikely(!ctx->hv)) {
4080 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4081 return;
4082 }
4083 gen_helper_hrfid(cpu_env);
4084 gen_sync_exception(ctx);
4085 #endif
4086 }
4087 #endif
4088
4089 /* sc */
4090 #if defined(CONFIG_USER_ONLY)
4091 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4092 #else
4093 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4094 #endif
4095 static void gen_sc(DisasContext *ctx)
4096 {
4097 uint32_t lev;
4098
4099 lev = (ctx->opcode >> 5) & 0x7F;
4100 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4101 }
4102
4103 /*** Trap ***/
4104
4105 /* tw */
4106 static void gen_tw(DisasContext *ctx)
4107 {
4108 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4109 /* Update the nip since this might generate a trap exception */
4110 gen_update_nip(ctx, ctx->nip);
4111 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4112 t0);
4113 tcg_temp_free_i32(t0);
4114 }
4115
4116 /* twi */
4117 static void gen_twi(DisasContext *ctx)
4118 {
4119 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4120 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4121 /* Update the nip since this might generate a trap exception */
4122 gen_update_nip(ctx, ctx->nip);
4123 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4124 tcg_temp_free(t0);
4125 tcg_temp_free_i32(t1);
4126 }
4127
4128 #if defined(TARGET_PPC64)
4129 /* td */
4130 static void gen_td(DisasContext *ctx)
4131 {
4132 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4133 /* Update the nip since this might generate a trap exception */
4134 gen_update_nip(ctx, ctx->nip);
4135 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4136 t0);
4137 tcg_temp_free_i32(t0);
4138 }
4139
4140 /* tdi */
4141 static void gen_tdi(DisasContext *ctx)
4142 {
4143 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4144 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4145 /* Update the nip since this might generate a trap exception */
4146 gen_update_nip(ctx, ctx->nip);
4147 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4148 tcg_temp_free(t0);
4149 tcg_temp_free_i32(t1);
4150 }
4151 #endif
4152
4153 /*** Processor control ***/
4154
4155 static void gen_read_xer(TCGv dst)
4156 {
4157 TCGv t0 = tcg_temp_new();
4158 TCGv t1 = tcg_temp_new();
4159 TCGv t2 = tcg_temp_new();
4160 tcg_gen_mov_tl(dst, cpu_xer);
4161 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4162 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4163 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4164 tcg_gen_or_tl(t0, t0, t1);
4165 tcg_gen_or_tl(dst, dst, t2);
4166 tcg_gen_or_tl(dst, dst, t0);
4167 tcg_temp_free(t0);
4168 tcg_temp_free(t1);
4169 tcg_temp_free(t2);
4170 }
4171
4172 static void gen_write_xer(TCGv src)
4173 {
4174 tcg_gen_andi_tl(cpu_xer, src,
4175 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4176 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4177 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4178 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4179 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4180 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4181 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4182 }
4183
4184 /* mcrxr */
4185 static void gen_mcrxr(DisasContext *ctx)
4186 {
4187 TCGv_i32 t0 = tcg_temp_new_i32();
4188 TCGv_i32 t1 = tcg_temp_new_i32();
4189 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4190
4191 tcg_gen_trunc_tl_i32(t0, cpu_so);
4192 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4193 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4194 tcg_gen_shli_i32(t0, t0, 3);
4195 tcg_gen_shli_i32(t1, t1, 2);
4196 tcg_gen_shli_i32(dst, dst, 1);
4197 tcg_gen_or_i32(dst, dst, t0);
4198 tcg_gen_or_i32(dst, dst, t1);
4199 tcg_temp_free_i32(t0);
4200 tcg_temp_free_i32(t1);
4201
4202 tcg_gen_movi_tl(cpu_so, 0);
4203 tcg_gen_movi_tl(cpu_ov, 0);
4204 tcg_gen_movi_tl(cpu_ca, 0);
4205 }
4206
4207 /* mfcr mfocrf */
4208 static void gen_mfcr(DisasContext *ctx)
4209 {
4210 uint32_t crm, crn;
4211
4212 if (likely(ctx->opcode & 0x00100000)) {
4213 crm = CRM(ctx->opcode);
4214 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4215 crn = ctz32 (crm);
4216 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4217 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4218 cpu_gpr[rD(ctx->opcode)], crn * 4);
4219 }
4220 } else {
4221 TCGv_i32 t0 = tcg_temp_new_i32();
4222 tcg_gen_mov_i32(t0, cpu_crf[0]);
4223 tcg_gen_shli_i32(t0, t0, 4);
4224 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4225 tcg_gen_shli_i32(t0, t0, 4);
4226 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4227 tcg_gen_shli_i32(t0, t0, 4);
4228 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4229 tcg_gen_shli_i32(t0, t0, 4);
4230 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4231 tcg_gen_shli_i32(t0, t0, 4);
4232 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4233 tcg_gen_shli_i32(t0, t0, 4);
4234 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4235 tcg_gen_shli_i32(t0, t0, 4);
4236 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4237 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4238 tcg_temp_free_i32(t0);
4239 }
4240 }
4241
4242 /* mfmsr */
4243 static void gen_mfmsr(DisasContext *ctx)
4244 {
4245 #if defined(CONFIG_USER_ONLY)
4246 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4247 #else
4248 if (unlikely(ctx->pr)) {
4249 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4250 return;
4251 }
4252 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4253 #endif
4254 }
4255
4256 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4257 {
4258 #if 0
4259 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4260 printf("ERROR: try to access SPR %d !\n", sprn);
4261 #endif
4262 }
4263 #define SPR_NOACCESS (&spr_noaccess)
4264
4265 /* mfspr */
4266 static inline void gen_op_mfspr(DisasContext *ctx)
4267 {
4268 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4269 uint32_t sprn = SPR(ctx->opcode);
4270
4271 #if !defined(CONFIG_USER_ONLY)
4272 if (ctx->hv)
4273 read_cb = ctx->spr_cb[sprn].hea_read;
4274 else if (!ctx->pr)
4275 read_cb = ctx->spr_cb[sprn].oea_read;
4276 else
4277 #endif
4278 read_cb = ctx->spr_cb[sprn].uea_read;
4279 if (likely(read_cb != NULL)) {
4280 if (likely(read_cb != SPR_NOACCESS)) {
4281 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4282 } else {
4283 /* Privilege exception */
4284 /* This is a hack to avoid warnings when running Linux:
4285 * this OS breaks the PowerPC virtualisation model,
4286 * allowing userland application to read the PVR
4287 */
4288 if (sprn != SPR_PVR) {
4289 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4290 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4291 if (qemu_log_separate()) {
4292 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4293 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4294 }
4295 }
4296 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4297 }
4298 } else {
4299 /* Not defined */
4300 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4301 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4302 if (qemu_log_separate()) {
4303 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4304 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4305 }
4306 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4307 }
4308 }
4309
4310 static void gen_mfspr(DisasContext *ctx)
4311 {
4312 gen_op_mfspr(ctx);
4313 }
4314
4315 /* mftb */
4316 static void gen_mftb(DisasContext *ctx)
4317 {
4318 gen_op_mfspr(ctx);
4319 }
4320
4321 /* mtcrf mtocrf*/
4322 static void gen_mtcrf(DisasContext *ctx)
4323 {
4324 uint32_t crm, crn;
4325
4326 crm = CRM(ctx->opcode);
4327 if (likely((ctx->opcode & 0x00100000))) {
4328 if (crm && ((crm & (crm - 1)) == 0)) {
4329 TCGv_i32 temp = tcg_temp_new_i32();
4330 crn = ctz32 (crm);
4331 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4332 tcg_gen_shri_i32(temp, temp, crn * 4);
4333 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4334 tcg_temp_free_i32(temp);
4335 }
4336 } else {
4337 TCGv_i32 temp = tcg_temp_new_i32();
4338 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4339 for (crn = 0 ; crn < 8 ; crn++) {
4340 if (crm & (1 << crn)) {
4341 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4342 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4343 }
4344 }
4345 tcg_temp_free_i32(temp);
4346 }
4347 }
4348
4349 /* mtmsr */
4350 #if defined(TARGET_PPC64)
4351 static void gen_mtmsrd(DisasContext *ctx)
4352 {
4353 #if defined(CONFIG_USER_ONLY)
4354 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4355 #else
4356 if (unlikely(ctx->pr)) {
4357 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4358 return;
4359 }
4360 if (ctx->opcode & 0x00010000) {
4361 /* Special form that does not need any synchronisation */
4362 TCGv t0 = tcg_temp_new();
4363 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4364 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4365 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4366 tcg_temp_free(t0);
4367 } else {
4368 /* XXX: we need to update nip before the store
4369 * if we enter power saving mode, we will exit the loop
4370 * directly from ppc_store_msr
4371 */
4372 gen_update_nip(ctx, ctx->nip);
4373 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4374 /* Must stop the translation as machine state (may have) changed */
4375 /* Note that mtmsr is not always defined as context-synchronizing */
4376 gen_stop_exception(ctx);
4377 }
4378 #endif
4379 }
4380 #endif
4381
4382 static void gen_mtmsr(DisasContext *ctx)
4383 {
4384 #if defined(CONFIG_USER_ONLY)
4385 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4386 #else
4387 if (unlikely(ctx->pr)) {
4388 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4389 return;
4390 }
4391 if (ctx->opcode & 0x00010000) {
4392 /* Special form that does not need any synchronisation */
4393 TCGv t0 = tcg_temp_new();
4394 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4395 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4396 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4397 tcg_temp_free(t0);
4398 } else {
4399 TCGv msr = tcg_temp_new();
4400
4401 /* XXX: we need to update nip before the store
4402 * if we enter power saving mode, we will exit the loop
4403 * directly from ppc_store_msr
4404 */
4405 gen_update_nip(ctx, ctx->nip);
4406 #if defined(TARGET_PPC64)
4407 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4408 #else
4409 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4410 #endif
4411 gen_helper_store_msr(cpu_env, msr);
4412 tcg_temp_free(msr);
4413 /* Must stop the translation as machine state (may have) changed */
4414 /* Note that mtmsr is not always defined as context-synchronizing */
4415 gen_stop_exception(ctx);
4416 }
4417 #endif
4418 }
4419
4420 /* mtspr */
4421 static void gen_mtspr(DisasContext *ctx)
4422 {
4423 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4424 uint32_t sprn = SPR(ctx->opcode);
4425
4426 #if !defined(CONFIG_USER_ONLY)
4427 if (ctx->hv)
4428 write_cb = ctx->spr_cb[sprn].hea_write;
4429 else if (!ctx->pr)
4430 write_cb = ctx->spr_cb[sprn].oea_write;
4431 else
4432 #endif
4433 write_cb = ctx->spr_cb[sprn].uea_write;
4434 if (likely(write_cb != NULL)) {
4435 if (likely(write_cb != SPR_NOACCESS)) {
4436 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4437 } else {
4438 /* Privilege exception */
4439 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4440 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4441 if (qemu_log_separate()) {
4442 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4443 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4444 }
4445 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4446 }
4447 } else {
4448 /* Not defined */
4449 if (qemu_log_separate()) {
4450 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4451 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4452 }
4453 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4454 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4455 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4456 }
4457 }
4458
4459 /*** Cache management ***/
4460
4461 /* dcbf */
4462 static void gen_dcbf(DisasContext *ctx)
4463 {
4464 /* XXX: specification says this is treated as a load by the MMU */
4465 TCGv t0;
4466 gen_set_access_type(ctx, ACCESS_CACHE);
4467 t0 = tcg_temp_new();
4468 gen_addr_reg_index(ctx, t0);
4469 gen_qemu_ld8u(ctx, t0, t0);
4470 tcg_temp_free(t0);
4471 }
4472
4473 /* dcbi (Supervisor only) */
4474 static void gen_dcbi(DisasContext *ctx)
4475 {
4476 #if defined(CONFIG_USER_ONLY)
4477 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4478 #else
4479 TCGv EA, val;
4480 if (unlikely(ctx->pr)) {
4481 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4482 return;
4483 }
4484 EA = tcg_temp_new();
4485 gen_set_access_type(ctx, ACCESS_CACHE);
4486 gen_addr_reg_index(ctx, EA);
4487 val = tcg_temp_new();
4488 /* XXX: specification says this should be treated as a store by the MMU */
4489 gen_qemu_ld8u(ctx, val, EA);
4490 gen_qemu_st8(ctx, val, EA);
4491 tcg_temp_free(val);
4492 tcg_temp_free(EA);
4493 #endif
4494 }
4495
4496 /* dcdst */
4497 static void gen_dcbst(DisasContext *ctx)
4498 {
4499 /* XXX: specification say this is treated as a load by the MMU */
4500 TCGv t0;
4501 gen_set_access_type(ctx, ACCESS_CACHE);
4502 t0 = tcg_temp_new();
4503 gen_addr_reg_index(ctx, t0);
4504 gen_qemu_ld8u(ctx, t0, t0);
4505 tcg_temp_free(t0);
4506 }
4507
4508 /* dcbt */
4509 static void gen_dcbt(DisasContext *ctx)
4510 {
4511 /* interpreted as no-op */
4512 /* XXX: specification say this is treated as a load by the MMU
4513 * but does not generate any exception
4514 */
4515 }
4516
4517 /* dcbtst */
4518 static void gen_dcbtst(DisasContext *ctx)
4519 {
4520 /* interpreted as no-op */
4521 /* XXX: specification say this is treated as a load by the MMU
4522 * but does not generate any exception
4523 */
4524 }
4525
4526 /* dcbtls */
4527 static void gen_dcbtls(DisasContext *ctx)
4528 {
4529 /* Always fails locking the cache */
4530 TCGv t0 = tcg_temp_new();
4531 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4532 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4533 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4534 tcg_temp_free(t0);
4535 }
4536
4537 /* dcbz */
4538 static void gen_dcbz(DisasContext *ctx)
4539 {
4540 TCGv tcgv_addr;
4541 TCGv_i32 tcgv_is_dcbzl;
4542 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4543
4544 gen_set_access_type(ctx, ACCESS_CACHE);
4545 /* NIP cannot be restored if the memory exception comes from an helper */
4546 gen_update_nip(ctx, ctx->nip - 4);
4547 tcgv_addr = tcg_temp_new();
4548 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4549
4550 gen_addr_reg_index(ctx, tcgv_addr);
4551 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4552
4553 tcg_temp_free(tcgv_addr);
4554 tcg_temp_free_i32(tcgv_is_dcbzl);
4555 }
4556
4557 /* dst / dstt */
4558 static void gen_dst(DisasContext *ctx)
4559 {
4560 if (rA(ctx->opcode) == 0) {
4561 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4562 } else {
4563 /* interpreted as no-op */
4564 }
4565 }
4566
4567 /* dstst /dststt */
4568 static void gen_dstst(DisasContext *ctx)
4569 {
4570 if (rA(ctx->opcode) == 0) {
4571 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4572 } else {
4573 /* interpreted as no-op */
4574 }
4575
4576 }
4577
4578 /* dss / dssall */
4579 static void gen_dss(DisasContext *ctx)
4580 {
4581 /* interpreted as no-op */
4582 }
4583
4584 /* icbi */
4585 static void gen_icbi(DisasContext *ctx)
4586 {
4587 TCGv t0;
4588 gen_set_access_type(ctx, ACCESS_CACHE);
4589 /* NIP cannot be restored if the memory exception comes from an helper */
4590 gen_update_nip(ctx, ctx->nip - 4);
4591 t0 = tcg_temp_new();
4592 gen_addr_reg_index(ctx, t0);
4593 gen_helper_icbi(cpu_env, t0);
4594 tcg_temp_free(t0);
4595 }
4596
4597 /* Optional: */
4598 /* dcba */
4599 static void gen_dcba(DisasContext *ctx)
4600 {
4601 /* interpreted as no-op */
4602 /* XXX: specification say this is treated as a store by the MMU
4603 * but does not generate any exception
4604 */
4605 }
4606
4607 /*** Segment register manipulation ***/
4608 /* Supervisor only: */
4609
4610 /* mfsr */
4611 static void gen_mfsr(DisasContext *ctx)
4612 {
4613 #if defined(CONFIG_USER_ONLY)
4614 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4615 #else
4616 TCGv t0;
4617 if (unlikely(ctx->pr)) {
4618 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4619 return;
4620 }
4621 t0 = tcg_const_tl(SR(ctx->opcode));
4622 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4623 tcg_temp_free(t0);
4624 #endif
4625 }
4626
4627 /* mfsrin */
4628 static void gen_mfsrin(DisasContext *ctx)
4629 {
4630 #if defined(CONFIG_USER_ONLY)
4631 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4632 #else
4633 TCGv t0;
4634 if (unlikely(ctx->pr)) {
4635 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4636 return;
4637 }
4638 t0 = tcg_temp_new();
4639 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4640 tcg_gen_andi_tl(t0, t0, 0xF);
4641 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4642 tcg_temp_free(t0);
4643 #endif
4644 }
4645
4646 /* mtsr */
4647 static void gen_mtsr(DisasContext *ctx)
4648 {
4649 #if defined(CONFIG_USER_ONLY)
4650 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4651 #else
4652 TCGv t0;
4653 if (unlikely(ctx->pr)) {
4654 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4655 return;
4656 }
4657 t0 = tcg_const_tl(SR(ctx->opcode));
4658 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4659 tcg_temp_free(t0);
4660 #endif
4661 }
4662
4663 /* mtsrin */
4664 static void gen_mtsrin(DisasContext *ctx)
4665 {
4666 #if defined(CONFIG_USER_ONLY)
4667 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4668 #else
4669 TCGv t0;
4670 if (unlikely(ctx->pr)) {
4671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4672 return;
4673 }
4674 t0 = tcg_temp_new();
4675 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4676 tcg_gen_andi_tl(t0, t0, 0xF);
4677 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4678 tcg_temp_free(t0);
4679 #endif
4680 }
4681
4682 #if defined(TARGET_PPC64)
4683 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4684
4685 /* mfsr */
4686 static void gen_mfsr_64b(DisasContext *ctx)
4687 {
4688 #if defined(CONFIG_USER_ONLY)
4689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4690 #else
4691 TCGv t0;
4692 if (unlikely(ctx->pr)) {
4693 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4694 return;
4695 }
4696 t0 = tcg_const_tl(SR(ctx->opcode));
4697 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4698 tcg_temp_free(t0);
4699 #endif
4700 }
4701
4702 /* mfsrin */
4703 static void gen_mfsrin_64b(DisasContext *ctx)
4704 {
4705 #if defined(CONFIG_USER_ONLY)
4706 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4707 #else
4708 TCGv t0;
4709 if (unlikely(ctx->pr)) {
4710 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4711 return;
4712 }
4713 t0 = tcg_temp_new();
4714 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4715 tcg_gen_andi_tl(t0, t0, 0xF);
4716 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4717 tcg_temp_free(t0);
4718 #endif
4719 }
4720
4721 /* mtsr */
4722 static void gen_mtsr_64b(DisasContext *ctx)
4723 {
4724 #if defined(CONFIG_USER_ONLY)
4725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4726 #else
4727 TCGv t0;
4728 if (unlikely(ctx->pr)) {
4729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4730 return;
4731 }
4732 t0 = tcg_const_tl(SR(ctx->opcode));
4733 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4734 tcg_temp_free(t0);
4735 #endif
4736 }
4737
4738 /* mtsrin */
4739 static void gen_mtsrin_64b(DisasContext *ctx)
4740 {
4741 #if defined(CONFIG_USER_ONLY)
4742 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4743 #else
4744 TCGv t0;
4745 if (unlikely(ctx->pr)) {
4746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4747 return;
4748 }
4749 t0 = tcg_temp_new();
4750 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4751 tcg_gen_andi_tl(t0, t0, 0xF);
4752 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4753 tcg_temp_free(t0);
4754 #endif
4755 }
4756
4757 /* slbmte */
4758 static void gen_slbmte(DisasContext *ctx)
4759 {
4760 #if defined(CONFIG_USER_ONLY)
4761 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4762 #else
4763 if (unlikely(ctx->pr)) {
4764 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4765 return;
4766 }
4767 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4768 cpu_gpr[rS(ctx->opcode)]);
4769 #endif
4770 }
4771
4772 static void gen_slbmfee(DisasContext *ctx)
4773 {
4774 #if defined(CONFIG_USER_ONLY)
4775 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4776 #else
4777 if (unlikely(ctx->pr)) {
4778 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4779 return;
4780 }
4781 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4782 cpu_gpr[rB(ctx->opcode)]);
4783 #endif
4784 }
4785
4786 static void gen_slbmfev(DisasContext *ctx)
4787 {
4788 #if defined(CONFIG_USER_ONLY)
4789 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4790 #else
4791 if (unlikely(ctx->pr)) {
4792 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4793 return;
4794 }
4795 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4796 cpu_gpr[rB(ctx->opcode)]);
4797 #endif
4798 }
4799 #endif /* defined(TARGET_PPC64) */
4800
4801 /*** Lookaside buffer management ***/
4802 /* Optional & supervisor only: */
4803
4804 /* tlbia */
4805 static void gen_tlbia(DisasContext *ctx)
4806 {
4807 #if defined(CONFIG_USER_ONLY)
4808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4809 #else
4810 if (unlikely(ctx->pr)) {
4811 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4812 return;
4813 }
4814 gen_helper_tlbia(cpu_env);
4815 #endif
4816 }
4817
4818 /* tlbiel */
4819 static void gen_tlbiel(DisasContext *ctx)
4820 {
4821 #if defined(CONFIG_USER_ONLY)
4822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4823 #else
4824 if (unlikely(ctx->pr)) {
4825 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4826 return;
4827 }
4828 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4829 #endif
4830 }
4831
4832 /* tlbie */
4833 static void gen_tlbie(DisasContext *ctx)
4834 {
4835 #if defined(CONFIG_USER_ONLY)
4836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4837 #else
4838 if (unlikely(ctx->pr)) {
4839 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4840 return;
4841 }
4842 if (NARROW_MODE(ctx)) {
4843 TCGv t0 = tcg_temp_new();
4844 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4845 gen_helper_tlbie(cpu_env, t0);
4846 tcg_temp_free(t0);
4847 } else {
4848 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4849 }
4850 #endif
4851 }
4852
4853 /* tlbsync */
4854 static void gen_tlbsync(DisasContext *ctx)
4855 {
4856 #if defined(CONFIG_USER_ONLY)
4857 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4858 #else
4859 if (unlikely(ctx->pr)) {
4860 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4861 return;
4862 }
4863 /* This has no effect: it should ensure that all previous
4864 * tlbie have completed
4865 */
4866 gen_stop_exception(ctx);
4867 #endif
4868 }
4869
4870 #if defined(TARGET_PPC64)
4871 /* slbia */
4872 static void gen_slbia(DisasContext *ctx)
4873 {
4874 #if defined(CONFIG_USER_ONLY)
4875 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4876 #else
4877 if (unlikely(ctx->pr)) {
4878 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4879 return;
4880 }
4881 gen_helper_slbia(cpu_env);
4882 #endif
4883 }
4884
4885 /* slbie */
4886 static void gen_slbie(DisasContext *ctx)
4887 {
4888 #if defined(CONFIG_USER_ONLY)
4889 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4890 #else
4891 if (unlikely(ctx->pr)) {
4892 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4893 return;
4894 }
4895 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4896 #endif
4897 }
4898 #endif
4899
4900 /*** External control ***/
4901 /* Optional: */
4902
4903 /* eciwx */
4904 static void gen_eciwx(DisasContext *ctx)
4905 {
4906 TCGv t0;
4907 /* Should check EAR[E] ! */
4908 gen_set_access_type(ctx, ACCESS_EXT);
4909 t0 = tcg_temp_new();
4910 gen_addr_reg_index(ctx, t0);
4911 gen_check_align(ctx, t0, 0x03);
4912 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4913 tcg_temp_free(t0);
4914 }
4915
4916 /* ecowx */
4917 static void gen_ecowx(DisasContext *ctx)
4918 {
4919 TCGv t0;
4920 /* Should check EAR[E] ! */
4921 gen_set_access_type(ctx, ACCESS_EXT);
4922 t0 = tcg_temp_new();
4923 gen_addr_reg_index(ctx, t0);
4924 gen_check_align(ctx, t0, 0x03);
4925 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4926 tcg_temp_free(t0);
4927 }
4928
4929 /* PowerPC 601 specific instructions */
4930
4931 /* abs - abs. */
4932 static void gen_abs(DisasContext *ctx)
4933 {
4934 TCGLabel *l1 = gen_new_label();
4935 TCGLabel *l2 = gen_new_label();
4936 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4937 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4938 tcg_gen_br(l2);
4939 gen_set_label(l1);
4940 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4941 gen_set_label(l2);
4942 if (unlikely(Rc(ctx->opcode) != 0))
4943 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4944 }
4945
4946 /* abso - abso. */
4947 static void gen_abso(DisasContext *ctx)
4948 {
4949 TCGLabel *l1 = gen_new_label();
4950 TCGLabel *l2 = gen_new_label();
4951 TCGLabel *l3 = gen_new_label();
4952 /* Start with XER OV disabled, the most likely case */
4953 tcg_gen_movi_tl(cpu_ov, 0);
4954 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4955 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4956 tcg_gen_movi_tl(cpu_ov, 1);
4957 tcg_gen_movi_tl(cpu_so, 1);
4958 tcg_gen_br(l2);
4959 gen_set_label(l1);
4960 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4961 tcg_gen_br(l3);
4962 gen_set_label(l2);
4963 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4964 gen_set_label(l3);
4965 if (unlikely(Rc(ctx->opcode) != 0))
4966 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4967 }
4968
4969 /* clcs */
4970 static void gen_clcs(DisasContext *ctx)
4971 {
4972 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4973 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4974 tcg_temp_free_i32(t0);
4975 /* Rc=1 sets CR0 to an undefined state */
4976 }
4977
4978 /* div - div. */
4979 static void gen_div(DisasContext *ctx)
4980 {
4981 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4982 cpu_gpr[rB(ctx->opcode)]);
4983 if (unlikely(Rc(ctx->opcode) != 0))
4984 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4985 }
4986
4987 /* divo - divo. */
4988 static void gen_divo(DisasContext *ctx)
4989 {
4990 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4991 cpu_gpr[rB(ctx->opcode)]);
4992 if (unlikely(Rc(ctx->opcode) != 0))
4993 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4994 }
4995
4996 /* divs - divs. */
4997 static void gen_divs(DisasContext *ctx)
4998 {
4999 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5000 cpu_gpr[rB(ctx->opcode)]);
5001 if (unlikely(Rc(ctx->opcode) != 0))
5002 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5003 }
5004
5005 /* divso - divso. */
5006 static void gen_divso(DisasContext *ctx)
5007 {
5008 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5009 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5010 if (unlikely(Rc(ctx->opcode) != 0))
5011 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5012 }
5013
5014 /* doz - doz. */
5015 static void gen_doz(DisasContext *ctx)
5016 {
5017 TCGLabel *l1 = gen_new_label();
5018 TCGLabel *l2 = gen_new_label();
5019 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5020 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5021 tcg_gen_br(l2);
5022 gen_set_label(l1);
5023 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5024 gen_set_label(l2);
5025 if (unlikely(Rc(ctx->opcode) != 0))
5026 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5027 }
5028
5029 /* dozo - dozo. */
5030 static void gen_dozo(DisasContext *ctx)
5031 {
5032 TCGLabel *l1 = gen_new_label();
5033 TCGLabel *l2 = gen_new_label();
5034 TCGv t0 = tcg_temp_new();
5035 TCGv t1 = tcg_temp_new();
5036 TCGv t2 = tcg_temp_new();
5037 /* Start with XER OV disabled, the most likely case */
5038 tcg_gen_movi_tl(cpu_ov, 0);
5039 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5040 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5041 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5042 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5043 tcg_gen_andc_tl(t1, t1, t2);
5044 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5045 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5046 tcg_gen_movi_tl(cpu_ov, 1);
5047 tcg_gen_movi_tl(cpu_so, 1);
5048 tcg_gen_br(l2);
5049 gen_set_label(l1);
5050 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5051 gen_set_label(l2);
5052 tcg_temp_free(t0);
5053 tcg_temp_free(t1);
5054 tcg_temp_free(t2);
5055 if (unlikely(Rc(ctx->opcode) != 0))
5056 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5057 }
5058
5059 /* dozi */
5060 static void gen_dozi(DisasContext *ctx)
5061 {
5062 target_long simm = SIMM(ctx->opcode);
5063 TCGLabel *l1 = gen_new_label();
5064 TCGLabel *l2 = gen_new_label();
5065 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5066 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5067 tcg_gen_br(l2);
5068 gen_set_label(l1);
5069 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5070 gen_set_label(l2);
5071 if (unlikely(Rc(ctx->opcode) != 0))
5072 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5073 }
5074
5075 /* lscbx - lscbx. */
5076 static void gen_lscbx(DisasContext *ctx)
5077 {
5078 TCGv t0 = tcg_temp_new();
5079 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5080 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5081 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5082
5083 gen_addr_reg_index(ctx, t0);
5084 /* NIP cannot be restored if the memory exception comes from an helper */
5085 gen_update_nip(ctx, ctx->nip - 4);
5086 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5087 tcg_temp_free_i32(t1);
5088 tcg_temp_free_i32(t2);
5089 tcg_temp_free_i32(t3);
5090 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5091 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5092 if (unlikely(Rc(ctx->opcode) != 0))
5093 gen_set_Rc0(ctx, t0);
5094 tcg_temp_free(t0);
5095 }
5096
5097 /* maskg - maskg. */
5098 static void gen_maskg(DisasContext *ctx)
5099 {
5100 TCGLabel *l1 = gen_new_label();
5101 TCGv t0 = tcg_temp_new();
5102 TCGv t1 = tcg_temp_new();
5103 TCGv t2 = tcg_temp_new();
5104 TCGv t3 = tcg_temp_new();
5105 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5106 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5107 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5108 tcg_gen_addi_tl(t2, t0, 1);
5109 tcg_gen_shr_tl(t2, t3, t2);
5110 tcg_gen_shr_tl(t3, t3, t1);
5111 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5112 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5113 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5114 gen_set_label(l1);
5115 tcg_temp_free(t0);
5116 tcg_temp_free(t1);
5117 tcg_temp_free(t2);
5118 tcg_temp_free(t3);
5119 if (unlikely(Rc(ctx->opcode) != 0))
5120 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5121 }
5122
5123 /* maskir - maskir. */
5124 static void gen_maskir(DisasContext *ctx)
5125 {
5126 TCGv t0 = tcg_temp_new();
5127 TCGv t1 = tcg_temp_new();
5128 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5129 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5130 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5131 tcg_temp_free(t0);
5132 tcg_temp_free(t1);
5133 if (unlikely(Rc(ctx->opcode) != 0))
5134 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5135 }
5136
5137 /* mul - mul. */
5138 static void gen_mul(DisasContext *ctx)
5139 {
5140 TCGv_i64 t0 = tcg_temp_new_i64();
5141 TCGv_i64 t1 = tcg_temp_new_i64();
5142 TCGv t2 = tcg_temp_new();
5143 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5144 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5145 tcg_gen_mul_i64(t0, t0, t1);
5146 tcg_gen_trunc_i64_tl(t2, t0);
5147 gen_store_spr(SPR_MQ, t2);
5148 tcg_gen_shri_i64(t1, t0, 32);
5149 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5150 tcg_temp_free_i64(t0);
5151 tcg_temp_free_i64(t1);
5152 tcg_temp_free(t2);
5153 if (unlikely(Rc(ctx->opcode) != 0))
5154 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5155 }
5156
5157 /* mulo - mulo. */
5158 static void gen_mulo(DisasContext *ctx)
5159 {
5160 TCGLabel *l1 = gen_new_label();
5161 TCGv_i64 t0 = tcg_temp_new_i64();
5162 TCGv_i64 t1 = tcg_temp_new_i64();
5163 TCGv t2 = tcg_temp_new();
5164 /* Start with XER OV disabled, the most likely case */
5165 tcg_gen_movi_tl(cpu_ov, 0);
5166 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5167 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5168 tcg_gen_mul_i64(t0, t0, t1);
5169 tcg_gen_trunc_i64_tl(t2, t0);
5170 gen_store_spr(SPR_MQ, t2);
5171 tcg_gen_shri_i64(t1, t0, 32);
5172 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5173 tcg_gen_ext32s_i64(t1, t0);
5174 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5175 tcg_gen_movi_tl(cpu_ov, 1);
5176 tcg_gen_movi_tl(cpu_so, 1);
5177 gen_set_label(l1);
5178 tcg_temp_free_i64(t0);
5179 tcg_temp_free_i64(t1);
5180 tcg_temp_free(t2);
5181 if (unlikely(Rc(ctx->opcode) != 0))
5182 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5183 }
5184
5185 /* nabs - nabs. */
5186 static void gen_nabs(DisasContext *ctx)
5187 {
5188 TCGLabel *l1 = gen_new_label();
5189 TCGLabel *l2 = gen_new_label();
5190 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5191 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5192 tcg_gen_br(l2);
5193 gen_set_label(l1);
5194 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5195 gen_set_label(l2);
5196 if (unlikely(Rc(ctx->opcode) != 0))
5197 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5198 }
5199
5200 /* nabso - nabso. */
5201 static void gen_nabso(DisasContext *ctx)
5202 {
5203 TCGLabel *l1 = gen_new_label();
5204 TCGLabel *l2 = gen_new_label();
5205 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5206 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5207 tcg_gen_br(l2);
5208 gen_set_label(l1);
5209 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5210 gen_set_label(l2);
5211 /* nabs never overflows */
5212 tcg_gen_movi_tl(cpu_ov, 0);
5213 if (unlikely(Rc(ctx->opcode) != 0))
5214 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5215 }
5216
5217 /* rlmi - rlmi. */
5218 static void gen_rlmi(DisasContext *ctx)
5219 {
5220 uint32_t mb = MB(ctx->opcode);
5221 uint32_t me = ME(ctx->opcode);
5222 TCGv t0 = tcg_temp_new();
5223 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5224 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5225 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5226 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5227 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5228 tcg_temp_free(t0);
5229 if (unlikely(Rc(ctx->opcode) != 0))
5230 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5231 }
5232
5233 /* rrib - rrib. */
5234 static void gen_rrib(DisasContext *ctx)
5235 {
5236 TCGv t0 = tcg_temp_new();
5237 TCGv t1 = tcg_temp_new();
5238 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5239 tcg_gen_movi_tl(t1, 0x80000000);
5240 tcg_gen_shr_tl(t1, t1, t0);
5241 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5242 tcg_gen_and_tl(t0, t0, t1);
5243 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5244 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5245 tcg_temp_free(t0);
5246 tcg_temp_free(t1);
5247 if (unlikely(Rc(ctx->opcode) != 0))
5248 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5249 }
5250
5251 /* sle - sle. */
5252 static void gen_sle(DisasContext *ctx)
5253 {
5254 TCGv t0 = tcg_temp_new();
5255 TCGv t1 = tcg_temp_new();
5256 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5257 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5258 tcg_gen_subfi_tl(t1, 32, t1);
5259 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5260 tcg_gen_or_tl(t1, t0, t1);
5261 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5262 gen_store_spr(SPR_MQ, t1);
5263 tcg_temp_free(t0);
5264 tcg_temp_free(t1);
5265 if (unlikely(Rc(ctx->opcode) != 0))
5266 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5267 }
5268
5269 /* sleq - sleq. */
5270 static void gen_sleq(DisasContext *ctx)
5271 {
5272 TCGv t0 = tcg_temp_new();
5273 TCGv t1 = tcg_temp_new();
5274 TCGv t2 = tcg_temp_new();
5275 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5276 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5277 tcg_gen_shl_tl(t2, t2, t0);
5278 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5279 gen_load_spr(t1, SPR_MQ);
5280 gen_store_spr(SPR_MQ, t0);
5281 tcg_gen_and_tl(t0, t0, t2);
5282 tcg_gen_andc_tl(t1, t1, t2);
5283 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5284 tcg_temp_free(t0);
5285 tcg_temp_free(t1);
5286 tcg_temp_free(t2);
5287 if (unlikely(Rc(ctx->opcode) != 0))
5288 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5289 }
5290
5291 /* sliq - sliq. */
5292 static void gen_sliq(DisasContext *ctx)
5293 {
5294 int sh = SH(ctx->opcode);
5295 TCGv t0 = tcg_temp_new();
5296 TCGv t1 = tcg_temp_new();
5297 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5298 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5299 tcg_gen_or_tl(t1, t0, t1);
5300 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5301 gen_store_spr(SPR_MQ, t1);
5302 tcg_temp_free(t0);
5303 tcg_temp_free(t1);
5304 if (unlikely(Rc(ctx->opcode) != 0))
5305 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5306 }
5307
5308 /* slliq - slliq. */
5309 static void gen_slliq(DisasContext *ctx)
5310 {
5311 int sh = SH(ctx->opcode);
5312 TCGv t0 = tcg_temp_new();
5313 TCGv t1 = tcg_temp_new();
5314 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5315 gen_load_spr(t1, SPR_MQ);
5316 gen_store_spr(SPR_MQ, t0);
5317 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5318 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5319 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5320 tcg_temp_free(t0);
5321 tcg_temp_free(t1);
5322 if (unlikely(Rc(ctx->opcode) != 0))
5323 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5324 }
5325
5326 /* sllq - sllq. */
5327 static void gen_sllq(DisasContext *ctx)
5328 {
5329 TCGLabel *l1 = gen_new_label();
5330 TCGLabel *l2 = gen_new_label();
5331 TCGv t0 = tcg_temp_local_new();
5332 TCGv t1 = tcg_temp_local_new();
5333 TCGv t2 = tcg_temp_local_new();
5334 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5335 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5336 tcg_gen_shl_tl(t1, t1, t2);
5337 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5338 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5339 gen_load_spr(t0, SPR_MQ);
5340 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5341 tcg_gen_br(l2);
5342 gen_set_label(l1);
5343 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5344 gen_load_spr(t2, SPR_MQ);
5345 tcg_gen_andc_tl(t1, t2, t1);
5346 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5347 gen_set_label(l2);
5348 tcg_temp_free(t0);
5349 tcg_temp_free(t1);
5350 tcg_temp_free(t2);
5351 if (unlikely(Rc(ctx->opcode) != 0))
5352 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5353 }
5354
5355 /* slq - slq. */
5356 static void gen_slq(DisasContext *ctx)
5357 {
5358 TCGLabel *l1 = gen_new_label();
5359 TCGv t0 = tcg_temp_new();
5360 TCGv t1 = tcg_temp_new();
5361 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5362 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5363 tcg_gen_subfi_tl(t1, 32, t1);
5364 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5365 tcg_gen_or_tl(t1, t0, t1);
5366 gen_store_spr(SPR_MQ, t1);
5367 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5368 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5369 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5370 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5371 gen_set_label(l1);
5372 tcg_temp_free(t0);
5373 tcg_temp_free(t1);
5374 if (unlikely(Rc(ctx->opcode) != 0))
5375 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5376 }
5377
5378 /* sraiq - sraiq. */
5379 static void gen_sraiq(DisasContext *ctx)
5380 {
5381 int sh = SH(ctx->opcode);
5382 TCGLabel *l1 = gen_new_label();
5383 TCGv t0 = tcg_temp_new();
5384 TCGv t1 = tcg_temp_new();
5385 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5386 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5387 tcg_gen_or_tl(t0, t0, t1);
5388 gen_store_spr(SPR_MQ, t0);
5389 tcg_gen_movi_tl(cpu_ca, 0);
5390 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5391 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5392 tcg_gen_movi_tl(cpu_ca, 1);
5393 gen_set_label(l1);
5394 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5395 tcg_temp_free(t0);
5396 tcg_temp_free(t1);
5397 if (unlikely(Rc(ctx->opcode) != 0))
5398 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5399 }
5400
5401 /* sraq - sraq. */
5402 static void gen_sraq(DisasContext *ctx)
5403 {
5404 TCGLabel *l1 = gen_new_label();
5405 TCGLabel *l2 = gen_new_label();
5406 TCGv t0 = tcg_temp_new();
5407 TCGv t1 = tcg_temp_local_new();
5408 TCGv t2 = tcg_temp_local_new();
5409 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5410 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5411 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5412 tcg_gen_subfi_tl(t2, 32, t2);
5413 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5414 tcg_gen_or_tl(t0, t0, t2);
5415 gen_store_spr(SPR_MQ, t0);
5416 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5417 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5418 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5419 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5420 gen_set_label(l1);
5421 tcg_temp_free(t0);
5422 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5423 tcg_gen_movi_tl(cpu_ca, 0);
5424 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5425 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5426 tcg_gen_movi_tl(cpu_ca, 1);
5427 gen_set_label(l2);
5428 tcg_temp_free(t1);
5429 tcg_temp_free(t2);
5430 if (unlikely(Rc(ctx->opcode) != 0))
5431 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5432 }
5433
5434 /* sre - sre. */
5435 static void gen_sre(DisasContext *ctx)
5436 {
5437 TCGv t0 = tcg_temp_new();
5438 TCGv t1 = tcg_temp_new();
5439 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5440 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5441 tcg_gen_subfi_tl(t1, 32, t1);
5442 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5443 tcg_gen_or_tl(t1, t0, t1);
5444 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5445 gen_store_spr(SPR_MQ, t1);
5446 tcg_temp_free(t0);
5447 tcg_temp_free(t1);
5448 if (unlikely(Rc(ctx->opcode) != 0))
5449 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5450 }
5451
5452 /* srea - srea. */
5453 static void gen_srea(DisasContext *ctx)
5454 {
5455 TCGv t0 = tcg_temp_new();
5456 TCGv t1 = tcg_temp_new();
5457 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5458 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5459 gen_store_spr(SPR_MQ, t0);
5460 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5461 tcg_temp_free(t0);
5462 tcg_temp_free(t1);
5463 if (unlikely(Rc(ctx->opcode) != 0))
5464 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5465 }
5466
5467 /* sreq */
5468 static void gen_sreq(DisasContext *ctx)
5469 {
5470 TCGv t0 = tcg_temp_new();
5471 TCGv t1 = tcg_temp_new();
5472 TCGv t2 = tcg_temp_new();
5473 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5474 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5475 tcg_gen_shr_tl(t1, t1, t0);
5476 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5477 gen_load_spr(t2, SPR_MQ);
5478 gen_store_spr(SPR_MQ, t0);
5479 tcg_gen_and_tl(t0, t0, t1);
5480 tcg_gen_andc_tl(t2, t2, t1);
5481 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5482 tcg_temp_free(t0);
5483 tcg_temp_free(t1);
5484 tcg_temp_free(t2);
5485 if (unlikely(Rc(ctx->opcode) != 0))
5486 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5487 }
5488
5489 /* sriq */
5490 static void gen_sriq(DisasContext *ctx)
5491 {
5492 int sh = SH(ctx->opcode);
5493 TCGv t0 = tcg_temp_new();
5494 TCGv t1 = tcg_temp_new();
5495 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5496 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5497 tcg_gen_or_tl(t1, t0, t1);
5498 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5499 gen_store_spr(SPR_MQ, t1);
5500 tcg_temp_free(t0);
5501 tcg_temp_free(t1);
5502 if (unlikely(Rc(ctx->opcode) != 0))
5503 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5504 }
5505
5506 /* srliq */
5507 static void gen_srliq(DisasContext *ctx)
5508 {
5509 int sh = SH(ctx->opcode);
5510 TCGv t0 = tcg_temp_new();
5511 TCGv t1 = tcg_temp_new();
5512 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5513 gen_load_spr(t1, SPR_MQ);
5514 gen_store_spr(SPR_MQ, t0);
5515 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5516 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5517 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5518 tcg_temp_free(t0);
5519 tcg_temp_free(t1);
5520 if (unlikely(Rc(ctx->opcode) != 0))
5521 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5522 }
5523
5524 /* srlq */
5525 static void gen_srlq(DisasContext *ctx)
5526 {
5527 TCGLabel *l1 = gen_new_label();
5528 TCGLabel *l2 = gen_new_label();
5529 TCGv t0 = tcg_temp_local_new();
5530 TCGv t1 = tcg_temp_local_new();
5531 TCGv t2 = tcg_temp_local_new();
5532 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5533 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5534 tcg_gen_shr_tl(t2, t1, t2);
5535 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5536 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5537 gen_load_spr(t0, SPR_MQ);
5538 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5539 tcg_gen_br(l2);
5540 gen_set_label(l1);
5541 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5542 tcg_gen_and_tl(t0, t0, t2);
5543 gen_load_spr(t1, SPR_MQ);
5544 tcg_gen_andc_tl(t1, t1, t2);
5545 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5546 gen_set_label(l2);
5547 tcg_temp_free(t0);
5548 tcg_temp_free(t1);
5549 tcg_temp_free(t2);
5550 if (unlikely(Rc(ctx->opcode) != 0))
5551 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5552 }
5553
5554 /* srq */
5555 static void gen_srq(DisasContext *ctx)
5556 {
5557 TCGLabel *l1 = gen_new_label();
5558 TCGv t0 = tcg_temp_new();
5559 TCGv t1 = tcg_temp_new();
5560 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5561 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5562 tcg_gen_subfi_tl(t1, 32, t1);
5563 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5564 tcg_gen_or_tl(t1, t0, t1);
5565 gen_store_spr(SPR_MQ, t1);
5566 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5567 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5568 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5569 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5570 gen_set_label(l1);
5571 tcg_temp_free(t0);
5572 tcg_temp_free(t1);
5573 if (unlikely(Rc(ctx->opcode) != 0))
5574 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5575 }
5576
5577 /* PowerPC 602 specific instructions */
5578
5579 /* dsa */
5580 static void gen_dsa(DisasContext *ctx)
5581 {
5582 /* XXX: TODO */
5583 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5584 }
5585
5586 /* esa */
5587 static void gen_esa(DisasContext *ctx)
5588 {
5589 /* XXX: TODO */
5590 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5591 }
5592
5593 /* mfrom */
5594 static void gen_mfrom(DisasContext *ctx)
5595 {
5596 #if defined(CONFIG_USER_ONLY)
5597 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5598 #else
5599 if (unlikely(ctx->pr)) {
5600 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5601 return;
5602 }
5603 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5604 #endif
5605 }
5606
5607 /* 602 - 603 - G2 TLB management */
5608
5609 /* tlbld */
5610 static void gen_tlbld_6xx(DisasContext *ctx)
5611 {
5612 #if defined(CONFIG_USER_ONLY)
5613 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5614 #else
5615 if (unlikely(ctx->pr)) {
5616 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5617 return;
5618 }
5619 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5620 #endif
5621 }
5622
5623 /* tlbli */
5624 static void gen_tlbli_6xx(DisasContext *ctx)
5625 {
5626 #if defined(CONFIG_USER_ONLY)
5627 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5628 #else
5629 if (unlikely(ctx->pr)) {
5630 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5631 return;
5632 }
5633 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5634 #endif
5635 }
5636
5637 /* 74xx TLB management */
5638
5639 /* tlbld */
5640 static void gen_tlbld_74xx(DisasContext *ctx)
5641 {
5642 #if defined(CONFIG_USER_ONLY)
5643 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5644 #else
5645 if (unlikely(ctx->pr)) {
5646 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5647 return;
5648 }
5649 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5650 #endif
5651 }
5652
5653 /* tlbli */
5654 static void gen_tlbli_74xx(DisasContext *ctx)
5655 {
5656 #if defined(CONFIG_USER_ONLY)
5657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5658 #else
5659 if (unlikely(ctx->pr)) {
5660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5661 return;
5662 }
5663 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5664 #endif
5665 }
5666
5667 /* POWER instructions not in PowerPC 601 */
5668
5669 /* clf */
5670 static void gen_clf(DisasContext *ctx)
5671 {
5672 /* Cache line flush: implemented as no-op */
5673 }
5674
5675 /* cli */
5676 static void gen_cli(DisasContext *ctx)
5677 {
5678 /* Cache line invalidate: privileged and treated as no-op */
5679 #if defined(CONFIG_USER_ONLY)
5680 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5681 #else
5682 if (unlikely(ctx->pr)) {
5683 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5684 return;
5685 }
5686 #endif
5687 }
5688
5689 /* dclst */
5690 static void gen_dclst(DisasContext *ctx)
5691 {
5692 /* Data cache line store: treated as no-op */
5693 }
5694
5695 static void gen_mfsri(DisasContext *ctx)
5696 {
5697 #if defined(CONFIG_USER_ONLY)
5698 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5699 #else
5700 int ra = rA(ctx->opcode);
5701 int rd = rD(ctx->opcode);
5702 TCGv t0;
5703 if (unlikely(ctx->pr)) {
5704 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5705 return;
5706 }
5707 t0 = tcg_temp_new();
5708 gen_addr_reg_index(ctx, t0);
5709 tcg_gen_shri_tl(t0, t0, 28);
5710 tcg_gen_andi_tl(t0, t0, 0xF);
5711 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5712 tcg_temp_free(t0);
5713 if (ra != 0 && ra != rd)
5714 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5715 #endif
5716 }
5717
5718 static void gen_rac(DisasContext *ctx)
5719 {
5720 #if defined(CONFIG_USER_ONLY)
5721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5722 #else
5723 TCGv t0;
5724 if (unlikely(ctx->pr)) {
5725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5726 return;
5727 }
5728 t0 = tcg_temp_new();
5729 gen_addr_reg_index(ctx, t0);
5730 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5731 tcg_temp_free(t0);
5732 #endif
5733 }
5734
5735 static void gen_rfsvc(DisasContext *ctx)
5736 {
5737 #if defined(CONFIG_USER_ONLY)
5738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5739 #else
5740 if (unlikely(ctx->pr)) {
5741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5742 return;
5743 }
5744 gen_helper_rfsvc(cpu_env);
5745 gen_sync_exception(ctx);
5746 #endif
5747 }
5748
5749 /* svc is not implemented for now */
5750
5751 /* POWER2 specific instructions */
5752 /* Quad manipulation (load/store two floats at a time) */
5753
5754 /* lfq */
5755 static void gen_lfq(DisasContext *ctx)
5756 {
5757 int rd = rD(ctx->opcode);
5758 TCGv t0;
5759 gen_set_access_type(ctx, ACCESS_FLOAT);
5760 t0 = tcg_temp_new();
5761 gen_addr_imm_index(ctx, t0, 0);
5762 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5763 gen_addr_add(ctx, t0, t0, 8);
5764 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5765 tcg_temp_free(t0);
5766 }
5767
5768 /* lfqu */
5769 static void gen_lfqu(DisasContext *ctx)
5770 {
5771 int ra = rA(ctx->opcode);
5772 int rd = rD(ctx->opcode);
5773 TCGv t0, t1;
5774 gen_set_access_type(ctx, ACCESS_FLOAT);
5775 t0 = tcg_temp_new();
5776 t1 = tcg_temp_new();
5777 gen_addr_imm_index(ctx, t0, 0);
5778 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5779 gen_addr_add(ctx, t1, t0, 8);
5780 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5781 if (ra != 0)
5782 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5783 tcg_temp_free(t0);
5784 tcg_temp_free(t1);
5785 }
5786
5787 /* lfqux */
5788 static void gen_lfqux(DisasContext *ctx)
5789 {
5790 int ra = rA(ctx->opcode);
5791 int rd = rD(ctx->opcode);
5792 gen_set_access_type(ctx, ACCESS_FLOAT);
5793 TCGv t0, t1;
5794 t0 = tcg_temp_new();
5795 gen_addr_reg_index(ctx, t0);
5796 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5797 t1 = tcg_temp_new();
5798 gen_addr_add(ctx, t1, t0, 8);
5799 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5800 tcg_temp_free(t1);
5801 if (ra != 0)
5802 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5803 tcg_temp_free(t0);
5804 }
5805
5806 /* lfqx */
5807 static void gen_lfqx(DisasContext *ctx)
5808 {
5809 int rd = rD(ctx->opcode);
5810 TCGv t0;
5811 gen_set_access_type(ctx, ACCESS_FLOAT);
5812 t0 = tcg_temp_new();
5813 gen_addr_reg_index(ctx, t0);
5814 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5815 gen_addr_add(ctx, t0, t0, 8);
5816 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5817 tcg_temp_free(t0);
5818 }
5819
5820 /* stfq */
5821 static void gen_stfq(DisasContext *ctx)
5822 {
5823 int rd = rD(ctx->opcode);
5824 TCGv t0;
5825 gen_set_access_type(ctx, ACCESS_FLOAT);
5826 t0 = tcg_temp_new();
5827 gen_addr_imm_index(ctx, t0, 0);
5828 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5829 gen_addr_add(ctx, t0, t0, 8);
5830 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5831 tcg_temp_free(t0);
5832 }
5833
5834 /* stfqu */
5835 static void gen_stfqu(DisasContext *ctx)
5836 {
5837 int ra = rA(ctx->opcode);
5838 int rd = rD(ctx->opcode);
5839 TCGv t0, t1;
5840 gen_set_access_type(ctx, ACCESS_FLOAT);
5841 t0 = tcg_temp_new();
5842 gen_addr_imm_index(ctx, t0, 0);
5843 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5844 t1 = tcg_temp_new();
5845 gen_addr_add(ctx, t1, t0, 8);
5846 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5847 tcg_temp_free(t1);
5848 if (ra != 0)
5849 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5850 tcg_temp_free(t0);
5851 }
5852
5853 /* stfqux */
5854 static void gen_stfqux(DisasContext *ctx)
5855 {
5856 int ra = rA(ctx->opcode);
5857 int rd = rD(ctx->opcode);
5858 TCGv t0, t1;
5859 gen_set_access_type(ctx, ACCESS_FLOAT);
5860 t0 = tcg_temp_new();
5861 gen_addr_reg_index(ctx, t0);
5862 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5863 t1 = tcg_temp_new();
5864 gen_addr_add(ctx, t1, t0, 8);
5865 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5866 tcg_temp_free(t1);
5867 if (ra != 0)
5868 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5869 tcg_temp_free(t0);
5870 }
5871
5872 /* stfqx */
5873 static void gen_stfqx(DisasContext *ctx)
5874 {
5875 int rd = rD(ctx->opcode);
5876 TCGv t0;
5877 gen_set_access_type(ctx, ACCESS_FLOAT);
5878 t0 = tcg_temp_new();
5879 gen_addr_reg_index(ctx, t0);
5880 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5881 gen_addr_add(ctx, t0, t0, 8);
5882 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5883 tcg_temp_free(t0);
5884 }
5885
5886 /* BookE specific instructions */
5887
5888 /* XXX: not implemented on 440 ? */
5889 static void gen_mfapidi(DisasContext *ctx)
5890 {
5891 /* XXX: TODO */
5892 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5893 }
5894
5895 /* XXX: not implemented on 440 ? */
5896 static void gen_tlbiva(DisasContext *ctx)
5897 {
5898 #if defined(CONFIG_USER_ONLY)
5899 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5900 #else
5901 TCGv t0;
5902 if (unlikely(ctx->pr)) {
5903 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5904 return;
5905 }
5906 t0 = tcg_temp_new();
5907 gen_addr_reg_index(ctx, t0);
5908 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5909 tcg_temp_free(t0);
5910 #endif
5911 }
5912
5913 /* All 405 MAC instructions are translated here */
5914 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5915 int ra, int rb, int rt, int Rc)
5916 {
5917 TCGv t0, t1;
5918
5919 t0 = tcg_temp_local_new();
5920 t1 = tcg_temp_local_new();
5921
5922 switch (opc3 & 0x0D) {
5923 case 0x05:
5924 /* macchw - macchw. - macchwo - macchwo. */
5925 /* macchws - macchws. - macchwso - macchwso. */
5926 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5927 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5928 /* mulchw - mulchw. */
5929 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5930 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5931 tcg_gen_ext16s_tl(t1, t1);
5932 break;
5933 case 0x04:
5934 /* macchwu - macchwu. - macchwuo - macchwuo. */
5935 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5936 /* mulchwu - mulchwu. */
5937 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5938 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5939 tcg_gen_ext16u_tl(t1, t1);
5940 break;
5941 case 0x01:
5942 /* machhw - machhw. - machhwo - machhwo. */
5943 /* machhws - machhws. - machhwso - machhwso. */
5944 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5945 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5946 /* mulhhw - mulhhw. */
5947 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5948 tcg_gen_ext16s_tl(t0, t0);
5949 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5950 tcg_gen_ext16s_tl(t1, t1);
5951 break;
5952 case 0x00:
5953 /* machhwu - machhwu. - machhwuo - machhwuo. */
5954 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5955 /* mulhhwu - mulhhwu. */
5956 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5957 tcg_gen_ext16u_tl(t0, t0);
5958 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5959 tcg_gen_ext16u_tl(t1, t1);
5960 break;
5961 case 0x0D:
5962 /* maclhw - maclhw. - maclhwo - maclhwo. */
5963 /* maclhws - maclhws. - maclhwso - maclhwso. */
5964 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5965 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5966 /* mullhw - mullhw. */
5967 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5968 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5969 break;
5970 case 0x0C:
5971 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5972 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5973 /* mullhwu - mullhwu. */
5974 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5975 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5976 break;
5977 }
5978 if (opc2 & 0x04) {
5979 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5980 tcg_gen_mul_tl(t1, t0, t1);
5981 if (opc2 & 0x02) {
5982 /* nmultiply-and-accumulate (0x0E) */
5983 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5984 } else {
5985 /* multiply-and-accumulate (0x0C) */
5986 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5987 }
5988
5989 if (opc3 & 0x12) {
5990 /* Check overflow and/or saturate */
5991 TCGLabel *l1 = gen_new_label();
5992
5993 if (opc3 & 0x10) {
5994 /* Start with XER OV disabled, the most likely case */
5995 tcg_gen_movi_tl(cpu_ov, 0);
5996 }
5997 if (opc3 & 0x01) {
5998 /* Signed */
5999 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6000 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6001 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6002 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6003 if (opc3 & 0x02) {
6004 /* Saturate */
6005 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6006 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6007 }
6008 } else {
6009 /* Unsigned */
6010 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6011 if (opc3 & 0x02) {
6012 /* Saturate */
6013 tcg_gen_movi_tl(t0, UINT32_MAX);
6014 }
6015 }
6016 if (opc3 & 0x10) {
6017 /* Check overflow */
6018 tcg_gen_movi_tl(cpu_ov, 1);
6019 tcg_gen_movi_tl(cpu_so, 1);
6020 }
6021 gen_set_label(l1);
6022 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6023 }
6024 } else {
6025 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6026 }
6027 tcg_temp_free(t0);
6028 tcg_temp_free(t1);
6029 if (unlikely(Rc) != 0) {
6030 /* Update Rc0 */
6031 gen_set_Rc0(ctx, cpu_gpr[rt]);
6032 }
6033 }
6034
6035 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6036 static void glue(gen_, name)(DisasContext *ctx) \
6037 { \
6038 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6039 rD(ctx->opcode), Rc(ctx->opcode)); \
6040 }
6041
6042 /* macchw - macchw. */
6043 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6044 /* macchwo - macchwo. */
6045 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6046 /* macchws - macchws. */
6047 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6048 /* macchwso - macchwso. */
6049 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6050 /* macchwsu - macchwsu. */
6051 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6052 /* macchwsuo - macchwsuo. */
6053 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6054 /* macchwu - macchwu. */
6055 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6056 /* macchwuo - macchwuo. */
6057 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6058 /* machhw - machhw. */
6059 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6060 /* machhwo - machhwo. */
6061 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6062 /* machhws - machhws. */
6063 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6064 /* machhwso - machhwso. */
6065 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6066 /* machhwsu - machhwsu. */
6067 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6068 /* machhwsuo - machhwsuo. */
6069 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6070 /* machhwu - machhwu. */
6071 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6072 /* machhwuo - machhwuo. */
6073 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6074 /* maclhw - maclhw. */
6075 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6076 /* maclhwo - maclhwo. */
6077 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6078 /* maclhws - maclhws. */
6079 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6080 /* maclhwso - maclhwso. */
6081 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6082 /* maclhwu - maclhwu. */
6083 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6084 /* maclhwuo - maclhwuo. */
6085 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6086 /* maclhwsu - maclhwsu. */
6087 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6088 /* maclhwsuo - maclhwsuo. */
6089 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6090 /* nmacchw - nmacchw. */
6091 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6092 /* nmacchwo - nmacchwo. */
6093 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6094 /* nmacchws - nmacchws. */
6095 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6096 /* nmacchwso - nmacchwso. */
6097 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6098 /* nmachhw - nmachhw. */
6099 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6100 /* nmachhwo - nmachhwo. */
6101 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6102 /* nmachhws - nmachhws. */
6103 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6104 /* nmachhwso - nmachhwso. */
6105 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6106 /* nmaclhw - nmaclhw. */
6107 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6108 /* nmaclhwo - nmaclhwo. */
6109 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6110 /* nmaclhws - nmaclhws. */
6111 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6112 /* nmaclhwso - nmaclhwso. */
6113 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6114
6115 /* mulchw - mulchw. */
6116 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6117 /* mulchwu - mulchwu. */
6118 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6119 /* mulhhw - mulhhw. */
6120 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6121 /* mulhhwu - mulhhwu. */
6122 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6123 /* mullhw - mullhw. */
6124 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6125 /* mullhwu - mullhwu. */
6126 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6127
6128 /* mfdcr */
6129 static void gen_mfdcr(DisasContext *ctx)
6130 {
6131 #if defined(CONFIG_USER_ONLY)
6132 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6133 #else
6134 TCGv dcrn;
6135 if (unlikely(ctx->pr)) {
6136 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6137 return;
6138 }
6139 /* NIP cannot be restored if the memory exception comes from an helper */
6140 gen_update_nip(ctx, ctx->nip - 4);
6141 dcrn = tcg_const_tl(SPR(ctx->opcode));
6142 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6143 tcg_temp_free(dcrn);
6144 #endif
6145 }
6146
6147 /* mtdcr */
6148 static void gen_mtdcr(DisasContext *ctx)
6149 {
6150 #if defined(CONFIG_USER_ONLY)
6151 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6152 #else
6153 TCGv dcrn;
6154 if (unlikely(ctx->pr)) {
6155 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6156 return;
6157 }
6158 /* NIP cannot be restored if the memory exception comes from an helper */
6159 gen_update_nip(ctx, ctx->nip - 4);
6160 dcrn = tcg_const_tl(SPR(ctx->opcode));
6161 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6162 tcg_temp_free(dcrn);
6163 #endif
6164 }
6165
6166 /* mfdcrx */
6167 /* XXX: not implemented on 440 ? */
6168 static void gen_mfdcrx(DisasContext *ctx)
6169 {
6170 #if defined(CONFIG_USER_ONLY)
6171 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6172 #else
6173 if (unlikely(ctx->pr)) {
6174 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6175 return;
6176 }
6177 /* NIP cannot be restored if the memory exception comes from an helper */
6178 gen_update_nip(ctx, ctx->nip - 4);
6179 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6180 cpu_gpr[rA(ctx->opcode)]);
6181 /* Note: Rc update flag set leads to undefined state of Rc0 */
6182 #endif
6183 }
6184
6185 /* mtdcrx */
6186 /* XXX: not implemented on 440 ? */
6187 static void gen_mtdcrx(DisasContext *ctx)
6188 {
6189 #if defined(CONFIG_USER_ONLY)
6190 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6191 #else
6192 if (unlikely(ctx->pr)) {
6193 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6194 return;
6195 }
6196 /* NIP cannot be restored if the memory exception comes from an helper */
6197 gen_update_nip(ctx, ctx->nip - 4);
6198 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6199 cpu_gpr[rS(ctx->opcode)]);
6200 /* Note: Rc update flag set leads to undefined state of Rc0 */
6201 #endif
6202 }
6203
6204 /* mfdcrux (PPC 460) : user-mode access to DCR */
6205 static void gen_mfdcrux(DisasContext *ctx)
6206 {
6207 /* NIP cannot be restored if the memory exception comes from an helper */
6208 gen_update_nip(ctx, ctx->nip - 4);
6209 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6210 cpu_gpr[rA(ctx->opcode)]);
6211 /* Note: Rc update flag set leads to undefined state of Rc0 */
6212 }
6213
6214 /* mtdcrux (PPC 460) : user-mode access to DCR */
6215 static void gen_mtdcrux(DisasContext *ctx)
6216 {
6217 /* NIP cannot be restored if the memory exception comes from an helper */
6218 gen_update_nip(ctx, ctx->nip - 4);
6219 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6220 cpu_gpr[rS(ctx->opcode)]);
6221 /* Note: Rc update flag set leads to undefined state of Rc0 */
6222 }
6223
6224 /* dccci */
6225 static void gen_dccci(DisasContext *ctx)
6226 {
6227 #if defined(CONFIG_USER_ONLY)
6228 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6229 #else
6230 if (unlikely(ctx->pr)) {
6231 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6232 return;
6233 }
6234 /* interpreted as no-op */
6235 #endif
6236 }
6237
6238 /* dcread */
6239 static void gen_dcread(DisasContext *ctx)
6240 {
6241 #if defined(CONFIG_USER_ONLY)
6242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6243 #else
6244 TCGv EA, val;
6245 if (unlikely(ctx->pr)) {
6246 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6247 return;
6248 }
6249 gen_set_access_type(ctx, ACCESS_CACHE);
6250 EA = tcg_temp_new();
6251 gen_addr_reg_index(ctx, EA);
6252 val = tcg_temp_new();
6253 gen_qemu_ld32u(ctx, val, EA);
6254 tcg_temp_free(val);
6255 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6256 tcg_temp_free(EA);
6257 #endif
6258 }
6259
6260 /* icbt */
6261 static void gen_icbt_40x(DisasContext *ctx)
6262 {
6263 /* interpreted as no-op */
6264 /* XXX: specification say this is treated as a load by the MMU
6265 * but does not generate any exception
6266 */
6267 }
6268
6269 /* iccci */
6270 static void gen_iccci(DisasContext *ctx)
6271 {
6272 #if defined(CONFIG_USER_ONLY)
6273 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6274 #else
6275 if (unlikely(ctx->pr)) {
6276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6277 return;
6278 }
6279 /* interpreted as no-op */
6280 #endif
6281 }
6282
6283 /* icread */
6284 static void gen_icread(DisasContext *ctx)
6285 {
6286 #if defined(CONFIG_USER_ONLY)
6287 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6288 #else
6289 if (unlikely(ctx->pr)) {
6290 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6291 return;
6292 }
6293 /* interpreted as no-op */
6294 #endif
6295 }
6296
6297 /* rfci (supervisor only) */
6298 static void gen_rfci_40x(DisasContext *ctx)
6299 {
6300 #if defined(CONFIG_USER_ONLY)
6301 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6302 #else
6303 if (unlikely(ctx->pr)) {
6304 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6305 return;
6306 }
6307 /* Restore CPU state */
6308 gen_helper_40x_rfci(cpu_env);
6309 gen_sync_exception(ctx);
6310 #endif
6311 }
6312
6313 static void gen_rfci(DisasContext *ctx)
6314 {
6315 #if defined(CONFIG_USER_ONLY)
6316 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6317 #else
6318 if (unlikely(ctx->pr)) {
6319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6320 return;
6321 }
6322 /* Restore CPU state */
6323 gen_helper_rfci(cpu_env);
6324 gen_sync_exception(ctx);
6325 #endif
6326 }
6327
6328 /* BookE specific */
6329
6330 /* XXX: not implemented on 440 ? */
6331 static void gen_rfdi(DisasContext *ctx)
6332 {
6333 #if defined(CONFIG_USER_ONLY)
6334 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6335 #else
6336 if (unlikely(ctx->pr)) {
6337 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6338 return;
6339 }
6340 /* Restore CPU state */
6341 gen_helper_rfdi(cpu_env);
6342 gen_sync_exception(ctx);
6343 #endif
6344 }
6345
6346 /* XXX: not implemented on 440 ? */
6347 static void gen_rfmci(DisasContext *ctx)
6348 {
6349 #if defined(CONFIG_USER_ONLY)
6350 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6351 #else
6352 if (unlikely(ctx->pr)) {
6353 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6354 return;
6355 }
6356 /* Restore CPU state */
6357 gen_helper_rfmci(cpu_env);
6358 gen_sync_exception(ctx);
6359 #endif
6360 }
6361
6362 /* TLB management - PowerPC 405 implementation */
6363
6364 /* tlbre */
6365 static void gen_tlbre_40x(DisasContext *ctx)
6366 {
6367 #if defined(CONFIG_USER_ONLY)
6368 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6369 #else
6370 if (unlikely(ctx->pr)) {
6371 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6372 return;
6373 }
6374 switch (rB(ctx->opcode)) {
6375 case 0:
6376 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6377 cpu_gpr[rA(ctx->opcode)]);
6378 break;
6379 case 1:
6380 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6381 cpu_gpr[rA(ctx->opcode)]);
6382 break;
6383 default:
6384 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6385 break;
6386 }
6387 #endif
6388 }
6389
6390 /* tlbsx - tlbsx. */
6391 static void gen_tlbsx_40x(DisasContext *ctx)
6392 {
6393 #if defined(CONFIG_USER_ONLY)
6394 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6395 #else
6396 TCGv t0;
6397 if (unlikely(ctx->pr)) {
6398 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6399 return;
6400 }
6401 t0 = tcg_temp_new();
6402 gen_addr_reg_index(ctx, t0);
6403 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6404 tcg_temp_free(t0);
6405 if (Rc(ctx->opcode)) {
6406 TCGLabel *l1 = gen_new_label();
6407 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6408 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6409 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6410 gen_set_label(l1);
6411 }
6412 #endif
6413 }
6414
6415 /* tlbwe */
6416 static void gen_tlbwe_40x(DisasContext *ctx)
6417 {
6418 #if defined(CONFIG_USER_ONLY)
6419 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6420 #else
6421 if (unlikely(ctx->pr)) {
6422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6423 return;
6424 }
6425 switch (rB(ctx->opcode)) {
6426 case 0:
6427 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6428 cpu_gpr[rS(ctx->opcode)]);
6429 break;
6430 case 1:
6431 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6432 cpu_gpr[rS(ctx->opcode)]);
6433 break;
6434 default:
6435 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6436 break;
6437 }
6438 #endif
6439 }
6440
6441 /* TLB management - PowerPC 440 implementation */
6442
6443 /* tlbre */
6444 static void gen_tlbre_440(DisasContext *ctx)
6445 {
6446 #if defined(CONFIG_USER_ONLY)
6447 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6448 #else
6449 if (unlikely(ctx->pr)) {
6450 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6451 return;
6452 }
6453 switch (rB(ctx->opcode)) {
6454 case 0:
6455 case 1:
6456 case 2:
6457 {
6458 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6459 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6460 t0, cpu_gpr[rA(ctx->opcode)]);
6461 tcg_temp_free_i32(t0);
6462 }
6463 break;
6464 default:
6465 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6466 break;
6467 }
6468 #endif
6469 }
6470
6471 /* tlbsx - tlbsx. */
6472 static void gen_tlbsx_440(DisasContext *ctx)
6473 {
6474 #if defined(CONFIG_USER_ONLY)
6475 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6476 #else
6477 TCGv t0;
6478 if (unlikely(ctx->pr)) {
6479 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6480 return;
6481 }
6482 t0 = tcg_temp_new();
6483 gen_addr_reg_index(ctx, t0);
6484 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6485 tcg_temp_free(t0);
6486 if (Rc(ctx->opcode)) {
6487 TCGLabel *l1 = gen_new_label();
6488 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6489 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6490 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6491 gen_set_label(l1);
6492 }
6493 #endif
6494 }
6495
6496 /* tlbwe */
6497 static void gen_tlbwe_440(DisasContext *ctx)
6498 {
6499 #if defined(CONFIG_USER_ONLY)
6500 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6501 #else
6502 if (unlikely(ctx->pr)) {
6503 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6504 return;
6505 }
6506 switch (rB(ctx->opcode)) {
6507 case 0:
6508 case 1:
6509 case 2:
6510 {
6511 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6512 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6513 cpu_gpr[rS(ctx->opcode)]);
6514 tcg_temp_free_i32(t0);
6515 }
6516 break;
6517 default:
6518 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6519 break;
6520 }
6521 #endif
6522 }
6523
6524 /* TLB management - PowerPC BookE 2.06 implementation */
6525
6526 /* tlbre */
6527 static void gen_tlbre_booke206(DisasContext *ctx)
6528 {
6529 #if defined(CONFIG_USER_ONLY)
6530 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6531 #else
6532 if (unlikely(ctx->pr)) {
6533 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6534 return;
6535 }
6536
6537 gen_helper_booke206_tlbre(cpu_env);
6538 #endif
6539 }
6540
6541 /* tlbsx - tlbsx. */
6542 static void gen_tlbsx_booke206(DisasContext *ctx)
6543 {
6544 #if defined(CONFIG_USER_ONLY)
6545 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6546 #else
6547 TCGv t0;
6548 if (unlikely(ctx->pr)) {
6549 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6550 return;
6551 }
6552
6553 if (rA(ctx->opcode)) {
6554 t0 = tcg_temp_new();
6555 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6556 } else {
6557 t0 = tcg_const_tl(0);
6558 }
6559
6560 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6561 gen_helper_booke206_tlbsx(cpu_env, t0);
6562 tcg_temp_free(t0);
6563 #endif
6564 }
6565
6566 /* tlbwe */
6567 static void gen_tlbwe_booke206(DisasContext *ctx)
6568 {
6569 #if defined(CONFIG_USER_ONLY)
6570 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6571 #else
6572 if (unlikely(ctx->pr)) {
6573 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6574 return;
6575 }
6576 gen_update_nip(ctx, ctx->nip - 4);
6577 gen_helper_booke206_tlbwe(cpu_env);
6578 #endif
6579 }
6580
6581 static void gen_tlbivax_booke206(DisasContext *ctx)
6582 {
6583 #if defined(CONFIG_USER_ONLY)
6584 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6585 #else
6586 TCGv t0;
6587 if (unlikely(ctx->pr)) {
6588 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6589 return;
6590 }
6591
6592 t0 = tcg_temp_new();
6593 gen_addr_reg_index(ctx, t0);
6594
6595 gen_helper_booke206_tlbivax(cpu_env, t0);
6596 tcg_temp_free(t0);
6597 #endif
6598 }
6599
6600 static void gen_tlbilx_booke206(DisasContext *ctx)
6601 {
6602 #if defined(CONFIG_USER_ONLY)
6603 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6604 #else
6605 TCGv t0;
6606 if (unlikely(ctx->pr)) {
6607 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6608 return;
6609 }
6610
6611 t0 = tcg_temp_new();
6612 gen_addr_reg_index(ctx, t0);
6613
6614 switch((ctx->opcode >> 21) & 0x3) {
6615 case 0:
6616 gen_helper_booke206_tlbilx0(cpu_env, t0);
6617 break;
6618 case 1:
6619 gen_helper_booke206_tlbilx1(cpu_env, t0);
6620 break;
6621 case 3:
6622 gen_helper_booke206_tlbilx3(cpu_env, t0);
6623 break;
6624 default:
6625 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6626 break;
6627 }
6628
6629 tcg_temp_free(t0);
6630 #endif
6631 }
6632
6633
6634 /* wrtee */
6635 static void gen_wrtee(DisasContext *ctx)
6636 {
6637 #if defined(CONFIG_USER_ONLY)
6638 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6639 #else
6640 TCGv t0;
6641 if (unlikely(ctx->pr)) {
6642 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6643 return;
6644 }
6645 t0 = tcg_temp_new();
6646 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6647 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6648 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6649 tcg_temp_free(t0);
6650 /* Stop translation to have a chance to raise an exception
6651 * if we just set msr_ee to 1
6652 */
6653 gen_stop_exception(ctx);
6654 #endif
6655 }
6656
6657 /* wrteei */
6658 static void gen_wrteei(DisasContext *ctx)
6659 {
6660 #if defined(CONFIG_USER_ONLY)
6661 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6662 #else
6663 if (unlikely(ctx->pr)) {
6664 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6665 return;
6666 }
6667 if (ctx->opcode & 0x00008000) {
6668 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6669 /* Stop translation to have a chance to raise an exception */
6670 gen_stop_exception(ctx);
6671 } else {
6672 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6673 }
6674 #endif
6675 }
6676
6677 /* PowerPC 440 specific instructions */
6678
6679 /* dlmzb */
6680 static void gen_dlmzb(DisasContext *ctx)
6681 {
6682 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6683 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6684 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6685 tcg_temp_free_i32(t0);
6686 }
6687
6688 /* mbar replaces eieio on 440 */
6689 static void gen_mbar(DisasContext *ctx)
6690 {
6691 /* interpreted as no-op */
6692 }
6693
6694 /* msync replaces sync on 440 */
6695 static void gen_msync_4xx(DisasContext *ctx)
6696 {
6697 /* interpreted as no-op */
6698 }
6699
6700 /* icbt */
6701 static void gen_icbt_440(DisasContext *ctx)
6702 {
6703 /* interpreted as no-op */
6704 /* XXX: specification say this is treated as a load by the MMU
6705 * but does not generate any exception
6706 */
6707 }
6708
6709 /* Embedded.Processor Control */
6710
6711 static void gen_msgclr(DisasContext *ctx)
6712 {
6713 #if defined(CONFIG_USER_ONLY)
6714 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6715 #else
6716 if (unlikely(ctx->pr)) {
6717 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6718 return;
6719 }
6720
6721 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6722 #endif
6723 }
6724
6725 static void gen_msgsnd(DisasContext *ctx)
6726 {
6727 #if defined(CONFIG_USER_ONLY)
6728 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6729 #else
6730 if (unlikely(ctx->pr)) {
6731 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6732 return;
6733 }
6734
6735 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6736 #endif
6737 }
6738
6739 /*** Altivec vector extension ***/
6740 /* Altivec registers moves */
6741
6742 static inline TCGv_ptr gen_avr_ptr(int reg)
6743 {
6744 TCGv_ptr r = tcg_temp_new_ptr();
6745 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6746 return r;
6747 }
6748
6749 #define GEN_VR_LDX(name, opc2, opc3) \
6750 static void glue(gen_, name)(DisasContext *ctx) \
6751 { \
6752 TCGv EA; \
6753 if (unlikely(!ctx->altivec_enabled)) { \
6754 gen_exception(ctx, POWERPC_EXCP_VPU); \
6755 return; \
6756 } \
6757 gen_set_access_type(ctx, ACCESS_INT); \
6758 EA = tcg_temp_new(); \
6759 gen_addr_reg_index(ctx, EA); \
6760 tcg_gen_andi_tl(EA, EA, ~0xf); \
6761 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6762 64-bit byteswap already. */ \
6763 if (ctx->le_mode) { \
6764 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6765 tcg_gen_addi_tl(EA, EA, 8); \
6766 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6767 } else { \
6768 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6769 tcg_gen_addi_tl(EA, EA, 8); \
6770 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6771 } \
6772 tcg_temp_free(EA); \
6773 }
6774
6775 #define GEN_VR_STX(name, opc2, opc3) \
6776 static void gen_st##name(DisasContext *ctx) \
6777 { \
6778 TCGv EA; \
6779 if (unlikely(!ctx->altivec_enabled)) { \
6780 gen_exception(ctx, POWERPC_EXCP_VPU); \
6781 return; \
6782 } \
6783 gen_set_access_type(ctx, ACCESS_INT); \
6784 EA = tcg_temp_new(); \
6785 gen_addr_reg_index(ctx, EA); \
6786 tcg_gen_andi_tl(EA, EA, ~0xf); \
6787 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6788 64-bit byteswap already. */ \
6789 if (ctx->le_mode) { \
6790 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6791 tcg_gen_addi_tl(EA, EA, 8); \
6792 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6793 } else { \
6794 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6795 tcg_gen_addi_tl(EA, EA, 8); \
6796 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6797 } \
6798 tcg_temp_free(EA); \
6799 }
6800
6801 #define GEN_VR_LVE(name, opc2, opc3, size) \
6802 static void gen_lve##name(DisasContext *ctx) \
6803 { \
6804 TCGv EA; \
6805 TCGv_ptr rs; \
6806 if (unlikely(!ctx->altivec_enabled)) { \
6807 gen_exception(ctx, POWERPC_EXCP_VPU); \
6808 return; \
6809 } \
6810 gen_set_access_type(ctx, ACCESS_INT); \
6811 EA = tcg_temp_new(); \
6812 gen_addr_reg_index(ctx, EA); \
6813 if (size > 1) { \
6814 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6815 } \
6816 rs = gen_avr_ptr(rS(ctx->opcode)); \
6817 gen_helper_lve##name(cpu_env, rs, EA); \
6818 tcg_temp_free(EA); \
6819 tcg_temp_free_ptr(rs); \
6820 }
6821
6822 #define GEN_VR_STVE(name, opc2, opc3, size) \
6823 static void gen_stve##name(DisasContext *ctx) \
6824 { \
6825 TCGv EA; \
6826 TCGv_ptr rs; \
6827 if (unlikely(!ctx->altivec_enabled)) { \
6828 gen_exception(ctx, POWERPC_EXCP_VPU); \
6829 return; \
6830 } \
6831 gen_set_access_type(ctx, ACCESS_INT); \
6832 EA = tcg_temp_new(); \
6833 gen_addr_reg_index(ctx, EA); \
6834 if (size > 1) { \
6835 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6836 } \
6837 rs = gen_avr_ptr(rS(ctx->opcode)); \
6838 gen_helper_stve##name(cpu_env, rs, EA); \
6839 tcg_temp_free(EA); \
6840 tcg_temp_free_ptr(rs); \
6841 }
6842
6843 GEN_VR_LDX(lvx, 0x07, 0x03);
6844 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6845 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6846
6847 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6848 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6849 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6850
6851 GEN_VR_STX(svx, 0x07, 0x07);
6852 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6853 GEN_VR_STX(svxl, 0x07, 0x0F);
6854
6855 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6856 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6857 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6858
6859 static void gen_lvsl(DisasContext *ctx)
6860 {
6861 TCGv_ptr rd;
6862 TCGv EA;
6863 if (unlikely(!ctx->altivec_enabled)) {
6864 gen_exception(ctx, POWERPC_EXCP_VPU);
6865 return;
6866 }
6867 EA = tcg_temp_new();
6868 gen_addr_reg_index(ctx, EA);
6869 rd = gen_avr_ptr(rD(ctx->opcode));
6870 gen_helper_lvsl(rd, EA);
6871 tcg_temp_free(EA);
6872 tcg_temp_free_ptr(rd);
6873 }
6874
6875 static void gen_lvsr(DisasContext *ctx)
6876 {
6877 TCGv_ptr rd;
6878 TCGv EA;
6879 if (unlikely(!ctx->altivec_enabled)) {
6880 gen_exception(ctx, POWERPC_EXCP_VPU);
6881 return;
6882 }
6883 EA = tcg_temp_new();
6884 gen_addr_reg_index(ctx, EA);
6885 rd = gen_avr_ptr(rD(ctx->opcode));
6886 gen_helper_lvsr(rd, EA);
6887 tcg_temp_free(EA);
6888 tcg_temp_free_ptr(rd);
6889 }
6890
6891 static void gen_mfvscr(DisasContext *ctx)
6892 {
6893 TCGv_i32 t;
6894 if (unlikely(!ctx->altivec_enabled)) {
6895 gen_exception(ctx, POWERPC_EXCP_VPU);
6896 return;
6897 }
6898 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6899 t = tcg_temp_new_i32();
6900 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6901 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6902 tcg_temp_free_i32(t);
6903 }
6904
6905 static void gen_mtvscr(DisasContext *ctx)
6906 {
6907 TCGv_ptr p;
6908 if (unlikely(!ctx->altivec_enabled)) {
6909 gen_exception(ctx, POWERPC_EXCP_VPU);
6910 return;
6911 }
6912 p = gen_avr_ptr(rB(ctx->opcode));
6913 gen_helper_mtvscr(cpu_env, p);
6914 tcg_temp_free_ptr(p);
6915 }
6916
6917 /* Logical operations */
6918 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6919 static void glue(gen_, name)(DisasContext *ctx) \
6920 { \
6921 if (unlikely(!ctx->altivec_enabled)) { \
6922 gen_exception(ctx, POWERPC_EXCP_VPU); \
6923 return; \
6924 } \
6925 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6926 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6927 }
6928
6929 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6930 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6931 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6932 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6933 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6934 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6935 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6936 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6937
6938 #define GEN_VXFORM(name, opc2, opc3) \
6939 static void glue(gen_, name)(DisasContext *ctx) \
6940 { \
6941 TCGv_ptr ra, rb, rd; \
6942 if (unlikely(!ctx->altivec_enabled)) { \
6943 gen_exception(ctx, POWERPC_EXCP_VPU); \
6944 return; \
6945 } \
6946 ra = gen_avr_ptr(rA(ctx->opcode)); \
6947 rb = gen_avr_ptr(rB(ctx->opcode)); \
6948 rd = gen_avr_ptr(rD(ctx->opcode)); \
6949 gen_helper_##name (rd, ra, rb); \
6950 tcg_temp_free_ptr(ra); \
6951 tcg_temp_free_ptr(rb); \
6952 tcg_temp_free_ptr(rd); \
6953 }
6954
6955 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6956 static void glue(gen_, name)(DisasContext *ctx) \
6957 { \
6958 TCGv_ptr ra, rb, rd; \
6959 if (unlikely(!ctx->altivec_enabled)) { \
6960 gen_exception(ctx, POWERPC_EXCP_VPU); \
6961 return; \
6962 } \
6963 ra = gen_avr_ptr(rA(ctx->opcode)); \
6964 rb = gen_avr_ptr(rB(ctx->opcode)); \
6965 rd = gen_avr_ptr(rD(ctx->opcode)); \
6966 gen_helper_##name(cpu_env, rd, ra, rb); \
6967 tcg_temp_free_ptr(ra); \
6968 tcg_temp_free_ptr(rb); \
6969 tcg_temp_free_ptr(rd); \
6970 }
6971
6972 #define GEN_VXFORM3(name, opc2, opc3) \
6973 static void glue(gen_, name)(DisasContext *ctx) \
6974 { \
6975 TCGv_ptr ra, rb, rc, rd; \
6976 if (unlikely(!ctx->altivec_enabled)) { \
6977 gen_exception(ctx, POWERPC_EXCP_VPU); \
6978 return; \
6979 } \
6980 ra = gen_avr_ptr(rA(ctx->opcode)); \
6981 rb = gen_avr_ptr(rB(ctx->opcode)); \
6982 rc = gen_avr_ptr(rC(ctx->opcode)); \
6983 rd = gen_avr_ptr(rD(ctx->opcode)); \
6984 gen_helper_##name(rd, ra, rb, rc); \
6985 tcg_temp_free_ptr(ra); \
6986 tcg_temp_free_ptr(rb); \
6987 tcg_temp_free_ptr(rc); \
6988 tcg_temp_free_ptr(rd); \
6989 }
6990
6991 /*
6992 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6993 * an opcode bit. In general, these pairs come from different
6994 * versions of the ISA, so we must also support a pair of flags for
6995 * each instruction.
6996 */
6997 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6998 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6999 { \
7000 if ((Rc(ctx->opcode) == 0) && \
7001 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7002 gen_##name0(ctx); \
7003 } else if ((Rc(ctx->opcode) == 1) && \
7004 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7005 gen_##name1(ctx); \
7006 } else { \
7007 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7008 } \
7009 }
7010
7011 GEN_VXFORM(vaddubm, 0, 0);
7012 GEN_VXFORM(vadduhm, 0, 1);
7013 GEN_VXFORM(vadduwm, 0, 2);
7014 GEN_VXFORM(vaddudm, 0, 3);
7015 GEN_VXFORM(vsububm, 0, 16);
7016 GEN_VXFORM(vsubuhm, 0, 17);
7017 GEN_VXFORM(vsubuwm, 0, 18);
7018 GEN_VXFORM(vsubudm, 0, 19);
7019 GEN_VXFORM(vmaxub, 1, 0);
7020 GEN_VXFORM(vmaxuh, 1, 1);
7021 GEN_VXFORM(vmaxuw, 1, 2);
7022 GEN_VXFORM(vmaxud, 1, 3);
7023 GEN_VXFORM(vmaxsb, 1, 4);
7024 GEN_VXFORM(vmaxsh, 1, 5);
7025 GEN_VXFORM(vmaxsw, 1, 6);
7026 GEN_VXFORM(vmaxsd, 1, 7);
7027 GEN_VXFORM(vminub, 1, 8);
7028 GEN_VXFORM(vminuh, 1, 9);
7029 GEN_VXFORM(vminuw, 1, 10);
7030 GEN_VXFORM(vminud, 1, 11);
7031 GEN_VXFORM(vminsb, 1, 12);
7032 GEN_VXFORM(vminsh, 1, 13);
7033 GEN_VXFORM(vminsw, 1, 14);
7034 GEN_VXFORM(vminsd, 1, 15);
7035 GEN_VXFORM(vavgub, 1, 16);
7036 GEN_VXFORM(vavguh, 1, 17);
7037 GEN_VXFORM(vavguw, 1, 18);
7038 GEN_VXFORM(vavgsb, 1, 20);
7039 GEN_VXFORM(vavgsh, 1, 21);
7040 GEN_VXFORM(vavgsw, 1, 22);
7041 GEN_VXFORM(vmrghb, 6, 0);
7042 GEN_VXFORM(vmrghh, 6, 1);
7043 GEN_VXFORM(vmrghw, 6, 2);
7044 GEN_VXFORM(vmrglb, 6, 4);
7045 GEN_VXFORM(vmrglh, 6, 5);
7046 GEN_VXFORM(vmrglw, 6, 6);
7047
7048 static void gen_vmrgew(DisasContext *ctx)
7049 {
7050 TCGv_i64 tmp;
7051 int VT, VA, VB;
7052 if (unlikely(!ctx->altivec_enabled)) {
7053 gen_exception(ctx, POWERPC_EXCP_VPU);
7054 return;
7055 }
7056 VT = rD(ctx->opcode);
7057 VA = rA(ctx->opcode);
7058 VB = rB(ctx->opcode);
7059 tmp = tcg_temp_new_i64();
7060 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7061 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7062 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7063 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7064 tcg_temp_free_i64(tmp);
7065 }
7066
7067 static void gen_vmrgow(DisasContext *ctx)
7068 {
7069 int VT, VA, VB;
7070 if (unlikely(!ctx->altivec_enabled)) {
7071 gen_exception(ctx, POWERPC_EXCP_VPU);
7072 return;
7073 }
7074 VT = rD(ctx->opcode);
7075 VA = rA(ctx->opcode);
7076 VB = rB(ctx->opcode);
7077
7078 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7079 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7080 }
7081
7082 GEN_VXFORM(vmuloub, 4, 0);
7083 GEN_VXFORM(vmulouh, 4, 1);
7084 GEN_VXFORM(vmulouw, 4, 2);
7085 GEN_VXFORM(vmuluwm, 4, 2);
7086 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7087 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7088 GEN_VXFORM(vmulosb, 4, 4);
7089 GEN_VXFORM(vmulosh, 4, 5);
7090 GEN_VXFORM(vmulosw, 4, 6);
7091 GEN_VXFORM(vmuleub, 4, 8);
7092 GEN_VXFORM(vmuleuh, 4, 9);
7093 GEN_VXFORM(vmuleuw, 4, 10);
7094 GEN_VXFORM(vmulesb, 4, 12);
7095 GEN_VXFORM(vmulesh, 4, 13);
7096 GEN_VXFORM(vmulesw, 4, 14);
7097 GEN_VXFORM(vslb, 2, 4);
7098 GEN_VXFORM(vslh, 2, 5);
7099 GEN_VXFORM(vslw, 2, 6);
7100 GEN_VXFORM(vsld, 2, 23);
7101 GEN_VXFORM(vsrb, 2, 8);
7102 GEN_VXFORM(vsrh, 2, 9);
7103 GEN_VXFORM(vsrw, 2, 10);
7104 GEN_VXFORM(vsrd, 2, 27);
7105 GEN_VXFORM(vsrab, 2, 12);
7106 GEN_VXFORM(vsrah, 2, 13);
7107 GEN_VXFORM(vsraw, 2, 14);
7108 GEN_VXFORM(vsrad, 2, 15);
7109 GEN_VXFORM(vslo, 6, 16);
7110 GEN_VXFORM(vsro, 6, 17);
7111 GEN_VXFORM(vaddcuw, 0, 6);
7112 GEN_VXFORM(vsubcuw, 0, 22);
7113 GEN_VXFORM_ENV(vaddubs, 0, 8);
7114 GEN_VXFORM_ENV(vadduhs, 0, 9);
7115 GEN_VXFORM_ENV(vadduws, 0, 10);
7116 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7117 GEN_VXFORM_ENV(vaddshs, 0, 13);
7118 GEN_VXFORM_ENV(vaddsws, 0, 14);
7119 GEN_VXFORM_ENV(vsububs, 0, 24);
7120 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7121 GEN_VXFORM_ENV(vsubuws, 0, 26);
7122 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7123 GEN_VXFORM_ENV(vsubshs, 0, 29);
7124 GEN_VXFORM_ENV(vsubsws, 0, 30);
7125 GEN_VXFORM(vadduqm, 0, 4);
7126 GEN_VXFORM(vaddcuq, 0, 5);
7127 GEN_VXFORM3(vaddeuqm, 30, 0);
7128 GEN_VXFORM3(vaddecuq, 30, 0);
7129 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7130 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7131 GEN_VXFORM(vsubuqm, 0, 20);
7132 GEN_VXFORM(vsubcuq, 0, 21);
7133 GEN_VXFORM3(vsubeuqm, 31, 0);
7134 GEN_VXFORM3(vsubecuq, 31, 0);
7135 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7136 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7137 GEN_VXFORM(vrlb, 2, 0);
7138 GEN_VXFORM(vrlh, 2, 1);
7139 GEN_VXFORM(vrlw, 2, 2);
7140 GEN_VXFORM(vrld, 2, 3);
7141 GEN_VXFORM(vsl, 2, 7);
7142 GEN_VXFORM(vsr, 2, 11);
7143 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7144 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7145 GEN_VXFORM_ENV(vpkudum, 7, 17);
7146 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7147 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7148 GEN_VXFORM_ENV(vpkudus, 7, 19);
7149 GEN_VXFORM_ENV(vpkshus, 7, 4);
7150 GEN_VXFORM_ENV(vpkswus, 7, 5);
7151 GEN_VXFORM_ENV(vpksdus, 7, 21);
7152 GEN_VXFORM_ENV(vpkshss, 7, 6);
7153 GEN_VXFORM_ENV(vpkswss, 7, 7);
7154 GEN_VXFORM_ENV(vpksdss, 7, 23);
7155 GEN_VXFORM(vpkpx, 7, 12);
7156 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7157 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7158 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7159 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7160 GEN_VXFORM_ENV(vsumsws, 4, 30);
7161 GEN_VXFORM_ENV(vaddfp, 5, 0);
7162 GEN_VXFORM_ENV(vsubfp, 5, 1);
7163 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7164 GEN_VXFORM_ENV(vminfp, 5, 17);
7165
7166 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7167 static void glue(gen_, name)(DisasContext *ctx) \
7168 { \
7169 TCGv_ptr ra, rb, rd; \
7170 if (unlikely(!ctx->altivec_enabled)) { \
7171 gen_exception(ctx, POWERPC_EXCP_VPU); \
7172 return; \
7173 } \
7174 ra = gen_avr_ptr(rA(ctx->opcode)); \
7175 rb = gen_avr_ptr(rB(ctx->opcode)); \
7176 rd = gen_avr_ptr(rD(ctx->opcode)); \
7177 gen_helper_##opname(cpu_env, rd, ra, rb); \
7178 tcg_temp_free_ptr(ra); \
7179 tcg_temp_free_ptr(rb); \
7180 tcg_temp_free_ptr(rd); \
7181 }
7182
7183 #define GEN_VXRFORM(name, opc2, opc3) \
7184 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7185 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7186
7187 /*
7188 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7189 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7190 * come from different versions of the ISA, so we must also support a
7191 * pair of flags for each instruction.
7192 */
7193 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7194 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7195 { \
7196 if ((Rc(ctx->opcode) == 0) && \
7197 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7198 if (Rc21(ctx->opcode) == 0) { \
7199 gen_##name0(ctx); \
7200 } else { \
7201 gen_##name0##_(ctx); \
7202 } \
7203 } else if ((Rc(ctx->opcode) == 1) && \
7204 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7205 if (Rc21(ctx->opcode) == 0) { \
7206 gen_##name1(ctx); \
7207 } else { \
7208 gen_##name1##_(ctx); \
7209 } \
7210 } else { \
7211 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7212 } \
7213 }
7214
7215 GEN_VXRFORM(vcmpequb, 3, 0)
7216 GEN_VXRFORM(vcmpequh, 3, 1)
7217 GEN_VXRFORM(vcmpequw, 3, 2)
7218 GEN_VXRFORM(vcmpequd, 3, 3)
7219 GEN_VXRFORM(vcmpgtsb, 3, 12)
7220 GEN_VXRFORM(vcmpgtsh, 3, 13)
7221 GEN_VXRFORM(vcmpgtsw, 3, 14)
7222 GEN_VXRFORM(vcmpgtsd, 3, 15)
7223 GEN_VXRFORM(vcmpgtub, 3, 8)
7224 GEN_VXRFORM(vcmpgtuh, 3, 9)
7225 GEN_VXRFORM(vcmpgtuw, 3, 10)
7226 GEN_VXRFORM(vcmpgtud, 3, 11)
7227 GEN_VXRFORM(vcmpeqfp, 3, 3)
7228 GEN_VXRFORM(vcmpgefp, 3, 7)
7229 GEN_VXRFORM(vcmpgtfp, 3, 11)
7230 GEN_VXRFORM(vcmpbfp, 3, 15)
7231
7232 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7233 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7234 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7235 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7236 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7237 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7238
7239 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7240 static void glue(gen_, name)(DisasContext *ctx) \
7241 { \
7242 TCGv_ptr rd; \
7243 TCGv_i32 simm; \
7244 if (unlikely(!ctx->altivec_enabled)) { \
7245 gen_exception(ctx, POWERPC_EXCP_VPU); \
7246 return; \
7247 } \
7248 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7249 rd = gen_avr_ptr(rD(ctx->opcode)); \
7250 gen_helper_##name (rd, simm); \
7251 tcg_temp_free_i32(simm); \
7252 tcg_temp_free_ptr(rd); \
7253 }
7254
7255 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7256 GEN_VXFORM_SIMM(vspltish, 6, 13);
7257 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7258
7259 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7260 static void glue(gen_, name)(DisasContext *ctx) \
7261 { \
7262 TCGv_ptr rb, rd; \
7263 if (unlikely(!ctx->altivec_enabled)) { \
7264 gen_exception(ctx, POWERPC_EXCP_VPU); \
7265 return; \
7266 } \
7267 rb = gen_avr_ptr(rB(ctx->opcode)); \
7268 rd = gen_avr_ptr(rD(ctx->opcode)); \
7269 gen_helper_##name (rd, rb); \
7270 tcg_temp_free_ptr(rb); \
7271 tcg_temp_free_ptr(rd); \
7272 }
7273
7274 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7275 static void glue(gen_, name)(DisasContext *ctx) \
7276 { \
7277 TCGv_ptr rb, rd; \
7278 \
7279 if (unlikely(!ctx->altivec_enabled)) { \
7280 gen_exception(ctx, POWERPC_EXCP_VPU); \
7281 return; \
7282 } \
7283 rb = gen_avr_ptr(rB(ctx->opcode)); \
7284 rd = gen_avr_ptr(rD(ctx->opcode)); \
7285 gen_helper_##name(cpu_env, rd, rb); \
7286 tcg_temp_free_ptr(rb); \
7287 tcg_temp_free_ptr(rd); \
7288 }
7289
7290 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7291 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7292 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7293 GEN_VXFORM_NOA(vupklsb, 7, 10);
7294 GEN_VXFORM_NOA(vupklsh, 7, 11);
7295 GEN_VXFORM_NOA(vupklsw, 7, 27);
7296 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7297 GEN_VXFORM_NOA(vupklpx, 7, 15);
7298 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7299 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7300 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7301 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7302 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7303 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7304 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7305 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7306
7307 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7308 static void glue(gen_, name)(DisasContext *ctx) \
7309 { \
7310 TCGv_ptr rd; \
7311 TCGv_i32 simm; \
7312 if (unlikely(!ctx->altivec_enabled)) { \
7313 gen_exception(ctx, POWERPC_EXCP_VPU); \
7314 return; \
7315 } \
7316 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7317 rd = gen_avr_ptr(rD(ctx->opcode)); \
7318 gen_helper_##name (rd, simm); \
7319 tcg_temp_free_i32(simm); \
7320 tcg_temp_free_ptr(rd); \
7321 }
7322
7323 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7324 static void glue(gen_, name)(DisasContext *ctx) \
7325 { \
7326 TCGv_ptr rb, rd; \
7327 TCGv_i32 uimm; \
7328 if (unlikely(!ctx->altivec_enabled)) { \
7329 gen_exception(ctx, POWERPC_EXCP_VPU); \
7330 return; \
7331 } \
7332 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7333 rb = gen_avr_ptr(rB(ctx->opcode)); \
7334 rd = gen_avr_ptr(rD(ctx->opcode)); \
7335 gen_helper_##name (rd, rb, uimm); \
7336 tcg_temp_free_i32(uimm); \
7337 tcg_temp_free_ptr(rb); \
7338 tcg_temp_free_ptr(rd); \
7339 }
7340
7341 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7342 static void glue(gen_, name)(DisasContext *ctx) \
7343 { \
7344 TCGv_ptr rb, rd; \
7345 TCGv_i32 uimm; \
7346 \
7347 if (unlikely(!ctx->altivec_enabled)) { \
7348 gen_exception(ctx, POWERPC_EXCP_VPU); \
7349 return; \
7350 } \
7351 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7352 rb = gen_avr_ptr(rB(ctx->opcode)); \
7353 rd = gen_avr_ptr(rD(ctx->opcode)); \
7354 gen_helper_##name(cpu_env, rd, rb, uimm); \
7355 tcg_temp_free_i32(uimm); \
7356 tcg_temp_free_ptr(rb); \
7357 tcg_temp_free_ptr(rd); \
7358 }
7359
7360 GEN_VXFORM_UIMM(vspltb, 6, 8);
7361 GEN_VXFORM_UIMM(vsplth, 6, 9);
7362 GEN_VXFORM_UIMM(vspltw, 6, 10);
7363 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7364 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7365 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7366 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7367
7368 static void gen_vsldoi(DisasContext *ctx)
7369 {
7370 TCGv_ptr ra, rb, rd;
7371 TCGv_i32 sh;
7372 if (unlikely(!ctx->altivec_enabled)) {
7373 gen_exception(ctx, POWERPC_EXCP_VPU);
7374 return;
7375 }
7376 ra = gen_avr_ptr(rA(ctx->opcode));
7377 rb = gen_avr_ptr(rB(ctx->opcode));
7378 rd = gen_avr_ptr(rD(ctx->opcode));
7379 sh = tcg_const_i32(VSH(ctx->opcode));
7380 gen_helper_vsldoi (rd, ra, rb, sh);
7381 tcg_temp_free_ptr(ra);
7382 tcg_temp_free_ptr(rb);
7383 tcg_temp_free_ptr(rd);
7384 tcg_temp_free_i32(sh);
7385 }
7386
7387 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7388 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7389 { \
7390 TCGv_ptr ra, rb, rc, rd; \
7391 if (unlikely(!ctx->altivec_enabled)) { \
7392 gen_exception(ctx, POWERPC_EXCP_VPU); \
7393 return; \
7394 } \
7395 ra = gen_avr_ptr(rA(ctx->opcode)); \
7396 rb = gen_avr_ptr(rB(ctx->opcode)); \
7397 rc = gen_avr_ptr(rC(ctx->opcode)); \
7398 rd = gen_avr_ptr(rD(ctx->opcode)); \
7399 if (Rc(ctx->opcode)) { \
7400 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7401 } else { \
7402 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7403 } \
7404 tcg_temp_free_ptr(ra); \
7405 tcg_temp_free_ptr(rb); \
7406 tcg_temp_free_ptr(rc); \
7407 tcg_temp_free_ptr(rd); \
7408 }
7409
7410 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7411
7412 static void gen_vmladduhm(DisasContext *ctx)
7413 {
7414 TCGv_ptr ra, rb, rc, rd;
7415 if (unlikely(!ctx->altivec_enabled)) {
7416 gen_exception(ctx, POWERPC_EXCP_VPU);
7417 return;
7418 }
7419 ra = gen_avr_ptr(rA(ctx->opcode));
7420 rb = gen_avr_ptr(rB(ctx->opcode));
7421 rc = gen_avr_ptr(rC(ctx->opcode));
7422 rd = gen_avr_ptr(rD(ctx->opcode));
7423 gen_helper_vmladduhm(rd, ra, rb, rc);
7424 tcg_temp_free_ptr(ra);
7425 tcg_temp_free_ptr(rb);
7426 tcg_temp_free_ptr(rc);
7427 tcg_temp_free_ptr(rd);
7428 }
7429
7430 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7431 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7432 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7433 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7434 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7435
7436 GEN_VXFORM_NOA(vclzb, 1, 28)
7437 GEN_VXFORM_NOA(vclzh, 1, 29)
7438 GEN_VXFORM_NOA(vclzw, 1, 30)
7439 GEN_VXFORM_NOA(vclzd, 1, 31)
7440 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7441 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7442 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7443 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7444 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7445 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7446 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7447 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7448 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7449 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7450 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7451 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7452 GEN_VXFORM(vbpermq, 6, 21);
7453 GEN_VXFORM_NOA(vgbbd, 6, 20);
7454 GEN_VXFORM(vpmsumb, 4, 16)
7455 GEN_VXFORM(vpmsumh, 4, 17)
7456 GEN_VXFORM(vpmsumw, 4, 18)
7457 GEN_VXFORM(vpmsumd, 4, 19)
7458
7459 #define GEN_BCD(op) \
7460 static void gen_##op(DisasContext *ctx) \
7461 { \
7462 TCGv_ptr ra, rb, rd; \
7463 TCGv_i32 ps; \
7464 \
7465 if (unlikely(!ctx->altivec_enabled)) { \
7466 gen_exception(ctx, POWERPC_EXCP_VPU); \
7467 return; \
7468 } \
7469 \
7470 ra = gen_avr_ptr(rA(ctx->opcode)); \
7471 rb = gen_avr_ptr(rB(ctx->opcode)); \
7472 rd = gen_avr_ptr(rD(ctx->opcode)); \
7473 \
7474 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7475 \
7476 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7477 \
7478 tcg_temp_free_ptr(ra); \
7479 tcg_temp_free_ptr(rb); \
7480 tcg_temp_free_ptr(rd); \
7481 tcg_temp_free_i32(ps); \
7482 }
7483
7484 GEN_BCD(bcdadd)
7485 GEN_BCD(bcdsub)
7486
7487 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7488 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7489 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7490 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7491 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7492 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7493 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7494 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7495
7496 static void gen_vsbox(DisasContext *ctx)
7497 {
7498 TCGv_ptr ra, rd;
7499 if (unlikely(!ctx->altivec_enabled)) {
7500 gen_exception(ctx, POWERPC_EXCP_VPU);
7501 return;
7502 }
7503 ra = gen_avr_ptr(rA(ctx->opcode));
7504 rd = gen_avr_ptr(rD(ctx->opcode));
7505 gen_helper_vsbox(rd, ra);
7506 tcg_temp_free_ptr(ra);
7507 tcg_temp_free_ptr(rd);
7508 }
7509
7510 GEN_VXFORM(vcipher, 4, 20)
7511 GEN_VXFORM(vcipherlast, 4, 20)
7512 GEN_VXFORM(vncipher, 4, 21)
7513 GEN_VXFORM(vncipherlast, 4, 21)
7514
7515 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7516 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7517 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7518 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7519
7520 #define VSHASIGMA(op) \
7521 static void gen_##op(DisasContext *ctx) \
7522 { \
7523 TCGv_ptr ra, rd; \
7524 TCGv_i32 st_six; \
7525 if (unlikely(!ctx->altivec_enabled)) { \
7526 gen_exception(ctx, POWERPC_EXCP_VPU); \
7527 return; \
7528 } \
7529 ra = gen_avr_ptr(rA(ctx->opcode)); \
7530 rd = gen_avr_ptr(rD(ctx->opcode)); \
7531 st_six = tcg_const_i32(rB(ctx->opcode)); \
7532 gen_helper_##op(rd, ra, st_six); \
7533 tcg_temp_free_ptr(ra); \
7534 tcg_temp_free_ptr(rd); \
7535 tcg_temp_free_i32(st_six); \
7536 }
7537
7538 VSHASIGMA(vshasigmaw)
7539 VSHASIGMA(vshasigmad)
7540
7541 GEN_VXFORM3(vpermxor, 22, 0xFF)
7542 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7543 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7544
7545 /*** VSX extension ***/
7546
7547 static inline TCGv_i64 cpu_vsrh(int n)
7548 {
7549 if (n < 32) {
7550 return cpu_fpr[n];
7551 } else {
7552 return cpu_avrh[n-32];
7553 }
7554 }
7555
7556 static inline TCGv_i64 cpu_vsrl(int n)
7557 {
7558 if (n < 32) {
7559 return cpu_vsr[n];
7560 } else {
7561 return cpu_avrl[n-32];
7562 }
7563 }
7564
7565 #define VSX_LOAD_SCALAR(name, operation) \
7566 static void gen_##name(DisasContext *ctx) \
7567 { \
7568 TCGv EA; \
7569 if (unlikely(!ctx->vsx_enabled)) { \
7570 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7571 return; \
7572 } \
7573 gen_set_access_type(ctx, ACCESS_INT); \
7574 EA = tcg_temp_new(); \
7575 gen_addr_reg_index(ctx, EA); \
7576 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7577 /* NOTE: cpu_vsrl is undefined */ \
7578 tcg_temp_free(EA); \
7579 }
7580
7581 VSX_LOAD_SCALAR(lxsdx, ld64)
7582 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7583 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7584 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7585
7586 static void gen_lxvd2x(DisasContext *ctx)
7587 {
7588 TCGv EA;
7589 if (unlikely(!ctx->vsx_enabled)) {
7590 gen_exception(ctx, POWERPC_EXCP_VSXU);
7591 return;
7592 }
7593 gen_set_access_type(ctx, ACCESS_INT);
7594 EA = tcg_temp_new();
7595 gen_addr_reg_index(ctx, EA);
7596 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7597 tcg_gen_addi_tl(EA, EA, 8);
7598 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7599 tcg_temp_free(EA);
7600 }
7601
7602 static void gen_lxvdsx(DisasContext *ctx)
7603 {
7604 TCGv EA;
7605 if (unlikely(!ctx->vsx_enabled)) {
7606 gen_exception(ctx, POWERPC_EXCP_VSXU);
7607 return;
7608 }
7609 gen_set_access_type(ctx, ACCESS_INT);
7610 EA = tcg_temp_new();
7611 gen_addr_reg_index(ctx, EA);
7612 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7613 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7614 tcg_temp_free(EA);
7615 }
7616
7617 static void gen_lxvw4x(DisasContext *ctx)
7618 {
7619 TCGv EA;
7620 TCGv_i64 tmp;
7621 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7622 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7623 if (unlikely(!ctx->vsx_enabled)) {
7624 gen_exception(ctx, POWERPC_EXCP_VSXU);
7625 return;
7626 }
7627 gen_set_access_type(ctx, ACCESS_INT);
7628 EA = tcg_temp_new();
7629 tmp = tcg_temp_new_i64();
7630
7631 gen_addr_reg_index(ctx, EA);
7632 gen_qemu_ld32u_i64(ctx, tmp, EA);
7633 tcg_gen_addi_tl(EA, EA, 4);
7634 gen_qemu_ld32u_i64(ctx, xth, EA);
7635 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7636
7637 tcg_gen_addi_tl(EA, EA, 4);
7638 gen_qemu_ld32u_i64(ctx, tmp, EA);
7639 tcg_gen_addi_tl(EA, EA, 4);
7640 gen_qemu_ld32u_i64(ctx, xtl, EA);
7641 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7642
7643 tcg_temp_free(EA);
7644 tcg_temp_free_i64(tmp);
7645 }
7646
7647 #define VSX_STORE_SCALAR(name, operation) \
7648 static void gen_##name(DisasContext *ctx) \
7649 { \
7650 TCGv EA; \
7651 if (unlikely(!ctx->vsx_enabled)) { \
7652 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7653 return; \
7654 } \
7655 gen_set_access_type(ctx, ACCESS_INT); \
7656 EA = tcg_temp_new(); \
7657 gen_addr_reg_index(ctx, EA); \
7658 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7659 tcg_temp_free(EA); \
7660 }
7661
7662 VSX_STORE_SCALAR(stxsdx, st64)
7663 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7664 VSX_STORE_SCALAR(stxsspx, st32fs)
7665
7666 static void gen_stxvd2x(DisasContext *ctx)
7667 {
7668 TCGv EA;
7669 if (unlikely(!ctx->vsx_enabled)) {
7670 gen_exception(ctx, POWERPC_EXCP_VSXU);
7671 return;
7672 }
7673 gen_set_access_type(ctx, ACCESS_INT);
7674 EA = tcg_temp_new();
7675 gen_addr_reg_index(ctx, EA);
7676 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7677 tcg_gen_addi_tl(EA, EA, 8);
7678 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7679 tcg_temp_free(EA);
7680 }
7681
7682 static void gen_stxvw4x(DisasContext *ctx)
7683 {
7684 TCGv_i64 tmp;
7685 TCGv EA;
7686 if (unlikely(!ctx->vsx_enabled)) {
7687 gen_exception(ctx, POWERPC_EXCP_VSXU);
7688 return;
7689 }
7690 gen_set_access_type(ctx, ACCESS_INT);
7691 EA = tcg_temp_new();
7692 gen_addr_reg_index(ctx, EA);
7693 tmp = tcg_temp_new_i64();
7694
7695 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7696 gen_qemu_st32_i64(ctx, tmp, EA);
7697 tcg_gen_addi_tl(EA, EA, 4);
7698 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7699
7700 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7701 tcg_gen_addi_tl(EA, EA, 4);
7702 gen_qemu_st32_i64(ctx, tmp, EA);
7703 tcg_gen_addi_tl(EA, EA, 4);
7704 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7705
7706 tcg_temp_free(EA);
7707 tcg_temp_free_i64(tmp);
7708 }
7709
7710 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7711 static void gen_##name(DisasContext *ctx) \
7712 { \
7713 if (xS(ctx->opcode) < 32) { \
7714 if (unlikely(!ctx->fpu_enabled)) { \
7715 gen_exception(ctx, POWERPC_EXCP_FPU); \
7716 return; \
7717 } \
7718 } else { \
7719 if (unlikely(!ctx->altivec_enabled)) { \
7720 gen_exception(ctx, POWERPC_EXCP_VPU); \
7721 return; \
7722 } \
7723 } \
7724 TCGv_i64 tmp = tcg_temp_new_i64(); \
7725 tcg_gen_##tcgop1(tmp, source); \
7726 tcg_gen_##tcgop2(target, tmp); \
7727 tcg_temp_free_i64(tmp); \
7728 }
7729
7730
7731 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7732 cpu_vsrh(xS(ctx->opcode)))
7733 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7734 cpu_gpr[rA(ctx->opcode)])
7735 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7736 cpu_gpr[rA(ctx->opcode)])
7737
7738 #if defined(TARGET_PPC64)
7739 #define MV_VSRD(name, target, source) \
7740 static void gen_##name(DisasContext *ctx) \
7741 { \
7742 if (xS(ctx->opcode) < 32) { \
7743 if (unlikely(!ctx->fpu_enabled)) { \
7744 gen_exception(ctx, POWERPC_EXCP_FPU); \
7745 return; \
7746 } \
7747 } else { \
7748 if (unlikely(!ctx->altivec_enabled)) { \
7749 gen_exception(ctx, POWERPC_EXCP_VPU); \
7750 return; \
7751 } \
7752 } \
7753 tcg_gen_mov_i64(target, source); \
7754 }
7755
7756 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7757 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7758
7759 #endif
7760
7761 static void gen_xxpermdi(DisasContext *ctx)
7762 {
7763 if (unlikely(!ctx->vsx_enabled)) {
7764 gen_exception(ctx, POWERPC_EXCP_VSXU);
7765 return;
7766 }
7767
7768 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7769 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7770 TCGv_i64 xh, xl;
7771
7772 xh = tcg_temp_new_i64();
7773 xl = tcg_temp_new_i64();
7774
7775 if ((DM(ctx->opcode) & 2) == 0) {
7776 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7777 } else {
7778 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7779 }
7780 if ((DM(ctx->opcode) & 1) == 0) {
7781 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7782 } else {
7783 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7784 }
7785
7786 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7787 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7788
7789 tcg_temp_free_i64(xh);
7790 tcg_temp_free_i64(xl);
7791 } else {
7792 if ((DM(ctx->opcode) & 2) == 0) {
7793 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7794 } else {
7795 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7796 }
7797 if ((DM(ctx->opcode) & 1) == 0) {
7798 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7799 } else {
7800 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7801 }
7802 }
7803 }
7804
7805 #define OP_ABS 1
7806 #define OP_NABS 2
7807 #define OP_NEG 3
7808 #define OP_CPSGN 4
7809 #define SGN_MASK_DP 0x8000000000000000ull
7810 #define SGN_MASK_SP 0x8000000080000000ull
7811
7812 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7813 static void glue(gen_, name)(DisasContext * ctx) \
7814 { \
7815 TCGv_i64 xb, sgm; \
7816 if (unlikely(!ctx->vsx_enabled)) { \
7817 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7818 return; \
7819 } \
7820 xb = tcg_temp_new_i64(); \
7821 sgm = tcg_temp_new_i64(); \
7822 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7823 tcg_gen_movi_i64(sgm, sgn_mask); \
7824 switch (op) { \
7825 case OP_ABS: { \
7826 tcg_gen_andc_i64(xb, xb, sgm); \
7827 break; \
7828 } \
7829 case OP_NABS: { \
7830 tcg_gen_or_i64(xb, xb, sgm); \
7831 break; \
7832 } \
7833 case OP_NEG: { \
7834 tcg_gen_xor_i64(xb, xb, sgm); \
7835 break; \
7836 } \
7837 case OP_CPSGN: { \
7838 TCGv_i64 xa = tcg_temp_new_i64(); \
7839 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7840 tcg_gen_and_i64(xa, xa, sgm); \
7841 tcg_gen_andc_i64(xb, xb, sgm); \
7842 tcg_gen_or_i64(xb, xb, xa); \
7843 tcg_temp_free_i64(xa); \
7844 break; \
7845 } \
7846 } \
7847 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7848 tcg_temp_free_i64(xb); \
7849 tcg_temp_free_i64(sgm); \
7850 }
7851
7852 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7853 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7854 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7855 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7856
7857 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7858 static void glue(gen_, name)(DisasContext * ctx) \
7859 { \
7860 TCGv_i64 xbh, xbl, sgm; \
7861 if (unlikely(!ctx->vsx_enabled)) { \
7862 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7863 return; \
7864 } \
7865 xbh = tcg_temp_new_i64(); \
7866 xbl = tcg_temp_new_i64(); \
7867 sgm = tcg_temp_new_i64(); \
7868 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7869 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7870 tcg_gen_movi_i64(sgm, sgn_mask); \
7871 switch (op) { \
7872 case OP_ABS: { \
7873 tcg_gen_andc_i64(xbh, xbh, sgm); \
7874 tcg_gen_andc_i64(xbl, xbl, sgm); \
7875 break; \
7876 } \
7877 case OP_NABS: { \
7878 tcg_gen_or_i64(xbh, xbh, sgm); \
7879 tcg_gen_or_i64(xbl, xbl, sgm); \
7880 break; \
7881 } \
7882 case OP_NEG: { \
7883 tcg_gen_xor_i64(xbh, xbh, sgm); \
7884 tcg_gen_xor_i64(xbl, xbl, sgm); \
7885 break; \
7886 } \
7887 case OP_CPSGN: { \
7888 TCGv_i64 xah = tcg_temp_new_i64(); \
7889 TCGv_i64 xal = tcg_temp_new_i64(); \
7890 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7891 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7892 tcg_gen_and_i64(xah, xah, sgm); \
7893 tcg_gen_and_i64(xal, xal, sgm); \
7894 tcg_gen_andc_i64(xbh, xbh, sgm); \
7895 tcg_gen_andc_i64(xbl, xbl, sgm); \
7896 tcg_gen_or_i64(xbh, xbh, xah); \
7897 tcg_gen_or_i64(xbl, xbl, xal); \
7898 tcg_temp_free_i64(xah); \
7899 tcg_temp_free_i64(xal); \
7900 break; \
7901 } \
7902 } \
7903 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7904 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7905 tcg_temp_free_i64(xbh); \
7906 tcg_temp_free_i64(xbl); \
7907 tcg_temp_free_i64(sgm); \
7908 }
7909
7910 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7911 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7912 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7913 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7914 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7915 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7916 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7917 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7918
7919 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7920 static void gen_##name(DisasContext * ctx) \
7921 { \
7922 TCGv_i32 opc; \
7923 if (unlikely(!ctx->vsx_enabled)) { \
7924 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7925 return; \
7926 } \
7927 /* NIP cannot be restored if the memory exception comes from an helper */ \
7928 gen_update_nip(ctx, ctx->nip - 4); \
7929 opc = tcg_const_i32(ctx->opcode); \
7930 gen_helper_##name(cpu_env, opc); \
7931 tcg_temp_free_i32(opc); \
7932 }
7933
7934 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7935 static void gen_##name(DisasContext * ctx) \
7936 { \
7937 if (unlikely(!ctx->vsx_enabled)) { \
7938 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7939 return; \
7940 } \
7941 /* NIP cannot be restored if the exception comes */ \
7942 /* from a helper. */ \
7943 gen_update_nip(ctx, ctx->nip - 4); \
7944 \
7945 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7946 cpu_vsrh(xB(ctx->opcode))); \
7947 }
7948
7949 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7950 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7951 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7952 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7953 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7954 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7955 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7956 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7957 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7958 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7959 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7960 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7961 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7962 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7963 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7964 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7965 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7966 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7967 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7968 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7969 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7970 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7971 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7972 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7973 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7974 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7975 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7976 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7977 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7978 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7979 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7980 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7981 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7982 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7983 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7984 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7985 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7986
7987 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7988 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7989 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7990 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7991 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7992 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7993 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7994 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7995 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7996 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7997 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7998 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7999 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8000 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8001 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
8002 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8003 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
8004
8005 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8006 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
8007 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
8008 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8009 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8010 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8011 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8012 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8013 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8014 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8015 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8016 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8017 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8018 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8019 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8020 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8021 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8022 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8023 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8024 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8025 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8026 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8027 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8028 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8029 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8030 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8031 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8032 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8033 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8034 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8035 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8036 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8037 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8038 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8039 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8040 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8041
8042 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8043 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8044 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8045 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8046 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8047 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8048 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8049 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8050 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8051 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8052 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8053 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8054 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8055 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8056 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8057 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8058 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8059 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8060 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8061 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8062 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8063 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8064 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8065 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8066 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8067 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8068 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8069 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8070 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8071 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8072 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8073 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8074 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8075 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8076 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8077 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8078
8079 #define VSX_LOGICAL(name, tcg_op) \
8080 static void glue(gen_, name)(DisasContext * ctx) \
8081 { \
8082 if (unlikely(!ctx->vsx_enabled)) { \
8083 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8084 return; \
8085 } \
8086 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8087 cpu_vsrh(xB(ctx->opcode))); \
8088 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8089 cpu_vsrl(xB(ctx->opcode))); \
8090 }
8091
8092 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8093 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8094 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8095 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8096 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8097 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8098 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8099 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8100
8101 #define VSX_XXMRG(name, high) \
8102 static void glue(gen_, name)(DisasContext * ctx) \
8103 { \
8104 TCGv_i64 a0, a1, b0, b1; \
8105 if (unlikely(!ctx->vsx_enabled)) { \
8106 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8107 return; \
8108 } \
8109 a0 = tcg_temp_new_i64(); \
8110 a1 = tcg_temp_new_i64(); \
8111 b0 = tcg_temp_new_i64(); \
8112 b1 = tcg_temp_new_i64(); \
8113 if (high) { \
8114 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8115 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8116 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8117 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8118 } else { \
8119 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8120 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8121 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8122 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8123 } \
8124 tcg_gen_shri_i64(a0, a0, 32); \
8125 tcg_gen_shri_i64(b0, b0, 32); \
8126 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8127 b0, a0, 32, 32); \
8128 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8129 b1, a1, 32, 32); \
8130 tcg_temp_free_i64(a0); \
8131 tcg_temp_free_i64(a1); \
8132 tcg_temp_free_i64(b0); \
8133 tcg_temp_free_i64(b1); \
8134 }
8135
8136 VSX_XXMRG(xxmrghw, 1)
8137 VSX_XXMRG(xxmrglw, 0)
8138
8139 static void gen_xxsel(DisasContext * ctx)
8140 {
8141 TCGv_i64 a, b, c;
8142 if (unlikely(!ctx->vsx_enabled)) {
8143 gen_exception(ctx, POWERPC_EXCP_VSXU);
8144 return;
8145 }
8146 a = tcg_temp_new_i64();
8147 b = tcg_temp_new_i64();
8148 c = tcg_temp_new_i64();
8149
8150 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8151 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8152 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8153
8154 tcg_gen_and_i64(b, b, c);
8155 tcg_gen_andc_i64(a, a, c);
8156 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8157
8158 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8159 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8160 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8161
8162 tcg_gen_and_i64(b, b, c);
8163 tcg_gen_andc_i64(a, a, c);
8164 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8165
8166 tcg_temp_free_i64(a);
8167 tcg_temp_free_i64(b);
8168 tcg_temp_free_i64(c);
8169 }
8170
8171 static void gen_xxspltw(DisasContext *ctx)
8172 {
8173 TCGv_i64 b, b2;
8174 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8175 cpu_vsrl(xB(ctx->opcode)) :
8176 cpu_vsrh(xB(ctx->opcode));
8177
8178 if (unlikely(!ctx->vsx_enabled)) {
8179 gen_exception(ctx, POWERPC_EXCP_VSXU);
8180 return;
8181 }
8182
8183 b = tcg_temp_new_i64();
8184 b2 = tcg_temp_new_i64();
8185
8186 if (UIM(ctx->opcode) & 1) {
8187 tcg_gen_ext32u_i64(b, vsr);
8188 } else {
8189 tcg_gen_shri_i64(b, vsr, 32);
8190 }
8191
8192 tcg_gen_shli_i64(b2, b, 32);
8193 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8194 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8195
8196 tcg_temp_free_i64(b);
8197 tcg_temp_free_i64(b2);
8198 }
8199
8200 static void gen_xxsldwi(DisasContext *ctx)
8201 {
8202 TCGv_i64 xth, xtl;
8203 if (unlikely(!ctx->vsx_enabled)) {
8204 gen_exception(ctx, POWERPC_EXCP_VSXU);
8205 return;
8206 }
8207 xth = tcg_temp_new_i64();
8208 xtl = tcg_temp_new_i64();
8209
8210 switch (SHW(ctx->opcode)) {
8211 case 0: {
8212 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8213 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8214 break;
8215 }
8216 case 1: {
8217 TCGv_i64 t0 = tcg_temp_new_i64();
8218 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8219 tcg_gen_shli_i64(xth, xth, 32);
8220 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8221 tcg_gen_shri_i64(t0, t0, 32);
8222 tcg_gen_or_i64(xth, xth, t0);
8223 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8224 tcg_gen_shli_i64(xtl, xtl, 32);
8225 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8226 tcg_gen_shri_i64(t0, t0, 32);
8227 tcg_gen_or_i64(xtl, xtl, t0);
8228 tcg_temp_free_i64(t0);
8229 break;
8230 }
8231 case 2: {
8232 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8233 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8234 break;
8235 }
8236 case 3: {
8237 TCGv_i64 t0 = tcg_temp_new_i64();
8238 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8239 tcg_gen_shli_i64(xth, xth, 32);
8240 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8241 tcg_gen_shri_i64(t0, t0, 32);
8242 tcg_gen_or_i64(xth, xth, t0);
8243 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8244 tcg_gen_shli_i64(xtl, xtl, 32);
8245 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8246 tcg_gen_shri_i64(t0, t0, 32);
8247 tcg_gen_or_i64(xtl, xtl, t0);
8248 tcg_temp_free_i64(t0);
8249 break;
8250 }
8251 }
8252
8253 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8254 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8255
8256 tcg_temp_free_i64(xth);
8257 tcg_temp_free_i64(xtl);
8258 }
8259
8260 /*** Decimal Floating Point ***/
8261
8262 static inline TCGv_ptr gen_fprp_ptr(int reg)
8263 {
8264 TCGv_ptr r = tcg_temp_new_ptr();
8265 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8266 return r;
8267 }
8268
8269 #define GEN_DFP_T_A_B_Rc(name) \
8270 static void gen_##name(DisasContext *ctx) \
8271 { \
8272 TCGv_ptr rd, ra, rb; \
8273 if (unlikely(!ctx->fpu_enabled)) { \
8274 gen_exception(ctx, POWERPC_EXCP_FPU); \
8275 return; \
8276 } \
8277 gen_update_nip(ctx, ctx->nip - 4); \
8278 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8279 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8280 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8281 gen_helper_##name(cpu_env, rd, ra, rb); \
8282 if (unlikely(Rc(ctx->opcode) != 0)) { \
8283 gen_set_cr1_from_fpscr(ctx); \
8284 } \
8285 tcg_temp_free_ptr(rd); \
8286 tcg_temp_free_ptr(ra); \
8287 tcg_temp_free_ptr(rb); \
8288 }
8289
8290 #define GEN_DFP_BF_A_B(name) \
8291 static void gen_##name(DisasContext *ctx) \
8292 { \
8293 TCGv_ptr ra, rb; \
8294 if (unlikely(!ctx->fpu_enabled)) { \
8295 gen_exception(ctx, POWERPC_EXCP_FPU); \
8296 return; \
8297 } \
8298 gen_update_nip(ctx, ctx->nip - 4); \
8299 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8300 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8301 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8302 cpu_env, ra, rb); \
8303 tcg_temp_free_ptr(ra); \
8304 tcg_temp_free_ptr(rb); \
8305 }
8306
8307 #define GEN_DFP_BF_A_DCM(name) \
8308 static void gen_##name(DisasContext *ctx) \
8309 { \
8310 TCGv_ptr ra; \
8311 TCGv_i32 dcm; \
8312 if (unlikely(!ctx->fpu_enabled)) { \
8313 gen_exception(ctx, POWERPC_EXCP_FPU); \
8314 return; \
8315 } \
8316 gen_update_nip(ctx, ctx->nip - 4); \
8317 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8318 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8319 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8320 cpu_env, ra, dcm); \
8321 tcg_temp_free_ptr(ra); \
8322 tcg_temp_free_i32(dcm); \
8323 }
8324
8325 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8326 static void gen_##name(DisasContext *ctx) \
8327 { \
8328 TCGv_ptr rt, rb; \
8329 TCGv_i32 u32_1, u32_2; \
8330 if (unlikely(!ctx->fpu_enabled)) { \
8331 gen_exception(ctx, POWERPC_EXCP_FPU); \
8332 return; \
8333 } \
8334 gen_update_nip(ctx, ctx->nip - 4); \
8335 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8336 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8337 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8338 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8339 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8340 if (unlikely(Rc(ctx->opcode) != 0)) { \
8341 gen_set_cr1_from_fpscr(ctx); \
8342 } \
8343 tcg_temp_free_ptr(rt); \
8344 tcg_temp_free_ptr(rb); \
8345 tcg_temp_free_i32(u32_1); \
8346 tcg_temp_free_i32(u32_2); \
8347 }
8348
8349 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8350 static void gen_##name(DisasContext *ctx) \
8351 { \
8352 TCGv_ptr rt, ra, rb; \
8353 TCGv_i32 i32; \
8354 if (unlikely(!ctx->fpu_enabled)) { \
8355 gen_exception(ctx, POWERPC_EXCP_FPU); \
8356 return; \
8357 } \
8358 gen_update_nip(ctx, ctx->nip - 4); \
8359 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8360 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8361 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8362 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8363 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8364 if (unlikely(Rc(ctx->opcode) != 0)) { \
8365 gen_set_cr1_from_fpscr(ctx); \
8366 } \
8367 tcg_temp_free_ptr(rt); \
8368 tcg_temp_free_ptr(rb); \
8369 tcg_temp_free_ptr(ra); \
8370 tcg_temp_free_i32(i32); \
8371 }
8372
8373 #define GEN_DFP_T_B_Rc(name) \
8374 static void gen_##name(DisasContext *ctx) \
8375 { \
8376 TCGv_ptr rt, rb; \
8377 if (unlikely(!ctx->fpu_enabled)) { \
8378 gen_exception(ctx, POWERPC_EXCP_FPU); \
8379 return; \
8380 } \
8381 gen_update_nip(ctx, ctx->nip - 4); \
8382 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8383 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8384 gen_helper_##name(cpu_env, rt, rb); \
8385 if (unlikely(Rc(ctx->opcode) != 0)) { \
8386 gen_set_cr1_from_fpscr(ctx); \
8387 } \
8388 tcg_temp_free_ptr(rt); \
8389 tcg_temp_free_ptr(rb); \
8390 }
8391
8392 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8393 static void gen_##name(DisasContext *ctx) \
8394 { \
8395 TCGv_ptr rt, rs; \
8396 TCGv_i32 i32; \
8397 if (unlikely(!ctx->fpu_enabled)) { \
8398 gen_exception(ctx, POWERPC_EXCP_FPU); \
8399 return; \
8400 } \
8401 gen_update_nip(ctx, ctx->nip - 4); \
8402 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8403 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8404 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8405 gen_helper_##name(cpu_env, rt, rs, i32); \
8406 if (unlikely(Rc(ctx->opcode) != 0)) { \
8407 gen_set_cr1_from_fpscr(ctx); \
8408 } \
8409 tcg_temp_free_ptr(rt); \
8410 tcg_temp_free_ptr(rs); \
8411 tcg_temp_free_i32(i32); \
8412 }
8413
8414 GEN_DFP_T_A_B_Rc(dadd)
8415 GEN_DFP_T_A_B_Rc(daddq)
8416 GEN_DFP_T_A_B_Rc(dsub)
8417 GEN_DFP_T_A_B_Rc(dsubq)
8418 GEN_DFP_T_A_B_Rc(dmul)
8419 GEN_DFP_T_A_B_Rc(dmulq)
8420 GEN_DFP_T_A_B_Rc(ddiv)
8421 GEN_DFP_T_A_B_Rc(ddivq)
8422 GEN_DFP_BF_A_B(dcmpu)
8423 GEN_DFP_BF_A_B(dcmpuq)
8424 GEN_DFP_BF_A_B(dcmpo)
8425 GEN_DFP_BF_A_B(dcmpoq)
8426 GEN_DFP_BF_A_DCM(dtstdc)
8427 GEN_DFP_BF_A_DCM(dtstdcq)
8428 GEN_DFP_BF_A_DCM(dtstdg)
8429 GEN_DFP_BF_A_DCM(dtstdgq)
8430 GEN_DFP_BF_A_B(dtstex)
8431 GEN_DFP_BF_A_B(dtstexq)
8432 GEN_DFP_BF_A_B(dtstsf)
8433 GEN_DFP_BF_A_B(dtstsfq)
8434 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8435 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8436 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8437 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8438 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8439 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8440 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8441 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8442 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8443 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8444 GEN_DFP_T_B_Rc(dctdp)
8445 GEN_DFP_T_B_Rc(dctqpq)
8446 GEN_DFP_T_B_Rc(drsp)
8447 GEN_DFP_T_B_Rc(drdpq)
8448 GEN_DFP_T_B_Rc(dcffix)
8449 GEN_DFP_T_B_Rc(dcffixq)
8450 GEN_DFP_T_B_Rc(dctfix)
8451 GEN_DFP_T_B_Rc(dctfixq)
8452 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8453 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8454 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8455 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8456 GEN_DFP_T_B_Rc(dxex)
8457 GEN_DFP_T_B_Rc(dxexq)
8458 GEN_DFP_T_A_B_Rc(diex)
8459 GEN_DFP_T_A_B_Rc(diexq)
8460 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8461 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8462 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8463 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8464
8465 /*** SPE extension ***/
8466 /* Register moves */
8467
8468 static inline void gen_evmra(DisasContext *ctx)
8469 {
8470
8471 if (unlikely(!ctx->spe_enabled)) {
8472 gen_exception(ctx, POWERPC_EXCP_SPEU);
8473 return;
8474 }
8475
8476 TCGv_i64 tmp = tcg_temp_new_i64();
8477
8478 /* tmp := rA_lo + rA_hi << 32 */
8479 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8480
8481 /* spe_acc := tmp */
8482 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8483 tcg_temp_free_i64(tmp);
8484
8485 /* rD := rA */
8486 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8487 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8488 }
8489
8490 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8491 {
8492 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8493 }
8494
8495 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8496 {
8497 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8498 }
8499
8500 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8501 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8502 { \
8503 if (Rc(ctx->opcode)) \
8504 gen_##name1(ctx); \
8505 else \
8506 gen_##name0(ctx); \
8507 }
8508
8509 /* Handler for undefined SPE opcodes */
8510 static inline void gen_speundef(DisasContext *ctx)
8511 {
8512 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8513 }
8514
8515 /* SPE logic */
8516 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8517 static inline void gen_##name(DisasContext *ctx) \
8518 { \
8519 if (unlikely(!ctx->spe_enabled)) { \
8520 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8521 return; \
8522 } \
8523 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8524 cpu_gpr[rB(ctx->opcode)]); \
8525 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8526 cpu_gprh[rB(ctx->opcode)]); \
8527 }
8528
8529 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8530 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8531 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8532 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8533 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8534 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8535 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8536 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8537
8538 /* SPE logic immediate */
8539 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8540 static inline void gen_##name(DisasContext *ctx) \
8541 { \
8542 TCGv_i32 t0; \
8543 if (unlikely(!ctx->spe_enabled)) { \
8544 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8545 return; \
8546 } \
8547 t0 = tcg_temp_new_i32(); \
8548 \
8549 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8550 tcg_opi(t0, t0, rB(ctx->opcode)); \
8551 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8552 \
8553 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8554 tcg_opi(t0, t0, rB(ctx->opcode)); \
8555 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8556 \
8557 tcg_temp_free_i32(t0); \
8558 }
8559 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8560 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8561 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8562 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8563
8564 /* SPE arithmetic */
8565 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8566 static inline void gen_##name(DisasContext *ctx) \
8567 { \
8568 TCGv_i32 t0; \
8569 if (unlikely(!ctx->spe_enabled)) { \
8570 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8571 return; \
8572 } \
8573 t0 = tcg_temp_new_i32(); \
8574 \
8575 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8576 tcg_op(t0, t0); \
8577 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8578 \
8579 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8580 tcg_op(t0, t0); \
8581 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8582 \
8583 tcg_temp_free_i32(t0); \
8584 }
8585
8586 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8587 {
8588 TCGLabel *l1 = gen_new_label();
8589 TCGLabel *l2 = gen_new_label();
8590
8591 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8592 tcg_gen_neg_i32(ret, arg1);
8593 tcg_gen_br(l2);
8594 gen_set_label(l1);
8595 tcg_gen_mov_i32(ret, arg1);
8596 gen_set_label(l2);
8597 }
8598 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8599 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8600 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8601 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8602 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8603 {
8604 tcg_gen_addi_i32(ret, arg1, 0x8000);
8605 tcg_gen_ext16u_i32(ret, ret);
8606 }
8607 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8608 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8609 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8610
8611 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8612 static inline void gen_##name(DisasContext *ctx) \
8613 { \
8614 TCGv_i32 t0, t1; \
8615 if (unlikely(!ctx->spe_enabled)) { \
8616 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8617 return; \
8618 } \
8619 t0 = tcg_temp_new_i32(); \
8620 t1 = tcg_temp_new_i32(); \
8621 \
8622 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8623 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8624 tcg_op(t0, t0, t1); \
8625 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8626 \
8627 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8628 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8629 tcg_op(t0, t0, t1); \
8630 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8631 \
8632 tcg_temp_free_i32(t0); \
8633 tcg_temp_free_i32(t1); \
8634 }
8635
8636 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8637 {
8638 TCGLabel *l1 = gen_new_label();
8639 TCGLabel *l2 = gen_new_label();
8640 TCGv_i32 t0 = tcg_temp_local_new_i32();
8641
8642 /* No error here: 6 bits are used */
8643 tcg_gen_andi_i32(t0, arg2, 0x3F);
8644 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8645 tcg_gen_shr_i32(ret, arg1, t0);
8646 tcg_gen_br(l2);
8647 gen_set_label(l1);
8648 tcg_gen_movi_i32(ret, 0);
8649 gen_set_label(l2);
8650 tcg_temp_free_i32(t0);
8651 }
8652 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8653 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8654 {
8655 TCGLabel *l1 = gen_new_label();
8656 TCGLabel *l2 = gen_new_label();
8657 TCGv_i32 t0 = tcg_temp_local_new_i32();
8658
8659 /* No error here: 6 bits are used */
8660 tcg_gen_andi_i32(t0, arg2, 0x3F);
8661 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8662 tcg_gen_sar_i32(ret, arg1, t0);
8663 tcg_gen_br(l2);
8664 gen_set_label(l1);
8665 tcg_gen_movi_i32(ret, 0);
8666 gen_set_label(l2);
8667 tcg_temp_free_i32(t0);
8668 }
8669 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8670 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8671 {
8672 TCGLabel *l1 = gen_new_label();
8673 TCGLabel *l2 = gen_new_label();
8674 TCGv_i32 t0 = tcg_temp_local_new_i32();
8675
8676 /* No error here: 6 bits are used */
8677 tcg_gen_andi_i32(t0, arg2, 0x3F);
8678 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8679 tcg_gen_shl_i32(ret, arg1, t0);
8680 tcg_gen_br(l2);
8681 gen_set_label(l1);
8682 tcg_gen_movi_i32(ret, 0);
8683 gen_set_label(l2);
8684 tcg_temp_free_i32(t0);
8685 }
8686 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8687 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8688 {
8689 TCGv_i32 t0 = tcg_temp_new_i32();
8690 tcg_gen_andi_i32(t0, arg2, 0x1F);
8691 tcg_gen_rotl_i32(ret, arg1, t0);
8692 tcg_temp_free_i32(t0);
8693 }
8694 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8695 static inline void gen_evmergehi(DisasContext *ctx)
8696 {
8697 if (unlikely(!ctx->spe_enabled)) {
8698 gen_exception(ctx, POWERPC_EXCP_SPEU);
8699 return;
8700 }
8701 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8702 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8703 }
8704 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8705 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8706 {
8707 tcg_gen_sub_i32(ret, arg2, arg1);
8708 }
8709 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8710
8711 /* SPE arithmetic immediate */
8712 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8713 static inline void gen_##name(DisasContext *ctx) \
8714 { \
8715 TCGv_i32 t0; \
8716 if (unlikely(!ctx->spe_enabled)) { \
8717 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8718 return; \
8719 } \
8720 t0 = tcg_temp_new_i32(); \
8721 \
8722 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8723 tcg_op(t0, t0, rA(ctx->opcode)); \
8724 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8725 \
8726 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8727 tcg_op(t0, t0, rA(ctx->opcode)); \
8728 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8729 \
8730 tcg_temp_free_i32(t0); \
8731 }
8732 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8733 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8734
8735 /* SPE comparison */
8736 #define GEN_SPEOP_COMP(name, tcg_cond) \
8737 static inline void gen_##name(DisasContext *ctx) \
8738 { \
8739 if (unlikely(!ctx->spe_enabled)) { \
8740 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8741 return; \
8742 } \
8743 TCGLabel *l1 = gen_new_label(); \
8744 TCGLabel *l2 = gen_new_label(); \
8745 TCGLabel *l3 = gen_new_label(); \
8746 TCGLabel *l4 = gen_new_label(); \
8747 \
8748 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8749 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8750 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8751 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8752 \
8753 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8754 cpu_gpr[rB(ctx->opcode)], l1); \
8755 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8756 tcg_gen_br(l2); \
8757 gen_set_label(l1); \
8758 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8759 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8760 gen_set_label(l2); \
8761 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8762 cpu_gprh[rB(ctx->opcode)], l3); \
8763 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8764 ~(CRF_CH | CRF_CH_AND_CL)); \
8765 tcg_gen_br(l4); \
8766 gen_set_label(l3); \
8767 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8768 CRF_CH | CRF_CH_OR_CL); \
8769 gen_set_label(l4); \
8770 }
8771 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8772 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8773 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8774 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8775 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8776
8777 /* SPE misc */
8778 static inline void gen_brinc(DisasContext *ctx)
8779 {
8780 /* Note: brinc is usable even if SPE is disabled */
8781 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8782 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8783 }
8784 static inline void gen_evmergelo(DisasContext *ctx)
8785 {
8786 if (unlikely(!ctx->spe_enabled)) {
8787 gen_exception(ctx, POWERPC_EXCP_SPEU);
8788 return;
8789 }
8790 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8791 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8792 }
8793 static inline void gen_evmergehilo(DisasContext *ctx)
8794 {
8795 if (unlikely(!ctx->spe_enabled)) {
8796 gen_exception(ctx, POWERPC_EXCP_SPEU);
8797 return;
8798 }
8799 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8800 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8801 }
8802 static inline void gen_evmergelohi(DisasContext *ctx)
8803 {
8804 if (unlikely(!ctx->spe_enabled)) {
8805 gen_exception(ctx, POWERPC_EXCP_SPEU);
8806 return;
8807 }
8808 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8809 TCGv tmp = tcg_temp_new();
8810 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8811 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8812 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8813 tcg_temp_free(tmp);
8814 } else {
8815 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8816 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8817 }
8818 }
8819 static inline void gen_evsplati(DisasContext *ctx)
8820 {
8821 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8822
8823 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8824 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8825 }
8826 static inline void gen_evsplatfi(DisasContext *ctx)
8827 {
8828 uint64_t imm = rA(ctx->opcode) << 27;
8829
8830 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8831 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8832 }
8833
8834 static inline void gen_evsel(DisasContext *ctx)
8835 {
8836 TCGLabel *l1 = gen_new_label();
8837 TCGLabel *l2 = gen_new_label();
8838 TCGLabel *l3 = gen_new_label();
8839 TCGLabel *l4 = gen_new_label();
8840 TCGv_i32 t0 = tcg_temp_local_new_i32();
8841
8842 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8843 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8844 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8845 tcg_gen_br(l2);
8846 gen_set_label(l1);
8847 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8848 gen_set_label(l2);
8849 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8850 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8851 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8852 tcg_gen_br(l4);
8853 gen_set_label(l3);
8854 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8855 gen_set_label(l4);
8856 tcg_temp_free_i32(t0);
8857 }
8858
8859 static void gen_evsel0(DisasContext *ctx)
8860 {
8861 gen_evsel(ctx);
8862 }
8863
8864 static void gen_evsel1(DisasContext *ctx)
8865 {
8866 gen_evsel(ctx);
8867 }
8868
8869 static void gen_evsel2(DisasContext *ctx)
8870 {
8871 gen_evsel(ctx);
8872 }
8873
8874 static void gen_evsel3(DisasContext *ctx)
8875 {
8876 gen_evsel(ctx);
8877 }
8878
8879 /* Multiply */
8880
8881 static inline void gen_evmwumi(DisasContext *ctx)
8882 {
8883 TCGv_i64 t0, t1;
8884
8885 if (unlikely(!ctx->spe_enabled)) {
8886 gen_exception(ctx, POWERPC_EXCP_SPEU);
8887 return;
8888 }
8889
8890 t0 = tcg_temp_new_i64();
8891 t1 = tcg_temp_new_i64();
8892
8893 /* t0 := rA; t1 := rB */
8894 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8895 tcg_gen_ext32u_i64(t0, t0);
8896 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8897 tcg_gen_ext32u_i64(t1, t1);
8898
8899 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8900
8901 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8902
8903 tcg_temp_free_i64(t0);
8904 tcg_temp_free_i64(t1);
8905 }
8906
8907 static inline void gen_evmwumia(DisasContext *ctx)
8908 {
8909 TCGv_i64 tmp;
8910
8911 if (unlikely(!ctx->spe_enabled)) {
8912 gen_exception(ctx, POWERPC_EXCP_SPEU);
8913 return;
8914 }
8915
8916 gen_evmwumi(ctx); /* rD := rA * rB */
8917
8918 tmp = tcg_temp_new_i64();
8919
8920 /* acc := rD */
8921 gen_load_gpr64(tmp, rD(ctx->opcode));
8922 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8923 tcg_temp_free_i64(tmp);
8924 }
8925
8926 static inline void gen_evmwumiaa(DisasContext *ctx)
8927 {
8928 TCGv_i64 acc;
8929 TCGv_i64 tmp;
8930
8931 if (unlikely(!ctx->spe_enabled)) {
8932 gen_exception(ctx, POWERPC_EXCP_SPEU);
8933 return;
8934 }
8935
8936 gen_evmwumi(ctx); /* rD := rA * rB */
8937
8938 acc = tcg_temp_new_i64();
8939 tmp = tcg_temp_new_i64();
8940
8941 /* tmp := rD */
8942 gen_load_gpr64(tmp, rD(ctx->opcode));
8943
8944 /* Load acc */
8945 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8946
8947 /* acc := tmp + acc */
8948 tcg_gen_add_i64(acc, acc, tmp);
8949
8950 /* Store acc */
8951 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8952
8953 /* rD := acc */
8954 gen_store_gpr64(rD(ctx->opcode), acc);
8955
8956 tcg_temp_free_i64(acc);
8957 tcg_temp_free_i64(tmp);
8958 }
8959
8960 static inline void gen_evmwsmi(DisasContext *ctx)
8961 {
8962 TCGv_i64 t0, t1;
8963
8964 if (unlikely(!ctx->spe_enabled)) {
8965 gen_exception(ctx, POWERPC_EXCP_SPEU);
8966 return;
8967 }
8968
8969 t0 = tcg_temp_new_i64();
8970 t1 = tcg_temp_new_i64();
8971
8972 /* t0 := rA; t1 := rB */
8973 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8974 tcg_gen_ext32s_i64(t0, t0);
8975 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8976 tcg_gen_ext32s_i64(t1, t1);
8977
8978 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8979
8980 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8981
8982 tcg_temp_free_i64(t0);
8983 tcg_temp_free_i64(t1);
8984 }
8985
8986 static inline void gen_evmwsmia(DisasContext *ctx)
8987 {
8988 TCGv_i64 tmp;
8989
8990 gen_evmwsmi(ctx); /* rD := rA * rB */
8991
8992 tmp = tcg_temp_new_i64();
8993
8994 /* acc := rD */
8995 gen_load_gpr64(tmp, rD(ctx->opcode));
8996 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8997
8998 tcg_temp_free_i64(tmp);
8999 }
9000
9001 static inline void gen_evmwsmiaa(DisasContext *ctx)
9002 {
9003 TCGv_i64 acc = tcg_temp_new_i64();
9004 TCGv_i64 tmp = tcg_temp_new_i64();
9005
9006 gen_evmwsmi(ctx); /* rD := rA * rB */
9007
9008 acc = tcg_temp_new_i64();
9009 tmp = tcg_temp_new_i64();
9010
9011 /* tmp := rD */
9012 gen_load_gpr64(tmp, rD(ctx->opcode));
9013
9014 /* Load acc */
9015 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9016
9017 /* acc := tmp + acc */
9018 tcg_gen_add_i64(acc, acc, tmp);
9019
9020 /* Store acc */
9021 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9022
9023 /* rD := acc */
9024 gen_store_gpr64(rD(ctx->opcode), acc);
9025
9026 tcg_temp_free_i64(acc);
9027 tcg_temp_free_i64(tmp);
9028 }
9029
9030 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9031 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9032 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9033 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9034 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9035 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9036 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9037 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9038 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9039 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9040 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9041 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9042 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9043 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9044 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9045 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9046 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9047 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9048 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9049 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9050 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9051 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9052 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9053 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9054 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9055 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9056 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9057 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9058 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9059
9060 /* SPE load and stores */
9061 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9062 {
9063 target_ulong uimm = rB(ctx->opcode);
9064
9065 if (rA(ctx->opcode) == 0) {
9066 tcg_gen_movi_tl(EA, uimm << sh);
9067 } else {
9068 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9069 if (NARROW_MODE(ctx)) {
9070 tcg_gen_ext32u_tl(EA, EA);
9071 }
9072 }
9073 }
9074
9075 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9076 {
9077 TCGv_i64 t0 = tcg_temp_new_i64();
9078 gen_qemu_ld64(ctx, t0, addr);
9079 gen_store_gpr64(rD(ctx->opcode), t0);
9080 tcg_temp_free_i64(t0);
9081 }
9082
9083 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9084 {
9085 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9086 gen_addr_add(ctx, addr, addr, 4);
9087 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9088 }
9089
9090 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9091 {
9092 TCGv t0 = tcg_temp_new();
9093 gen_qemu_ld16u(ctx, t0, addr);
9094 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9095 gen_addr_add(ctx, addr, addr, 2);
9096 gen_qemu_ld16u(ctx, t0, addr);
9097 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9098 gen_addr_add(ctx, addr, addr, 2);
9099 gen_qemu_ld16u(ctx, t0, addr);
9100 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9101 gen_addr_add(ctx, addr, addr, 2);
9102 gen_qemu_ld16u(ctx, t0, addr);
9103 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9104 tcg_temp_free(t0);
9105 }
9106
9107 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9108 {
9109 TCGv t0 = tcg_temp_new();
9110 gen_qemu_ld16u(ctx, t0, addr);
9111 tcg_gen_shli_tl(t0, t0, 16);
9112 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9113 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9114 tcg_temp_free(t0);
9115 }
9116
9117 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9118 {
9119 TCGv t0 = tcg_temp_new();
9120 gen_qemu_ld16u(ctx, t0, addr);
9121 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9122 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9123 tcg_temp_free(t0);
9124 }
9125
9126 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9127 {
9128 TCGv t0 = tcg_temp_new();
9129 gen_qemu_ld16s(ctx, t0, addr);
9130 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9131 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9132 tcg_temp_free(t0);
9133 }
9134
9135 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9136 {
9137 TCGv t0 = tcg_temp_new();
9138 gen_qemu_ld16u(ctx, t0, addr);
9139 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9140 gen_addr_add(ctx, addr, addr, 2);
9141 gen_qemu_ld16u(ctx, t0, addr);
9142 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9143 tcg_temp_free(t0);
9144 }
9145
9146 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9147 {
9148 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9149 gen_addr_add(ctx, addr, addr, 2);
9150 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9151 }
9152
9153 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9154 {
9155 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9156 gen_addr_add(ctx, addr, addr, 2);
9157 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9158 }
9159
9160 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9161 {
9162 TCGv t0 = tcg_temp_new();
9163 gen_qemu_ld32u(ctx, t0, addr);
9164 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9165 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9166 tcg_temp_free(t0);
9167 }
9168
9169 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9170 {
9171 TCGv t0 = tcg_temp_new();
9172 gen_qemu_ld16u(ctx, t0, addr);
9173 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9174 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9175 gen_addr_add(ctx, addr, addr, 2);
9176 gen_qemu_ld16u(ctx, t0, addr);
9177 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9178 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9179 tcg_temp_free(t0);
9180 }
9181
9182 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9183 {
9184 TCGv_i64 t0 = tcg_temp_new_i64();
9185 gen_load_gpr64(t0, rS(ctx->opcode));
9186 gen_qemu_st64(ctx, t0, addr);
9187 tcg_temp_free_i64(t0);
9188 }
9189
9190 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9191 {
9192 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9193 gen_addr_add(ctx, addr, addr, 4);
9194 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9195 }
9196
9197 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9198 {
9199 TCGv t0 = tcg_temp_new();
9200 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9201 gen_qemu_st16(ctx, t0, addr);
9202 gen_addr_add(ctx, addr, addr, 2);
9203 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9204 gen_addr_add(ctx, addr, addr, 2);
9205 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9206 gen_qemu_st16(ctx, t0, addr);
9207 tcg_temp_free(t0);
9208 gen_addr_add(ctx, addr, addr, 2);
9209 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9210 }
9211
9212 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9213 {
9214 TCGv t0 = tcg_temp_new();
9215 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9216 gen_qemu_st16(ctx, t0, addr);
9217 gen_addr_add(ctx, addr, addr, 2);
9218 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9219 gen_qemu_st16(ctx, t0, addr);
9220 tcg_temp_free(t0);
9221 }
9222
9223 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9224 {
9225 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9226 gen_addr_add(ctx, addr, addr, 2);
9227 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9228 }
9229
9230 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9231 {
9232 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9233 }
9234
9235 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9236 {
9237 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9238 }
9239
9240 #define GEN_SPEOP_LDST(name, opc2, sh) \
9241 static void glue(gen_, name)(DisasContext *ctx) \
9242 { \
9243 TCGv t0; \
9244 if (unlikely(!ctx->spe_enabled)) { \
9245 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9246 return; \
9247 } \
9248 gen_set_access_type(ctx, ACCESS_INT); \
9249 t0 = tcg_temp_new(); \
9250 if (Rc(ctx->opcode)) { \
9251 gen_addr_spe_imm_index(ctx, t0, sh); \
9252 } else { \
9253 gen_addr_reg_index(ctx, t0); \
9254 } \
9255 gen_op_##name(ctx, t0); \
9256 tcg_temp_free(t0); \
9257 }
9258
9259 GEN_SPEOP_LDST(evldd, 0x00, 3);
9260 GEN_SPEOP_LDST(evldw, 0x01, 3);
9261 GEN_SPEOP_LDST(evldh, 0x02, 3);
9262 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9263 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9264 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9265 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9266 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9267 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9268 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9269 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9270
9271 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9272 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9273 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9274 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9275 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9276 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9277 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9278
9279 /* Multiply and add - TODO */
9280 #if 0
9281 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9282 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9283 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9284 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9285 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9286 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9287 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9288 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9289 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9290 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9291 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9292 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9293
9294 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9295 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9296 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9297 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9298 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9299 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9300 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9301 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9302 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9303 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9304 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9305 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9306
9307 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9308 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9309 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9310 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9311 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9312
9313 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9314 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9315 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9316 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9317 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9318 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9319 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9320 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9321 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9322 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9323 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9324 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9325
9326 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9327 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9328 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9329 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9330
9331 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9332 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9333 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9334 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9335 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9336 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9337 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9338 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9339 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9340 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9341 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9342 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9343
9344 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9345 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9346 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9347 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9348 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9349 #endif
9350
9351 /*** SPE floating-point extension ***/
9352 #define GEN_SPEFPUOP_CONV_32_32(name) \
9353 static inline void gen_##name(DisasContext *ctx) \
9354 { \
9355 TCGv_i32 t0 = tcg_temp_new_i32(); \
9356 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9357 gen_helper_##name(t0, cpu_env, t0); \
9358 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9359 tcg_temp_free_i32(t0); \
9360 }
9361 #define GEN_SPEFPUOP_CONV_32_64(name) \
9362 static inline void gen_##name(DisasContext *ctx) \
9363 { \
9364 TCGv_i64 t0 = tcg_temp_new_i64(); \
9365 TCGv_i32 t1 = tcg_temp_new_i32(); \
9366 gen_load_gpr64(t0, rB(ctx->opcode)); \
9367 gen_helper_##name(t1, cpu_env, t0); \
9368 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9369 tcg_temp_free_i64(t0); \
9370 tcg_temp_free_i32(t1); \
9371 }
9372 #define GEN_SPEFPUOP_CONV_64_32(name) \
9373 static inline void gen_##name(DisasContext *ctx) \
9374 { \
9375 TCGv_i64 t0 = tcg_temp_new_i64(); \
9376 TCGv_i32 t1 = tcg_temp_new_i32(); \
9377 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9378 gen_helper_##name(t0, cpu_env, t1); \
9379 gen_store_gpr64(rD(ctx->opcode), t0); \
9380 tcg_temp_free_i64(t0); \
9381 tcg_temp_free_i32(t1); \
9382 }
9383 #define GEN_SPEFPUOP_CONV_64_64(name) \
9384 static inline void gen_##name(DisasContext *ctx) \
9385 { \
9386 TCGv_i64 t0 = tcg_temp_new_i64(); \
9387 gen_load_gpr64(t0, rB(ctx->opcode)); \
9388 gen_helper_##name(t0, cpu_env, t0); \
9389 gen_store_gpr64(rD(ctx->opcode), t0); \
9390 tcg_temp_free_i64(t0); \
9391 }
9392 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9393 static inline void gen_##name(DisasContext *ctx) \
9394 { \
9395 TCGv_i32 t0, t1; \
9396 if (unlikely(!ctx->spe_enabled)) { \
9397 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9398 return; \
9399 } \
9400 t0 = tcg_temp_new_i32(); \
9401 t1 = tcg_temp_new_i32(); \
9402 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9403 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9404 gen_helper_##name(t0, cpu_env, t0, t1); \
9405 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9406 \
9407 tcg_temp_free_i32(t0); \
9408 tcg_temp_free_i32(t1); \
9409 }
9410 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9411 static inline void gen_##name(DisasContext *ctx) \
9412 { \
9413 TCGv_i64 t0, t1; \
9414 if (unlikely(!ctx->spe_enabled)) { \
9415 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9416 return; \
9417 } \
9418 t0 = tcg_temp_new_i64(); \
9419 t1 = tcg_temp_new_i64(); \
9420 gen_load_gpr64(t0, rA(ctx->opcode)); \
9421 gen_load_gpr64(t1, rB(ctx->opcode)); \
9422 gen_helper_##name(t0, cpu_env, t0, t1); \
9423 gen_store_gpr64(rD(ctx->opcode), t0); \
9424 tcg_temp_free_i64(t0); \
9425 tcg_temp_free_i64(t1); \
9426 }
9427 #define GEN_SPEFPUOP_COMP_32(name) \
9428 static inline void gen_##name(DisasContext *ctx) \
9429 { \
9430 TCGv_i32 t0, t1; \
9431 if (unlikely(!ctx->spe_enabled)) { \
9432 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9433 return; \
9434 } \
9435 t0 = tcg_temp_new_i32(); \
9436 t1 = tcg_temp_new_i32(); \
9437 \
9438 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9439 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9440 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9441 \
9442 tcg_temp_free_i32(t0); \
9443 tcg_temp_free_i32(t1); \
9444 }
9445 #define GEN_SPEFPUOP_COMP_64(name) \
9446 static inline void gen_##name(DisasContext *ctx) \
9447 { \
9448 TCGv_i64 t0, t1; \
9449 if (unlikely(!ctx->spe_enabled)) { \
9450 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9451 return; \
9452 } \
9453 t0 = tcg_temp_new_i64(); \
9454 t1 = tcg_temp_new_i64(); \
9455 gen_load_gpr64(t0, rA(ctx->opcode)); \
9456 gen_load_gpr64(t1, rB(ctx->opcode)); \
9457 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9458 tcg_temp_free_i64(t0); \
9459 tcg_temp_free_i64(t1); \
9460 }
9461
9462 /* Single precision floating-point vectors operations */
9463 /* Arithmetic */
9464 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9465 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9466 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9467 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9468 static inline void gen_evfsabs(DisasContext *ctx)
9469 {
9470 if (unlikely(!ctx->spe_enabled)) {
9471 gen_exception(ctx, POWERPC_EXCP_SPEU);
9472 return;
9473 }
9474 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9475 ~0x80000000);
9476 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9477 ~0x80000000);
9478 }
9479 static inline void gen_evfsnabs(DisasContext *ctx)
9480 {
9481 if (unlikely(!ctx->spe_enabled)) {
9482 gen_exception(ctx, POWERPC_EXCP_SPEU);
9483 return;
9484 }
9485 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9486 0x80000000);
9487 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9488 0x80000000);
9489 }
9490 static inline void gen_evfsneg(DisasContext *ctx)
9491 {
9492 if (unlikely(!ctx->spe_enabled)) {
9493 gen_exception(ctx, POWERPC_EXCP_SPEU);
9494 return;
9495 }
9496 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9497 0x80000000);
9498 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9499 0x80000000);
9500 }
9501
9502 /* Conversion */
9503 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9504 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9505 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9506 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9507 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9508 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9509 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9510 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9511 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9512 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9513
9514 /* Comparison */
9515 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9516 GEN_SPEFPUOP_COMP_64(evfscmplt);
9517 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9518 GEN_SPEFPUOP_COMP_64(evfststgt);
9519 GEN_SPEFPUOP_COMP_64(evfststlt);
9520 GEN_SPEFPUOP_COMP_64(evfststeq);
9521
9522 /* Opcodes definitions */
9523 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9524 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9525 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9526 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9527 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9528 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9529 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9530 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9531 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9532 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9533 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9534 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9535 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9536 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9537
9538 /* Single precision floating-point operations */
9539 /* Arithmetic */
9540 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9541 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9542 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9543 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9544 static inline void gen_efsabs(DisasContext *ctx)
9545 {
9546 if (unlikely(!ctx->spe_enabled)) {
9547 gen_exception(ctx, POWERPC_EXCP_SPEU);
9548 return;
9549 }
9550 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9551 }
9552 static inline void gen_efsnabs(DisasContext *ctx)
9553 {
9554 if (unlikely(!ctx->spe_enabled)) {
9555 gen_exception(ctx, POWERPC_EXCP_SPEU);
9556 return;
9557 }
9558 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9559 }
9560 static inline void gen_efsneg(DisasContext *ctx)
9561 {
9562 if (unlikely(!ctx->spe_enabled)) {
9563 gen_exception(ctx, POWERPC_EXCP_SPEU);
9564 return;
9565 }
9566 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9567 }
9568
9569 /* Conversion */
9570 GEN_SPEFPUOP_CONV_32_32(efscfui);
9571 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9572 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9573 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9574 GEN_SPEFPUOP_CONV_32_32(efsctui);
9575 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9576 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9577 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9578 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9579 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9580 GEN_SPEFPUOP_CONV_32_64(efscfd);
9581
9582 /* Comparison */
9583 GEN_SPEFPUOP_COMP_32(efscmpgt);
9584 GEN_SPEFPUOP_COMP_32(efscmplt);
9585 GEN_SPEFPUOP_COMP_32(efscmpeq);
9586 GEN_SPEFPUOP_COMP_32(efststgt);
9587 GEN_SPEFPUOP_COMP_32(efststlt);
9588 GEN_SPEFPUOP_COMP_32(efststeq);
9589
9590 /* Opcodes definitions */
9591 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9592 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9593 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9594 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9595 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9596 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9597 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9598 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9599 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9600 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9601 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9602 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9603 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9604 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9605
9606 /* Double precision floating-point operations */
9607 /* Arithmetic */
9608 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9609 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9610 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9611 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9612 static inline void gen_efdabs(DisasContext *ctx)
9613 {
9614 if (unlikely(!ctx->spe_enabled)) {
9615 gen_exception(ctx, POWERPC_EXCP_SPEU);
9616 return;
9617 }
9618 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9619 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9620 ~0x80000000);
9621 }
9622 static inline void gen_efdnabs(DisasContext *ctx)
9623 {
9624 if (unlikely(!ctx->spe_enabled)) {
9625 gen_exception(ctx, POWERPC_EXCP_SPEU);
9626 return;
9627 }
9628 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9629 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9630 0x80000000);
9631 }
9632 static inline void gen_efdneg(DisasContext *ctx)
9633 {
9634 if (unlikely(!ctx->spe_enabled)) {
9635 gen_exception(ctx, POWERPC_EXCP_SPEU);
9636 return;
9637 }
9638 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9639 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9640 0x80000000);
9641 }
9642
9643 /* Conversion */
9644 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9645 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9646 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9647 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9648 GEN_SPEFPUOP_CONV_32_64(efdctui);
9649 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9650 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9651 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9652 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9653 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9654 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9655 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9656 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9657 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9658 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9659
9660 /* Comparison */
9661 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9662 GEN_SPEFPUOP_COMP_64(efdcmplt);
9663 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9664 GEN_SPEFPUOP_COMP_64(efdtstgt);
9665 GEN_SPEFPUOP_COMP_64(efdtstlt);
9666 GEN_SPEFPUOP_COMP_64(efdtsteq);
9667
9668 /* Opcodes definitions */
9669 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9670 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9671 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9672 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9673 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9674 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9675 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9676 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9677 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9678 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9679 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9680 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9681 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9682 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9683 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9684 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9685
9686 static void gen_tbegin(DisasContext *ctx)
9687 {
9688 if (unlikely(!ctx->tm_enabled)) {
9689 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9690 return;
9691 }
9692 gen_helper_tbegin(cpu_env);
9693 }
9694
9695 #define GEN_TM_NOOP(name) \
9696 static inline void gen_##name(DisasContext *ctx) \
9697 { \
9698 if (unlikely(!ctx->tm_enabled)) { \
9699 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9700 return; \
9701 } \
9702 /* Because tbegin always fails in QEMU, these user \
9703 * space instructions all have a simple implementation: \
9704 * \
9705 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9706 * = 0b0 || 0b00 || 0b0 \
9707 */ \
9708 tcg_gen_movi_i32(cpu_crf[0], 0); \
9709 }
9710
9711 GEN_TM_NOOP(tend);
9712 GEN_TM_NOOP(tabort);
9713 GEN_TM_NOOP(tabortwc);
9714 GEN_TM_NOOP(tabortwci);
9715 GEN_TM_NOOP(tabortdc);
9716 GEN_TM_NOOP(tabortdci);
9717 GEN_TM_NOOP(tsr);
9718
9719 static void gen_tcheck(DisasContext *ctx)
9720 {
9721 if (unlikely(!ctx->tm_enabled)) {
9722 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9723 return;
9724 }
9725 /* Because tbegin always fails, the tcheck implementation
9726 * is simple:
9727 *
9728 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9729 * = 0b1 || 0b00 || 0b0
9730 */
9731 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9732 }
9733
9734 #if defined(CONFIG_USER_ONLY)
9735 #define GEN_TM_PRIV_NOOP(name) \
9736 static inline void gen_##name(DisasContext *ctx) \
9737 { \
9738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9739 }
9740
9741 #else
9742
9743 #define GEN_TM_PRIV_NOOP(name) \
9744 static inline void gen_##name(DisasContext *ctx) \
9745 { \
9746 if (unlikely(ctx->pr)) { \
9747 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9748 return; \
9749 } \
9750 if (unlikely(!ctx->tm_enabled)) { \
9751 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9752 return; \
9753 } \
9754 /* Because tbegin always fails, the implementation is \
9755 * simple: \
9756 * \
9757 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9758 * = 0b0 || 0b00 | 0b0 \
9759 */ \
9760 tcg_gen_movi_i32(cpu_crf[0], 0); \
9761 }
9762
9763 #endif
9764
9765 GEN_TM_PRIV_NOOP(treclaim);
9766 GEN_TM_PRIV_NOOP(trechkpt);
9767
9768 static opcode_t opcodes[] = {
9769 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9770 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9771 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9772 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9773 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9774 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9775 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9776 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9777 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9778 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9779 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9780 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9781 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9782 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9783 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9784 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9785 #if defined(TARGET_PPC64)
9786 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9787 #endif
9788 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9789 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9790 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9791 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9792 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9793 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9794 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9795 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9796 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9797 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9798 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9799 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9800 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9801 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9802 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9803 #if defined(TARGET_PPC64)
9804 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9805 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9806 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9807 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9808 #endif
9809 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9810 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9811 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9812 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9813 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9814 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9815 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9816 #if defined(TARGET_PPC64)
9817 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9818 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9819 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9820 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9821 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9822 #endif
9823 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9824 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9825 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9826 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9827 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9828 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9829 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9830 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9831 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9832 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9833 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9834 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9835 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9836 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9837 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9838 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9839 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9840 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9841 #if defined(TARGET_PPC64)
9842 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9843 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9844 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9845 #endif
9846 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9847 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9848 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9849 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9850 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9851 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9852 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9853 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9854 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9855 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9856 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9857 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9858 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9859 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9860 #if defined(TARGET_PPC64)
9861 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9862 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9863 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9864 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9865 #endif
9866 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9867 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9868 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9869 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9870 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9871 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9872 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9873 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9874 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9875 #if defined(TARGET_PPC64)
9876 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9877 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9878 #endif
9879 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9880 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9881 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9882 #if defined(TARGET_PPC64)
9883 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9884 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9885 #endif
9886 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9887 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9888 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9889 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9890 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9891 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9892 #if defined(TARGET_PPC64)
9893 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9894 #endif
9895 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9896 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
9897 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9898 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9899 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9900 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9901 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9902 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9903 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9904 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9905 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9906 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9907 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9908 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9909 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9910 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9911 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9912 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9913 #if defined(TARGET_PPC64)
9914 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9915 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9916 PPC_SEGMENT_64B),
9917 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9918 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9919 PPC_SEGMENT_64B),
9920 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9921 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9922 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9923 #endif
9924 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9925 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9926 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9927 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9928 #if defined(TARGET_PPC64)
9929 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9930 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9931 #endif
9932 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9933 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9934 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9935 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9936 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9937 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9938 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9939 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9940 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9941 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9942 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9943 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9944 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9945 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9946 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9947 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9948 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9949 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9950 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9951 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9952 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9953 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9954 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9955 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9956 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9957 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9958 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9959 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9960 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9961 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9962 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9963 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9964 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9965 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9966 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9967 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9968 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9969 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9970 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9971 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9972 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9973 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9974 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9975 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9976 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9977 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9978 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9979 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9980 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9981 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9982 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9983 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9984 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9985 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9986 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9987 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9988 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9989 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9990 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9991 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9992 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9993 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9994 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9995 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9996 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9997 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9998 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9999 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10000 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10001 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10002 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
10003 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10004 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10005 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10006 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10007 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10008 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10009 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10010 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10011 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10012 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10013 PPC_NONE, PPC2_BOOKE206),
10014 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10015 PPC_NONE, PPC2_BOOKE206),
10016 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10017 PPC_NONE, PPC2_BOOKE206),
10018 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10019 PPC_NONE, PPC2_BOOKE206),
10020 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10021 PPC_NONE, PPC2_BOOKE206),
10022 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10023 PPC_NONE, PPC2_PRCNTL),
10024 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10025 PPC_NONE, PPC2_PRCNTL),
10026 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10027 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10028 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10029 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10030 PPC_BOOKE, PPC2_BOOKE206),
10031 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10032 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10033 PPC_BOOKE, PPC2_BOOKE206),
10034 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10035 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10036 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10037 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10038 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10039 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10040 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10041 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10042 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10043
10044 #undef GEN_INT_ARITH_ADD
10045 #undef GEN_INT_ARITH_ADD_CONST
10046 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10047 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10048 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10049 add_ca, compute_ca, compute_ov) \
10050 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10051 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10052 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10053 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10054 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10055 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10056 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10057 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10058 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10059 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10060 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10061
10062 #undef GEN_INT_ARITH_DIVW
10063 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10064 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10065 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10066 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10067 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10068 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10069 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10070 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10071 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10072 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10073
10074 #if defined(TARGET_PPC64)
10075 #undef GEN_INT_ARITH_DIVD
10076 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10077 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10078 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10079 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10080 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10081 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10082
10083 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10084 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10085 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10086 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10087
10088 #undef GEN_INT_ARITH_MUL_HELPER
10089 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10090 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10091 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10092 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10093 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10094 #endif
10095
10096 #undef GEN_INT_ARITH_SUBF
10097 #undef GEN_INT_ARITH_SUBF_CONST
10098 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10099 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10100 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10101 add_ca, compute_ca, compute_ov) \
10102 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10103 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10104 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10105 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10106 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10107 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10108 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10109 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10110 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10111 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10112 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10113
10114 #undef GEN_LOGICAL1
10115 #undef GEN_LOGICAL2
10116 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10117 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10118 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10119 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10120 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10121 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10122 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10123 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10124 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10125 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10126 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10127 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10128 #if defined(TARGET_PPC64)
10129 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10130 #endif
10131
10132 #if defined(TARGET_PPC64)
10133 #undef GEN_PPC64_R2
10134 #undef GEN_PPC64_R4
10135 #define GEN_PPC64_R2(name, opc1, opc2) \
10136 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10137 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10138 PPC_64B)
10139 #define GEN_PPC64_R4(name, opc1, opc2) \
10140 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10141 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10142 PPC_64B), \
10143 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10144 PPC_64B), \
10145 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10146 PPC_64B)
10147 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10148 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10149 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10150 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10151 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10152 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10153 #endif
10154
10155 #undef _GEN_FLOAT_ACB
10156 #undef GEN_FLOAT_ACB
10157 #undef _GEN_FLOAT_AB
10158 #undef GEN_FLOAT_AB
10159 #undef _GEN_FLOAT_AC
10160 #undef GEN_FLOAT_AC
10161 #undef GEN_FLOAT_B
10162 #undef GEN_FLOAT_BS
10163 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10164 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10165 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10166 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10167 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10168 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10169 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10170 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10171 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10172 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10173 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10174 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10175 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10176 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10177 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10178 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10179 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10180 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10181 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10182
10183 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10184 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10185 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10186 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10187 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10188 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10189 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10190 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10191 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10192 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10193 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10194 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10195 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10196 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10197 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10198 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10199 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10200 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10201 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10202 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10203 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10204 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10205 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10206 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10207 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10208 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10209 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10210 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10211 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10212 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10213 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10214
10215 #undef GEN_LD
10216 #undef GEN_LDU
10217 #undef GEN_LDUX
10218 #undef GEN_LDX_E
10219 #undef GEN_LDS
10220 #define GEN_LD(name, ldop, opc, type) \
10221 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10222 #define GEN_LDU(name, ldop, opc, type) \
10223 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10224 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10225 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10226 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10227 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10228 #define GEN_LDS(name, ldop, op, type) \
10229 GEN_LD(name, ldop, op | 0x20, type) \
10230 GEN_LDU(name, ldop, op | 0x21, type) \
10231 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10232 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10233
10234 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10235 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10236 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10237 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10238 #if defined(TARGET_PPC64)
10239 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10240 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10241 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10242 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10243 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10244 #endif
10245 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10246 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10247
10248 #undef GEN_ST
10249 #undef GEN_STU
10250 #undef GEN_STUX
10251 #undef GEN_STX_E
10252 #undef GEN_STS
10253 #define GEN_ST(name, stop, opc, type) \
10254 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10255 #define GEN_STU(name, stop, opc, type) \
10256 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10257 #define GEN_STUX(name, stop, opc2, opc3, type) \
10258 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10259 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10260 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10261 #define GEN_STS(name, stop, op, type) \
10262 GEN_ST(name, stop, op | 0x20, type) \
10263 GEN_STU(name, stop, op | 0x21, type) \
10264 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10265 GEN_STX(name, stop, 0x17, op | 0x00, type)
10266
10267 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10268 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10269 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10270 #if defined(TARGET_PPC64)
10271 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10272 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10273 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10274 #endif
10275 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10276 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10277
10278 #undef GEN_LDF
10279 #undef GEN_LDUF
10280 #undef GEN_LDUXF
10281 #undef GEN_LDXF
10282 #undef GEN_LDFS
10283 #define GEN_LDF(name, ldop, opc, type) \
10284 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10285 #define GEN_LDUF(name, ldop, opc, type) \
10286 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10287 #define GEN_LDUXF(name, ldop, opc, type) \
10288 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10289 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10290 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10291 #define GEN_LDFS(name, ldop, op, type) \
10292 GEN_LDF(name, ldop, op | 0x20, type) \
10293 GEN_LDUF(name, ldop, op | 0x21, type) \
10294 GEN_LDUXF(name, ldop, op | 0x01, type) \
10295 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10296
10297 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10298 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10299 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10300 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10301 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10302 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10303
10304 #undef GEN_STF
10305 #undef GEN_STUF
10306 #undef GEN_STUXF
10307 #undef GEN_STXF
10308 #undef GEN_STFS
10309 #define GEN_STF(name, stop, opc, type) \
10310 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10311 #define GEN_STUF(name, stop, opc, type) \
10312 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10313 #define GEN_STUXF(name, stop, opc, type) \
10314 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10315 #define GEN_STXF(name, stop, opc2, opc3, type) \
10316 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10317 #define GEN_STFS(name, stop, op, type) \
10318 GEN_STF(name, stop, op | 0x20, type) \
10319 GEN_STUF(name, stop, op | 0x21, type) \
10320 GEN_STUXF(name, stop, op | 0x01, type) \
10321 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10322
10323 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10324 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10325 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10326 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10327 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10328
10329 #undef GEN_CRLOGIC
10330 #define GEN_CRLOGIC(name, tcg_op, opc) \
10331 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10332 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10333 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10334 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10335 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10336 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10337 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10338 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10339 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10340
10341 #undef GEN_MAC_HANDLER
10342 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10343 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10344 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10345 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10346 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10347 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10348 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10349 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10350 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10351 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10352 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10353 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10354 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10355 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10356 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10357 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10358 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10359 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10360 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10361 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10362 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10363 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10364 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10365 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10366 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10367 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10368 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10369 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10370 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10371 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10372 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10373 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10374 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10375 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10376 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10377 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10378 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10379 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10380 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10381 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10382 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10383 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10384 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10385 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10386
10387 #undef GEN_VR_LDX
10388 #undef GEN_VR_STX
10389 #undef GEN_VR_LVE
10390 #undef GEN_VR_STVE
10391 #define GEN_VR_LDX(name, opc2, opc3) \
10392 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10393 #define GEN_VR_STX(name, opc2, opc3) \
10394 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10395 #define GEN_VR_LVE(name, opc2, opc3) \
10396 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10397 #define GEN_VR_STVE(name, opc2, opc3) \
10398 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10399 GEN_VR_LDX(lvx, 0x07, 0x03),
10400 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10401 GEN_VR_LVE(bx, 0x07, 0x00),
10402 GEN_VR_LVE(hx, 0x07, 0x01),
10403 GEN_VR_LVE(wx, 0x07, 0x02),
10404 GEN_VR_STX(svx, 0x07, 0x07),
10405 GEN_VR_STX(svxl, 0x07, 0x0F),
10406 GEN_VR_STVE(bx, 0x07, 0x04),
10407 GEN_VR_STVE(hx, 0x07, 0x05),
10408 GEN_VR_STVE(wx, 0x07, 0x06),
10409
10410 #undef GEN_VX_LOGICAL
10411 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10412 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10413
10414 #undef GEN_VX_LOGICAL_207
10415 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10416 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10417
10418 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10419 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10420 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10421 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10422 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10423 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10424 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10425 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10426
10427 #undef GEN_VXFORM
10428 #define GEN_VXFORM(name, opc2, opc3) \
10429 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10430
10431 #undef GEN_VXFORM_207
10432 #define GEN_VXFORM_207(name, opc2, opc3) \
10433 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10434
10435 #undef GEN_VXFORM_DUAL
10436 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10437 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10438
10439 #undef GEN_VXRFORM_DUAL
10440 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10441 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10442 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10443
10444 GEN_VXFORM(vaddubm, 0, 0),
10445 GEN_VXFORM(vadduhm, 0, 1),
10446 GEN_VXFORM(vadduwm, 0, 2),
10447 GEN_VXFORM_207(vaddudm, 0, 3),
10448 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10449 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10450 GEN_VXFORM(vsubuwm, 0, 18),
10451 GEN_VXFORM_207(vsubudm, 0, 19),
10452 GEN_VXFORM(vmaxub, 1, 0),
10453 GEN_VXFORM(vmaxuh, 1, 1),
10454 GEN_VXFORM(vmaxuw, 1, 2),
10455 GEN_VXFORM_207(vmaxud, 1, 3),
10456 GEN_VXFORM(vmaxsb, 1, 4),
10457 GEN_VXFORM(vmaxsh, 1, 5),
10458 GEN_VXFORM(vmaxsw, 1, 6),
10459 GEN_VXFORM_207(vmaxsd, 1, 7),
10460 GEN_VXFORM(vminub, 1, 8),
10461 GEN_VXFORM(vminuh, 1, 9),
10462 GEN_VXFORM(vminuw, 1, 10),
10463 GEN_VXFORM_207(vminud, 1, 11),
10464 GEN_VXFORM(vminsb, 1, 12),
10465 GEN_VXFORM(vminsh, 1, 13),
10466 GEN_VXFORM(vminsw, 1, 14),
10467 GEN_VXFORM_207(vminsd, 1, 15),
10468 GEN_VXFORM(vavgub, 1, 16),
10469 GEN_VXFORM(vavguh, 1, 17),
10470 GEN_VXFORM(vavguw, 1, 18),
10471 GEN_VXFORM(vavgsb, 1, 20),
10472 GEN_VXFORM(vavgsh, 1, 21),
10473 GEN_VXFORM(vavgsw, 1, 22),
10474 GEN_VXFORM(vmrghb, 6, 0),
10475 GEN_VXFORM(vmrghh, 6, 1),
10476 GEN_VXFORM(vmrghw, 6, 2),
10477 GEN_VXFORM(vmrglb, 6, 4),
10478 GEN_VXFORM(vmrglh, 6, 5),
10479 GEN_VXFORM(vmrglw, 6, 6),
10480 GEN_VXFORM_207(vmrgew, 6, 30),
10481 GEN_VXFORM_207(vmrgow, 6, 26),
10482 GEN_VXFORM(vmuloub, 4, 0),
10483 GEN_VXFORM(vmulouh, 4, 1),
10484 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10485 GEN_VXFORM(vmulosb, 4, 4),
10486 GEN_VXFORM(vmulosh, 4, 5),
10487 GEN_VXFORM_207(vmulosw, 4, 6),
10488 GEN_VXFORM(vmuleub, 4, 8),
10489 GEN_VXFORM(vmuleuh, 4, 9),
10490 GEN_VXFORM_207(vmuleuw, 4, 10),
10491 GEN_VXFORM(vmulesb, 4, 12),
10492 GEN_VXFORM(vmulesh, 4, 13),
10493 GEN_VXFORM_207(vmulesw, 4, 14),
10494 GEN_VXFORM(vslb, 2, 4),
10495 GEN_VXFORM(vslh, 2, 5),
10496 GEN_VXFORM(vslw, 2, 6),
10497 GEN_VXFORM_207(vsld, 2, 23),
10498 GEN_VXFORM(vsrb, 2, 8),
10499 GEN_VXFORM(vsrh, 2, 9),
10500 GEN_VXFORM(vsrw, 2, 10),
10501 GEN_VXFORM_207(vsrd, 2, 27),
10502 GEN_VXFORM(vsrab, 2, 12),
10503 GEN_VXFORM(vsrah, 2, 13),
10504 GEN_VXFORM(vsraw, 2, 14),
10505 GEN_VXFORM_207(vsrad, 2, 15),
10506 GEN_VXFORM(vslo, 6, 16),
10507 GEN_VXFORM(vsro, 6, 17),
10508 GEN_VXFORM(vaddcuw, 0, 6),
10509 GEN_VXFORM(vsubcuw, 0, 22),
10510 GEN_VXFORM(vaddubs, 0, 8),
10511 GEN_VXFORM(vadduhs, 0, 9),
10512 GEN_VXFORM(vadduws, 0, 10),
10513 GEN_VXFORM(vaddsbs, 0, 12),
10514 GEN_VXFORM(vaddshs, 0, 13),
10515 GEN_VXFORM(vaddsws, 0, 14),
10516 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10517 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10518 GEN_VXFORM(vsubuws, 0, 26),
10519 GEN_VXFORM(vsubsbs, 0, 28),
10520 GEN_VXFORM(vsubshs, 0, 29),
10521 GEN_VXFORM(vsubsws, 0, 30),
10522 GEN_VXFORM_207(vadduqm, 0, 4),
10523 GEN_VXFORM_207(vaddcuq, 0, 5),
10524 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10525 GEN_VXFORM_207(vsubuqm, 0, 20),
10526 GEN_VXFORM_207(vsubcuq, 0, 21),
10527 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10528 GEN_VXFORM(vrlb, 2, 0),
10529 GEN_VXFORM(vrlh, 2, 1),
10530 GEN_VXFORM(vrlw, 2, 2),
10531 GEN_VXFORM_207(vrld, 2, 3),
10532 GEN_VXFORM(vsl, 2, 7),
10533 GEN_VXFORM(vsr, 2, 11),
10534 GEN_VXFORM(vpkuhum, 7, 0),
10535 GEN_VXFORM(vpkuwum, 7, 1),
10536 GEN_VXFORM_207(vpkudum, 7, 17),
10537 GEN_VXFORM(vpkuhus, 7, 2),
10538 GEN_VXFORM(vpkuwus, 7, 3),
10539 GEN_VXFORM_207(vpkudus, 7, 19),
10540 GEN_VXFORM(vpkshus, 7, 4),
10541 GEN_VXFORM(vpkswus, 7, 5),
10542 GEN_VXFORM_207(vpksdus, 7, 21),
10543 GEN_VXFORM(vpkshss, 7, 6),
10544 GEN_VXFORM(vpkswss, 7, 7),
10545 GEN_VXFORM_207(vpksdss, 7, 23),
10546 GEN_VXFORM(vpkpx, 7, 12),
10547 GEN_VXFORM(vsum4ubs, 4, 24),
10548 GEN_VXFORM(vsum4sbs, 4, 28),
10549 GEN_VXFORM(vsum4shs, 4, 25),
10550 GEN_VXFORM(vsum2sws, 4, 26),
10551 GEN_VXFORM(vsumsws, 4, 30),
10552 GEN_VXFORM(vaddfp, 5, 0),
10553 GEN_VXFORM(vsubfp, 5, 1),
10554 GEN_VXFORM(vmaxfp, 5, 16),
10555 GEN_VXFORM(vminfp, 5, 17),
10556
10557 #undef GEN_VXRFORM1
10558 #undef GEN_VXRFORM
10559 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10560 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10561 #define GEN_VXRFORM(name, opc2, opc3) \
10562 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10563 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10564 GEN_VXRFORM(vcmpequb, 3, 0)
10565 GEN_VXRFORM(vcmpequh, 3, 1)
10566 GEN_VXRFORM(vcmpequw, 3, 2)
10567 GEN_VXRFORM(vcmpgtsb, 3, 12)
10568 GEN_VXRFORM(vcmpgtsh, 3, 13)
10569 GEN_VXRFORM(vcmpgtsw, 3, 14)
10570 GEN_VXRFORM(vcmpgtub, 3, 8)
10571 GEN_VXRFORM(vcmpgtuh, 3, 9)
10572 GEN_VXRFORM(vcmpgtuw, 3, 10)
10573 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10574 GEN_VXRFORM(vcmpgefp, 3, 7)
10575 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10576 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10577
10578 #undef GEN_VXFORM_SIMM
10579 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10580 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10581 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10582 GEN_VXFORM_SIMM(vspltish, 6, 13),
10583 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10584
10585 #undef GEN_VXFORM_NOA
10586 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10587 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10588 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10589 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10590 GEN_VXFORM_207(vupkhsw, 7, 25),
10591 GEN_VXFORM_NOA(vupklsb, 7, 10),
10592 GEN_VXFORM_NOA(vupklsh, 7, 11),
10593 GEN_VXFORM_207(vupklsw, 7, 27),
10594 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10595 GEN_VXFORM_NOA(vupklpx, 7, 15),
10596 GEN_VXFORM_NOA(vrefp, 5, 4),
10597 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10598 GEN_VXFORM_NOA(vexptefp, 5, 6),
10599 GEN_VXFORM_NOA(vlogefp, 5, 7),
10600 GEN_VXFORM_NOA(vrfim, 5, 11),
10601 GEN_VXFORM_NOA(vrfin, 5, 8),
10602 GEN_VXFORM_NOA(vrfip, 5, 10),
10603 GEN_VXFORM_NOA(vrfiz, 5, 9),
10604
10605 #undef GEN_VXFORM_UIMM
10606 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10607 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10608 GEN_VXFORM_UIMM(vspltb, 6, 8),
10609 GEN_VXFORM_UIMM(vsplth, 6, 9),
10610 GEN_VXFORM_UIMM(vspltw, 6, 10),
10611 GEN_VXFORM_UIMM(vcfux, 5, 12),
10612 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10613 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10614 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10615
10616 #undef GEN_VAFORM_PAIRED
10617 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10618 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10619 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10620 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10621 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10622 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10623 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10624 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10625
10626 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10627 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10628 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10629 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10630
10631 GEN_VXFORM_207(vbpermq, 6, 21),
10632 GEN_VXFORM_207(vgbbd, 6, 20),
10633 GEN_VXFORM_207(vpmsumb, 4, 16),
10634 GEN_VXFORM_207(vpmsumh, 4, 17),
10635 GEN_VXFORM_207(vpmsumw, 4, 18),
10636 GEN_VXFORM_207(vpmsumd, 4, 19),
10637
10638 GEN_VXFORM_207(vsbox, 4, 23),
10639
10640 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10641 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10642
10643 GEN_VXFORM_207(vshasigmaw, 1, 26),
10644 GEN_VXFORM_207(vshasigmad, 1, 27),
10645
10646 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10647
10648 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10649 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10650 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10651 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10652 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10653 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10654 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10655
10656 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10657 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10658 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10659 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10660 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10661
10662 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10663 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10664 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10665 #if defined(TARGET_PPC64)
10666 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10667 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10668 #endif
10669
10670 #undef GEN_XX2FORM
10671 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10672 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10673 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10674
10675 #undef GEN_XX3FORM
10676 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10677 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10678 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10679 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10680 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10681
10682 #undef GEN_XX2IFORM
10683 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10684 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10685 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10686 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10687 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10688
10689 #undef GEN_XX3_RC_FORM
10690 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10691 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10692 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10693 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10694 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10695 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10696 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10697 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10698 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10699
10700 #undef GEN_XX3FORM_DM
10701 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10702 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10703 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10704 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10705 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10706 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10707 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10708 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10709 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10710 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10711 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10712 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10713 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10714 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10715 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10716 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10717 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10718
10719 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10720 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10721 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10722 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10723
10724 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10725 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10726 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10727 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10728 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10729 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10730 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10731 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10732
10733 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10734 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10735 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10736 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10737 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10738 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10739 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10740 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10741 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10742 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10743 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10744 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10745 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10746 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10747 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10748 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10749 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10750 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10751 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10752 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10753 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10754 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10755 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10756 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10757 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10758 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10759 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10760 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10761 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10762 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10763 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10764 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10765 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10766 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10767 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10768 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10769
10770 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10771 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10772 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10773 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10774 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10775 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10776 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10777 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10778 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10779 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10780 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10781 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10782 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10783 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10784 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10785 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10786 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10787 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10788
10789 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10790 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10791 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10792 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10793 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10794 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10795 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10796 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10797 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10798 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10799 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10800 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10801 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10802 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10803 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10804 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10805 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10806 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10807 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10808 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10809 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10810 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10811 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10812 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10813 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10814 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10815 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10816 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10817 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10818 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10819 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10820 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10821 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10822 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10823 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10824 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10825
10826 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10827 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10828 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10829 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10830 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10831 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10832 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10833 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10834 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10835 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10836 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10837 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10838 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10839 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10840 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10841 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10842 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10843 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10844 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10845 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10846 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10847 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10848 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10849 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10850 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10851 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10852 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10853 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10854 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10855 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10856 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10857 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10858 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10859 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10860 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10861 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10862
10863 #undef VSX_LOGICAL
10864 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10865 GEN_XX3FORM(name, opc2, opc3, fl2)
10866
10867 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10868 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10869 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10870 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10871 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10872 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10873 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10874 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10875 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10876 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10877 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10878 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10879
10880 #define GEN_XXSEL_ROW(opc3) \
10881 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10882 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10883 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10884 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10885 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10886 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10887 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10888 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10889
10890 GEN_XXSEL_ROW(0x00)
10891 GEN_XXSEL_ROW(0x01)
10892 GEN_XXSEL_ROW(0x02)
10893 GEN_XXSEL_ROW(0x03)
10894 GEN_XXSEL_ROW(0x04)
10895 GEN_XXSEL_ROW(0x05)
10896 GEN_XXSEL_ROW(0x06)
10897 GEN_XXSEL_ROW(0x07)
10898 GEN_XXSEL_ROW(0x08)
10899 GEN_XXSEL_ROW(0x09)
10900 GEN_XXSEL_ROW(0x0A)
10901 GEN_XXSEL_ROW(0x0B)
10902 GEN_XXSEL_ROW(0x0C)
10903 GEN_XXSEL_ROW(0x0D)
10904 GEN_XXSEL_ROW(0x0E)
10905 GEN_XXSEL_ROW(0x0F)
10906 GEN_XXSEL_ROW(0x10)
10907 GEN_XXSEL_ROW(0x11)
10908 GEN_XXSEL_ROW(0x12)
10909 GEN_XXSEL_ROW(0x13)
10910 GEN_XXSEL_ROW(0x14)
10911 GEN_XXSEL_ROW(0x15)
10912 GEN_XXSEL_ROW(0x16)
10913 GEN_XXSEL_ROW(0x17)
10914 GEN_XXSEL_ROW(0x18)
10915 GEN_XXSEL_ROW(0x19)
10916 GEN_XXSEL_ROW(0x1A)
10917 GEN_XXSEL_ROW(0x1B)
10918 GEN_XXSEL_ROW(0x1C)
10919 GEN_XXSEL_ROW(0x1D)
10920 GEN_XXSEL_ROW(0x1E)
10921 GEN_XXSEL_ROW(0x1F)
10922
10923 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10924
10925 #undef GEN_DFP_T_A_B_Rc
10926 #undef GEN_DFP_BF_A_B
10927 #undef GEN_DFP_BF_A_DCM
10928 #undef GEN_DFP_T_B_U32_U32_Rc
10929 #undef GEN_DFP_T_A_B_I32_Rc
10930 #undef GEN_DFP_T_B_Rc
10931 #undef GEN_DFP_T_FPR_I32_Rc
10932
10933 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10934 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10935
10936 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10937 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10938 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10939
10940 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10941 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10942 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10943 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10944 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10945
10946 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10947 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10948
10949 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10950 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10951 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10952
10953 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10954 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10955 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10956 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10957 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10958
10959 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10960 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10961
10962 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10963 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10964
10965 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10966 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10967
10968 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10969 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10970
10971 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10972 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10973
10974 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10975 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10976
10977 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10978 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10979
10980 #define GEN_DFP_BF_A_B(name, op1, op2) \
10981 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10982
10983 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10984 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10985
10986 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
10987 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10988
10989 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
10990 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10991
10992 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10993 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10994
10995 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10996 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10997
10998 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10999 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11000
11001 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11002 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11003
11004 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11005 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11006
11007 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11008 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11009
11010 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11011 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11012
11013 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11014 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11015
11016 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11017 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11018
11019 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11020 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11021
11022 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11023 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11024
11025 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11026 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11027
11028 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11029 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11030
11031 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11032 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11033
11034 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11035 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11036 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11037 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11038 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11039 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11040 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11041 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11042 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11043 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11044 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11045 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11046 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11047 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11048 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11049 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11050 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11051 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11052 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11053 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11054 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11055 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11056 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11057 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11058 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11059 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11060 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11061 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11062 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11063 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11064 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11065 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11066 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11067 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11068 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11069 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11070 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11071 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11072 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11073 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11074 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11075 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11076 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11077 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11078 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11079 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11080 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11081 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11082 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11083 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11084
11085 #undef GEN_SPE
11086 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11087 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11088 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11089 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11090 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11091 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11092 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11093 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11094 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11095 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11096 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11097 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11098 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11099 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11100 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11101 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11102 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11103 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11104 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11105 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11106 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11107 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11108 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11109 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11110 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11111 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11112 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11113 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11114 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11115 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11116 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11117
11118 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11119 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11120 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11121 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11122 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11123 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11124 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11125 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11126 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11127 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11128 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11129 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11130 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11131 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11132
11133 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11134 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11135 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11136 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11137 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11138 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11139 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11140 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11141 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11142 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11143 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11144 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11145 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11146 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11147
11148 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11149 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11150 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11151 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11152 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11153 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11154 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11155 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11156 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11157 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11158 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11159 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11160 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11161 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11162 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11163 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11164
11165 #undef GEN_SPEOP_LDST
11166 #define GEN_SPEOP_LDST(name, opc2, sh) \
11167 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11168 GEN_SPEOP_LDST(evldd, 0x00, 3),
11169 GEN_SPEOP_LDST(evldw, 0x01, 3),
11170 GEN_SPEOP_LDST(evldh, 0x02, 3),
11171 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11172 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11173 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11174 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11175 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11176 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11177 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11178 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11179
11180 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11181 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11182 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11183 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11184 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11185 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11186 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11187
11188 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11189 PPC_NONE, PPC2_TM),
11190 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11191 PPC_NONE, PPC2_TM),
11192 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11193 PPC_NONE, PPC2_TM),
11194 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11195 PPC_NONE, PPC2_TM),
11196 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11197 PPC_NONE, PPC2_TM),
11198 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11199 PPC_NONE, PPC2_TM),
11200 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11201 PPC_NONE, PPC2_TM),
11202 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11203 PPC_NONE, PPC2_TM),
11204 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11205 PPC_NONE, PPC2_TM),
11206 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11207 PPC_NONE, PPC2_TM),
11208 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11209 PPC_NONE, PPC2_TM),
11210 };
11211
11212 #include "helper_regs.h"
11213 #include "translate_init.c"
11214
11215 /*****************************************************************************/
11216 /* Misc PowerPC helpers */
11217 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11218 int flags)
11219 {
11220 #define RGPL 4
11221 #define RFPL 4
11222
11223 PowerPCCPU *cpu = POWERPC_CPU(cs);
11224 CPUPPCState *env = &cpu->env;
11225 int i;
11226
11227 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11228 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11229 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11230 cs->cpu_index);
11231 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11232 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11233 env->hflags, env->mmu_idx);
11234 #if !defined(NO_TIMER_DUMP)
11235 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11236 #if !defined(CONFIG_USER_ONLY)
11237 " DECR %08" PRIu32
11238 #endif
11239 "\n",
11240 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11241 #if !defined(CONFIG_USER_ONLY)
11242 , cpu_ppc_load_decr(env)
11243 #endif
11244 );
11245 #endif
11246 for (i = 0; i < 32; i++) {
11247 if ((i & (RGPL - 1)) == 0)
11248 cpu_fprintf(f, "GPR%02d", i);
11249 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11250 if ((i & (RGPL - 1)) == (RGPL - 1))
11251 cpu_fprintf(f, "\n");
11252 }
11253 cpu_fprintf(f, "CR ");
11254 for (i = 0; i < 8; i++)
11255 cpu_fprintf(f, "%01x", env->crf[i]);
11256 cpu_fprintf(f, " [");
11257 for (i = 0; i < 8; i++) {
11258 char a = '-';
11259 if (env->crf[i] & 0x08)
11260 a = 'L';
11261 else if (env->crf[i] & 0x04)
11262 a = 'G';
11263 else if (env->crf[i] & 0x02)
11264 a = 'E';
11265 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11266 }
11267 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11268 env->reserve_addr);
11269 for (i = 0; i < 32; i++) {
11270 if ((i & (RFPL - 1)) == 0)
11271 cpu_fprintf(f, "FPR%02d", i);
11272 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11273 if ((i & (RFPL - 1)) == (RFPL - 1))
11274 cpu_fprintf(f, "\n");
11275 }
11276 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11277 #if !defined(CONFIG_USER_ONLY)
11278 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11279 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11280 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11281 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11282
11283 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11284 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11285 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11286 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11287
11288 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11289 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11290 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11291 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11292
11293 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11294 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11295 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11296 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11297 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11298
11299 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11300 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11301 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11302 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11303
11304 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11305 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11306 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11307 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11308
11309 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11310 " EPR " TARGET_FMT_lx "\n",
11311 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11312 env->spr[SPR_BOOKE_EPR]);
11313
11314 /* FSL-specific */
11315 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11316 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11317 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11318 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11319
11320 /*
11321 * IVORs are left out as they are large and do not change often --
11322 * they can be read with "p $ivor0", "p $ivor1", etc.
11323 */
11324 }
11325
11326 #if defined(TARGET_PPC64)
11327 if (env->flags & POWERPC_FLAG_CFAR) {
11328 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11329 }
11330 #endif
11331
11332 switch (env->mmu_model) {
11333 case POWERPC_MMU_32B:
11334 case POWERPC_MMU_601:
11335 case POWERPC_MMU_SOFT_6xx:
11336 case POWERPC_MMU_SOFT_74xx:
11337 #if defined(TARGET_PPC64)
11338 case POWERPC_MMU_64B:
11339 case POWERPC_MMU_2_03:
11340 case POWERPC_MMU_2_06:
11341 case POWERPC_MMU_2_07:
11342 #endif
11343 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11344 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11345 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11346 break;
11347 case POWERPC_MMU_BOOKE206:
11348 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11349 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11350 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11351 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11352
11353 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11354 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11355 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11356 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11357
11358 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11359 " TLB1CFG " TARGET_FMT_lx "\n",
11360 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11361 env->spr[SPR_BOOKE_TLB1CFG]);
11362 break;
11363 default:
11364 break;
11365 }
11366 #endif
11367
11368 #undef RGPL
11369 #undef RFPL
11370 }
11371
11372 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11373 fprintf_function cpu_fprintf, int flags)
11374 {
11375 #if defined(DO_PPC_STATISTICS)
11376 PowerPCCPU *cpu = POWERPC_CPU(cs);
11377 opc_handler_t **t1, **t2, **t3, *handler;
11378 int op1, op2, op3;
11379
11380 t1 = cpu->env.opcodes;
11381 for (op1 = 0; op1 < 64; op1++) {
11382 handler = t1[op1];
11383 if (is_indirect_opcode(handler)) {
11384 t2 = ind_table(handler);
11385 for (op2 = 0; op2 < 32; op2++) {
11386 handler = t2[op2];
11387 if (is_indirect_opcode(handler)) {
11388 t3 = ind_table(handler);
11389 for (op3 = 0; op3 < 32; op3++) {
11390 handler = t3[op3];
11391 if (handler->count == 0)
11392 continue;
11393 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11394 "%016" PRIx64 " %" PRId64 "\n",
11395 op1, op2, op3, op1, (op3 << 5) | op2,
11396 handler->oname,
11397 handler->count, handler->count);
11398 }
11399 } else {
11400 if (handler->count == 0)
11401 continue;
11402 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11403 "%016" PRIx64 " %" PRId64 "\n",
11404 op1, op2, op1, op2, handler->oname,
11405 handler->count, handler->count);
11406 }
11407 }
11408 } else {
11409 if (handler->count == 0)
11410 continue;
11411 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11412 " %" PRId64 "\n",
11413 op1, op1, handler->oname,
11414 handler->count, handler->count);
11415 }
11416 }
11417 #endif
11418 }
11419
11420 /*****************************************************************************/
11421 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11422 {
11423 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11424 CPUState *cs = CPU(cpu);
11425 DisasContext ctx, *ctxp = &ctx;
11426 opc_handler_t **table, *handler;
11427 target_ulong pc_start;
11428 int num_insns;
11429 int max_insns;
11430
11431 pc_start = tb->pc;
11432 ctx.nip = pc_start;
11433 ctx.tb = tb;
11434 ctx.exception = POWERPC_EXCP_NONE;
11435 ctx.spr_cb = env->spr_cb;
11436 ctx.pr = msr_pr;
11437 ctx.hv = !msr_pr && msr_hv;
11438 ctx.mem_idx = env->mmu_idx;
11439 ctx.insns_flags = env->insns_flags;
11440 ctx.insns_flags2 = env->insns_flags2;
11441 ctx.access_type = -1;
11442 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11443 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11444 #if defined(TARGET_PPC64)
11445 ctx.sf_mode = msr_is_64bit(env, env->msr);
11446 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11447 #endif
11448 ctx.fpu_enabled = msr_fp;
11449 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11450 ctx.spe_enabled = msr_spe;
11451 else
11452 ctx.spe_enabled = 0;
11453 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11454 ctx.altivec_enabled = msr_vr;
11455 else
11456 ctx.altivec_enabled = 0;
11457 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11458 ctx.vsx_enabled = msr_vsx;
11459 } else {
11460 ctx.vsx_enabled = 0;
11461 }
11462 #if defined(TARGET_PPC64)
11463 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11464 ctx.tm_enabled = msr_tm;
11465 } else {
11466 ctx.tm_enabled = 0;
11467 }
11468 #endif
11469 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11470 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11471 else
11472 ctx.singlestep_enabled = 0;
11473 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11474 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11475 if (unlikely(cs->singlestep_enabled)) {
11476 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11477 }
11478 #if defined (DO_SINGLE_STEP) && 0
11479 /* Single step trace mode */
11480 msr_se = 1;
11481 #endif
11482 num_insns = 0;
11483 max_insns = tb->cflags & CF_COUNT_MASK;
11484 if (max_insns == 0) {
11485 max_insns = CF_COUNT_MASK;
11486 }
11487 if (max_insns > TCG_MAX_INSNS) {
11488 max_insns = TCG_MAX_INSNS;
11489 }
11490
11491 gen_tb_start(tb);
11492 tcg_clear_temp_count();
11493 /* Set env in case of segfault during code fetch */
11494 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11495 tcg_gen_insn_start(ctx.nip);
11496 num_insns++;
11497
11498 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11499 gen_debug_exception(ctxp);
11500 /* The address covered by the breakpoint must be included in
11501 [tb->pc, tb->pc + tb->size) in order to for it to be
11502 properly cleared -- thus we increment the PC here so that
11503 the logic setting tb->size below does the right thing. */
11504 ctx.nip += 4;
11505 break;
11506 }
11507
11508 LOG_DISAS("----------------\n");
11509 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11510 ctx.nip, ctx.mem_idx, (int)msr_ir);
11511 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11512 gen_io_start();
11513 if (unlikely(need_byteswap(&ctx))) {
11514 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11515 } else {
11516 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11517 }
11518 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11519 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11520 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11521 ctx.nip += 4;
11522 table = env->opcodes;
11523 handler = table[opc1(ctx.opcode)];
11524 if (is_indirect_opcode(handler)) {
11525 table = ind_table(handler);
11526 handler = table[opc2(ctx.opcode)];
11527 if (is_indirect_opcode(handler)) {
11528 table = ind_table(handler);
11529 handler = table[opc3(ctx.opcode)];
11530 }
11531 }
11532 /* Is opcode *REALLY* valid ? */
11533 if (unlikely(handler->handler == &gen_invalid)) {
11534 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11535 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11536 opc1(ctx.opcode), opc2(ctx.opcode),
11537 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11538 } else {
11539 uint32_t inval;
11540
11541 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11542 inval = handler->inval2;
11543 } else {
11544 inval = handler->inval1;
11545 }
11546
11547 if (unlikely((ctx.opcode & inval) != 0)) {
11548 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11549 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11550 ctx.opcode & inval, opc1(ctx.opcode),
11551 opc2(ctx.opcode), opc3(ctx.opcode),
11552 ctx.opcode, ctx.nip - 4);
11553 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11554 break;
11555 }
11556 }
11557 (*(handler->handler))(&ctx);
11558 #if defined(DO_PPC_STATISTICS)
11559 handler->count++;
11560 #endif
11561 /* Check trace mode exceptions */
11562 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11563 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11564 ctx.exception != POWERPC_SYSCALL &&
11565 ctx.exception != POWERPC_EXCP_TRAP &&
11566 ctx.exception != POWERPC_EXCP_BRANCH)) {
11567 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11568 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11569 (cs->singlestep_enabled) ||
11570 singlestep ||
11571 num_insns >= max_insns)) {
11572 /* if we reach a page boundary or are single stepping, stop
11573 * generation
11574 */
11575 break;
11576 }
11577 if (tcg_check_temp_count()) {
11578 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11579 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11580 ctx.opcode);
11581 exit(1);
11582 }
11583 }
11584 if (tb->cflags & CF_LAST_IO)
11585 gen_io_end();
11586 if (ctx.exception == POWERPC_EXCP_NONE) {
11587 gen_goto_tb(&ctx, 0, ctx.nip);
11588 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11589 if (unlikely(cs->singlestep_enabled)) {
11590 gen_debug_exception(ctxp);
11591 }
11592 /* Generate the return instruction */
11593 tcg_gen_exit_tb(0);
11594 }
11595 gen_tb_end(tb, num_insns);
11596
11597 tb->size = ctx.nip - pc_start;
11598 tb->icount = num_insns;
11599
11600 #if defined(DEBUG_DISAS)
11601 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11602 int flags;
11603 flags = env->bfd_mach;
11604 flags |= ctx.le_mode << 16;
11605 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11606 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11607 qemu_log("\n");
11608 }
11609 #endif
11610 }
11611
11612 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11613 target_ulong *data)
11614 {
11615 env->nip = data[0];
11616 }
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