hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30
  31 #include "qemu/osdep.h"
  32 #include "qemu/units.h"
  33 #include "hw/loader.h"
  34 #include "hw/i2c/smbus_eeprom.h"
  35 #include "hw/rtc/mc146818rtc.h"
  36 #include "sysemu/kvm.h"
  37 #include "hw/kvm/clock.h"
  38 #include "hw/pci-host/q35.h"
  39 #include "hw/pci/pcie_port.h"
  40 #include "hw/qdev-properties.h"
  41 #include "hw/i386/x86.h"
  42 #include "hw/i386/pc.h"
  43 #include "hw/i386/ich9.h"
  44 #include "hw/i386/amd_iommu.h"
  45 #include "hw/i386/intel_iommu.h"
  46 #include "hw/display/ramfb.h"
  47 #include "hw/firmware/smbios.h"
  48 #include "hw/ide/pci.h"
  49 #include "hw/ide/ahci.h"
  50 #include "hw/usb.h"
  51 #include "hw/usb/hcd-uhci.h"
  52 #include "qapi/error.h"
  53 #include "qemu/error-report.h"
  54 #include "sysemu/numa.h"
  55 #include "hw/hyperv/vmbus-bridge.h"
  56 #include "hw/mem/nvdimm.h"
  57 #include "hw/i386/acpi-build.h"
  58
  59 /* ICH9 AHCI has 6 ports */
  60 #define MAX_SATA_PORTS     6
  61
  62 struct ehci_companions {
  63     const char *name;
  64     int func;
  65     int port;
  66 };
  67
  68 static const struct ehci_companions ich9_1d[] = {
  69     { .name = TYPE_ICH9_USB_UHCI(1), .func = 0, .port = 0 },
  70     { .name = TYPE_ICH9_USB_UHCI(2), .func = 1, .port = 2 },
  71     { .name = TYPE_ICH9_USB_UHCI(3), .func = 2, .port = 4 },
  72 };
  73
  74 static const struct ehci_companions ich9_1a[] = {
  75     { .name = TYPE_ICH9_USB_UHCI(4), .func = 0, .port = 0 },
  76     { .name = TYPE_ICH9_USB_UHCI(5), .func = 1, .port = 2 },
  77     { .name = TYPE_ICH9_USB_UHCI(6), .func = 2, .port = 4 },
  78 };
  79
  80 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
  81 {
  82     const struct ehci_companions *comp;
  83     PCIDevice *ehci, *uhci;
  84     BusState *usbbus;
  85     const char *name;
  86     int i;
  87
  88     switch (slot) {
  89     case 0x1d:
  90         name = "ich9-usb-ehci1";
  91         comp = ich9_1d;
  92         break;
  93     case 0x1a:
  94         name = "ich9-usb-ehci2";
  95         comp = ich9_1a;
  96         break;
  97     default:
  98         return -1;
  99     }
 100
 101     ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), true, name);
 102     pci_realize_and_unref(ehci, bus, &error_fatal);
 103     usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
 104
 105     for (i = 0; i < 3; i++) {
 106         uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true,
 107                                      comp[i].name);
 108         qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
 109         qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
 110         pci_realize_and_unref(uhci, bus, &error_fatal);
 111     }
 112     return 0;
 113 }
 114
 115 /* PC hardware initialisation */
 116 static void pc_q35_init(MachineState *machine)
 117 {
 118     PCMachineState *pcms = PC_MACHINE(machine);
 119     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
 120     X86MachineState *x86ms = X86_MACHINE(machine);
 121     Q35PCIHost *q35_host;
 122     PCIHostState *phb;
 123     PCIBus *host_bus;
 124     PCIDevice *lpc;
 125     DeviceState *lpc_dev;
 126     BusState *idebus[MAX_SATA_PORTS];
 127     ISADevice *rtc_state;
 128     MemoryRegion *system_io = get_system_io();
 129     MemoryRegion *pci_memory;
 130     MemoryRegion *rom_memory;
 131     MemoryRegion *ram_memory;
 132     GSIState *gsi_state;
 133     ISABus *isa_bus;
 134     int i;
 135     ICH9LPCState *ich9_lpc;
 136     PCIDevice *ahci;
 137     ram_addr_t lowmem;
 138     DriveInfo *hd[MAX_SATA_PORTS];
 139     MachineClass *mc = MACHINE_GET_CLASS(machine);
 140     bool acpi_pcihp;
 141     bool keep_pci_slot_hpc;
 142     uint64_t pci_hole64_size = 0;
 143
 144     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
 145      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
 146      * also known as MMCFG).
 147      * If it doesn't, we need to split it in chunks below and above 4G.
 148      * In any case, try to make sure that guest addresses aligned at
 149      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
 150      */
 151     if (machine->ram_size >= 0xb0000000) {
 152         lowmem = 0x80000000;
 153     } else {
 154         lowmem = 0xb0000000;
 155     }
 156
 157     /* Handle the machine opt max-ram-below-4g.  It is basically doing
 158      * min(qemu limit, user limit).
 159      */
 160     if (!pcms->max_ram_below_4g) {
 161         pcms->max_ram_below_4g = 4 * GiB;
 162     }
 163     if (lowmem > pcms->max_ram_below_4g) {
 164         lowmem = pcms->max_ram_below_4g;
 165         if (machine->ram_size - lowmem > lowmem &&
 166             lowmem & (1 * GiB - 1)) {
 167             warn_report("There is possibly poor performance as the ram size "
 168                         " (0x%" PRIx64 ") is more then twice the size of"
 169                         " max-ram-below-4g (%"PRIu64") and"
 170                         " max-ram-below-4g is not a multiple of 1G.",
 171                         (uint64_t)machine->ram_size, pcms->max_ram_below_4g);
 172         }
 173     }
 174
 175     if (machine->ram_size >= lowmem) {
 176         x86ms->above_4g_mem_size = machine->ram_size - lowmem;
 177         x86ms->below_4g_mem_size = lowmem;
 178     } else {
 179         x86ms->above_4g_mem_size = 0;
 180         x86ms->below_4g_mem_size = machine->ram_size;
 181     }
 182
 183     pc_machine_init_sgx_epc(pcms);
 184     x86_cpus_init(x86ms, pcmc->default_cpu_version);
 185
 186     kvmclock_create(pcmc->kvmclock_create_always);
 187
 188     /* pci enabled */
 189     if (pcmc->pci_enabled) {
 190         pci_memory = g_new(MemoryRegion, 1);
 191         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 192         rom_memory = pci_memory;
 193     } else {
 194         pci_memory = NULL;
 195         rom_memory = get_system_memory();
 196     }
 197
 198     pc_guest_info_init(pcms);
 199
 200     if (pcmc->smbios_defaults) {
 201         /* These values are guest ABI, do not change */
 202         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 203                             mc->name, pcmc->smbios_legacy_mode,
 204                             pcmc->smbios_uuid_encoded,
 205                             pcms->smbios_entry_point_type);
 206     }
 207
 208     /* create pci host bus */
 209     q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE));
 210
 211     if (pcmc->pci_enabled) {
 212         pci_hole64_size = object_property_get_uint(OBJECT(q35_host),
 213                                                    PCI_HOST_PROP_PCI_HOLE64_SIZE,
 214                                                    &error_abort);
 215     }
 216
 217     /* allocate ram and load rom/bios */
 218     pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory,
 219                    pci_hole64_size);
 220
 221     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host));
 222     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM,
 223                              OBJECT(ram_memory), NULL);
 224     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM,
 225                              OBJECT(pci_memory), NULL);
 226     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM,
 227                              OBJECT(get_system_memory()), NULL);
 228     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM,
 229                              OBJECT(system_io), NULL);
 230     object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE,
 231                             x86ms->below_4g_mem_size, NULL);
 232     object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE,
 233                             x86ms->above_4g_mem_size, NULL);
 234     /* pci */
 235     sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal);
 236     phb = PCI_HOST_BRIDGE(q35_host);
 237     host_bus = phb->bus;
 238     /* create ISA bus */
 239     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 240                                           ICH9_LPC_FUNC), true,
 241                                           TYPE_ICH9_LPC_DEVICE);
 242
 243     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 244                              TYPE_HOTPLUG_HANDLER,
 245                              (Object **)&x86ms->acpi_dev,
 246                              object_property_allow_set_link,
 247                              OBJ_PROP_LINK_STRONG);
 248     object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 249                              OBJECT(lpc), &error_abort);
 250
 251     acpi_pcihp = object_property_get_bool(OBJECT(lpc),
 252                                           ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
 253                                           NULL);
 254
 255     keep_pci_slot_hpc = object_property_get_bool(OBJECT(lpc),
 256                                                  "x-keep-pci-slot-hpc",
 257                                                  NULL);
 258
 259     if (!keep_pci_slot_hpc && acpi_pcihp) {
 260         object_register_sugar_prop(TYPE_PCIE_SLOT, "x-native-hotplug",
 261                                    "false", true);
 262     }
 263
 264     /* irq lines */
 265     gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
 266
 267     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 268     lpc_dev = DEVICE(lpc);
 269     for (i = 0; i < GSI_NUM_PINS; i++) {
 270         qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
 271     }
 272     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc, ICH9_LPC_NB_PIRQS);
 273     pci_bus_map_irqs(host_bus, ich9_lpc_map_irq);
 274     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 275     isa_bus = ich9_lpc->isa_bus;
 276
 277     if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) {
 278         pc_i8259_create(isa_bus, gsi_state->i8259_irq);
 279     }
 280
 281     if (pcmc->pci_enabled) {
 282         ioapic_init_gsi(gsi_state, "q35");
 283     }
 284
 285     if (tcg_enabled()) {
 286         x86_register_ferr_irq(x86ms->gsi[13]);
 287     }
 288
 289     assert(pcms->vmport != ON_OFF_AUTO__MAX);
 290     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 291         pcms->vmport = ON_OFF_AUTO_ON;
 292     }
 293
 294     /* init basic PC hardware */
 295     pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy,
 296                          0xff0104);
 297
 298     /* connect pm stuff to lpc */
 299     ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms));
 300
 301     if (pcms->sata_enabled) {
 302         /* ahci and SATA device, for q35 1 ahci controller is built-in */
 303         ahci = pci_create_simple_multifunction(host_bus,
 304                                                PCI_DEVFN(ICH9_SATA1_DEV,
 305                                                          ICH9_SATA1_FUNC),
 306                                                true, "ich9-ahci");
 307         idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 308         idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 309         g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
 310         ide_drive_get(hd, ahci_get_num_ports(ahci));
 311         ahci_ide_create_devs(ahci, hd);
 312     } else {
 313         idebus[0] = idebus[1] = NULL;
 314     }
 315
 316     if (machine_usb(machine)) {
 317         /* Should we create 6 UHCI according to ich9 spec? */
 318         ehci_create_ich9_with_companions(host_bus, 0x1d);
 319     }
 320
 321     if (pcms->smbus_enabled) {
 322         /* TODO: Populate SPD eeprom data.  */
 323         pcms->smbus = ich9_smb_init(host_bus,
 324                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 325                                     0xb100);
 326         smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
 327     }
 328
 329     pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 330
 331     /* the rest devices to which pci devfn is automatically assigned */
 332     pc_vga_init(isa_bus, host_bus);
 333     pc_nic_init(pcmc, isa_bus, host_bus);
 334
 335     if (machine->nvdimms_state->is_enabled) {
 336         nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
 337                                x86_nvdimm_acpi_dsmio,
 338                                x86ms->fw_cfg, OBJECT(pcms));
 339     }
 340 }
 341
 342 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 343     static void pc_init_##suffix(MachineState *machine) \
 344     { \
 345         void (*compat)(MachineState *m) = (compatfn); \
 346         if (compat) { \
 347             compat(machine); \
 348         } \
 349         pc_q35_init(machine); \
 350     } \
 351     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 352
 353
 354 static void pc_q35_machine_options(MachineClass *m)
 355 {
 356     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 357     pcmc->default_nic_model = "e1000e";
 358     pcmc->pci_root_uid = 0;
 359     pcmc->default_cpu_version = 1;
 360
 361     m->family = "pc_q35";
 362     m->desc = "Standard PC (Q35 + ICH9, 2009)";
 363     m->units_per_default_bus = 1;
 364     m->default_machine_opts = "firmware=bios-256k.bin";
 365     m->default_display = "std";
 366     m->default_kernel_irqchip_split = false;
 367     m->no_floppy = 1;
 368     machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
 369     machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
 370     machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
 371     machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
 372     m->max_cpus = 288;
 373 }
 374
 375 static void pc_q35_8_0_machine_options(MachineClass *m)
 376 {
 377     pc_q35_machine_options(m);
 378     m->alias = "q35";
 379 }
 380
 381 DEFINE_Q35_MACHINE(v8_0, "pc-q35-8.0", NULL,
 382                    pc_q35_8_0_machine_options);
 383
 384 static void pc_q35_7_2_machine_options(MachineClass *m)
 385 {
 386     pc_q35_8_0_machine_options(m);
 387     m->alias = NULL;
 388     compat_props_add(m->compat_props, hw_compat_7_2, hw_compat_7_2_len);
 389     compat_props_add(m->compat_props, pc_compat_7_2, pc_compat_7_2_len);
 390 }
 391
 392 DEFINE_Q35_MACHINE(v7_2, "pc-q35-7.2", NULL,
 393                    pc_q35_7_2_machine_options);
 394
 395 static void pc_q35_7_1_machine_options(MachineClass *m)
 396 {
 397     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 398     pc_q35_7_2_machine_options(m);
 399     pcmc->legacy_no_rng_seed = true;
 400     compat_props_add(m->compat_props, hw_compat_7_1, hw_compat_7_1_len);
 401     compat_props_add(m->compat_props, pc_compat_7_1, pc_compat_7_1_len);
 402 }
 403
 404 DEFINE_Q35_MACHINE(v7_1, "pc-q35-7.1", NULL,
 405                    pc_q35_7_1_machine_options);
 406
 407 static void pc_q35_7_0_machine_options(MachineClass *m)
 408 {
 409     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 410     pc_q35_7_1_machine_options(m);
 411     pcmc->enforce_amd_1tb_hole = false;
 412     compat_props_add(m->compat_props, hw_compat_7_0, hw_compat_7_0_len);
 413     compat_props_add(m->compat_props, pc_compat_7_0, pc_compat_7_0_len);
 414 }
 415
 416 DEFINE_Q35_MACHINE(v7_0, "pc-q35-7.0", NULL,
 417                    pc_q35_7_0_machine_options);
 418
 419 static void pc_q35_6_2_machine_options(MachineClass *m)
 420 {
 421     pc_q35_7_0_machine_options(m);
 422     compat_props_add(m->compat_props, hw_compat_6_2, hw_compat_6_2_len);
 423     compat_props_add(m->compat_props, pc_compat_6_2, pc_compat_6_2_len);
 424 }
 425
 426 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL,
 427                    pc_q35_6_2_machine_options);
 428
 429 static void pc_q35_6_1_machine_options(MachineClass *m)
 430 {
 431     pc_q35_6_2_machine_options(m);
 432     compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len);
 433     compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len);
 434     m->smp_props.prefer_sockets = true;
 435 }
 436
 437 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL,
 438                    pc_q35_6_1_machine_options);
 439
 440 static void pc_q35_6_0_machine_options(MachineClass *m)
 441 {
 442     pc_q35_6_1_machine_options(m);
 443     compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len);
 444     compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len);
 445 }
 446
 447 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL,
 448                    pc_q35_6_0_machine_options);
 449
 450 static void pc_q35_5_2_machine_options(MachineClass *m)
 451 {
 452     pc_q35_6_0_machine_options(m);
 453     compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len);
 454     compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len);
 455 }
 456
 457 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL,
 458                    pc_q35_5_2_machine_options);
 459
 460 static void pc_q35_5_1_machine_options(MachineClass *m)
 461 {
 462     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 463
 464     pc_q35_5_2_machine_options(m);
 465     compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len);
 466     compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len);
 467     pcmc->kvmclock_create_always = false;
 468     pcmc->pci_root_uid = 1;
 469 }
 470
 471 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL,
 472                    pc_q35_5_1_machine_options);
 473
 474 static void pc_q35_5_0_machine_options(MachineClass *m)
 475 {
 476     pc_q35_5_1_machine_options(m);
 477     m->numa_mem_supported = true;
 478     compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len);
 479     compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len);
 480     m->auto_enable_numa_with_memdev = false;
 481 }
 482
 483 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL,
 484                    pc_q35_5_0_machine_options);
 485
 486 static void pc_q35_4_2_machine_options(MachineClass *m)
 487 {
 488     pc_q35_5_0_machine_options(m);
 489     compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len);
 490     compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len);
 491 }
 492
 493 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL,
 494                    pc_q35_4_2_machine_options);
 495
 496 static void pc_q35_4_1_machine_options(MachineClass *m)
 497 {
 498     pc_q35_4_2_machine_options(m);
 499     compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len);
 500     compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len);
 501 }
 502
 503 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
 504                    pc_q35_4_1_machine_options);
 505
 506 static void pc_q35_4_0_1_machine_options(MachineClass *m)
 507 {
 508     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 509     pc_q35_4_1_machine_options(m);
 510     pcmc->default_cpu_version = CPU_VERSION_LEGACY;
 511     /*
 512      * This is the default machine for the 4.0-stable branch. It is basically
 513      * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the
 514      * 4.0 compat props.
 515      */
 516     compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
 517     compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
 518 }
 519
 520 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL,
 521                    pc_q35_4_0_1_machine_options);
 522
 523 static void pc_q35_4_0_machine_options(MachineClass *m)
 524 {
 525     pc_q35_4_0_1_machine_options(m);
 526     m->default_kernel_irqchip_split = true;
 527     /* Compat props are applied by the 4.0.1 machine */
 528 }
 529
 530 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL,
 531                    pc_q35_4_0_machine_options);
 532
 533 static void pc_q35_3_1_machine_options(MachineClass *m)
 534 {
 535     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 536
 537     pc_q35_4_0_machine_options(m);
 538     m->default_kernel_irqchip_split = false;
 539     m->smbus_no_migration_support = true;
 540     pcmc->pvh_enabled = false;
 541     compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len);
 542     compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
 543 }
 544
 545 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
 546                    pc_q35_3_1_machine_options);
 547
 548 static void pc_q35_3_0_machine_options(MachineClass *m)
 549 {
 550     pc_q35_3_1_machine_options(m);
 551     compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len);
 552     compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
 553 }
 554
 555 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
 556                     pc_q35_3_0_machine_options);
 557
 558 static void pc_q35_2_12_machine_options(MachineClass *m)
 559 {
 560     pc_q35_3_0_machine_options(m);
 561     compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
 562     compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
 563 }
 564
 565 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
 566                    pc_q35_2_12_machine_options);
 567
 568 static void pc_q35_2_11_machine_options(MachineClass *m)
 569 {
 570     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 571
 572     pc_q35_2_12_machine_options(m);
 573     pcmc->default_nic_model = "e1000";
 574     compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len);
 575     compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
 576 }
 577
 578 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
 579                    pc_q35_2_11_machine_options);
 580
 581 static void pc_q35_2_10_machine_options(MachineClass *m)
 582 {
 583     pc_q35_2_11_machine_options(m);
 584     compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len);
 585     compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len);
 586     m->auto_enable_numa_with_memhp = false;
 587 }
 588
 589 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
 590                    pc_q35_2_10_machine_options);
 591
 592 static void pc_q35_2_9_machine_options(MachineClass *m)
 593 {
 594     pc_q35_2_10_machine_options(m);
 595     compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len);
 596     compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
 597 }
 598
 599 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
 600                    pc_q35_2_9_machine_options);
 601
 602 static void pc_q35_2_8_machine_options(MachineClass *m)
 603 {
 604     pc_q35_2_9_machine_options(m);
 605     compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len);
 606     compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
 607 }
 608
 609 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
 610                    pc_q35_2_8_machine_options);
 611
 612 static void pc_q35_2_7_machine_options(MachineClass *m)
 613 {
 614     pc_q35_2_8_machine_options(m);
 615     m->max_cpus = 255;
 616     compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len);
 617     compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
 618 }
 619
 620 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
 621                    pc_q35_2_7_machine_options);
 622
 623 static void pc_q35_2_6_machine_options(MachineClass *m)
 624 {
 625     X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
 626     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 627
 628     pc_q35_2_7_machine_options(m);
 629     pcmc->legacy_cpu_hotplug = true;
 630     x86mc->fwcfg_dma_enabled = false;
 631     compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len);
 632     compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
 633 }
 634
 635 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
 636                    pc_q35_2_6_machine_options);
 637
 638 static void pc_q35_2_5_machine_options(MachineClass *m)
 639 {
 640     X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
 641
 642     pc_q35_2_6_machine_options(m);
 643     x86mc->save_tsc_khz = false;
 644     m->legacy_fw_cfg_order = 1;
 645     compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
 646     compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
 647 }
 648
 649 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
 650                    pc_q35_2_5_machine_options);
 651
 652 static void pc_q35_2_4_machine_options(MachineClass *m)
 653 {
 654     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 655
 656     pc_q35_2_5_machine_options(m);
 657     m->hw_version = "2.4.0";
 658     pcmc->broken_reserved_end = true;
 659     compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
 660     compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
 661 }
 662
 663 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 664                    pc_q35_2_4_machine_options);