2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu-timer.h"
34 #define DPRINTF(fmt, ...) \
35 do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
37 #define DPRINTF(fmt, ...)
40 //#define DEBUG_IRQ_LATENCY
41 //#define DEBUG_IRQ_COUNT
43 typedef struct PicState
{
44 uint8_t last_irr
; /* edge detection */
45 uint8_t irr
; /* interrupt request register */
46 uint8_t imr
; /* interrupt mask register */
47 uint8_t isr
; /* interrupt service register */
48 uint8_t priority_add
; /* highest irq priority */
50 uint8_t read_reg_select
;
55 uint8_t rotate_on_auto_eoi
;
56 uint8_t special_fully_nested_mode
;
57 uint8_t init4
; /* true if 4 byte init */
58 uint8_t single_mode
; /* true if slave pic is not initialized */
59 uint8_t elcr
; /* PIIX edge/trigger selection*/
61 PicState2
*pics_state
;
67 /* 0 is master pic, 1 is slave pic */
68 /* XXX: better separation between the two pics */
71 void *irq_request_opaque
;
74 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
75 static int irq_level
[16];
77 #ifdef DEBUG_IRQ_COUNT
78 static uint64_t irq_count
[16];
82 /* set irq level. If an edge is detected, then the IRR is set to 1 */
83 static inline void pic_set_irq1(PicState
*s
, int irq
, int level
)
99 if ((s
->last_irr
& mask
) == 0)
103 s
->last_irr
&= ~mask
;
108 /* return the highest priority found in mask (highest = smallest
109 number). Return 8 if no irq */
110 static inline int get_priority(PicState
*s
, int mask
)
116 while ((mask
& (1 << ((priority
+ s
->priority_add
) & 7))) == 0)
121 /* return the pic wanted interrupt. return -1 if none */
122 static int pic_get_irq(PicState
*s
)
124 int mask
, cur_priority
, priority
;
126 mask
= s
->irr
& ~s
->imr
;
127 priority
= get_priority(s
, mask
);
130 /* compute current priority. If special fully nested mode on the
131 master, the IRQ coming from the slave is not taken into account
132 for the priority computation. */
136 if (s
->special_fully_nested_mode
&& s
== &s
->pics_state
->pics
[0])
138 cur_priority
= get_priority(s
, mask
);
139 if (priority
< cur_priority
) {
140 /* higher priority found: an irq should be generated */
141 return (priority
+ s
->priority_add
) & 7;
147 /* raise irq to CPU if necessary. must be called every time the active
149 /* XXX: should not export it, but it is needed for an APIC kludge */
150 void pic_update_irq(PicState2
*s
)
154 /* first look at slave pic */
155 irq2
= pic_get_irq(&s
->pics
[1]);
157 /* if irq request by slave pic, signal master PIC */
158 pic_set_irq1(&s
->pics
[0], 2, 1);
159 pic_set_irq1(&s
->pics
[0], 2, 0);
161 /* look at requested irq */
162 irq
= pic_get_irq(&s
->pics
[0]);
164 #if defined(DEBUG_PIC)
167 for(i
= 0; i
< 2; i
++) {
168 printf("pic%d: imr=%x irr=%x padd=%d\n",
169 i
, s
->pics
[i
].imr
, s
->pics
[i
].irr
,
170 s
->pics
[i
].priority_add
);
174 printf("pic: cpu_interrupt\n");
176 qemu_irq_raise(s
->parent_irq
);
179 /* all targets should do this rather than acking the IRQ in the cpu */
180 #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA)
182 qemu_irq_lower(s
->parent_irq
);
187 #ifdef DEBUG_IRQ_LATENCY
188 int64_t irq_time
[16];
191 static void i8259_set_irq(void *opaque
, int irq
, int level
)
193 PicState2
*s
= opaque
;
195 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
196 if (level
!= irq_level
[irq
]) {
197 DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq
, level
);
198 irq_level
[irq
] = level
;
199 #ifdef DEBUG_IRQ_COUNT
205 #ifdef DEBUG_IRQ_LATENCY
207 irq_time
[irq
] = qemu_get_clock_ns(vm_clock
);
210 pic_set_irq1(&s
->pics
[irq
>> 3], irq
& 7, level
);
214 /* acknowledge interrupt 'irq' */
215 static inline void pic_intack(PicState
*s
, int irq
)
218 if (s
->rotate_on_auto_eoi
)
219 s
->priority_add
= (irq
+ 1) & 7;
221 s
->isr
|= (1 << irq
);
223 /* We don't clear a level sensitive interrupt here */
224 if (!(s
->elcr
& (1 << irq
)))
225 s
->irr
&= ~(1 << irq
);
228 int pic_read_irq(PicState2
*s
)
230 int irq
, irq2
, intno
;
232 irq
= pic_get_irq(&s
->pics
[0]);
234 pic_intack(&s
->pics
[0], irq
);
236 irq2
= pic_get_irq(&s
->pics
[1]);
238 pic_intack(&s
->pics
[1], irq2
);
240 /* spurious IRQ on slave controller */
243 intno
= s
->pics
[1].irq_base
+ irq2
;
244 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
248 intno
= s
->pics
[0].irq_base
+ irq
;
251 /* spurious IRQ on host controller */
253 intno
= s
->pics
[0].irq_base
+ irq
;
257 #ifdef DEBUG_IRQ_LATENCY
258 printf("IRQ%d latency=%0.3fus\n",
260 (double)(qemu_get_clock_ns(vm_clock
) -
261 irq_time
[irq
]) * 1000000.0 / get_ticks_per_sec());
263 DPRINTF("pic_interrupt: irq=%d\n", irq
);
267 static void pic_reset(void *opaque
)
269 PicState
*s
= opaque
;
277 s
->read_reg_select
= 0;
282 s
->rotate_on_auto_eoi
= 0;
283 s
->special_fully_nested_mode
= 0;
286 /* Note: ELCR is not reset */
289 static void pic_ioport_write(void *opaque
, target_phys_addr_t addr64
,
290 uint64_t val64
, unsigned size
)
292 PicState
*s
= opaque
;
293 uint32_t addr
= addr64
;
294 uint32_t val
= val64
;
295 int priority
, cmd
, irq
;
297 DPRINTF("write: addr=0x%02x val=0x%02x\n", addr
, val
);
302 /* deassert a pending interrupt */
303 qemu_irq_lower(s
->pics_state
->parent_irq
);
306 s
->single_mode
= val
& 2;
308 hw_error("level sensitive irq not supported");
309 } else if (val
& 0x08) {
313 s
->read_reg_select
= val
& 1;
315 s
->special_mask
= (val
>> 5) & 1;
321 s
->rotate_on_auto_eoi
= cmd
>> 2;
323 case 1: /* end of interrupt */
325 priority
= get_priority(s
, s
->isr
);
327 irq
= (priority
+ s
->priority_add
) & 7;
328 s
->isr
&= ~(1 << irq
);
330 s
->priority_add
= (irq
+ 1) & 7;
331 pic_update_irq(s
->pics_state
);
336 s
->isr
&= ~(1 << irq
);
337 pic_update_irq(s
->pics_state
);
340 s
->priority_add
= (val
+ 1) & 7;
341 pic_update_irq(s
->pics_state
);
345 s
->isr
&= ~(1 << irq
);
346 s
->priority_add
= (irq
+ 1) & 7;
347 pic_update_irq(s
->pics_state
);
355 switch(s
->init_state
) {
359 pic_update_irq(s
->pics_state
);
362 s
->irq_base
= val
& 0xf8;
363 s
->init_state
= s
->single_mode
? (s
->init4
? 3 : 0) : 2;
373 s
->special_fully_nested_mode
= (val
>> 4) & 1;
374 s
->auto_eoi
= (val
>> 1) & 1;
381 static uint32_t pic_poll_read(PicState
*s
)
385 ret
= pic_get_irq(s
);
387 bool slave
= (s
== &isa_pic
->pics
[1]);
390 s
->pics_state
->pics
[0].isr
&= ~(1 << 2);
391 s
->pics_state
->pics
[0].irr
&= ~(1 << 2);
393 s
->irr
&= ~(1 << ret
);
394 s
->isr
&= ~(1 << ret
);
395 if (slave
|| ret
!= 2)
396 pic_update_irq(s
->pics_state
);
399 pic_update_irq(s
->pics_state
);
405 static uint64_t pic_ioport_read(void *opaque
, target_phys_addr_t addr1
,
408 PicState
*s
= opaque
;
409 unsigned int addr
= addr1
;
413 ret
= pic_poll_read(s
);
417 if (s
->read_reg_select
)
425 DPRINTF("read: addr=0x%02x val=0x%02x\n", addr
, ret
);
429 /* memory mapped interrupt status */
430 /* XXX: may be the same than pic_read_irq() */
431 uint32_t pic_intack_read(PicState2
*s
)
435 ret
= pic_poll_read(&s
->pics
[0]);
437 ret
= pic_poll_read(&s
->pics
[1]) + 8;
438 /* Prepare for ISR read */
439 s
->pics
[0].read_reg_select
= 1;
444 static void elcr_ioport_write(void *opaque
, target_phys_addr_t addr
,
445 uint64_t val
, unsigned size
)
447 PicState
*s
= opaque
;
448 s
->elcr
= val
& s
->elcr_mask
;
451 static uint64_t elcr_ioport_read(void *opaque
, target_phys_addr_t addr
,
454 PicState
*s
= opaque
;
458 static const VMStateDescription vmstate_pic
= {
461 .minimum_version_id
= 1,
462 .minimum_version_id_old
= 1,
463 .fields
= (VMStateField
[]) {
464 VMSTATE_UINT8(last_irr
, PicState
),
465 VMSTATE_UINT8(irr
, PicState
),
466 VMSTATE_UINT8(imr
, PicState
),
467 VMSTATE_UINT8(isr
, PicState
),
468 VMSTATE_UINT8(priority_add
, PicState
),
469 VMSTATE_UINT8(irq_base
, PicState
),
470 VMSTATE_UINT8(read_reg_select
, PicState
),
471 VMSTATE_UINT8(poll
, PicState
),
472 VMSTATE_UINT8(special_mask
, PicState
),
473 VMSTATE_UINT8(init_state
, PicState
),
474 VMSTATE_UINT8(auto_eoi
, PicState
),
475 VMSTATE_UINT8(rotate_on_auto_eoi
, PicState
),
476 VMSTATE_UINT8(special_fully_nested_mode
, PicState
),
477 VMSTATE_UINT8(init4
, PicState
),
478 VMSTATE_UINT8(single_mode
, PicState
),
479 VMSTATE_UINT8(elcr
, PicState
),
480 VMSTATE_END_OF_LIST()
484 static const MemoryRegionOps pic_base_ioport_ops
= {
485 .read
= pic_ioport_read
,
486 .write
= pic_ioport_write
,
488 .min_access_size
= 1,
489 .max_access_size
= 1,
493 static const MemoryRegionOps pic_elcr_ioport_ops
= {
494 .read
= elcr_ioport_read
,
495 .write
= elcr_ioport_write
,
497 .min_access_size
= 1,
498 .max_access_size
= 1,
502 /* XXX: add generic master/slave system */
503 static void pic_init1(int io_addr
, int elcr_addr
, PicState
*s
)
505 memory_region_init_io(&s
->base_io
, &pic_base_ioport_ops
, s
, "pic", 2);
506 memory_region_init_io(&s
->elcr_io
, &pic_elcr_ioport_ops
, s
, "elcr", 1);
508 isa_register_ioport(NULL
, &s
->base_io
, io_addr
);
509 if (elcr_addr
>= 0) {
510 isa_register_ioport(NULL
, &s
->elcr_io
, elcr_addr
);
513 vmstate_register(NULL
, io_addr
, &vmstate_pic
, s
);
514 qemu_register_reset(pic_reset
, s
);
517 void pic_info(Monitor
*mon
)
526 s
= &isa_pic
->pics
[i
];
527 monitor_printf(mon
, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
528 "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
529 i
, s
->irr
, s
->imr
, s
->isr
, s
->priority_add
,
530 s
->irq_base
, s
->read_reg_select
, s
->elcr
,
531 s
->special_fully_nested_mode
);
535 void irq_info(Monitor
*mon
)
537 #ifndef DEBUG_IRQ_COUNT
538 monitor_printf(mon
, "irq statistic code not compiled.\n");
543 monitor_printf(mon
, "IRQ statistics:\n");
544 for (i
= 0; i
< 16; i
++) {
545 count
= irq_count
[i
];
547 monitor_printf(mon
, "%2d: %" PRId64
"\n", i
, count
);
552 qemu_irq
*i8259_init(qemu_irq parent_irq
)
556 s
= g_malloc0(sizeof(PicState2
));
557 pic_init1(0x20, 0x4d0, &s
->pics
[0]);
558 pic_init1(0xa0, 0x4d1, &s
->pics
[1]);
559 s
->pics
[0].elcr_mask
= 0xf8;
560 s
->pics
[1].elcr_mask
= 0xde;
561 s
->parent_irq
= parent_irq
;
562 s
->pics
[0].pics_state
= s
;
563 s
->pics
[1].pics_state
= s
;
565 return qemu_allocate_irqs(i8259_set_irq
, s
, 16);